Encryption device for nonvolatile memory in chip

Abstract

The utility model provides an encryption device of a nonvolatile memory in a chip, which relates to the technical field of data encryption, comprises a secret key module, a bus module and an advanced encryption standard (AES) encryption module, realizes the function of dynamically generating a secret key by integrating an oscillator unit and a counter, and particularly relates to the encryption device of the nonvolatile memory in the chip. Through the two oscillators with different frequencies and the corresponding counters, the binary secret key based on the oscillation frequency can be generated in real time, and due to the fact that in the actual manufacturing process, the precision technologies of the oscillators are different, the oscillation frequency of each first oscillator and the oscillation frequency of each second oscillator are different to a certain extent, and the accuracy of the binary secret key is improved. And the difference is unpredictable, so that the key generation mode has unpredictability and real-time performance, and the cracking difficulty is greatly increased.

Description

Technical Field

[0001] The utility model relates to the technical field of data encryption, in particular to an encryption device for a non-volatile memory in a chip. Background Art

[0002] Equipment manufacturers usually store a large amount of confidential information, including algorithms, software codes, etc., in the chip of the control board. Chip encryption can ensure that these sensitive data are protected during transmission and storage to prevent leakage and theft. Modern system chips integrate non-volatile memory to store important data, such as the basic code required to initialize hardware and load the operating system when the storage system starts. Chip encryption can protect the flow of data within the chip, but once the data is written to the external non-volatile memory, its security needs to be ensured by encrypting the memory itself. Non-volatile memory is used to store data persistently, which means that the data still exists even when the device is powered off or offline. If these memories are not encrypted, attackers may be able to extract sensitive information by physically accessing these memories.

[0003] Publication number CN220709663U provides a data encryption and decryption device, chip and printer, which solves the problem of poor chip data security by using two key accesses, and improves the security strength of data encryption and decryption. Its encryption method essentially relies on a fixed key, which means that once the key is cracked, all data will face the risk of leakage. In addition, the encryption method with a fixed key is easily cracked by malicious attackers through repeated attempts, thus posing a threat to data security. Therefore, an encryption device that can dynamically generate keys is needed to improve data security and anti-attack capabilities. Utility Model Content

[0004] The purpose of the utility model is to provide an encryption device for a non-volatile memory in a chip to solve the problems raised in the above background technology.

[0005] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0006] An encryption device for a non-volatile memory in a chip, the encryption device is suitable for encrypting data input into the non-volatile memory from a data input port, the encryption device comprises a key module, a bus module and an AES encryption module, wherein:

[0007] The key module includes an oscillator unit and a control module. The oscillator unit has two oscillation frequencies, a first oscillator and a second oscillator, and the oscillation frequency of the first oscillator is higher than that of the second oscillator. The output of the first oscillator is electrically connected to the data input end of the first counter, and the data output end of the first counter is electrically connected to the bus module. The first counter is used to count the oscillation frequency of the first oscillator and send the counted oscillation frequency data to the bus module in the form of binary numbers.

[0008] The output of the second oscillator is electrically connected to the input of the second counter, the overflow output of the second counter is electrically connected to the stop input of the first counter, the second counter is used to count the oscillation frequency of the second oscillator, and send an enable signal when the count is full to control the first counter to stop counting;

[0009] The control module is electrically connected to the oscillator unit, the first counter and the second counter, respectively, and is used to control the start and stop of the oscillator unit, the first counter and the second counter;

[0010] The bus module is electrically connected to the key module and the AES encryption module respectively, and is used to send the binary number of the oscillation frequency data counted by the first counter to the AES encryption module. The input port and output port of the AES encryption module are electrically connected to the data input port and the non-volatile memory respectively, and is used to use the binary number of the oscillation frequency data counted by the first counter as a key, perform AES encryption on the data input from the data input port, and then send it to the non-volatile memory for storage.

[0011] Furthermore, the first oscillator includes a first inverter group consisting of a NAND gate Nand1 and a plurality of inverters connected in series, the input end of the first inverter group is electrically connected to the output end of the NAND gate Nand1, one input end of the NAND gate Nand1 is electrically connected to the control module, and the other input end is electrically connected to the output end of the first inverter group, and the output end of the first inverter group is also electrically connected to the data input end of the first counter.

[0012] Furthermore, the second oscillator includes a second inverter group consisting of a NAND gate Nand2 and a plurality of inverters connected in series, the input end of the second inverter group is electrically connected to the output end of the NAND gate Nand2, one input end of the NAND gate Nand2 is electrically connected to the control module, the other input end is electrically connected to the output end of the second inverter group, and the output end of the second inverter group is also electrically connected to the data input end of the second counter.

[0013] Furthermore, the number of inverters in the first inverter group is greater than the number of inverters in the second inverter group.

[0014] Furthermore, the control module includes a D flip-flop and two AND gates And1 and And2, the clock input end of the D flip-flop is connected to an external clock signal, the output end is electrically connected to an input end of an OR gate and an input end of an XOR gate, the other input end of the OR gate is electrically connected to the output end of the AND gate And1, the other input end of the XOR gate is connected to the output end of the AND gate And2, the output end of the OR gate is electrically connected to the first oscillator and the second oscillator, and is used to control the operation of the first oscillator and the second oscillator, and the output end of the XOR gate is electrically connected to the first counter and the second counter, and is used to control the operation of the first counter and the second counter.

[0015] Compared with the prior art, the beneficial effects of the utility model are:

[0016] The utility model realizes the function of dynamically generating keys by integrating an oscillator unit and a counter. Specifically, two oscillators with different frequencies and corresponding counters can generate binary keys based on the oscillation frequency in real time. Since the oscillators and precision processes may vary in the actual manufacturing process, there may be certain differences in the oscillation frequencies of each first oscillator and the second oscillator, and such differences are unpredictable. Therefore, such a key generation method has unpredictability and real-time characteristics, which greatly increases the difficulty of cracking.

[0017] In addition, since the key is generated based on the oscillation frequency of the physical device, even if the attacker obtains the chip, it is difficult to copy or predict the key, thereby effectively protecting the data stored in the non-volatile memory. This encryption device not only improves the security of the data, but also enhances the overall anti-attack capability of the system, ensuring the security of data during storage and transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the overall system structure of the utility model;

[0019] Figure 2 It is a schematic diagram of the circuit structure of the oscillator unit in the utility model;

[0020] Figure 3 This is a schematic diagram of the circuit structure of the control module in the utility model;

[0021] Figure 4 It is a schematic diagram of the circuit connection structure of the oscillator unit and the control module in the utility model.

[0022] In the figure: a key module 10 , an oscillator unit 11 , a control module 12 , a second counter 13 , a first counter 14 , a bus module 20 , an AES encryption module 30 , an input port 40 , and a non-volatile memory 50 . DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0024] Example:

[0025] See also Figures 1 to 4 , the utility model provides a technical solution:

[0026] An encryption device for a non-volatile memory in a chip, the encryption device is suitable for encrypting data input from a data input port 40 to a non-volatile memory 50, the encryption device comprises a key module 10, a bus module 20 and an AES encryption module 30, wherein:

[0027] Data is first generated by various sources, which can be user input, data from sensors or information generated by the device itself. This data is transmitted to the data input port 40 and is ready for encryption processing. After the data input port 40 receives the data, the data needs to be encrypted before being stored in the non-volatile memory.

[0028] In this embodiment, the data input port 40 refers to an interface for receiving data for processing and storage, such as a USB port: usually used for data transmission between an external device and a host device, a serial port and a parallel port, etc. The non-volatile memory 50 refers to a storage device that can maintain stored information even in the event of a power outage, such as a NAND flash memory, a NOR flash memory, an electrically erasable programmable read-only memory, etc.

[0029] The key module 10 includes an oscillator unit 11 and a control module 12. The oscillator unit 11 has two oscillation frequencies, a first oscillator and a second oscillator, and the oscillation frequency of the first oscillator is higher than that of the second oscillator. The output of the first oscillator is electrically connected to the data input end of the first counter 14, and the data output end of the first counter 14 is electrically connected to the bus module 20. The first counter 14 is used to count the oscillation frequency of the first oscillator and send the counted oscillation frequency data to the bus module 20 in the form of binary numbers.

[0030] In this embodiment, the first oscillator includes a first inverter group consisting of a NAND gate Nand1 and multiple inverters connected in series. The input and output of the inverters inside the first inverter group are connected in series in sequence. At the same time, the input end of the first inverter group is electrically connected to the output end of the NAND gate Nand1. One input end of the NAND gate Nand1 is electrically connected to the control module 12, and the other input end is electrically connected to the output end of the first inverter group. Therefore, the first inverter group is essentially a ring oscillator. The output end of the first inverter group is also electrically connected to the data input end of the first counter 14. In fact, the output end of the first oscillator is directly connected to the clock input end of the first counter 14. This connection method allows the clock signal generated by the ring oscillator to directly drive the first counter 14 to perform counting operations.

[0031] In this embodiment, the second oscillator includes a second inverter group consisting of a NAND gate Nand2 and multiple inverters connected in series, the input and output of the inverters inside the second inverter group are connected in series in sequence, the input end of the second inverter group is electrically connected to the output end of the NAND gate Nand2, one input end of the NAND gate Nand2 is electrically connected to the control module 12, and the other input end is electrically connected to the output end of the second inverter group, so the second inverter group is essentially also a ring oscillator, the output end of the second inverter group is also electrically connected to the data input end of the second counter 13, in fact, the output end of the second oscillator is directly connected to the clock input end of the second counter 13, this connection method allows the clock signal generated by the ring oscillator to directly drive the second counter 13 to perform counting operations.

[0032] In this embodiment, the model used by the NAND gate Nand1 and the NAND gate Nand2 is 74HC00, which is a quad 2-input NAND gate, which is produced by Texas Instruments and NXP, etc., and each chip contains four independent 2-input NAND gates. The model used by the inverter is 74HC0, which is a hexa-inverter, which is produced by many manufacturers such as Texas Instruments and NXP, and each chip contains six independent inverters, usually in 14-pin DIP or SOIC packages, and the corresponding number can be selected according to actual use.

[0033] Furthermore, the number of inverters inside the first inverter group is greater than the number of inverters inside the second inverter group, and the number of inverters inside the first inverter group and the second inverter group are both odd numbers. The first oscillator and the second oscillator both have an odd number of inverters connected in series to form a closed loop, thereby generating oscillations. The output of the first oscillator and the second oscillator is a periodic square wave signal, and its frequency depends on the number of inverters and the delay of each inverter. Such a design allows the oscillator frequencies of the first oscillator and the second oscillator to be different.

[0034] In the actual manufacturing process, the delay of each inverter is different, so the delay of the loop of the first oscillator and the second oscillator composed of them will also be different, and the process of each inverter is also different. Therefore, there will be a certain difference in the oscillation frequency of the first oscillator and the second oscillator, and this difference is random and uncontrollable.

[0035] The output of the second oscillator is electrically connected to the input of the second counter 13, the overflow output of the second counter 13 is electrically connected to the stop input of the first counter 14, the second counter 13 is used to count the oscillation frequency of the second oscillator, and send an enable signal when the count is full to control the first counter 14 to stop counting.

[0036] In this embodiment, the output end of the second oscillator is connected to the clock input end of the second counter 13. The second counter 13 will count according to the square wave signal generated by the second oscillator. The overflow output end of the second counter 13 is connected to the stop input end of the first counter 14. When the second counter 13 is full and overflows, it will send a signal to the first counter 14 to stop counting.

[0037] In this embodiment, the second counter 13 adopts the model 74HC161, which is a 4-bit binary synchronous counter with synchronous clearing and preset functions. The first counter 14 adopts the model 74HC163, which is also a 4-bit binary synchronous counter, similar to 74HC161, but has a synchronous clearing function.

[0038] When the second oscillator starts to oscillate, its output square wave signal drives the second counter 13 to count. When the second counter 13 is full, that is, reaches the maximum count value, its overflow output terminal will become a high level, which will trigger the stop input terminal of the first counter 14, thereby stopping the counting of the first counter 14. The counting process of the first counter 14 is controlled by the frequency of the second oscillator, thereby realizing dynamic control of the first counter 14.

[0039] The control module 12 is electrically connected to the oscillator unit 11 and the first counter 14 and the second counter 13 , respectively, and is used to control the start and stop of the oscillator unit 11 , the first counter 14 , and the second counter 13 .

[0040] In this embodiment, the control module 12 includes a D flip-flop and two AND gates And1 and And2, the clock input end of the D flip-flop is connected to the clock signal, the Q output end is electrically connected to an input end of the OR gate Or and an input end of the XOR gate Nxor, the other input end of the OR gate Or is electrically connected to the output end of the AND gate And1, the other input end of the XOR gate Nxor is connected to the output end of the AND gate And2, the output end EN1 of the OR gate Or is electrically connected to the other input end of the NAND gate Nand1 inside the first oscillator and the other input end of the NAND gate Nand2 inside the second oscillator, and is used to control the operation of the first oscillator and the second oscillator, the output end EN2 of the XOR gate Nxor is electrically connected to the first counter 14 and the second counter 13, and is used to control the operation of the first counter 14 and the second counter 13.

[0041] In this embodiment, the characteristic of the XOR gate Nxor is to output a high level (1) when the logic states of the input terminals are different, and to output a low level (0) when the logic states of the input terminals are the same. The output terminal EN2 of the XOR gate Nxor is connected to the first counter 14 and the second counter 13. The signal output by the XOR gate Nxor is used to control the working states of the two counters. In this embodiment, the model used by the first counter 14 and the second counter 13 is 74HC161 or 74HC163.

[0042] Taking 74HC161 and 74HC163 as examples, both models of counters have ENP pins, which are used to enable the input and counting functions of the counter. By controlling the ENT pin through the XOR gate Nxor, the counting function of the counter can be enabled or disabled. If EN2 is high, the counter can count normally; if EN2 is low, it stops counting.

[0043] Furthermore, one end input of the NAND gate Nand1 and the NAND gate Nand2 of the first oscillator and the second oscillator is the output EN1 from the control module 12. When EN1 is 1, the first oscillator and the second oscillator start to work, and the first oscillator and the second oscillator start to oscillate and generate two oscillation frequencies. Since the structures of the first oscillator and the second oscillator are different, the two frequencies generated are also different. Their oscillation frequencies are respectively counted by a group of first counters 14 and second counters 13.

[0044] An input end of the AND gate And1 is defined as SA, an input end of the AND gate And2 is defined as EN, and the other end of the AND gate And1 and the AND gate And2 is connected and defined as TE. In this embodiment, SA1 is a signal fixed to a high level, and the TE end is a control signal during testing. When the TE end is 1, testing can be performed. When testing is performed, the two inputs of the AND gate And1 are 1. At this time, the output of EN1 is related to the AND gate And1. When EN1 is 1, the first oscillator and the second oscillator are started and start to generate an oscillation frequency. When the EN signal is 1, the input of the AND gate And2 is 1. At this time, the output of the XOR gate Nxor is 1. EN2 is used to control the first counter 14 and the second counter 13. When EN2 is 1, the counting module is started and starts to count the frequencies of the two ring oscillators.

[0045] In this embodiment, the key finally input into the bus module 20 is the binary number of the oscillation frequency counted by the first counter 14. The counter itself is mainly used for counting, and its value is increased or decreased in binary form. Therefore, the counter performs binary operations internally without conversion. The frequency of the first oscillator is greater than the frequency of the second oscillator, so the value counted by the first counter 14 is greater than the value counted by the second counter 13. When the second counter 13 is full, a stop signal is generated to stop the counting of the first counter 14. The binary value obtained by the first counter 14 is the key of the AES encryption module 30. Since the first counter 14 and the second counter 13 are respectively used to count the frequencies of the two oscillators, since the frequency of the first oscillator is higher, the value counted by the first counter 14 is naturally larger. When the second counter 13 is full and a stop signal is generated, the counting of the first counter 14 stops. At this time, the value of the first counter 14 is the key. In this process, the generation of the key does not depend on the absolute frequency of any oscillator, but depends on the relative relationship between the frequencies of the two oscillators. Therefore, even if the temperature changes and causes the frequencies of the two oscillators to shift, as long as the shift is relatively consistent, the generation of the key will not be affected by the temperature change.

[0046] In this embodiment, the function of dynamically generating keys is implemented by integrating an oscillator unit and a counter. Specifically, a binary key based on the oscillation frequency can be generated in real time through two oscillators with different frequencies and corresponding counters. Since the oscillators and precision processes may vary during the actual manufacturing process, there may be certain differences in the oscillation frequencies of each of the first oscillator and the second oscillator, and such differences are unpredictable. Therefore, this key generation method is unpredictable and real-time, which greatly increases the difficulty of cracking.

[0047] The bus module 20 is electrically connected to the key module 10 and the AES encryption module 30 respectively, and is used to send the binary number of the oscillation frequency data counted by the first counter 14 to the AES encryption module 30. The input port and output port of the AES encryption module 30 are electrically connected to the data input port 40 and the non-volatile memory 50 respectively, and is used to use the binary number of the oscillation frequency data counted by the first counter 14 as a key, AES encrypt the data input from the data input port 40, and then send it to the non-volatile memory 50 for storage.

[0048] In this embodiment, the model adopted by the AES encryption module 30 is ATAES132A, and the model adopted by the bus module 20 is NXP's PCA9548A. The digital output port of the first counter 14 will be directly connected to the GPIO port of the bus module 20, and the I2C channel output of the bus module 20 will be connected to the I2C interface of the AES encryption module 30. The bus module 20 is used as an intermediary of the I2C bus to allow communication between the first counter 14 and the AES encryption module 30.

[0049] The bus module 20 serves as a channel for key transmission. The bus module 20 is responsible for transmitting the key data generated by the key module 10 to the AES encryption module 30. Efficient data transmission ensures the real-time and continuity of the encryption process, reduces human intervention, and improves the automation and security of key generation. Direct key transmission reduces intermediate links and reduces the risk of data leakage. At the same time, the AES encryption module 30 combines real-time updated keys to ensure that the data encryption process is both fast and secure. Since the key is generated based on the oscillation frequency of the physical device, even if the attacker obtains the chip, it is difficult to copy or predict the key, thereby effectively protecting the data stored in the non-volatile memory. This encryption device not only improves the security of the data, but also enhances the overall anti-attack capability of the system, ensuring the security of data during storage and transmission.

[0050] The decryption process needs to correspond to the encryption process and use the same key as that used for encryption. The decryption process is performed through an AES decryption module, which needs to receive the same key as that used for encryption from the key module 10. This key will be transmitted through the bus module 20. After receiving the key, the AES decryption module can use the key to restore the encrypted data to the original data.

[0051] The use principle of this utility model:

[0052] The frequency of the first oscillator is higher, and the frequency of the second oscillator is lower. The output of the first oscillator is connected to the first counter 14, which is used to count the oscillation frequency and convert it into a binary number. The second oscillator is connected to the second counter 13, and its overflow signal is used to control the stop of the first counter 14, thereby forming a dynamic key generation mechanism. The control module 23 controls the start and stop of the oscillator and the counter through the D flip-flop and the AND gate. The D flip-flop receives an external clock signal and controls the working state of the oscillator and the counter through the combination of logic gates to ensure the synchronization of the key generation and the encryption process;

[0053] The bus module 20 is responsible for transmitting the binary number generated by the first counter 14 to the AES encryption module 30 . The AES encryption module 30 uses the dynamic key to encrypt the data received from the data input port 40 , and then stores the encrypted data in the non-volatile memory 50 .

[0054] The utility model uses the characteristics of the oscillator and the counter to generate a dynamically changing key through precise hardware design, thereby enhancing the security of data encryption, and at the same time ensures the accuracy and synchronization of the entire encryption process through the control module 12.

[0055] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An encryption device for a non-volatile memory in a chip, the encryption device being suitable for encrypting data inputted into the non-volatile memory from a data input port, the encryption device comprising a key module, a bus module and an AES encryption module, characterized in that: The key module includes an oscillator unit and a control module. The oscillator unit has two oscillation frequencies, a first oscillator and a second oscillator, and the oscillation frequency of the first oscillator is higher than that of the second oscillator. The output of the first oscillator is electrically connected to the data input end of the first counter, and the data output end of the first counter is electrically connected to the bus module. The first counter is used to count the oscillation frequency of the first oscillator and send the counted oscillation frequency data to the bus module in the form of binary numbers. The output of the second oscillator is electrically connected to the input of the second counter, the overflow output of the second counter is electrically connected to the stop input of the first counter, the second counter is used to count the oscillation frequency of the second oscillator, and send an enable signal when the count is full to control the first counter to stop counting; The control module is electrically connected to the oscillator unit, the first counter and the second counter, respectively, and is used to control the start and stop of the oscillator unit, the first counter and the second counter; The bus module is electrically connected to the key module and the AES encryption module respectively, and is used to send the binary number of the oscillation frequency data counted by the first counter to the AES encryption module. The input port and output port of the AES encryption module are electrically connected to the data input port and the non-volatile memory respectively, and is used to use the binary number of the oscillation frequency data counted by the first counter as a key, perform AES encryption on the data input from the data input port, and then send it to the non-volatile memory for storage.

2. The encryption device for a non-volatile memory in a chip according to claim 1, characterized in that: The first oscillator includes a first inverter group consisting of a NAND gate Nand1 and multiple inverters connected in series, the input end of the first inverter group is electrically connected to the output end of the NAND gate Nand1, one input end of the NAND gate Nand1 is electrically connected to the control module, and the other input end is electrically connected to the output end of the first inverter group, and the output end of the first inverter group is also electrically connected to the data input end of the first counter.

3. The encryption device of a non-volatile memory in a chip according to claim 2, characterized in that: The second oscillator includes a second inverter group consisting of a NAND gate Nand2 and multiple inverters connected in series, the input end of the second inverter group is electrically connected to the output end of the NAND gate Nand2, one input end of the NAND gate Nand2 is electrically connected to the control module, the other input end is electrically connected to the output end of the second inverter group, and the output end of the second inverter group is also electrically connected to the data input end of the second counter.

4. The encryption device for a non-volatile memory in a chip according to claim 3, characterized in that: The number of inverters in the first inverter group is greater than the number of inverters in the second inverter group.

5. The encryption device for a non-volatile memory in a chip according to claim 1, characterized in that: The control module includes a D flip-flop and two AND gates And1 and And2, wherein the clock input of the D flip-flop is connected to an external clock signal, the output of the D flip-flop is electrically connected to an input of an OR gate and an input of an XOR gate, the other input of the OR gate is electrically connected to the output of the AND gate And1, the other input of the XOR gate is connected to the output of the AND gate And2, the output of the OR gate is electrically connected to a first oscillator and a second oscillator for controlling the operation of the first oscillator and the second oscillator, and the output of the XOR gate is electrically connected to a first counter and a second counter for controlling the operation of the first counter and the second counter.

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