Circuit and circuit for oscillator

Abstract

The utility model provides a circuit and a circuit for an oscillator. The circuit comprises a voltage limiting unit, a voltage detection unit connected to the voltage limiting unit, and a power supply tracking bias unit connected to the voltage detection unit. The voltage limiting unit comprises a first voltage limiting unit and a second voltage limiting unit. The voltage detection unit includes a first voltage detection unit configured to detect the presence of a first threshold voltage in the input signal and a second voltage detection unit configured to detect the presence of a second threshold voltage in the input signal. The power supply tracking bias unit is configured to supply a control signal to the voltage detection unit.

Description

Technical Field

[0001] The present invention relates to a circuit, and more particularly to an input hysteresis buffer in an overdrive design. Background Art

[0002] In advanced technologies, design constraints can make it difficult to provide high voltage devices. For example, a crystal oscillator driver can operate at a voltage higher than the nominal voltage range of the device in the circuit, requiring complex circuit techniques to avoid reliability issues. Changes in process, voltage, and temperature (PVT) further complicate high voltage design. Summary of the invention

[0003] The present disclosure provides a circuit, including a voltage limiting unit, a voltage detection unit, and a power tracking bias unit. The voltage limiting unit includes a first voltage limiter and a second voltage limiter connected in parallel, wherein the voltage limiting unit is configured to divide an input signal into a first path through the first voltage limiter and a second path through the second voltage limiter, wherein: the first voltage limiter is configured to be connected to a first power supply and a second power supply and configured to output a first modified signal, the first modified signal varies between a first minimum voltage corresponding to the first power supply and a first maximum voltage corresponding to the second power supply, and there is a first threshold voltage between the first minimum voltage and the first maximum voltage, and the second voltage limiter is configured to be connected to a third power supply and a fourth power supply and configured to output a second modified signal, the second modified signal varies between a second minimum voltage corresponding to the third power supply and a second maximum voltage corresponding to the fourth power supply, and there is a second threshold voltage between the second minimum voltage and the second maximum voltage. A voltage detection unit is connected to the voltage limiting unit, the voltage detection unit includes a first voltage detector and a second voltage detector, the first voltage detector is connected to the first voltage limiter and is configured to detect the first threshold voltage in the first modified signal, the second voltage detector is connected to the second voltage limiter and is configured to detect the second threshold voltage in the second modified signal. A power tracking bias unit is connected to the voltage detection unit, the power tracking bias unit includes a first unit connected to the first voltage detector and a second unit connected to the second voltage detector, wherein the first unit is configured to supply a first control signal to the first voltage detector, the first control signal changes in response to a change in the first power supply or a change in the second power supply, and the second unit is configured to supply a second control signal to the second voltage detector, the second control signal changes in response to a change in the third power supply or a change in the fourth power supply.

[0004] The present disclosure provides a circuit for an oscillator, comprising an oscillator driver upper threshold voltage determination unit, a lower threshold voltage determination unit, a power tracking bias unit and a decision unit. The oscillator driver is configured to output a pad signal. The upper threshold voltage determination unit is configured to receive the pad signal and generate a first determination output. The lower threshold voltage determination unit is configured to receive the pad signal and generate a second determination output. The power tracking bias unit is configured to supply a first control signal to the upper threshold voltage determination unit and a second control signal to the lower threshold voltage determination unit, wherein the first control signal is configured to compensate for a change in the upper threshold voltage, and the second control signal is configured to compensate for a change in the lower threshold voltage. The decision unit is configured to deliver an output signal based on the first determination output and the second determination output.

[0005] The present disclosure provides a method for operating a circuit, comprising: generating a pad signal that varies between a lower voltage limit and an upper voltage limit; dividing the pad signal into a first determination path and a second determination path, wherein the first determination path supplies a first portion of the pad signal to a first voltage detector connected between a first power source and a second power source, and the second determination path supplies a second portion of the pad signal to a second voltage detector connected between a third power source and a fourth power source; supplying a first control signal as a function of the first power source and the second power source to the first voltage detector, wherein the first control signal is generated by a first power source tracking bias unit; supplying a second control signal as a function of the third power source and the fourth power source to the second voltage detector, wherein the second control signal is A first translated signal is generated by a second power tracking bias unit; a first translated signal is generated from the first voltage detector, wherein the first translated signal has a low value when the first portion of the pad signal is lower than a first threshold voltage level and has a high value when the first portion of the pad signal is higher than the first threshold voltage level; a second translated signal is generated from the second voltage detector, wherein the second translated signal has a low value when the second portion of the pad signal is lower than a second threshold voltage level and has a high value when the second portion of the pad signal is higher than the second threshold voltage level; and an output voltage signal is generated based on the first translated signal and the second translated signal, so that the output voltage signal defines a hysteresis window between the first threshold voltage level and the second threshold voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0007] Figure 1is a block diagram illustrating an input hysteresis buffer according to an embodiment;

[0008] Figure 2 is a block diagram illustrating a circuit for overdriving a crystal oscillator including an input hysteresis buffer according to an embodiment;

[0009] Figure 3 is a graphical illustration depicting a function of an input hysteresis buffer according to an embodiment;

[0010] Figure 4 is a graphical illustration depicting a hysteresis window generated according to an embodiment;

[0011] Figure 5 is a circuit diagram showing a portion of a voltage detector according to an embodiment;

[0012] Figure 6 is a circuit diagram showing a portion of another voltage detector according to an embodiment;

[0013] Figure 7 is a circuit diagram illustrating a voltage detector having a power tracking bias unit according to an embodiment;

[0014] Figure 8 is a circuit diagram illustrating another voltage detector having a power tracking bias unit according to an embodiment;

[0015] Fig. 9A is a circuit diagram illustrating a circuit used in an overdrive design according to an embodiment; Fig. 9B A table summarizing some effects of the circuit according to an embodiment is shown;

[0016] Fig.10 is a circuit diagram illustrating another circuit used in an overdrive design according to an embodiment;

[0017] Fig.11 is a flow chart illustrating a method of providing an input hysteresis buffer according to an embodiment.

[0018] Description of Figure Numbers

[0019] 100, 202: input hysteresis buffer;

[0020] 105, 205: pad signal;

[0021] 110, 240, 715, 815, 940A, 940B, 1040: power tracking bias unit;

[0022] 115: Process and temperature compensation technology;

[0023] 120: Schmitt trigger;

[0024] 200: Overdriving the crystal oscillator / circuit;

[0025] 201: crystal oscillator unit;

[0026] 210, 910, 1010: high side voltage limiter;

[0027] 215, 915, 1015: low side voltage limiter;

[0028] 220: higher threshold voltage detector / high side voltage detector;

[0029] 225: lower threshold voltage detector / low side voltage detector;

[0030] 230: decision maker / decision making unit;

[0031] 240A: Unit 1 / Unit;

[0032] 240B: Unit 2 / Unit;

[0033] 250: voltage limiting unit;

[0034] 260: voltage detection unit;

[0035] 310, 320, 330, 340, 400, 405: curve graphs;

[0036] 401, 402: point;

[0037] 410, 420, 430, 440: frame;

[0038] 500, 600: voltage detector;

[0039] 510, 610, 810: CMOS inverter;

[0040] 520, 620, 720, 820: table;

[0041] 700: circuit;

[0042] 900: Overdriving the crystal oscillator circuit;

[0043] 901: driving circuit;

[0044] 920: high side voltage detector / voltage detector;

[0045] 925: low side voltage detector / voltage detector;

[0046] 930, 1030: decision-making unit;

[0047] 1000: Overdrive the crystal oscillator;

[0048] 1020: high side voltage detector;

[0049] 1025: low side voltage detector;

[0050] 1042: low-side control signal generator;

[0051] 1044: high-side control signal generator;

[0052] 1050A: first determination path;

[0053] 1050B: second path;

[0054] 1100: method;

[0055] 1105, 1110, 1115, 1125, 1130: steps;

[0056] I N ,I P : current;

[0057] M1, M2: control circuit / compensation components;

[0058] M3: controlled resistance component / controlled resistance element / compensation component / component;

[0059] M4: controlled resistance component / compensation component / component;

[0060] VDD: Maximum value / maximum voltage / maximum pad voltage;

[0061] VDDL, VSSH: intermediate voltage / intermediate level / power supply voltage / power supply;

[0062] VDDmid1: middle voltage level;

[0063] V OUT :output signal / final output / signal / output voltage / final voltage signal / final signal / final output signal;

[0064] V OUTH :Signal / output;

[0065] V OUTL :Signal / output / output signal;

[0066] VSS: minimum voltage / minimum value / power supply;

[0067] V TH : Higher threshold voltage / upper threshold voltage / high threshold voltage;

[0068] V TL :Lower threshold voltage / lower threshold voltage / lower threshold voltage. DETAILED DESCRIPTION

[0069] The following detailed description is provided to help the reader fully understand the methods, devices and / or systems described herein. Therefore, various changes, modifications and equivalent forms of the systems, devices and / or methods described herein will be suggested to those with ordinary knowledge in the art. In addition, for the sake of clarity and brevity, the description of well-known functions and structures may be omitted.

[0070] It should be understood that the phrases and terms used herein are for the purpose of illustration and should not be considered as limiting. For example, the use of singular terms such as "a" is not intended to limit the number of items. In addition, for clarity, the use of relational terms such as but not limited to "top", "bottom", "left", "right", "upper", "lower", "down", "up", "side" and the like is used in the description, and the relational terms are not intended to limit the scope of the present invention or the scope of the attached patent application. In addition, it should be understood that any of the features can be used alone or in combination with other features. After checking the detailed description, other systems, methods, features and advantages of the present invention will be obvious or will become obvious to those skilled in the art. All such additional systems, methods, features and advantages are all intended to be included in this description, included in the scope of the present invention and protected by the attached patent application.

[0071] Overdrive designs may require complex circuit techniques to ensure that devices are not damaged or otherwise compromised by applied voltages above the nominal operating range of the device. Therefore, some systems may utilize overdrive designs that facilitate operation of such circuits at high voltages. Crystal oscillator architectures may include Schmitt triggers to stabilize the digital output of the oscillator in the presence of noise and external influences. However, employing conventional Schmitt triggers in overdrive designs may make it difficult to meet input threshold hysteresis buffer requirements while maintaining oscillator performance in terms of start-up time and phase noise profiles.

[0072] In some cases, voltage limiters may be implemented as a protective measure for these devices. However, in a crystal oscillator design, this may result in a direct current (DC) bias gap between the crystal oscillator driver and the Schmitt trigger or hysteresis buffer. Such a gap may increase the startup time and phase noise. In addition, variations in process, voltage, and temperature (PVT variations) result in a further offset between the DC bias level of the signal provided by the crystal oscillator driver and the hysteresis window.

[0073] Various embodiments described herein generally relate to circuit design, and more specifically to circuits and methods for providing compensation for PVT variations in overdrive designs. By incorporating compensation components and power tracking bias cells into the circuit design, performance fluctuations caused by PVT variations can be offset, thereby achieving a more reliable hysteresis buffer. Certain embodiments described herein utilize a power tracking bias cell to supply a control signal to a voltage detector of an input hysteresis buffer. The voltage detector is used to determine whether the input signal is above a threshold voltage that defines a hysteresis window of the input hysteresis buffer. The control signal and various components located within the voltage detector provide compensation for changes in these threshold voltage values ​​caused by PVT variations on the circuit. Through this compensation, changes in the hysteresis window are minimized, and the offset between the DC bias level of the input signal and the center of the hysteresis window is reduced.

[0074] Figure 1 1 is a block diagram showing an overview of the input hysteresis buffer 100 of the present disclosure incorporating a power tracking bias unit 110 according to an embodiment. The Schmitt trigger 120 is configured to receive a pad signal (PAD signal) 105. The voltage of the pad signal 105 varies between a minimum voltage value and a maximum voltage value over time. The Schmitt trigger 120 is incorporated to clean up the noise in the pad signal 105 and sharpen the rise and fall of the voltage signal into a square wave signal with V OUT is output to other devices in the design. This translation is accomplished by defining a hysteresis window between a higher threshold voltage on the rising edge of the signal and a lower threshold voltage on the falling edge of the signal. As the pad signal 105 rises from the minimum voltage to the maximum voltage, the Schmitt trigger 120 switches the output of the pad signal 105 from low to high when the pad signal 105 crosses the higher threshold voltage. As the pad signal 105 drops from the maximum voltage back to the minimum voltage, the Schmitt trigger 120 switches the output of the pad signal 105 from high to low when the pad signal 105 crosses the lower threshold voltage.

[0075] The performance of the Schmitt trigger 120 can be improved by incorporating a power tracking bias cell 110 that employs process and temperature compensation techniques 115. In the absence of such a cell, PVT variations may cause variations in the hysteresis window, resulting in erroneous transitions and weaker noise suppression and resulting in an offset between the DC bias level of the pad signal 105 and the center of the hysteresis window. As will be shown in further detail with respect to the following figures, implementing the power tracking bias cell 110 enables better control of the threshold voltages of the Schmitt trigger. These voltages are compensated in an opposite trend to resist power supply voltage variations. Incorporating process and temperature compensation techniques 115 into the power tracking bias cell provides full PVT compensation for the Schmitt trigger 120, thereby ensuring the reliability of the hysteresis window and transition voltages. In the embodiments described herein, the power tracking bias cell 110 and the Schmitt trigger 120 operate between a minimum voltage VSS and a maximum voltage VDD. However, the present disclosure is not limited thereto, and the cells may operate with intermediate voltage levels (e.g. Figure 1 is used together with VDDmid1) shown in FIG.

[0076] Figure 2 1 is a block diagram of a circuit for overdriving a crystal oscillator 200 incorporating an input hysteresis buffer 202 according to some embodiments. The circuit includes a crystal oscillator unit 201 that outputs a pad signal 205 to the input hysteresis buffer 202, the input hysteresis buffer 202 including a voltage limiting unit 250, a voltage detection unit 260 incorporating a power tracking bias unit 240, and a decision maker 230. In a specific embodiment, the signal varies between a minimum value VSS and a maximum value VDD. The circuit can be designed to respond to a lower threshold voltage V TL And the upper limit voltage V TH The setting is performed so that the center of the hysteresis window corresponds to the DC bias level of the pad signal 205 .

[0077] The input hysteresis buffer 202 translates the pad signal 205 into an output signal V OUT , the output signal V OUT Has sharp edges and defines a low threshold voltage V TL With high threshold voltage V TH The voltage limiting unit 250 and the voltage detecting unit 260 take the pad signal 205 as input and output a signal corresponding to the presence of the threshold voltage to the decision unit 230. The decision unit 230 then outputs V based on the presence of the threshold voltage. OUT .

[0078] In some embodiments, the crystal oscillator unit 201 includes an overdriven crystal oscillator driver that is a self-biasing buffer with a non-rail-to-rail signal. Such a scenario is depicted in the following figures, but the present disclosure is not limited thereto and may incorporate drivers with different characteristics.

[0079] At the beginning, the voltage limiting unit 250 splits the pad signal 205 into two paths. The first path goes through the low-side voltage limiter 215 and the low-side voltage detector 225 to determine whether the pad signal 205 is higher than the lower threshold voltage V TL The low-side voltage limiter 215 receives a portion of the pad signal 205 and converts the signal from a signal varying between VSS and VDD to a signal varying between VSS and an intermediate voltage VDDL. This signal is passed to the lower threshold voltage detector 225 .

[0080] The lower threshold voltage detector 225 evaluates whether the signal from the low-side voltage limiter 215 is higher than the lower threshold voltage V TL Or below the lower threshold voltage V TL The lower threshold voltage detector 225 outputs a signal V based on the signal received from the low-side voltage limiter 215. OUTL , the signal V OUTL When the input signal is lower than V TL It is in the first state and when the input signal is higher than V TL The following is for Figure 3 This translation is described in more detail.

[0081] The lower threshold voltage detector 225 incorporates a power tracking bias unit 240. The power tracking bias unit may include a plurality of units 240A / 240B. In one embodiment, the first unit 240A supplies a control signal to the lower threshold voltage detector 225, which helps to adjust the V caused by PVT variations. TL By incorporating a power tracking bias unit, the lower threshold voltage detector provides better control of the lower threshold voltage and protection against variations in the hysteresis window.

[0082] The second path passes through the high-side voltage limiter 210 and the high-side voltage detector 220 to determine whether the pad signal 205 is higher than the upper threshold voltage V TH The high-side voltage limiter 210 receives a portion of the pad signal 205 and converts the signal from a signal varying between VSS and VDD to a signal varying between an intermediate voltage VSSH and VDD. This signal is passed to the higher threshold voltage detector 220.

[0083] The upper threshold voltage detector 220 evaluates whether the signal from the high-side voltage limiter 210 is higher than the upper threshold voltage V TH Or lower than the upper threshold voltage V TH The higher threshold voltage detector 220 outputs a signal V based on the signal received from the high-side voltage limiter 210. OUTH , the signal V OUTH When the input signal is lower than V TH It is in the first state and when the input signal is higher than V TH The following is for Figure 3 This translation is described in more detail.

[0084] The upper threshold voltage detector 220 incorporates a power tracking bias unit 240. In one embodiment, the second unit 240B of the power tracking bias unit supplies a control signal to the upper threshold voltage detector 220, which helps to adjust the V caused by PVT changes. TH By incorporating a power tracking bias unit, the upper threshold voltage detector provides better control of the upper threshold voltage and protection against variations in the hysteresis window.

[0085] Then, the decision maker 230 responds to the signal V OUTL and V OUTH is evaluated to form the final output V OUT , the final output V OUT Incorporated with V TL With V TH The hysteresis window between Figure 3 The operation of these paths is discussed further.

[0086] Figure 3 310 shows a graph showing the voltage of a circuit for overdriving a crystal oscillator incorporating an input hysteresis buffer over time according to an embodiment. Graph 310 shows the period of pad signal 205. In an embodiment, the signal may vary between a minimum voltage VSS and a maximum voltage VDD. The circuit may be designed to respond to a lower threshold voltage V TL And the upper limit voltage V TH The setting is performed so that the center of the hysteresis window corresponds to the DC bias level of the pad signal 205 .

[0087] Graph 320 depicts a function of the path through the high side of circuit 200. High side voltage limiter 210 passes a corresponding portion of the pad signal between the intermediate level VSSH and VDD to high side voltage detector 220. High side voltage detector 220 determines whether the input signal is higher than the upper threshold voltage V THAs shown in the graph 320 , the output V OUTH is a square wave that switches when it crosses a higher threshold voltage level.

[0088] The graph 330 depicts a function of the path through the low side of the circuit 200. The low side voltage limiter 215 passes the corresponding portion of the pad signal between VSS and the intermediate level VDDL to the low side voltage detector [225. The low side voltage detector 225 determines whether the input signal is higher than the lower threshold voltage V TL As shown in the graph 330 , the output V of the low-side voltage detector 225 OUTL is a square wave that switches when it crosses a lower threshold voltage level.

[0089] Both the high-side voltage detector 220 and the low-side voltage detector 225 are incorporated with a power tracking bias unit 240. The power tracking bias unit is connected to V TH and V TL To compensate for power changes. Figure 7 and Figure 8 Exemplary mechanisms for providing such compensation are discussed in further detail.

[0090] Then the output signal V from each path is OUTH and V OUTL is transmitted to the decision unit 230, which determines the final output V OUT To control. Figure 3 A graphical illustration of such a process is shown in the graph 340. OUTH Pulse and V OUTL The pulses are compared and the output signal V OUT , the signal V OUT Switches from low to high when the input signal crosses the higher threshold voltage and switches from high to low when the input signal crosses the lower threshold voltage. Decision unit 230 may include a set of logic gates or any other components to synthesize the input signal and generate the desired hysteresis window between the lower threshold voltage and the upper threshold voltage.

[0091] Figure 4 4 shows a graphical illustration of a hysteresis window formed according to an embodiment. Graph 400 shows the output voltage V OUT 400 and 405.

[0092] During an example period of signal propagation, the pad signal starts at a minimum value, VSS. This starting point is represented as point 401 in graph 400. As the pad signal moves from VSS to VDD, the voltage initially crosses a lower threshold voltage, V TL The input hysteresis buffer acts so that the output voltage V in graph 400 remains constant even when the input voltage increases. OUT VSS is still maintained through block 410 .

[0093] At block 420, the value of the input voltage continues to increase and crosses the upper threshold voltage V TH As shown in graph 400, when crossing V TH When the output voltage switches to the maximum level (denoted as VDD here), the pad signal remains above V TH For example, point 402 represents the time when the pad signal input is at its maximum value. IN Greater than V TH Here, when the input voltage drops back to the threshold voltage from 402, the output voltage V OUT Keep at VDD.

[0094] At block 430, the pad signal drops below the upper threshold voltage V TH Here, when the pad signal is on the falling edge, the input hysteresis buffer is on the edge of the signal passing through V TH level and close to the lower threshold voltage V TL At 440, the input voltage swings back below V TL , and at this point the output voltage switches back to the VSS level. In this way, the input hysteresis buffer causes the output voltage to switch to the higher threshold voltage V on the rising edge of the input signal. TH And switch to the lower threshold voltage V on the falling edge of the input signal TL This will define V TL With V TH This prevents false switching due to noise or PVT variations.

[0095] Figure 5 is a circuit diagram illustrating a portion of a voltage detector incorporating a power tracking bias unit according to an embodiment. Voltage detector 500 may be a lower threshold voltage detector of the above circuit, configured to detect V in an input signal. TLThe voltage detector can be connected between VSS and the intermediate voltage VDDL. A complementary metal-oxide-semiconductor (CMOS) inverter 510 of the voltage detector 500 receives a signal from the low-side voltage limiter as an input. The detector further includes a compensation component M1 that can provide compensation for PVT changes.

[0096] M1 is a control circuit implemented in series between the power supply voltage VDDL and the CMOS inverter. Figure 5 In the embodiment shown in , M1 includes an n-type metal-oxide-semiconductor (NMOS) transistor whose gate is connected to a voltage supply equal to the maximum pad voltage VDD. Adding this control circuit M1 can compensate for voltage variations of the power supply VDDL and can partially compensate for process and temperature variations. The effect of adding control circuit M1 is shown in Table 520. The table shows how changes in various power supply voltages affect the current (I P ) and the current of the NMOS transistor (I N ) and how these changes affect the lower threshold voltage V TL .

[0097] For example, in the absence of M1, the increase in VDDL due to the voltage change will result in an increase in the current across the transistor in the CMOS and thus a lower threshold voltage V TL However, adding control circuit M1 between VDDL and the PMOS device of the CMOS inverter leads to a corresponding decrease in the current through the PMOS transistor and thus leads to a lower threshold voltage V TL In this way, control circuit M1 can provide compensation for voltage variations. As shown in 520, if the VDDL supply voltage unexpectedly decreases, a similar effect occurs, where control circuit M1 can provide compensation in the opposite direction.

[0098] In addition to providing compensation for variations in the VDDL supply voltage, control circuit M1 also helps compensate for variations in the drive voltage of the NMOS components of the CMOS inverter that are caused by process and temperature variations. For example, a VDDL caused by process or temperature variations that increases the current through the NMOS due to the presence of control circuit M1 may be reduced. TL The increase of V TL compensated by the corresponding decrease in .

[0099] Another feature introduced by including control circuit M1 in the low-side voltage detector is that VTL As shown in the table, by adding M1, V TL An increase occurs in response to any increase in VDD due to PVT variations, and a corresponding decrease occurs in response to any decrease in VDD. This dependency is intentionally introduced to compensate for the DC bias gap between the pad signal and the input hysteresis buffer.

[0100] Figure 6 is a circuit diagram illustrating a portion of a voltage detector incorporating a power tracking bias unit according to an embodiment. Voltage detector 600 may be a higher threshold voltage detector of the above circuit, configured to detect V in an input signal. TH The voltage detector can be connected between the intermediate voltage VSSH and VDD. The complementary metal oxide semiconductor (CMOS) inverter 610 of the voltage detector 600 receives the signal from the low side voltage limiter as input. The detector further includes a compensation element M2 that can provide compensation for PVT changes.

[0101] M2 is a control circuit implemented in series between the power supply voltage VSSH and the CMOS inverter. Figure 6 In the specific embodiment shown in , M2 includes a connected p-type metal-oxide-semiconductor (PMOS) transistor. The gate of the PMOS transistor is connected to a voltage supply equal to the minimum pad voltage VSS. Adding this control circuit M2 can compensate for voltage variations of the power supply VSSH and can locally compensate for process and temperature variations. The effect of adding M2 is shown in Table 620. The table shows how changes in various power supply voltages affect the current (I P ) and the current of the NMOS transistor (I N ) and how these changes affect the higher threshold voltage V TH .

[0102] For example, in the absence of M2, the increase in VDD due to the voltage change will result in an increase in the current across the transistor in the CMOS and thus a higher threshold voltage V TH However, adding control circuit M2 between the VSSH and NMOS components of the CMOS inverter will lead to compensation for such changes by leading to a corresponding decrease in the higher threshold voltage. As shown in 620, a similar effect will occur if the VDD supply voltage unexpectedly decreases, where control circuit M2 can provide compensation in the opposite direction. Table 620 further shows how M2 helps provide compensation for changes in the VSSH voltage.

[0103] In addition to providing compensation for variations in the supply voltage, the control circuit M2 also helps compensate for variations in the drive voltage of the PMOS components of the CMOS inverter, which are caused by process and temperature variations. For example, due to the presence of the control circuit M2, the V TH The reduction is V TH compensated by the corresponding increase of .

[0104] Although the addition of M1 and M2 provides the above-mentioned beneficial effects, the performance of the voltage detector can be further improved by adding additional compensation components and connecting the voltage detector to the control signal supplied by the power tracking bias unit, as shown below for Figures 7 and 8 Explained.

[0105] Figure 7 FIG. 7 is a circuit diagram of a voltage detector with a power tracking bias unit according to an embodiment. The circuit 700 may be a lower threshold voltage detector connected to a power tracking bias unit 715 . Figure 7 The voltage detector in Figure 5 The voltage detector shown is similar, but includes an additional component M3. In an embodiment, M3 is a controlled resistance component connected in series between the CMOS inverter and the minimum voltage VSS. The controlled resistance component M3 may include an NMOS transistor, the gate of which is connected to the control signal from the power tracking bias unit 715. However, the present disclosure is not limited to this. For example, the controlled resistance component M3 can be changed to a voltage controlled resistor. The control signal supplied to M3 by the power tracking bias unit 715 sets the resistance of M3 to increase the compensation for PVT changes and the DC bias gap between the pad DC level and the hysteresis window.

[0106] The effect of adding the controlled resistance element M3 and the power tracking bias unit 715 is shown in Table 720. The power tracking bias circuit can be configured as a voltage divider to supply a specific control signal to M3. Figure 7 In the embodiment shown in FIG. 1 , the series impedance is selected so that the control signal is a portion of VDDL. Therefore, the VDDL caused by the change in VDDL across the low-side voltage detector TL The fluctuation is compensated by the resistance of M3.

[0107] Figure 8 FIG. 8 is a circuit diagram of another voltage detector with a power tracking bias unit according to an embodiment. The circuit 800 may be a higher threshold voltage detector connected to a power tracking bias unit 815 . Figure 8 The voltage detector in Figure 6The voltage detector shown is similar, but includes component M4. In an embodiment, M4 is a controlled resistance component connected in series between the maximum voltage VDD and the CMOS inverter 810. The controlled resistance component M4 may include a PMOS transistor, the gate of which is connected to the control signal from the power tracking bias unit 815. However, the present disclosure is not limited thereto. For example, the controlled resistance component M4 may be changed to a voltage controlled resistor. The control signal applied by the power tracking bias unit 815 sets the resistance of M4 to increase the compensation for PVT changes and the DC bias gap between the pad DC level and the hysteresis window.

[0108] Table 820 summarizes the effect of adding a controlled resistor element M4 to the high-side voltage detector. The power tracking bias circuit can be configured as a voltage divider to supply a specific control signal to M4. Figure 8 In the embodiment shown in FIG. 1 , the series impedance is selected so that the control signal is a function of VDD and VSSH. Therefore, the VDD caused by the change of VDD and VSSH across the low-side voltage detector is TH The fluctuation is compensated by the resistance of M4.

[0109] Fig. 9A A circuit diagram of an overdriven crystal oscillator circuit 900 incorporating a power supply tracking bias unit according to an embodiment is shown. Figure 2 The specific composition of the various units discussed. In the embodiment shown in Figure 9, the crystal oscillator unit includes a driving circuit 901 that outputs a pad signal. The pad signal can then be divided into a first path and a second path by a low-side voltage limiter 915 and a high-side voltage limiter 910. Each voltage limiter includes a group of transistors, and the group of transistors is configured so that the high-side voltage limiter 910 transmits a signal defined between VSSH and VDD, and the low-side voltage limiter 915 transmits a signal defined between VSS and VDDL. These signals can be transmitted to a low-side voltage detector 925 and a high-side voltage detector 920, each of which incorporates a power tracking bias unit 940A / 940B. These components can be used in conjunction with the previous description of Figure 7 and Figure 8 The components discussed are the same.

[0110] The low-side voltage detector 925 is configured to detect when the signal transmitted from the low-side voltage limiter 915 is higher than the lower threshold voltage V TL and when it is below the lower threshold voltage V TL To stabilize this measurement, the low-side voltage detector may include compensation components M1 and M3 and connected to a power tracking bias unit 940A. The power tracking bias unit 940A supplies a signal for controlling the resistance of M3. Figures 5 to 8As discussed in more detail in the tables shown in , by implementing these measures, the circuit can provide compensation for changes in threshold voltage caused by PVT changes. The compensation components and the power tracking bias unit also protect against gaps between the DC level of the input signal and the center of the hysteresis window defined between the threshold voltages. For example, an unforeseen change that increases the level of VDDL will correspondingly reduce the DC level of the pad signal. Using M1, M3 and the power tracking bias unit 940A, V TL In response, the level of is reduced, thereby moving the center of the hysteresis window in that direction and thereby reducing the offset between the DC level and the center of the window. Fig. 9B The table shown in shows these effects in more detail.

[0111] The high-side voltage detector 920 is configured to detect when the signal transmitted from the high-side voltage limiter 910 is higher than the upper threshold voltage V TH and when it is lower than the upper threshold voltage V TH To stabilize this measurement, the high-side voltage detector may include compensation components M2 and M4 and connected to a power tracking bias unit 940B. The power tracking bias unit 940B supplies a signal for controlling the resistance of M4. Figures 5 to 8 As discussed in more detail in the tables shown in , by implementing these measures, the circuit can provide compensation for changes in the threshold voltage caused by PVT changes. The compensation components and the power tracking bias unit also protect against gaps between the DC level of the input signal and the center of the hysteresis window defined between the threshold voltages. For example, an unforeseen change that increases the level of VSSH will cause a corresponding decrease in the DC level of the pad signal. Using M2, M4 and the power tracking bias unit 940B can guide V TH In response, the level of is reduced, thereby moving the center of the hysteresis window in that direction and thereby reducing the offset between the DC level and the center of the window. Fig. 9B The table shown in shows these effects in more detail.

[0112] The voltage detectors 920 and 925 are configured to output a signal V based on whether the input signal is above or below a threshold voltage level. OUTL and V OUTH Then, the decision unit 930 receives V OUTL and V OUTH , the decision unit 930 compares the signals and outputs a final voltage signal V OUT . Output signal V OUT VSS varies between VDD and defines V TL With V TH The hysteresis window between the input signal and V THIt switches from VSS to VDD on the rising edge and when the input signal drops below V TL Switches from VDD to VSS on the falling edge.

[0113] Fig. 9B The embodiment according to the present invention is shown Fig. 9A 975 summarizes some of the effects of the circuit shown. Adding compensation components in the voltage detector and incorporating a power tracking bias unit reduces the offset between the DC bias level of the pad signal and the center of the hysteresis window defined by the lower and upper threshold voltages. Table 975 shows how the fluctuations in the pad DC level and threshold voltage are compensated in the circuit.

[0114] Fig.10 An overdriven crystal oscillator 1000 incorporating a compensation component and a power tracking bias unit according to an embodiment is depicted. In this embodiment, the power tracking bias unit 1040 includes two control signal generators, which include a plurality of transistors. The circuit includes a low-side control signal generator 1042 and a high-side control signal generator 1044, the low-side control signal generator 1042 is configured to supply a signal to a low-side voltage detector 1025 and control the resistance of the compensation component located in the low-side control signal generator 1042, and the high-side control signal generator 1044 is configured to supply a signal to a high-side voltage detector 1020 and control the resistance of the compensation component located in the high-side control signal generator 1044.

[0115] The transistors constituting the low-side control signal generator 1042 are connected between VSS and VDDL. Thus, the signal supplied to the low-side voltage detector 1025 is dependent on the power supplies VSS and VDDL. In the event that PVT variations have an effect on VSS or VDDL, the signal supplied by the low-side control signal generator 1042 can incorporate such fluctuations and compensate accordingly.

[0116] The transistors constituting the high-side control signal generator 1044 are connected between VSSH and VDD. Thus, the signal supplied to the high-side voltage detector 1020 is dependent on the power supplies VSSH and VDDL. In the event that PVT variations have an effect on VSSH or VDDL, the signal supplied by the high-side control signal generator 1044 can incorporate such fluctuations and compensate accordingly.

[0117] like Fig.10 As shown in FIG. 1 , the low-side voltage limiter 1015 and the low-side voltage detector 1025 define a first determination path 1050A for determining whether the pad power supply is higher than the lower threshold voltage V TLThe high-side voltage limiter 1010 and the high-side voltage detector 1020 define a second determination path 1050B for determining whether the pad power supply is higher than the upper threshold voltage V TH The signal based on the determination is transmitted to the decision unit 1030 including the regeneration circuit. The regeneration circuit maintains V TL With V TH The input signal state between the falling edge and maintain V TH With V TL Then, the decision unit 1030 outputs the final signal V OUT Due to the incorporation of compensation components and power tracking bias units, the final output signal V OUT Reduced hysteresis window variation and reduced DC bias level offset relative to the center of the hysteresis window are exhibited.

[0118] Fig.11 1 is a flow chart illustrating a method 1100 for providing an input hysteresis buffer according to various embodiments of the present disclosure. The method starts at step 1105 by generating a pad signal. The pad signal alternates between a lower voltage value and an upper voltage value. For example, the pad signal may be generated by an overdriven crystal oscillator driver and may alternate between VSS and VDD. At step 1110, the pad signal may be divided into several decision paths. For example, the pad signal may be divided into a low threshold voltage decision path and a high threshold voltage decision path by providing a low side voltage limiter and a high side voltage limiter in parallel. The low threshold voltage decision path may include a component connected between a first power supply and a second power supply, and the high threshold voltage decision path may include a component connected between a third power supply and a fourth power supply. For example, the low threshold voltage decision path may be connected between VSS and an intermediate voltage VDDL, and the high threshold voltage decision path may be connected between an intermediate voltage VSSH and VDD.

[0119] Then, at 1115, the signal on each path is supplied to a voltage detector on the path. In an embodiment, the low threshold voltage determination path may include a low-side voltage detector, and a first portion of the input signal may be supplied to the low-side voltage detector. Similarly, the high threshold voltage determination path may include a high-side voltage detector, and a second portion of the input signal may be supplied to the high-side voltage detector.

[0120] At step 1125, a path is determined so that a translated signal is generated by the voltage detector. In order to provide reliable performance and compensation for PVT variations, a control signal is also supplied to the voltage detector within the determination path at step 1115. The voltage detector may include a plurality of compensation components, the plurality of compensation components including a controlled resistance component. The control signal may be supplied by a power tracking bias unit at step 1115. For example, a first power tracking bias unit may supply a first control signal to the first voltage detector, and a second power tracking bias unit may supply a second control signal to the second voltage detector. The first power tracking bias unit is connected between the first power supply and the second power supply, and the second power tracking bias unit is connected between the third power supply and the fourth power supply. As previously described with reference to Figures 7 and 8 As described, the signal generated by each power tracking bias unit can be a function of the power source connected to the power tracking bias unit. The control signal supplied at 1115 is provided to control the resistance of the controlled resistance element of the voltage detector to compensate for changes in the upper threshold voltage and changes in the lower threshold voltage.

[0121] The translated signal generated at step 1125 is a square wave whose value depends on whether the pad signal is higher than one of the threshold voltages. For example, the translated signal on the low threshold voltage determination path has a maximum value when the portion of the pad signal along the path is higher than the low threshold voltage, and has a minimum voltage when the portion of the pad signal along the path is lower than the low threshold voltage. Therefore, the translated signal on the high voltage path has a maximum value when the portion of the pad signal along the high threshold voltage determination path is higher than the high threshold voltage, and has a minimum voltage when the portion of the pad signal along the path is lower than the high threshold voltage.

[0122] At step 1130, an output voltage signal is generated based on the translated signal. For example, the translated signal on each decision path is output to a decision unit. The decision unit can use a logic gate or any other component to compare and evaluate the translated signal. The decision unit is configured so that the output voltage signal defines a hysteresis between a low threshold voltage signal and a high threshold voltage signal. In this way, the output voltage signal switches from low to high when the input voltage from the pad signal rises above the high threshold voltage and switches from high to low when the input voltage from the pad signal drops below the low threshold voltage. The generated output signal has sharp edges and low phase noise and can be transmitted to other devices in the circuit design with high reliability.

[0123] Circuits and methods are described herein. In one example, a circuit includes a voltage limiting unit, a voltage detection unit connected to the voltage limiting unit, and a power tracking bias unit connected to the voltage detection unit. The voltage limiting unit includes a first voltage limiting unit and a second voltage limiting unit connected in parallel, and the voltage limiting unit is configured to split an input signal into a first path through the first voltage limiter and a second path through the second voltage limiter. The first voltage limiter is configured to be connected to a first power supply and a second power supply and is configured to output a first modified signal, the first modified signal varies between a first minimum voltage corresponding to the first power supply and a first maximum voltage corresponding to the second power supply, and there is a first threshold voltage between the first minimum voltage and the first maximum voltage. The second voltage limiter is configured to be connected to a third power supply and a fourth power supply and is configured to output a second modified signal, the second modified signal varies between a second minimum voltage corresponding to the third power supply and a second maximum voltage corresponding to the fourth power supply, and there is a second threshold voltage between the second minimum voltage and the second maximum voltage. The voltage detection unit includes a first voltage detection unit configured to detect the presence of the first threshold voltage in the first modified signal and a second voltage detection unit configured to detect the presence of the second threshold voltage in the second modified signal. The power tracking bias unit includes a first unit connected to the first voltage detector and a second unit connected to the second voltage detector, wherein the first unit is configured to supply a first control signal to the first voltage detector, the first control signal changes in response to a change in the first power supply or a change in the second power supply, and the second unit is configured to supply a second control signal to the second voltage detector, the second control signal changes in response to a change in the third power supply or a change in the fourth power supply.

[0124] In another example, a circuit for an oscillator includes an oscillator driver configured to output a pad signal. The circuit further includes a higher threshold voltage determination unit and a lower threshold voltage determination unit, the higher threshold voltage determination unit is configured to receive the pad signal and generate a first determination output, and the lower threshold voltage determination unit is configured to receive the pad signal and generate a second determination output. A power tracking bias unit is included and the power tracking bias unit is configured to supply a first control signal to the higher threshold voltage determination unit and a second control signal to the lower threshold voltage determination unit, the first control signal is configured to compensate for changes in the higher threshold voltage, and the second control signal is configured to compensate for changes in the lower threshold voltage. The first determination output and the second determination output are received by a decision unit, and the decision unit is configured to deliver an output signal based on the first determination output and the second determination output.

[0125] In an exemplary method of providing an input hysteresis buffer, a pad signal that varies between a minimum voltage and a maximum voltage is generated. The pad signal is split into a first determination path and a second determination path, wherein the first determination path supplies a first portion of the pad signal to a first voltage detector, and the second determination path supplies a second portion of the pad signal to a second voltage detector. The first voltage detector is connected between a first power supply and a second power supply, and the second voltage detector is connected between a third power supply and a fourth power supply. A first control signal is supplied to the first voltage detector and a second control signal is supplied to the second voltage detector. The first control signal is a function of the first power supply and the second power supply and is generated by a first power supply tracking bias unit. The second control signal is a function of the third power supply and the fourth power supply and is generated by a second power supply tracking bias unit. A first translated signal is generated by the first voltage detector, wherein the first translated signal has a low value when the first portion of the pad signal is below a first threshold voltage level and has a high value when the first portion of the pad signal is above the first threshold voltage level. A second translated signal is generated by the second voltage detector, wherein the second translated signal has a low value when the second portion of the pad signal is below a second threshold voltage level and has a high value when the second portion of the pad signal is above the second threshold voltage level. An output voltage signal is generated based on the first translated signal and the second translated signal, such that the output voltage signal defines a hysteresis window between the first threshold voltage level and the second threshold voltage level.

[0126] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the scope of the present disclosure.

Claims

1. A circuit, characterized in that: include: A voltage limiting unit, comprising a first voltage limiter and a second voltage limiter connected in parallel, wherein the voltage limiting unit is configured to split an input signal into a first path via the first voltage limiter and a second path via the second voltage limiter, wherein: The first voltage limiter is configured to be connected to a first power supply and a second power supply and configured to output a first modified signal, the first modified signal varies between a first minimum voltage corresponding to the first power supply and a first maximum voltage corresponding to the second power supply, and there is a first threshold voltage between the first minimum voltage and the first maximum voltage, and The second voltage limiter is configured to be connected to a third power supply and a fourth power supply and configured to output a second modified signal, wherein the second modified signal varies between a second minimum voltage corresponding to the third power supply and a second maximum voltage corresponding to the fourth power supply, and a second threshold voltage exists between the second minimum voltage and the second maximum voltage; a voltage detection unit connected to the voltage limiting unit, the voltage detection unit comprising a first voltage detector and a second voltage detector, the first voltage detector being connected to the first voltage limiter and configured to detect the first threshold voltage in the first modified signal, the second voltage detector being connected to the second voltage limiter and configured to detect the second threshold voltage in the second modified signal; and a power tracking bias unit connected to the voltage detection unit, the power tracking bias unit comprising a first unit connected to the first voltage detector and a second unit connected to the second voltage detector, wherein the first unit is configured to supply a first control signal to the first voltage detector, the first control signal changes in response to a change of the first power supply or a change of the second power supply, and the second unit is configured to supply a second control signal to the second voltage detector, the second control signal changes in response to a change of the third power supply or a change of the fourth power supply.

2. The circuit according to claim 1, wherein the first voltage detector comprises: a first complementary metal oxide semiconductor (CMOS) inverter and a first plurality of compensation elements; and The second voltage detector includes a second complementary metal oxide semiconductor inverter and a second plurality of compensation components.

3. The circuit of claim 2, wherein the first plurality of compensation components comprises: A first transistor connected between the first power source and the first complementary metal oxide semiconductor inverter; as well as The controlled resistance component is connected between the first complementary metal oxide semiconductor inverter and the second power supply. 4 . The circuit of claim 3 , wherein the controlled resistance component comprises a second transistor, a resistance of the second transistor being controlled by the first unit.

5. The circuit of claim 4, wherein the first unit is connected to a gate of the second transistor.

6. The circuit of claim 2, wherein the second voltage detector comprises: A first transistor connected between the third power source and the second complementary metal oxide semiconductor inverter; as well as The controlled resistance component is connected between the second complementary metal oxide semiconductor inverter and the fourth power supply.

7. A circuit for an oscillator, characterized in that include: an oscillator driver configured to output a pad signal; a higher threshold voltage determination unit configured to receive the pad signal and generate a first determination output; a lower threshold voltage determination unit configured to receive the pad signal and generate a second determination output; A power tracking bias unit, configured to supply a first control signal to the higher threshold voltage determination unit and a second control signal to the lower threshold voltage determination unit, wherein the first control signal is configured to compensate for a change in the higher threshold voltage, and the second control signal is configured to compensate for a change in the lower threshold voltage; as well as A decision unit is configured to deliver an output signal based on the first decision output and the second decision output.

8. The circuit of claim 7, wherein the oscillator driver comprises a self-biased buffer with a non-rail-to-rail signal.

9. The circuit of claim 7, wherein the decision unit comprises a regeneration circuit.

10. A circuit for an oscillator, characterized in that include: a higher threshold voltage determination unit configured to receive a pad signal from an oscillator driver and generate a first determination output; a lower threshold voltage determination unit configured to receive the pad signal and generate a second determination output; A power tracking bias unit, configured to supply a first control signal to the higher threshold voltage determination unit and a second control signal to the lower threshold voltage determination unit, wherein the first control signal is configured to compensate for a change in the higher threshold voltage, and the second control signal is configured to compensate for a change in the lower threshold voltage; as well as A decision unit is configured to deliver an output signal based on the first decision output and the second decision output.

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