Filter wafer ESD protection circuit
By setting conductive metal lines and cutting anti-bias circuits in the filter wafer ESD protection circuit, the grounding module interconnection between multiple wafer layers is solved, and the chip damage caused by wafer charge aggregation is significantly reduced. The risk of ESD is significantly reduced , improves yield and processing reliability.
Patent Information
- Application Number
- CN202420820129.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-19
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2034-04-19
AI Technical Summary
When manufacturing filter wafers in traditional processes, the wafer is prone to charge accumulation, resulting in damage to the internal circuit of the chip, resulting in a decrease in the wafer processing yield.
A filter wafer ESD protection circuit is designed, and the grounding modules between the wafer layers are interconnected and shared electrostatic voltages are shared by setting conductive metal lines, connecting leads and cutting anti-biasing lines between the wafer layers.
Effectively share the electrostatic voltage generated during wafer manufacturing, transportation, storage, testing and packaging, significantly reduce the ESD risk during filter wafer processing, and improve product yield and processing reliability after processing.
Smart Images
Figure CN222464155U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of wafer ESD protection, in particular to a filter wafer ESD protection circuit. Background Art
[0002] ESD means "electrostatic discharge". ESD is a discipline that has been formed since the mid-20th century to study the generation, hazards and electrostatic protection of static electricity. Therefore, it is customary internationally to refer to equipment used for electrostatic protection as ESD.
[0003] Charge accumulation is easy to occur on wafers during the production and processing process, which can easily lead to ESD damage to the wafer. Electrostatic discharge can damage the internal circuit of the chip, causing the chip to fail to work properly or even be damaged. ESD may break through the internal circuit of the chip, thereby affecting the performance of the chip.
[0004] In view of this, it is particularly important to design and manufacture an ESD protection circuit that can effectively disperse electrostatic voltage and reduce circuit damage during wafer processing during filter wafer processing. Utility Model Content
[0005] The utility model aims to propose a filter wafer ESD protection circuit to solve the problem that when filter wafers are manufactured by traditional processes, charge accumulation on the wafers may cause damage to the internal circuit of the chip, resulting in a decrease in the wafer processing yield.
[0006] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0007] A filter wafer ESD protection circuit comprises a wafer layer, a signal input module arranged at the upper left corner of the wafer layer, a first grounding module arranged at the upper right corner of the wafer layer, a second grounding module arranged at the lower left corner of the wafer layer, a signal output module arranged at the lower right corner of the wafer layer, a first metal layer arranged between the signal input module and the first grounding module, a second metal layer arranged between the second grounding module and the signal output module, and an interdigital circuit staggered between the first metal layer and the second metal layer, wherein the wafer layer is arranged in a rectangular array with a plurality of wafer layers, the plurality of wafer layers are not in contact with each other to form a cutting channel, and a conductive metal line is arranged between the plurality of wafer layers and the cutting channel for interconnecting the grounding modules between the plurality of wafer layers to share the electrostatic voltage.
[0008] As a further description of the above technical solution:
[0009] The conductive metal circuit is composed of a plurality of metal line segments which are distributed in a staggered manner horizontally and vertically.
[0010] As a further description of the above technical solution:
[0011] The conductive metal circuit is composed of a plurality of metal line segments distributed in parallel in the transverse direction.
[0012] As a further description of the above technical solution:
[0013] The conductive metal circuit is composed of a plurality of metal line segments distributed in parallel in the longitudinal direction.
[0014] As a further description of the above technical solution:
[0015] The conductive metal circuit is connected to the first grounding module and the second grounding module through connecting leads, and cutting anti-deflection circuits are provided at the connection between the conductive metal circuit and the first grounding module and at the connection between the conductive metal circuit and the second grounding module.
[0016] As a further description of the above technical solution:
[0017] The cutting anti-deviation circuit is a wave-shaped structure.
[0018] As a further description of the above technical solution:
[0019] The first metal layer, the second metal layer and the interdigital circuit are all made by sputtering titanium, chromium or nickel metal materials, and the signal input module, the first grounding module, the second grounding module, the signal output module, the conductive metal circuit, the connecting leads and the cutting anti-deflection circuit are all made by sputtering aluminum, copper or silver metal materials.
[0020] In summary, due to the adoption of the above technical solution, the beneficial effects of the utility model are:
[0021] In the utility model, by scientifically and rationally improving the original wafer processing method, a conductive metal circuit, a connecting lead and a cutting anti-skew circuit are formed in the cutting channel in the secondary sputtering process, thereby realizing the interconnection between the grounding modules of multiple wafers, effectively sharing the electrostatic voltage generated during wafer manufacturing, transportation, storage, testing and packaging, and significantly reducing the ESD risk in the filter wafer processing process, thereby improving the product yield and processing reliability after processing. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Schematic diagram of the filter wafer ESD protection circuit in Example 1;
[0023] Figure 2 for Figure 1 A local enlarged schematic diagram of the middle A;
[0024] Figure 3 Schematic diagram of the filter wafer ESD protection circuit in Example 2;
[0025] Figure 4 Schematic diagram of the filter wafer ESD protection circuit in Example 3.
[0026] Legend:
[0027] 1. Wafer layer; 101. Signal input module; 102. First grounding module; 103. Second grounding module; 104. Signal output module; 105. First metal layer; 106. Second metal layer; 107. Interdigital circuit; 2. Conductive metal line; 3. Connecting lead; 4. Cutting anti-deflection line. DETAILED DESCRIPTION
[0028] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0029] See also Figure 1-4 The utility model provides a technical solution: a filter wafer ESD protection circuit, comprising a wafer layer 1, a signal input module 101 arranged at the upper left corner of the wafer layer 1, a first grounding module 102 arranged at the upper right corner of the wafer layer 1, a second grounding module 103 arranged at the lower left corner of the wafer layer 1, a signal output module 104 arranged at the lower right corner of the wafer layer 1, a first metal layer 105 arranged between the signal input module 101 and the first grounding module 102, a second metal layer 106 arranged between the second grounding module 103 and the signal output module 104, and an interdigital circuit 107 staggered between the first metal layer 105 and the second metal layer 106, the wafer layer 1 is provided with a plurality of wafers in a rectangular array, the plurality of wafer layers 1 do not contact each other to form a cutting channel, and a conductive metal line 2 is provided between the plurality of wafer layers 1 and the cutting channel for interconnecting the grounding modules between the plurality of wafer layers 1 to share the electrostatic voltage.
[0030] Example 1
[0031] Specifically, Figure 1 and 2As shown, the conductive metal circuit 2 is composed of a plurality of metal wire segments that are distributed in a staggered manner horizontally and vertically. Such a conductive metal circuit 2 is difficult to design and process, but it can stably interconnect the electrical circuits between a plurality of wafer layers 1 and can quickly disperse the electrostatic voltage. The conductive metal circuit 2 and the first grounding module 102 and the second grounding module 103 are respectively connected to each other through the connecting lead 3. The connection between the conductive metal circuit 2 and the first grounding module 102 and the connection between the conductive metal circuit 2 and the second grounding module 103 are both provided with a cutting anti-deflection circuit 4. At the same time, the cutting anti-deflection circuit 4 is a wavy structure. The setting of this structure, on the one hand, can make the cutting deviation range of the conductive metal circuit 2 larger, and can effectively prevent the grounding circuit from continuing to be turned on during the cutting process between the wafer layers 1. On the other hand, it can also effectively reduce the design accuracy of wafer cutting, save wafer processing costs, and improve the yield and stability of filter wafer processing.
[0032] Example 2
[0033] Specifically, Figure 3 As shown, the metal circuit 2 is composed of a plurality of metal line segments distributed in parallel laterally. Compared with the conductive metal circuit 2 in Example 1, the design difficulty and processing difficulty of such a conductive metal circuit 2 are lower. However, due to the small number of connection nodes, the rate and effect of dispersing the electrostatic voltage are lower than those of the conductive metal circuit 2 in Example 1. The conductive metal circuit 2 is connected to the first grounding module 102 and the second grounding module 103 through the connecting lead 3 respectively. The connection between the conductive metal circuit 2 and the first grounding module 102 and the connection between the conductive metal circuit 2 and the second grounding module 103 are both provided with a cutting anti-deflection circuit 4. At the same time, the cutting anti-deflection circuit 4 is a wavy structure. On the one hand, the cutting deviation range of the conductive metal circuit 2 can be made larger, which can effectively prevent the grounding circuit from continuing to be turned on during the cutting process between the wafer layers 1. On the other hand, it can also effectively reduce the design accuracy of wafer cutting, save wafer processing costs, and improve the yield and stability of filter wafer processing.
[0034] Example 3
[0035] Specifically, Figure 4As shown, the conductive metal circuit 2 is composed of a plurality of metal wire segments distributed in parallel in the longitudinal direction. Compared with the conductive metal circuit 2 in Example 1, the design difficulty and processing difficulty of such a conductive metal circuit 2 are lower, and are roughly the same as the conductive metal circuit 2 in Example 2. However, due to the small number of connection nodes, the rate and effect of dispersing the electrostatic voltage are lower than those of the conductive metal circuit 2 in Example 1. The conductive metal circuit 2 and the first grounding module 102 and the second grounding module 103 are respectively connected by connecting leads 3. The connection between the conductive metal circuit 2 and the first grounding module 102 and the connection between the conductive metal circuit 2 and the second grounding module 103 are both provided with cutting anti-deflection circuits 4. At the same time, the cutting anti-deflection circuit 4 is a wavy structure. On the one hand, the cutting deviation range of the conductive metal circuit 2 can be made larger, which can effectively prevent the grounding circuit from continuing to be turned on during the cutting process between the wafer layers 1. On the other hand, it can also effectively reduce the design accuracy of wafer cutting, save wafer processing costs, and improve the yield and stability of filter wafer processing.
[0036] Specifically, a filter wafer ESD protection method includes the following steps:
[0037] Step 1: Glue coating: Heat the wafer on a hot plate for a few minutes to remove moisture from the surface of the wafer. The heating temperature is set to 150-200°C and the heating time is set to 2-3 minutes. Apply photoresist on the wafer by spin coating. The best spin coating speed is 250-4000rpm.
[0038] Step 2, pre-bake: pre-bake or soft-bake volatilizes the organic solvent in the photoresist through temperature, so that the glue on the surface of the wafer is solidified. The pre-bake temperature is set to 90-100℃, and the pre-bake time is set to 15-25min. In this process, the glue film will be further dried and solidified, which can improve the adhesion between the photoresist and the substrate and reduce the occurrence of dark corrosion during the development process. At the same time, pre-bake can be carried out on a hot plate device or in an oven. The temperature and time of pre-bake are set scientifically and rationally according to the characteristics of each glue.
[0039] Step 3, exposure: exposing the photoresist on the wafer on an exposure machine, and defining the photoresist pattern to be left or removed according to the conductive metal circuit 2 to be formed;
[0040] Step 4, post-baking: The photoacid generated in the exposure step is used to cross-link the polymer during the cross-linking baking. The temperature is set at 90-100°C, and the specific baking time is controlled according to the diffusion of the photoactive substance in the photoresist, so as to eliminate the standing wave effect.
[0041] Step 5. Development: Send the exposed wafer to the developer for development to remove the photoresist on the wafer. The temperature is kept within the range of 21-23℃ with an error of ±0.5℃. The wafer can be developed by immersion, spray or stirring development methods.
[0042] S600, primary sputtering: sputtering a seed layer on the wafer layer 1, selecting titanium, chromium or nickel metal material as a sputtering object, forming a first metal layer 105, a second metal layer 106 and an interdigital circuit 107 at corresponding positions of the wafer layer 1, and the total sputtering thickness is less than 5000A;
[0043] S700, secondary sputtering: sputtering a metal layer on the wafer layer 1, using aluminum, copper or silver metal materials as sputtering objects, forming a signal input module 101, a first grounding module 102, a second grounding module 103, a signal output module 104, a conductive metal line 2, a connecting lead 3 and a cutting anti-deflection line 4 at corresponding positions of the wafer layer 1, and the total sputtering thickness is less than 5000A;
[0044] S800, stripping: using a stripping solution to dissolve the photoresist or mechanically removing the metal hard mask to obtain a target graphic structure consistent with the pattern of the conductive metal circuit 2.
[0045] To sum up, through the above-mentioned protection method, conductive metal circuits 2, connecting leads 3 and cutting anti-deviation circuits 4 can be formed in the cutting channels of multiple wafer layers 1, thereby realizing the interconnection between the grounding modules between multiple wafer layers 1, and being able to effectively share the electrostatic voltage generated during the subsequent cutting, transportation, storage, testing and packaging of the wafer, thereby significantly reducing the ESD risk during the filter wafer processing.
[0046] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the technical scope disclosed by the present invention according to the technical scheme and the utility model concept of the present invention, which should be covered by the protection scope of the present invention.
Claims
1. A filter wafer ESD protection circuit, comprising a wafer layer (1), a signal input module (101) arranged at the upper left corner of the wafer layer (1), a first grounding module (102) arranged at the upper right corner of the wafer layer (1), a second grounding module (103) arranged at the lower left corner of the wafer layer (1), a signal output module (104) arranged at the lower right corner of the wafer layer (1), a first metal layer (105) arranged between the signal input module (101) and the first grounding module (102), a second metal layer (106) arranged between the second grounding module (103) and the signal output module (104), and an interdigital circuit (107) interlaced between the first metal layer (105) and the second metal layer (106), characterized in that: The wafer layers (1) are arranged in a rectangular array and are multiple; the multiple wafer layers (1) are not in contact with each other to form a cutting channel; and a conductive metal line (2) is arranged between the multiple wafer layers (1) and the cutting channel for interconnecting the grounding modules between the multiple wafer layers (1) to share the electrostatic voltage.
2. A filter wafer ESD protection circuit according to claim 1, characterized in that: The conductive metal circuit (2) is composed of a plurality of metal line segments that are distributed in a staggered manner horizontally and vertically.
3. A filter wafer ESD protection circuit according to claim 1 or 2, characterized in that: The conductive metal line (2) is composed of a plurality of metal line segments distributed in parallel in the transverse direction.
4. A filter wafer ESD protection circuit according to claim 1 or 2, characterized in that: The conductive metal line (2) is composed of a plurality of metal line segments distributed in parallel in the longitudinal direction.
5. The filter wafer ESD protection circuit according to claim 1, characterized in that: The conductive metal line (2) is connected to the first grounding module (102) and the second grounding module (103) through a connecting lead (3), and a cutting anti-deflection circuit (4) is provided at the connection point between the conductive metal line (2) and the first grounding module (102) and the connection point between the conductive metal line (2) and the second grounding module (103).
6. The filter wafer ESD protection circuit according to claim 5, characterized in that: The cutting anti-deviation circuit (4) is a wave-shaped structure.
7. The filter wafer ESD protection circuit according to claim 1, characterized in that: The first metal layer (105), the second metal layer (106) and the interdigital circuit (107) are all made by sputtering titanium, chromium or nickel metal materials, and the signal input module (101), the first grounding module (102), the second grounding module (103), the signal output module (104), the conductive metal circuit (2), the connecting lead (3) and the cutting anti-deflection circuit (4) are all made by sputtering aluminum, copper or silver metal materials.