Semiconductor device structure

Abstract

The embodiment of the utility model provides a semiconductor device structure. The semiconductor device structure comprises capacitor switch assemblies which are located on a substrate and connected in parallel. The capacitor switch assembly includes a first capacitor switch assembly including a first series connected first capacitor and a first non-ohmic switching device having a first threshold voltage and including first primary and first secondary switch electrodes and a first non-ohmic switching material portion. The capacitor switch assembly includes a second capacitor switch assembly including a second series-connected second capacitor and a second non-ohmic switching device having a second threshold voltage different from the first threshold voltage and including second primary and second secondary switch electrodes and a second non-ohmic switching material portion. The non-ohmic switching device is conditionally switched on as a function of the extent of the applied voltage spike.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor device structure, and more particularly to a semiconductor device structure providing a capacitor circuit with self-adjusting capacitance. Background Art

[0002] Decoupling capacitors are used to optimize the performance of some semiconductor circuits. Generally speaking, an optimal value of the decoupling capacitor provides the best performance of such a semiconductor circuit. Although a large capacitance tends to provide some margin for device performance variations of semiconductor devices in a semiconductor circuit, an excessively large capacitance may degrade device performance. Utility Model Content

[0003] An embodiment of the utility model provides a semiconductor device structure including a plurality of capacitor switch assemblies connected in parallel and located on a substrate. The plurality of capacitor switch assemblies connected in parallel include a first capacitor switch assembly and a second capacitor switch assembly. The first capacitor switch assembly includes a first capacitor connected in series and a first non-ohmic switch device, the first non-ohmic switch device having a first threshold voltage and including a first primary switch electrode, a first secondary switch electrode, and a first non-ohmic switch material portion in contact with the first primary switch electrode and the first secondary switch electrode. The second capacitor switch assembly includes a second capacitor connected in series and a second non-ohmic switch device, the second non-ohmic switch device having a second threshold voltage and including a second primary switch electrode, a second secondary switch electrode, and a second non-ohmic switch material portion in contact with the second primary switch electrode and the second secondary switch electrode. The second threshold voltage is different from the first threshold voltage.

[0004] An embodiment of the utility model provides a semiconductor device structure including a semiconductor device located on the top surface of a semiconductor substrate, a plurality of first dielectric material layers located above the semiconductor device, a first metal interconnect structure located in the plurality of first dielectric material layers and electrically connected to a corresponding one of the semiconductor devices, and a capacitor circuit located above the plurality of first dielectric material layers and including a plurality of capacitor switch assemblies connected in parallel. The plurality of capacitor switch assemblies connected in parallel include a first capacitor switch assembly and a second capacitor switch assembly. The first capacitor switch assembly includes a first first capacitor connected in series and a first non-ohmic switch device, the first non-ohmic switch device having a first threshold voltage and including a first primary switch electrode, a first secondary switch electrode, and a first non-ohmic switch material portion in contact with the first primary switch electrode and the first secondary switch electrode. The second capacitor switch assembly includes a second second capacitor connected in series and a second non-ohmic switch device, the second non-ohmic switch device having a second threshold voltage and including a second primary switch electrode, a second secondary switch electrode, and a second non-ohmic switch material portion in contact with the second primary switch electrode and the second secondary switch electrode. The second threshold voltage is different from the first threshold voltage.

[0005] Based on the above, embodiments of the present invention can be used to provide a capacitor circuit that provides a capacitance at a predetermined capacitance level without using any actively controlled switch. The non-ohmic switching device of the embodiment of the present invention is passive, that is, it does not utilize any other semiconductor device to perform a switch-on operation or a switch-off operation. The passive non-ohmic switching device is turned on sequentially as the degree of the transient voltage spike increases. The increase in the capacitance of the capacitor circuit of the embodiment of the present invention reduces the degree of the subsequent transient voltage spike. After several rounds of passive switching on and passive switching off, the capacitor circuit can operate in a steady-state mode in which the capacitance is at an optimal level. Therefore, an appropriate level of capacitance can be provided while avoiding excessive capacitance without using any active switching device.

[0006] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a vertical cross-sectional view of a first structure after formation of a complementary metal-oxide-semiconductor (CMOS) transistor, metal interconnect structures and dielectric material layers, an optional dielectric cap layer, and a bottom via level dielectric layer according to an embodiment of the present disclosure.

[0008] FIG. 2A to FIG. 2Fare sequential vertical cross-sectional views of a first structure during formation of a device structure according to an embodiment of the present disclosure.

[0009] Figure 2G is a vertical cross-sectional view of an alternative embodiment of the first structure according to the disclosed embodiment.

[0010] FIG. 3A to FIG. 3C are sequential vertical cross-sectional views of a second structure during formation of a device structure according to an embodiment of the present disclosure.

[0011] Figure 3D is a vertical cross-sectional view of an alternative embodiment of the second structure according to the disclosed embodiment.

[0012] FIG. 4A to FIG. 4D are sequential vertical cross-sectional views of a third structure during formation of a device structure according to an embodiment of the present disclosure.

[0013] Figure 4E is a vertical cross-sectional view of an alternative embodiment of the third structure according to the disclosed embodiment.

[0014] Figure 5A is a schematic circuit diagram of a first capacitor circuit according to an embodiment of the present disclosure.

[0015] Figure 5B is a schematic circuit diagram of a second capacitor circuit according to an embodiment of the present disclosure.

[0016] Figure 6 is a graph showing the current-voltage characteristics of the non-ohmic switching device of the present disclosure.

[0017] Fig. 7A is a schematic energy band diagram of the non-ohmic switch device of the present disclosure in an off state.

[0018] Figure 7B is a schematic energy band diagram of the non-ohmic switch device of the present disclosure in an on state.

[0019] Figure 8 is a flow chart illustrating general processing steps for fabricating a device structure according to an embodiment of the present disclosure.

[0020] Description of Reference Numerals

[0021] 8: substrate; 9: semiconductor material layer; 12: non-ohmic switch material portion / first non-ohmic switch device / first non-ohmic switch material portion / second non-ohmic switch device / second non-ohmic switch material portion / third non-ohmic switch device / third non-ohmic switch material portion / additional non-ohmic switch device / non-ohmic switch device; 21: dielectric cap layer; 22: bottom capacitor contact via structure; 23: bottom via level dielectric layer; 30: capacitor; 30A, C1: first capacitor; 30B, C2: second capacitor; 30C, C3: third capacitor; 30D, C4: fourth capacitor / additional capacitor; 32: lower capacitor electrode plate; 32L: lower capacitor electrode layer; 34: node Point dielectric; 34L: node dielectric layer; 36: upper capacitor electrode plate; 36L: upper capacitor electrode layer; 37: capacitor level dielectric layer; 42: top capacitor contact through-hole structure / first top capacitor contact through-hole structure / second top capacitor contact through-hole structure / third top capacitor contact through-hole structure; 46, 56: secondary switch electrode / first secondary switch electrode / second secondary switch electrode / third secondary switch electrode / first non-ohmic switch device / second non-ohmic switch device / third non-ohmic switch device / additional non-ohmic switch device / non-ohmic switch device; 47: upper connection level dielectric layer; 48: primary switch electrode / first primary switch electrode / second primary switch electrode / third primary switch Electrode / first non-ohmic switch device / second non-ohmic switch device / third non-ohmic switch device / additional non-ohmic switch device / non-ohmic switch device; 51: through-hole level dielectric material layer; 53: line level dielectric material layer; 60: capacitor switch assembly; 60A: first capacitor switch assembly; 60B: second capacitor switch assembly; 60C: third capacitor switch assembly; 148A: first plate structure / plate structure; 148B: second plate structure / plate structure; 148C: third plate structure / plate structure; 148L: non-ohmic switch material layer; 152A, 248A: first non-ohmic switch material through-hole structure / non-ohmic switch material through-hole structure; 152B, 248B: second non-ohmic switch material through-hole structure Hole structure / non-ohmic switch material through-hole structure; 152C, 248C: third non-ohmic switch material through-hole structure / non-ohmic switch material through-hole structure; 159, 249: through-hole cavity; 159A: first through-hole cavity; 159B: second through-hole cavity; 159C: third through-hole cavity; 247: photoresist layer; 601: first dielectric material layer / contact level dielectric material layer / dielectric material layer / lower level dielectric material layer; 610: first internal wiring level dielectric material layer / dielectric material layer / lower level dielectric material layer / first dielectric material layer; 612: device contact through-hole structure / metal internal wiring structure / first metal internal wiring structure; 618: first wire structure / metal internal wiring structure / first metal internal wiring structure;620: second interconnect level dielectric material layer / dielectric material layer / lower level dielectric material layer / first dielectric material layer; 622: first conductive hole structure / metal interconnect structure / conductive hole structure / first metal interconnect structure; 628: second conductive line structure / metal interconnect structure / conductive line structure / first metal interconnect structure; 630: third interconnect level dielectric material layer / dielectric material layer / lower level dielectric material layer / first dielectric material layer; 632: second conductive hole structure / metal interconnect structure / conductive hole structure 638: third conductor structure / metal interconnect structure / conductor structure / first metal interconnect structure; 640: fourth interconnect level dielectric material layer / dielectric material layer / lower level dielectric material layer / first dielectric material layer 642: third via structure / metal interconnect structure / via structure / first metal interconnect structure 648: fourth conductor structure / metal interconnect structure / conductor structure / first metal interconnect structure; 650: fifth interconnect level dielectric material layer / dielectric material layer 658: fifth conductor structure; 660: sixth interconnect level dielectric material layer / dielectric material layer / second dielectric material layer; 662: fifth via structure; 668: sixth conductor structure; 670: seventh interconnect level dielectric material layer; 672: sixth via structure; 678: seventh conductor structure; 700: CMOS circuit; 701: semiconductor device; 720: shallow trench isolation structure; 732: source electrode; 735: semiconductor channel; 738: drain electrode; 742: source side metal semiconductor alloy region; 748: drain side metal semiconductor alloy region; 750: gate structure; 752: gate dielectric layer; 754: gate electrode; 756: dielectric gate spacer; 758: gate cap dielectric; 810, 820, 830: steps; AN1: first assembly node; AN2: second assembly node; S1: first switch / switch; S2: second switch / switch; S3: third switch / switch; V_th1, V_th2, V_th3: threshold voltage. ; DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clearly describing the present disclosure, rather than for defining the relationship between various embodiments and / or configurations.

[0023] In addition, for ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature shown in a figure to another (other) component or feature. In addition to the orientation shown in the figure, the spatially relative terms also cover different orientations of the device in use or operation. The device can have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used therein can also be interpreted in the same manner. Components with the same reference number refer to the same component and are assumed to have the same material composition and the same thickness range unless otherwise expressly stated.

[0024] Embodiments of the utility model relate to a capacitor circuit that provides self-adjusting capacitance and a method for forming the same. An optimal value is selected for the capacitance of the decoupling capacitor in order to provide an optimal level of decoupling capacitance. Excessive or insufficient values ​​of the decoupling capacitance may adversely affect the performance of the semiconductor circuit. Inherent wafer-to-wafer variation and within-wafer variation of the process parameters of the capacitor circuit may cause the decoupling capacitance to vary. These process parameters may include, but are not limited to, the thickness and material composition of various films used to form the decoupling capacitor.

[0025] According to aspects of the present disclosure, a plurality of corresponding capacitors connected in series and corresponding switching units connected in parallel may be provided as a capacitor circuit. The switching unit includes a voltage-activated non-Ohmic switching material, such as a phase change material or an ovonic threshold switch material that switches on at a corresponding threshold voltage (also referred to as a turn-on voltage). According to aspects of the present disclosure, the switching units are designed so that the threshold voltages are different from each other. In embodiments in which a voltage spike exceeding the corresponding threshold voltage is caused in any of the switching units due to insufficient capacitance of the capacitor circuit, at least one of the switching units in which the voltage spike exceeds the corresponding threshold voltage may be turned on, thereby increasing the total capacitance of the capacitor circuit. The capacitance and threshold voltage of each series connection of the capacitor and the switching unit may be selected so that a higher voltage spike switches on more switching units. As the total capacitance of the capacitor circuit increases, the extent of the voltage spike decreases, so that the total capacitance of the capacitor circuit converges to a value close to a predetermined value. Therefore, the total capacitance of the capacitor circuit can be self-tailored to a value close to the target value by using the capacitor circuit of the present disclosure without using any measuring circuit or any programming circuit. Various embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0026] Reference Figure 1 , showing an exemplary structure according to a first embodiment of the present disclosure. The exemplary structure includes a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at least at an upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single crystal semiconductor material, such as single crystal silicon. In one embodiment, the substrate 8 may include a single crystal silicon substrate including a single crystal silicon material.

[0027] A shallow trench isolation structure 720 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer 9. A suitable doped semiconductor well, such as a p-type well and an n-type well, may be formed in each region laterally enclosed by a portion of the shallow trench isolation structure 720. A semiconductor device 701 such as a field effect transistor may be formed on the top surface of the semiconductor material layer 9. For example, each field effect transistor may include: a source electrode 732, a drain electrode 738, a semiconductor channel 735 including a surface portion of the substrate 8 extending between the source electrode 732 and the drain electrode 738, and a gate structure 750. The semiconductor channel 735 may include a single crystalline semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal semiconductor alloy region 742 may be formed on each source electrode 732, and a drain-side metal semiconductor alloy region 748 may be formed on each drain electrode 738. The devices formed on the top surface of the semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (such as resistors, diodes, capacitor circuits, etc.), and are collectively referred to as CMOS circuits 700.

[0028] One or more of the field effect transistors in the CMOS circuit 700 may include a semiconductor channel 735, which includes a portion of a semiconductor material layer 9 located in the substrate 8. In an embodiment in which the semiconductor material layer 9 includes a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel 735 of each field effect transistor in the CMOS circuit 700 may include a single crystalline semiconductor channel such as a single crystalline silicon channel. In an embodiment, a subset of the field effect transistors in the CMOS circuit 700 may include a corresponding node, which is then electrically connected to a node of an energy harvesting device and / or is then electrically connected to a battery structure to be formed later.

[0029] In one embodiment, the substrate 8 may include a single crystal silicon substrate, and the field effect transistor may include a corresponding portion of the single crystal silicon substrate as a semiconducting channel. As used herein, a "semiconducting" device refers to a device having a width between 1.0×10 -6 Siemens / cm to 1.0×10 5 Siemens / cm. As used herein, "semiconductor material" refers to a semiconductor material having an electrical conductivity in the range of 1.0×10 -6 Siemens / cm to 1.0×10 5Siemens / cm range, and can be produced with conductivity ranging from 1.0 Siemens / cm to 1.0×10 5 Doped materials with electrical conductivities in the range of Siemens / cm.

[0030] Various metal interconnect structures formed in the dielectric material layer may then be formed over the substrate 8 and the semiconductor device 701 (e.g., a field effect transistor) located thereon. In an illustrative example, the dielectric material layer may include, for example, a first dielectric material layer 601 (the first dielectric material layer 601 may be a layer surrounding the contact structure connected to the source and the drain) (sometimes referred to as a contact-level dielectric material layer 601), a first interconnect-level dielectric material layer 610, a second interconnect-level dielectric material layer 620, a third interconnect-level dielectric material layer 630, and a fourth interconnect-level dielectric material layer 640. The metal interconnect structure may include: a device contact through-hole structure 612 formed in the first dielectric material layer 601 and contacting the corresponding components of the CMOS circuit 700, a first wire structure 618 formed in the first interconnect level dielectric material layer 610, a first conductive hole structure 622 formed in the lower portion of the second interconnect level dielectric material layer 620, a second conductive hole structure 628 formed in the upper portion of the second interconnect level dielectric material layer 620, a second conductive hole structure 632 formed in the lower portion of the third interconnect level dielectric material layer 630, a third conductive hole structure 638 formed in the upper portion of the third interconnect level dielectric material layer 630, a third conductive hole structure 642 formed in the lower portion of the fourth interconnect level dielectric material layer 640, and a fourth conductive hole structure 648 formed in the upper portion of the fourth interconnect level dielectric material layer 640. Although the present disclosure is described using embodiments in which four levels of conductive line structures are formed in dielectric material layers, embodiments in which fewer or greater numbers of conductive line structures are formed in dielectric material layers are expressly contemplated herein.

[0031] Each of the dielectric material layers (601, 610, 620, 630, 640) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner material (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal filler materials within the contemplation of the present disclosure may also be used. In one embodiment, the first conductive via structure 622 and the second conductive line structure 628 can be formed as an integrated line and via structure by a dual damascene process. In general, any contiguous set of conductive line structures (628, 638, 648) and at least one underlying conductive via structure (622, 632, 642) can be formed as an integrated line and via structure.

[0032] In general, the semiconductor device 701 may be formed on the substrate 8, and the metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) and the dielectric material layer (601, 610, 620, 630, 640) may be formed on the semiconductor device 701. The metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) may be formed in the dielectric material layer (601, 610, 620, 630, 640) and may be electrically connected to the semiconductor device. The metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) may be electrically connected to a corresponding one of the semiconductor devices 701. In one embodiment, each of the metal interconnect structures ( 612 , 618 , 622 , 628 , 632 , 638 , 642 , 648 ) may include and / or may consist essentially of a corresponding set of at least one metal material.

[0033] An optional dielectric cap layer 21 and a bottom via level dielectric layer 23 may be formed on the dielectric material layer (601, 610, 620, 630, 640). The optional dielectric cap layer 21 includes a dielectric cap material, such as silicon carbide, silicon nitride, or silicon carbonitride. Other suitable dielectric cap materials are also within the scope of the present disclosure. The thickness of the optional dielectric cap layer 21 (if present) may be in the range of 2 nanometers to 100 nanometers, but lesser or greater thicknesses may also be used. The bottom via level dielectric layer 23 includes a dielectric material, such as undoped silicate glass or doped silicate glass. The bottom via level dielectric layer 23 may include a flat top surface, i.e., a top surface that is completely located in a horizontal plane. The thickness of the bottom via level dielectric layer 23 may be in the range of 100 nanometers to 300 nanometers (e.g., from 120 nanometers to 200 nanometers), but lesser or greater thicknesses may also be used.

[0034] The bottom capacitor contact via structure 22 may be formed through the bottom via level dielectric layer 23 and the optional dielectric cap layer 21 directly above one of the underlying conductive line structures, such as the fourth conductive line structure 648. For example, a via cavity may be formed through the bottom via level dielectric layer 23 and the optional dielectric cap layer 21, and the via cavity may then be filled with at least one metal filling material to form the bottom capacitor contact via structure 22.

[0035] FIG. 2A to FIG. 2F are sequential vertical cross-sectional views of a first structure during formation of a device structure according to an embodiment of the present disclosure.

[0036] Reference Figure 2A The lower capacitor electrode layer 32L, the node dielectric layer 34L and the upper capacitor electrode layer 36L can be formed in sequence. Figure 1 The first structure is obtained by using the structure shown in . The lower capacitor electrode layer 32L includes at least one first metal material, such as a conductive metal nitride (e.g., TiN, TaN, WN, MoN, etc.), a conductive metal carbide (e.g., TiC, TaC, WC, etc.), an elemental metal (e.g., Ti, Ta, W, Mo, Co, Ru, Cu, etc.), an intermetallic alloy, or a combination or a stack thereof. The thickness of the lower capacitor electrode layer 32L can be in a range from 5 nanometers to 100 nanometers (e.g., from 10 nanometers to 50 nanometers), but smaller or larger thicknesses can also be used.

[0037] The node dielectric layer 34L includes a node dielectric material, such as silicon nitride, a dielectric metal oxide, or a combination or stack thereof. The thickness of the node dielectric layer 34L may range from 4 nm to 10 nm (e.g., from 4 nm to 8 nm), although lesser or greater thicknesses may also be used.

[0038] The upper capacitor electrode layer 36L includes at least one second metal material, such as a conductive metal nitride (e.g., TiN, TaN, WN, MoN, etc.), a conductive metal carbide (e.g., TiC, TaC, WC, etc.), an elemental metal (e.g., Ti, Ta, W, Mo, Co, Ru, Cu, etc.), an intermetallic alloy, or a combination or stack thereof. The thickness of the upper capacitor electrode layer 36L may range from 5 nanometers to 100 nanometers (e.g., from 10 nanometers to 50 nanometers), although lesser or greater thicknesses may also be used.

[0039] Reference Figure 2B , the stack of lower capacitor electrode layer 32L, node dielectric layer 34L, and upper capacitor electrode layer 36L may be patterned into a plurality of capacitors 30. For example, a first photoresist layer may be applied over the stack (e.g., 32L, 34L, 36L), and the first photoresist layer may be patterned photolithographically to cover regions where capacitors are subsequently to be formed. A first anisotropic etching process may be performed to remove portions of the stack (e.g., 32L, 34L, 36L) not covered by the first photoresist layer. The first photoresist layer may be removed, for example, by ashing. A second photoresist layer may be applied over the patterned portions of the stack (e.g., 32L, 34L, 36L), and the second photoresist layer may be patterned photolithographically to form linear openings over regions of the gap selected from the capacitors to be subsequently formed. A second anisotropic etching process may be performed to divide the upper capacitor electrode layer 36L into a plurality of regions. The node dielectric layer 34 may or may not be divided into a plurality of discrete portions.The second photoresist layer may be removed, for example, by ashing.

[0040] Each patterned portion of upper capacitor electrode layer 36L constitutes an upper capacitor electrode plate 36 of a corresponding capacitor 30. Each portion of node dielectric layer 34L that is located below a corresponding overlying upper capacitor electrode plate 36 and has an area overlapping with the corresponding overlying upper capacitor electrode plate 36 constitutes node dielectric 34. Each portion of lower capacitor electrode layer 32L that is located below a corresponding overlying upper capacitor electrode plate 36 and has an area overlapping with the corresponding overlying upper capacitor electrode plate 36 constitutes lower capacitor electrode plate 32.

[0041] Each combination of the upper capacitor electrode plate 36, the node dielectric 34 located below the upper capacitor electrode plate 36, and the lower capacitor electrode plate 32 located below the upper capacitor electrode plate 36 constitutes a capacitor 30. A plurality of capacitors 30 may be formed. Figure 2BIn the example shown in FIG. 3 , three capacitors 30 are shown, including a first capacitor 30A, a second capacitor 30B, and a third capacitor 30C. Although the present disclosure is described using an embodiment in which three capacitors 30 are formed, embodiments in which the total number of capacitors is 1, 2, 4, 5, 6, or any integer greater than 6 are expressly considered herein.

[0042] The area of ​​each capacitor 30 (the capacitance of each capacitor 30) may be the same or different. In one embodiment, the capacitors 30 may be formed to have the same size. In another embodiment, the capacitors 30 may be formed to have different sizes. In yet another embodiment, the capacitors 30 may be formed in multiple groups so that the capacitance is the same in the same group but different from other different groups. In yet another embodiment, the capacitors 30 may be formed so that the values ​​of the capacitance form a geometric sequence, for example, for each positive integer value i used to label the capacitor, the value of the capacitance is C0R (i-1) , i is a positive integer starting from 1, C0 is the value of the minimum capacitance, and R is the ratio of the capacitances between the capacitors numbered in sequence and has a value greater than 1. In general, the values ​​of the capacitances of the capacitors may be independent of each other. In some embodiments, the values ​​of the capacitances of the capacitors 30 may be selected so that when connected in parallel to each other, about half of all the capacitors 30 may provide a target capacitance value under nominal process conditions, and the range of capacitance values ​​that may be obtained by the capacitors 30 connected in parallel may be wide enough to cover the entire range of capacitance values ​​that may be required under extreme process conditions that may occur during the manufacturing process.

[0043] The upper capacitor electrode plates 36 of the capacitors 30 are formed as discrete conductive electrode plates that do not contact each other. For example, the upper capacitor electrode plates 36 of the first capacitor 30A and the upper capacitor electrode plates 36 of the second capacitor 30B include discrete conductive electrode plates that do not contact each other.

[0044] In some embodiments, the second anisotropic etching process may pattern the upper capacitor electrode layer 36L but not the lower capacitor electrode layer 32L. In this embodiment, the lower capacitor electrode plates 32 of the capacitors 30 may be combined into a single conductive electrode plate, i.e., a single continuous lower capacitor electrode plate. For example, the lower capacitor electrode plate 32 of the first capacitor 30A and the lower capacitor electrode plate 32 of the second capacitor 30B (and any additional capacitors 30) are combined into a single conductive electrode plate.

[0045] The node dielectric 34 may or may not be divided by the second anisotropic etching process. Thus, the node dielectric 34 may be formed as a plurality of discrete node dielectrics or may be formed as a single continuous node dielectric layer. In general, each of the capacitors 30 comprises a respective metal-insulator-metal (MIM) capacitor including a respective lower capacitor electrode plate 32 and a respective upper capacitor electrode plate 36.

[0046] Reference Figure 2C , at least one dielectric layer (such as 37, 47) may then be deposited on the capacitor 30. The portion of the at least one dielectric layer (such as 37, 47) located below the horizontal plane including the top surface of the upper capacitor electrode plate 36 is referred to herein as the capacitor-level dielectric layer 37. The portion of the at least one dielectric layer (such as 37, 47) overlying the horizontal plane including the top surface of the upper capacitor electrode plate 36 is referred to herein as the upper connection-level dielectric layer 47. The capacitor-level dielectric layer 37 and the upper connection-level dielectric layer 47 may be formed as a single dielectric material layer or may be formed as multiple dielectric material layers. The combination of the optional dielectric cap layer 21, the bottom via-level dielectric layer 23, the capacitor-level dielectric layer 37, and the upper connection-level dielectric layer 47 may be an inner connection-level dielectric material layer, and the via structure and the conductor structure are formed by the inner connection-level dielectric material layer. The combination of the optional dielectric cap layer 21 , the bottom via level dielectric layer 23 , the capacitor level dielectric layer 37 , and the upper connection level dielectric layer 47 is referred to herein as a fifth interconnect level dielectric material layer 650 .

[0047] A via structure and a conductive line structure may be formed in the fifth interconnect level dielectric material layer 650. The via structure formed in the fifth interconnect level dielectric material layer 650 is referred to as a fourth via structure, and the conductive line structure formed in the fifth interconnect level dielectric material layer 650 is referred to as a fifth conductive line structure. A first subset of fourth via structures (not shown) formed outside the region of the capacitor 30 may extend in a vertical direction through the optional dielectric cap layer 21, the bottom via level dielectric layer 23, the capacitor level dielectric layer 37, and may extend in a vertical direction through a lower portion of the upper connection level dielectric layer 47, and may contact a top surface of a corresponding fourth conductive line structure 648. A second subset of fourth via structures formed on a corresponding one of the upper capacitor electrode plates 36 is referred to herein as a top capacitor contact via structure 42.

[0048] Each of the fifth conductive line structures may be formed as a conductive line portion of an integrated conductive line and via structure that also includes a corresponding fourth conductive via structure or each of the fifth conductive line structures may be formed as a separate structure formed on at least one top surface of at least one underlying fourth conductive via structure. The fifth conductive line structures of the first subset may be formed outside the area of ​​capacitor 30. The fifth conductive line structures of the second subset may be formed within the area of ​​capacitor 30 on the top capacitor contact via structure 42 of the corresponding subset. In general, the fifth conductive line structures of the first subset and the fifth conductive line structures of the second subset may be formed simultaneously and may include the same set of at least one metallic material or may be formed using different sets of processing steps and, therefore, may include different sets of at least one metallic material.

[0049] In one embodiment, the fifth conductive structure of the second subset includes conductive electrodes of the first subset for non-ohmic switch devices. The conductive electrodes of the first subset for non-ohmic switch devices are collectively referred to as primary switch electrodes 48. According to the present disclosure, the primary switch electrode 48 includes a material that resists electrical migration and outdiffusion of the material under an external electrical bias voltage. For example, the primary switch electrode 48 may include and / or may be essentially composed of at least one metal barrier material, at least one refractory metal, a highly conductive metal, a conductive metal oxide, a heavily doped semiconductor material, an alloy or compound thereof, and / or a stack thereof. Non-limiting exemplary metal barrier materials that can be used for the primary switch electrode 48 include TiN, TaN, WN, MoN, TiC, TaC, WC, etc. Refractory metals include W, Ta, Re, Mo, and Nb. Non-limiting examples of highly conductive metals include Os, Ir, Pt, Au, Pd, Ni, Al, Ti, etc. A non-limiting example of a conductive metal oxide is iridium oxide (IrO2). Non-limiting examples of heavily doped semiconductor materials include heavily p-doped polysilicon, heavily n-doped polysilicon, heavily doped silicon-germanium alloys, etc. As used herein, heavily doped semiconductor materials refer to materials containing atoms with a concentration greater than 1.0×10 20 / cubic centimeter of electrical dopant semiconductor material.

[0050] In some embodiments, each of primary switch electrodes 48 may include a respective lower portion comprised of copper or aluminum or may not include a respective lower portion comprised of copper or aluminum. In one embodiment, the fifth conductive wire structure of the first subset formed outside the region of capacitor 30 may include copper or aluminum, and each of primary switch electrodes 48 may include a respective lower portion comprised of copper or aluminum. In one embodiment, primary switch electrodes 48 may include an upper portion comprised of a conductive material other than copper or aluminum. In this embodiment, the fifth conductive wire structure of the first subset formed outside the region of capacitor 30 may include the conductive material of the upper portion of primary switch electrodes 48 or may not include the conductive material of the upper portion of primary switch electrodes 48. In one embodiment, primary switch electrodes 48 may include a conductive material other than copper or aluminum and / or may consist essentially of a conductive material other than copper or aluminum, and the fifth conductive wire structure of the first subset may include a material different from the conductive material of primary switch electrodes 48. In one embodiment, the fifth conductive wire structure of the first subset may include copper and / or aluminum, and primary switch electrodes 48 may not include copper and / or aluminum.

[0051] The height of each primary switch electrode 48 may be in a range from 30 nm to 500 nm (e.g., from 50 nm to 300 nm), although lesser or greater thicknesses may also be used. In one embodiment, the top surface of the primary switch electrode 48 may be located in a horizontal plane including the top surface of the fifth interconnect level dielectric material layer 650.

[0052] In one embodiment, the upper capacitor electrode plate 36 of each capacitor 30 may be in contact with at least one via structure (e.g., at least one top capacitor contact via structure 42) electrically connected to the corresponding primary switch electrode. For example, the upper capacitor electrode plate 36 of the first capacitor 30A may be in contact with at least one first via structure (e.g., at least one first top capacitor contact via structure 42) electrically connected to the first primary switch electrode 48; the upper capacitor electrode plate 36 of the second capacitor 30B may be in contact with at least one second via structure (e.g., at least one second top capacitor contact via structure 42) electrically connected to the second primary switch electrode 48; and the upper capacitor electrode plate 36 of the third capacitor 30C may be in contact with at least one third via structure (e.g., at least one third top capacitor contact via structure 42) electrically connected to the third primary switch electrode 48.

[0053] Reference Figure 2DA via-level dielectric material layer 51 may be formed on the primary switch electrode 48 and the dielectric material layer (e.g., the fifth interconnect-level dielectric material layer 650) in which the primary switch electrode 48 is embedded. The via-level dielectric material layer 51 includes a dielectric material, such as undoped silicate glass, doped silicate glass, silicon nitride, or a combination or stack thereof. The thickness of the via-level dielectric material layer 51 may be in a range from 30 nanometers to 500 nanometers (e.g., from 60 nanometers to 300 nanometers), but a smaller or larger thickness may also be used.

[0054] A photoresist layer (not shown) may be applied over the via-level dielectric material layer 51 and may be patterned photolithographically to form discrete openings in the photoresist layer. The openings in the photoresist layer may be formed in the region of the primary switch electrode 48. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the via-level dielectric material layer 51. A via cavity 159 may be formed through the via-level dielectric material layer 51. A top surface segment of a corresponding primary switch electrode 48 may be physically exposed below each via cavity 159. For example, the through-hole cavity 159 may include: a first through-hole cavity 159A covering the first primary switch electrode 48 electrically connected to the upper capacitor electrode plate 36 of the first capacitor 30A, a second through-hole cavity 159B covering the second primary switch electrode 48 electrically connected to the upper capacitor electrode plate 36 of the second capacitor 30B, a third through-hole cavity 159C covering the third primary switch electrode 48 electrically connected to the upper capacitor electrode plate 36 of the third capacitor 30C, and the like.

[0055] In some embodiments, the via cavity 159 can be formed to have different sizes. For example, the via cavity 159 can be formed to have different maximum diameters to provide different volumes. The different sizes of the via cavity 159 can be advantageously used to provide different threshold voltages to the non-ohmic switching material portion that will be subsequently formed in the via cavity 159.

[0056] Reference Figure 2E, at least one non-ohmic switching material may be deposited in the through-hole cavity 159, and excess portions of the at least one non-ohmic switching material may be removed from outside the through-hole cavity 159 (i.e., from above the horizontal plane including the top surface of the through-hole level dielectric material layer 51). As used herein, a non-ohmic switching material refers to a material that exhibits nonlinear current characteristics that vary with an applied external voltage. As used herein, a non-ohmic switching material refers to a non-ohmic switching material that exhibits a higher effective resistivity (i.e., resistance divided by distance multiplied by area) at a low applied voltage and exhibits a low effective resistivity at a high applied voltage. The highest voltage at which a non-ohmic switching material exhibits a higher effective resistivity is referred to herein as a critical voltage. In general, a non-ohmic switching material has an inherent critical electric field, under which the characteristics of the non-ohmic switching material change from a high resistivity state to a low resistivity state as the external electric field increases. The critical voltage is typically the product of the inherent critical electric field and the thickness of the non-ohmic switching material (or the magnitude along the electric field).

[0057] Each remaining portion of the at least one non-ohmic switching material filling the corresponding via cavity 159 constitutes a non-ohmic switching material portion 12 as a non-ohmic switching material via structure (152A, 152B, 152C). The non-ohmic switching material via structure (152A, 152B, 152C) may be formed on the top surface of each of the primary switch electrodes 48. The non-ohmic switching material through-hole structure (152A, 152B, 152C) may include: a first non-ohmic switching material through-hole structure 152A formed on the top surface of the primary switch electrode 48 electrically connected to the upper capacitor plate electrode 36 of the first capacitor 30A, a second non-ohmic switching material through-hole structure 152B formed on the top surface of the primary switch electrode 48 electrically connected to the upper capacitor plate electrode 36 of the second capacitor 30B, a third non-ohmic switching material through-hole structure 152C formed on the top surface of the primary switch electrode 48 electrically connected to the upper capacitor plate electrode 36 of the third capacitor 30C, etc.

[0058] In one embodiment, each of the non-ohmic switching material portions 12 may include the same non-ohmic switching material. In this embodiment, the non-ohmic switching material portions 12 have different lateral dimensions to provide different threshold voltages. Alternatively, the non-ohmic switching material portions 12 may include different non-ohmic switching materials or different combinations of at least two non-ohmic switching materials. In this embodiment, the through-hole cavity 159 may be formed at different processing steps and the through-hole cavity 159 may be filled with different non-ohmic switching materials. In other words, multiple iterations of the processing sequence may be formed to provide non-ohmic switching material portions 12 including different non-ohmic switching materials. Each iteration of the processing sequence may include a corresponding through-hole cavity forming step to form a corresponding subset of through-hole cavities 159 and a corresponding non-ohmic switching material deposition step to form a corresponding subset of non-ohmic switching material portions 12. In general, the non-ohmic switching material portions 12 may be formed to provide different threshold voltages, and the electrical properties of the corresponding non-ohmic switching material portions 12 are transformed from a non-conductive state to a conductive state at different threshold voltages.

[0059] In general, each of the non-ohmic switching material portions 12 includes a respective bidirectional threshold material or a respective phase change memory material.

[0060] In one embodiment, at least one non-ohmic switching material portion 12, a plurality of non-ohmic switching material portions 12, or each of the non-ohmic switching material portions 12 includes and / or consists essentially of a bidirectional threshold value material, such as a germanium-antimony-tellurium compound, a germanium-tellurium compound, a germanium-antimony compound, an antimony-tellurium compound, a germanium-selenium compound, a germanium-selenium-nitrogen compound, a germanium-selenium-arsenic compound, a germanium-selenium-antimony compound, a silicon-tellurium compound, a zinc-tellurium compound, a carbon-tellurium compound, a boron-tellurium compound, a germanium-arsenic-tellurium compound, etc. The bidirectional threshold value material may be doped with at least one dopant atom or may not be doped with at least one dopant atom to enhance electrical properties, such as switching properties. The at least one dopant atom may include one or more of Si, N, O, Ni, Al, Ti, W, Cu, C, B, Sn, In, Ag, etc.

[0061] Alternatively or additionally, at least one non-ohmic switching material portion 12, a plurality of non-ohmic switching material portions 12, or each of the non-ohmic switching material portions 12 may include a phase change memory material and / or may be essentially composed of a phase change memory material. As used herein, "phase change memory material" refers to a material having at least two different phases that provide different resistivities. Phase change memory (PCM) materials can be used to store information as a resistivity state of a material, which can be in different resistivity states corresponding to the differences in the material. Different phases may include an amorphous state having a high resistivity and a crystalline state having a low resistivity (i.e., a resistivity lower than that of the amorphous state). Exemplary phase change memory materials include, but are not limited to, germanium antimony telluride (GST) compounds, such as Ge2Sb2Te5 or GeSb2Te4, germanium antimony compounds, indium germanium telluride compounds, aluminum telluride selenide compounds, indium telluride selenide compounds, and aluminum indium telluride selenide compounds. Generally speaking, a phase change memory material may or may not be a bidirectional threshold value material, and a bidirectional threshold value material may or may not be a phase change memory material.

[0062] The top surface of the switching material portion 12 , which may be included as a non-ohmic switching material via structure ( 152A, 152B, 152C), may be formed within a horizontal plane including the top surface of the via-level dielectric material layer 51 .

[0063] Reference Figure 2F , a line-level dielectric material layer 53 and a sixth conductive line structure 668 may be formed on the via-level dielectric material layer 51. The combination of the via-level dielectric material layer 51 and the line-level dielectric material layer 53 is referred to herein as an interconnect-level dielectric layer or a sixth interconnect-level dielectric material layer 660. The sixth conductive line structure 668 is a conductive line structure formed in the sixth interconnect-level dielectric material layer 660, such as a metal line structure.

[0064] The sixth conductive line structure 668 may include: a first subset of sixth conductive line structures 668 formed outside the area of ​​the capacitor 30 and used as metal interconnect routing of the semiconductor device 701 and a second subset of sixth conductive line structures 668 used as secondary switch electrodes 56. A fifth conductive via structure (not shown) may be formed outside the area of ​​the capacitor 30, and the first subset of sixth conductive line structures 668 may be formed on the top surface of a corresponding one of the fifth conductive via structures. As another option, the fifth conductive via structure and the first subset of sixth conductive line structures 668 may be formed as an integrated line and via structure. The first subset of sixth conductive line structures 668 and the second subset of sixth conductive line structures 668 may include the same set of conductive materials or may not include the same set of conductive materials. For example, the first subset of sixth conductive line structures 668 may include copper-based metal portions and / or aluminum-based metal portions. The second subset of sixth conductive line structures 668 including the secondary switch electrodes 56 may include any material that can be used for the primary switch electrodes 48 as discussed above.

[0065] In one embodiment, the secondary switch electrodes 56 may be interconnected to each other as a single continuous conductive structure. In this embodiment, each secondary switch electrode 56 of the non-ohmic switch device to be discussed later may be physically included as part of a single secondary switch electrode 56. In addition, although the present disclosure is described using an embodiment in which all secondary switch electrodes 56 are combined into a single conductive structure, embodiments in which the secondary switch electrodes 56 are formed as discrete structures and electrically connected to each other through a set of metal interconnect structures (e.g., metal via structures and / or metal line structures) to be formed later are explicitly considered herein. In general, all secondary switch electrodes 56 for multiple non-ohmic switch devices may be electrically connected to each other by forming the secondary switch electrodes 56 as a single continuous conductive structure or by forming the secondary switch electrodes 56 as discrete conductive structures and then providing conductive paths between each other using, for example, a set of metal interconnect structures.

[0066] According to aspects of the present disclosure, the secondary switch electrode 56 includes a material that is resistant to material electrical migration and out-diffusion under an external electrical bias voltage. For example, the secondary switch electrode 56 may include and / or may consist essentially of at least one metal barrier material, at least one refractory metal, a highly conductive metal, a conductive metal oxide, a heavily doped semiconductor material, an alloy or compound thereof, and / or a stack thereof.

[0067] In some embodiments, each of the secondary switch electrodes 56 may include a respective upper portion composed of copper or aluminum or may not include a respective upper portion composed of copper or aluminum. In one embodiment, the sixth conductive line structure 668 of the first subset formed outside the region of the capacitor 30 may include copper or aluminum, and each of the secondary switch electrodes 56 may include a respective upper portion composed of copper or aluminum. In one embodiment, the secondary switch electrodes 56 may include a lower portion that includes a conductive material different from copper or aluminum. In this embodiment, the sixth conductive line structure 668 of the first subset formed outside the region of the capacitor 30 may include a conductive material of the lower portion of the secondary switch electrodes 56 or may not include a conductive material of the lower portion of the secondary switch electrodes 56. In one embodiment, the secondary switch electrodes 56 may include a conductive material different from copper or aluminum and / or may consist essentially of a conductive material different from copper or aluminum, and the sixth conductive line structure 668 of the first subset may include a material different from the conductive material of the secondary switch electrodes 56. In one embodiment, the sixth conductive line structure 668 of the first subset may include copper and / or aluminum, and the secondary switch electrode 56 may be free of copper and / or aluminum.

[0068] The height of each secondary switch electrode 56 may be in the range of 30 nm to 500 nm (e.g., 50 nm to 300 nm), but smaller or larger thicknesses may also be used. In one embodiment, the top surface of the secondary switch electrode 56 may be located in a horizontal plane including the top surface of the sixth interconnect level dielectric material layer 660.

[0069] Subsequently, a seventh interconnection-level dielectric material layer 670, a sixth via structure 672, and a seventh conductive line structure 678 may be formed over the sixth interconnection-level dielectric material layer 660. Optionally, an additional seventh interconnection-level dielectric material layer (not shown), an additional via structure (not shown), and an additional conductive line structure (not shown) may be formed over the seventh interconnection-level dielectric material layer 670. A metal bonding structure such as a metal bonding pad and a passivation dielectric layer may be formed at the topmost level of the interconnection-level dielectric material layer.

[0070] Generally speaking, a capacitor circuit may be formed on a lower level dielectric material layer (601, 610, 620, 630, 640) (also referred to as a first dielectric material layer). The capacitor circuit includes a capacitor switch assembly 60 connected in parallel. The capacitor switch assembly connected in parallel may include: a first capacitor switch assembly 60A, including a first series-connected first capacitor 30A and a first non-ohmic switch device (48, 12, 56), the first non-ohmic switch device (48, 12, 56) having a first threshold voltage and including a first primary switch electrode 48, a first secondary switch electrode 56, and a first non-ohmic switch material portion 12 in contact with the first primary switch electrode 48 and the first secondary switch electrode 56; and a second capacitor switch assembly 60B, including a second series-connected second capacitor 30B and a second non-ohmic switch device (48, 12, 56), the second non-ohmic switch device (48, 12, 56) having a second threshold voltage and including a second primary switch electrode 48, a second secondary switch electrode 56, and a second non-ohmic switch material portion 12 in contact with the second primary switch electrode 48 and the second secondary switch electrode 56. According to aspects of the present disclosure, the second threshold voltage is different from the first threshold voltage. The capacitance of the second capacitor 30B may be the same as that of the first capacitor 30A or may be different from that of the first capacitor 30A.

[0071] Additionally, the parallel-connected capacitor switch assembly may include: a third capacitor switch assembly 60C, including a third capacitor 30C connected in series and a third non-ohmic switch device (48, 12, 56), the third non-ohmic switch device (48, 12, 56) having a third threshold voltage and including a third primary switch electrode 48, a third secondary switch electrode 56, and a third non-ohmic switch material portion 12 in contact with the third primary switch electrode 48 and the third secondary switch electrode 56; and optionally at least one additional capacitor switch assembly (not shown), including a corresponding additional additional capacitor 30 connected in series and an additional non-ohmic switch device (48, 12, 56), the additional non-ohmic switch device (48, 12, 56) having a corresponding threshold voltage and including a corresponding primary switch electrode 48, a corresponding secondary switch electrode 56, and a corresponding non-ohmic switch material portion 12 in contact with the corresponding primary switch electrode 48 and the corresponding secondary switch electrode 56. According to aspects of the present disclosure, the threshold voltages of the non-ohmic switch devices (48, 12, 56) may be different from each other.

[0072] In one embodiment, the first non-ohmic switching material portion 12 is formed as a first through-hole structure located on the top surface of the first primary switch electrode 48 , and the second non-ohmic switching material portion 12 is formed as a second through-hole structure located on the top surface of the second primary switch electrode 48 .

[0073] In one embodiment, each of the capacitors 30 (e.g., the first capacitor 30A, the second capacitor 30B, etc.), and each of the non-ohmic switching devices (48, 12, 56) (e.g., the first non-ohmic switching device (48, 12, 56) and the second non-ohmic switching device (48, 12, 56), etc.) is in contact with a corresponding one of the dielectric material layers (650, 660). In one embodiment, each of the non-ohmic switching material portions 12 (e.g., the first non-ohmic switching material portion 12, the second non-ohmic switching material portion 12, etc.) includes a corresponding sidewall in contact with a first dielectric material layer (e.g., the via-level dielectric material layer 51) selected from the dielectric material layers (650, 660).

[0074] In one embodiment, each primary switch electrode 48 contacts a bottom surface of a corresponding non-ohmic switching material portion 12 , and each secondary switch electrode 56 contacts a top surface of a corresponding non-ohmic switching material portion 12 .

[0075] See also Figure 2G , can be formed by forming an additional capacitor 30D (the additional capacitor 30D is connected in parallel to Figure 2F The capacitor switch assembly connected in parallel as shown in FIG. Figure 2F An alternative embodiment of the first structure according to the disclosed embodiment is obtained by using the first structure shown in . In this embodiment, a fifth via structure 662 may be provided between the secondary switch electrode 56 of the capacitor switch assembly connected in parallel and the fifth conductive wire structure 658 electrically connected to the upper capacitor electrode plate 36 of the additional capacitor 30D. The fifth via structure 662 is composed of at least one conductive material, thereby providing a conductive path between the secondary switch electrode 56 of the capacitor switch assembly connected in parallel and the upper capacitor electrode plate 36 of the additional capacitor 30D. In this way, the additional capacitor 30D is always connected to the capacitor switch assembly connected in parallel, and a capacitive coupling path is provided between the two end nodes of the capacitor switch assembly connected in parallel, regardless of the state of the non-ohmic switch device (48, 12, 56).

[0076] FIG. 3A to FIG. 3C are sequential vertical cross-sectional views of a second structure during formation of a device structure according to an embodiment of the present disclosure.

[0077] Reference Figure 3A , can be formed by forming an additional conductive line structure while forming the primary switch electrode 48. Figure 2CThe second exemplary structure is obtained by converting the first exemplary structure shown in . The additional wire structure is then used as a secondary switch electrode 46 for a corresponding non-ohmic switch device to be formed later. The secondary switch electrode 46 may include at least one conductive material of the same group as the primary switch electrode 48, and may have the same thickness as the primary switch electrode 48. The layout of the primary switch electrodes 48 may be modified as needed to accommodate the formation of the secondary switch electrode 46 adjacent to a corresponding one of the primary switch electrodes 48.

[0078] According to aspects of the present disclosure, each secondary switch electrode 46 can be formed adjacent to a corresponding one of the primary switch electrodes 48. In general, the secondary switch electrodes 46 can be formed as a single continuous structure or can be formed as a plurality of discrete structures electrically connected to each other by metal interconnect structures to be formed later. Although the present disclosure is described using embodiments in which the secondary switch electrodes 46 are formed as discrete material portions, embodiments in which the secondary switch electrodes 46 are formed as a single interconnected conductive structure are expressly contemplated herein.

[0079] A non-ohmic switching material layer 148L may be deposited on the top surfaces of the upper connection level dielectric layer 47, the primary switch electrode 48, and the secondary switch electrode 46. The material of the non-ohmic switching material layer 148L may include a Figure 2E Any of the materials described for the non-ohmic switching material portion 12. The thickness of the non-ohmic switching material layer 148L may range from 30 nm to 500 nm, such as from 60 nm to 300 nm, although lesser or greater thicknesses may also be used.

[0080] Reference Figure 3B , the non-ohmic switching material layer 148L may be patterned photolithographically to form various non-ohmic switching material portions 12. For example, a photoresist layer (not shown) may be applied over the non-ohmic switching material layer and the photoresist layer may be patterned photolithographically to form discrete photoresist material portions extending between adjacent multiple pairs of primary switch electrodes 48 and secondary switch electrodes 46 and covering end portions of adjacent multiple pairs of primary switch electrodes 48 and secondary switch electrodes 46. An etching process may be performed to remove portions of the non-ohmic switching material layer that are not covered by discrete photoresist material portions. The photoresist material portions may then be removed, for example, by ashing. In some embodiments, multiple non-ohmic switching material layers having different material compositions and / or different thicknesses may be used to provide multiple non-ohmic switching material portions 12 having different material compositions and / or different thicknesses.

[0081] In embodiments where multiple non-ohmic switching material layers are used to form the non-ohmic switching material portion 12, different non-ohmic switching materials and / or different thicknesses of the non-ohmic switching material may be used to provide different threshold voltages for the non-ohmic switching material portion 12. Additionally or alternatively, different spacings between corresponding adjacent pairs of primary switch electrodes 48 and secondary switch electrodes 46 may be used to provide multiple non-ohmic switching material portions 12 with different threshold voltages.

[0082] In the second exemplary structure, each non-ohmic switching material portion 12 may be formed as a plate structure (148A, 148B, 148C) having a corresponding uniform thickness all the way across the top surface of the corresponding primary switch electrode 48 and the top surface of the corresponding secondary switch electrode 46. In the illustrative example, the plate structures (148A, 148B, 148C) may include a first plate structure 148A, a second plate structure 148B, a third plate structure 148C, and the like. In one embodiment, the first non-ohmic switching material portion 12 may be formed as a first plate structure 148A, and the first plate structure 148A always has a uniform thickness on the top surface of the first primary switch electrode 48 and the top surface of the first secondary switch electrode 46; the second non-ohmic switching material portion 12 may be formed as a second plate structure 148B, and the second plate structure 148B always has a uniform thickness on the top surface of the second primary switch electrode 48 and the top surface of the second secondary switch electrode 46; the third non-ohmic switching material portion 12 may be formed as a third plate structure 148C, and the third plate structure 148C always has a uniform thickness on the top surface of the third primary switch electrode 48 and the top surface of the third secondary switch electrode 46, and so on.

[0083] Reference Figure 3C , a via-level dielectric material layer 51 and a line-level dielectric material layer 53 may be formed on the non-ohmic switching material portion 12. The combination of the via-level dielectric material layer 51 and the line-level dielectric material layer 53 is referred to herein as an interconnect-level dielectric layer or a sixth interconnect-level dielectric material layer 660. A via structure (referred to herein as a fifth via structure 662) may be formed in the via-level dielectric material layer 51. A conductive line structure (referred to herein as a sixth conductive line structure 668) may be formed in the line-level dielectric material layer 53. In some embodiments, the fifth conductive line structure 662 and the sixth conductive line structure 668 may be formed as an integrated line and via structure by performing a dual damascene process step.

[0084] Subsequently, a seventh interconnection-level dielectric material layer 670, a sixth via structure 672, and a seventh conductive line structure 678 may be formed over the sixth interconnection-level dielectric material layer 660. Optionally, an additional seventh interconnection-level dielectric material layer (not shown), an additional via structure (not shown), and an additional conductive line structure (not shown) may be formed over the seventh interconnection-level dielectric material layer 670. A metal bonding structure such as a metal bonding pad and a passivation dielectric layer may be formed at the topmost level of the interconnection-level dielectric material layer.

[0085] Generally speaking, a capacitor circuit may be formed on a lower level dielectric material layer (601, 610, 620, 630, 640) (also referred to as a first dielectric material layer). The capacitor circuit includes a capacitor switch assembly 60 connected in parallel. The capacitor switch assembly connected in parallel may include: a first capacitor switch assembly 60A, including a first series-connected first capacitor 30A and a first non-ohmic switch device (48, 12, 46), the first non-ohmic switch device (48, 12, 46) having a first threshold voltage and including a first primary switch electrode 48, a first secondary switch electrode 46, and a first non-ohmic switch material portion 12 in contact with the first primary switch electrode 48 and the first secondary switch electrode 46; and a second capacitor switch assembly 60B, including a second series-connected second capacitor 30B and a second non-ohmic switch device (48, 12, 46), the second non-ohmic switch device (48, 12, 46) having a second threshold voltage and including a second primary switch electrode 48, a second secondary switch electrode 46, and a second non-ohmic switch material portion 12 in contact with the second primary switch electrode 48 and the second secondary switch electrode 46. According to aspects of the present disclosure, the second threshold voltage is different from the first threshold voltage. The capacitance of the second capacitor 30B may be the same as that of the first capacitor 30A or may be different from that of the first capacitor 30A.

[0086] Additionally, the parallel-connected capacitor switch assembly may include: a third capacitor switch assembly 60C, including a third capacitor 30C connected in series and a third non-ohmic switch device (48, 12, 46), the third non-ohmic switch device (48, 12, 46) having a third threshold voltage and including a third primary switch electrode 48, a third secondary switch electrode 46 and a third non-ohmic switch material portion 12 in contact with the third primary switch electrode 48 and the third secondary switch electrode 46; and optionally at least one additional capacitor switch assembly (not shown), including a corresponding additional additional capacitor 30 connected in series and an additional non-ohmic switch device (48, 12, 46), the additional non-ohmic switch device (48, 12, 46) having a corresponding threshold voltage and including a corresponding primary switch electrode 48, a corresponding secondary switch electrode 46 and a corresponding non-ohmic switch material portion 12 in contact with the corresponding primary switch electrode 48 and the corresponding secondary switch electrode 46. According to aspects of the present disclosure, the threshold voltages of the non-ohmic switch devices (48, 12, 46) may be different from each other.

[0087] In one embodiment, each primary switch electrode 48 and each secondary switch electrode 46 has a top surface located in a horizontal plane, and each non-ohmic switch material portion 12 has a horizontal surface (e.g., a bottom surface) located in the horizontal plane. In one embodiment, the horizontal surface of each non-ohmic switch material portion 12 contacts a section of the top surface of the corresponding primary switch electrode 48 and contacts a section of the top surface of the corresponding secondary switch electrode 46.

[0088] In one embodiment, each of the capacitors 30 (e.g., the first capacitor 30A, the second capacitor 30B, etc.), and each of the non-ohmic switching devices (48, 12, 56) (e.g., the first non-ohmic switching device (48, 12, 56) and the second non-ohmic switching device (48, 12, 56), etc.) is in contact with a corresponding one of the dielectric material layers (650, 660). In one embodiment, each of the non-ohmic switching material portions 12 (e.g., the first non-ohmic switching material portion 12, the second non-ohmic switching material portion 12, etc.) includes a corresponding sidewall in contact with a first dielectric material layer (e.g., the via-level dielectric material layer 51) selected from the dielectric material layers (650, 660).

[0089] Reference Figure 3D , can be formed by forming an additional capacitor 30D (the additional capacitor 30D is connected in parallel to Figure 3C The capacitor switch assembly connected in parallel as shown in FIG. Figure 3CThe second exemplary structure shown in the figure obtains an alternative embodiment of the second structure according to the embodiment of the present disclosure. In this embodiment, a fifth conductive hole structure 662 can be set between the shared node (e.g., the sixth conductive wire structure 668) of the parallel-connected capacitor switch assembly and the fifth conductive wire structure 658 electrically connected to the upper capacitor electrode plate 36 of the additional capacitor 30D. The fifth conductive hole structure 662 is composed of at least one conductive material, thereby providing a conductive path between the shared node of the parallel-connected capacitor switch assembly and the upper capacitor electrode plate 36 of the additional capacitor 30D. In this way, the additional capacitor 30D is always connected to the parallel-connected capacitor switch assembly, and a capacitive coupling path is provided between the two end nodes of the parallel-connected capacitor switch assembly, regardless of the state of the non-ohmic switch device (48, 12, 56).

[0090] FIG. 4A to FIG. 4D are sequential vertical cross-sectional views of a third structure during formation of a device structure according to an embodiment of the present disclosure.

[0091] Reference Figure 4A , the non-ohmic switching material layer 148L can be omitted. Figure 3A The second exemplary structure shown in is used to obtain a third structure.

[0092] Reference Figure 4B , a photoresist layer 247 may be applied over the top surfaces of the upper connection level dielectric layer 47, the primary switch electrode 48, and the secondary switch electrode 46 and may be patterned photolithographically to form discrete openings overlying the corresponding gaps between the corresponding adjacent pairs of primary switch electrodes 48 and the secondary switch electrodes 46. In general, the pattern of the openings in the photoresist layer 247 may have the same pattern as the pattern of the plate structures (148A, 148B, 148C) in the second exemplary structure. Portions of the fifth interconnect level dielectric material layer 650 that are not located between the adjacent pairs of primary switch electrodes 48 and the secondary switch electrodes 46 are covered by the photoresist layer 247. As discussed above, the widths of the gaps between adjacent pairs of primary switch electrodes 48 and the secondary switch electrodes 46 may be different for at least two gaps and / or among all gaps.

[0093] An etching process may be performed to remove the upper portion of the fifth interconnect level dielectric material layer 650 that is not masked by the photoresist layer 247 (e.g., the upper portion of the upper connection level dielectric layer 47). The etching process may include an anisotropic etching process (e.g., a reactive ion etching process) or an isotropic etching process (e.g., a wet etching process). A via cavity 249 is formed in each volume in which the material of the fifth interconnect level dielectric material layer 650 is removed. The sidewalls of adjacent multiple pairs of corresponding primary switch electrodes 48 and corresponding secondary switch electrodes 46 may be physically exposed around each via cavity 249. The depth of each via cavity 249 may be greater than, less than, or equal to the height of the primary switch electrode 48 and the secondary switch electrode 46. The photoresist layer 247 may then be removed, for example, by ashing.

[0094] Reference Figure 4C At least one non-ohmic switching material may be deposited in the through hole cavity 249, and excess portions of the at least one non-ohmic switching material may be removed from outside the through hole cavity 249 (i.e., from above a horizontal plane including the top surface of the upper connection level dielectric layer 47). The at least one non-ohmic switching material used in the third structure may be a material that can be used for reference. Figure 2E Any of the non-ohmic switching materials of the non-ohmic switching material portion 12 described.

[0095] Each remaining portion of the at least one non-ohmic switching material filling the corresponding via cavity 249 constitutes a non-ohmic switching material portion 12 as a non-ohmic switching material via structure (248A, 248B, 248C). In one embodiment, each of the non-ohmic switching material via structures (248A, 248B, 248C) may have a horizontal top surface that is completely located within a horizontal plane including the top surface of the upper connection level dielectric layer 47. The non-ohmic switching material via structures (248A, 248B, 248C) may be formed between adjacent pairs of primary switch electrodes 48 and secondary switch electrodes 46. The non-ohmic switching material via structures (248A, 248B, 248C) may contact the sidewalls of the primary switch electrode 48 and the sidewalls of the secondary switch electrode 46.

[0096] The non-ohmic switch material via structures (248A, 248B, 248C) may include: a first non-ohmic switch material via structure 248A formed on the sidewalls of the primary switch electrode 48 electrically connected to the upper capacitor plate electrode 36 of the first capacitor 30A and on the sidewalls of the secondary switch electrode 46; a second non-ohmic switch material via structure 248B formed on the sidewalls of the primary switch electrode 48 electrically connected to the upper capacitor plate electrode 36 of the second capacitor 30B and on the sidewalls of another secondary switch electrode 46; a third non-ohmic switch material via structure 248C formed on the sidewalls of the primary switch electrode 48 electrically connected to the upper capacitor plate electrode 36 of the third capacitor 30C and on the sidewalls of another secondary switch electrode 46, etc. As discussed above, the secondary switch electrodes 46 may be formed as a single continuous conductive structure or may be subsequently electrically connected to each other through a metal interconnect structure to be formed later.

[0097] Generally speaking, the lateral dimensions and / or material composition of the non-ohmic switching material through-hole structures (248A, 248B, 248C) may be selected so that the non-ohmic switching material through-hole structures (248A, 248B, 248C) have different threshold voltages for switching from an off state to an on state.

[0098] Reference Figure 4D , a via-level dielectric material layer 51 and a line-level dielectric material layer 53 may be formed on the non-ohmic switching material portion 12. The combination of the via-level dielectric material layer 51 and the line-level dielectric material layer 53 is referred to herein as an interconnect-level dielectric layer or a sixth interconnect-level dielectric material layer 660. A via structure (referred to herein as a fifth via structure 662) may be formed in the via-level dielectric material layer 51. A conductive line structure (referred to herein as a sixth conductive line structure 668) may be formed in the line-level dielectric material layer 53. In some embodiments, the fifth conductive line structure 662 and the sixth conductive line structure 668 may be formed as an integrated line and via structure by performing a dual damascene process step.

[0099] Subsequently, a seventh interconnection-level dielectric material layer 670, a sixth via structure 672, and a seventh conductive line structure 678 may be formed over the sixth interconnection-level dielectric material layer 660. Optionally, an additional seventh interconnection-level dielectric material layer (not shown), an additional via structure (not shown), and an additional conductive line structure (not shown) may be formed over the seventh interconnection-level dielectric material layer 670. A metal bonding structure such as a metal bonding pad and a passivation dielectric layer may be formed at the topmost level of the interconnection-level dielectric material layer.

[0100] Generally speaking, a capacitor circuit may be formed on a lower level dielectric material layer (601, 610, 620, 630, 640) (also referred to as a first dielectric material layer). The capacitor circuit includes a capacitor switch assembly 60 connected in parallel. The capacitor switch assembly connected in parallel may include: a first capacitor switch assembly 60A, including a first series-connected first capacitor 30A and a first non-ohmic switch device (48, 12, 46), the first non-ohmic switch device (48, 12, 46) having a first threshold voltage and including a first primary switch electrode 48, a first secondary switch electrode 46, and a first non-ohmic switch material portion 12 in contact with the first primary switch electrode 48 and the first secondary switch electrode 46; and a second capacitor switch assembly 60B, including a second series-connected second capacitor 30B and a second non-ohmic switch device (48, 12, 46), the second non-ohmic switch device (48, 12, 46) having a second threshold voltage and including a second primary switch electrode 48, a second secondary switch electrode 46, and a second non-ohmic switch material portion 12 in contact with the second primary switch electrode 48 and the second secondary switch electrode 46. According to aspects of the present disclosure, the second threshold voltage is different from the first threshold voltage. The capacitance of the second capacitor 30B may be the same as that of the first capacitor 30A or may be different from that of the first capacitor 30A.

[0101] Additionally, the parallel-connected capacitor switch assembly may include: a third capacitor switch assembly 60C, including a third capacitor 30C connected in series and a third non-ohmic switch device (48, 12, 46), the third non-ohmic switch device (48, 12, 46) having a third threshold voltage and including a third primary switch electrode 48, a third secondary switch electrode 46 and a third non-ohmic switch material portion 12 in contact with the third primary switch electrode 48 and the third secondary switch electrode 46; and optionally at least one additional capacitor switch assembly (not shown), including a corresponding additional additional capacitor 30 connected in series and an additional non-ohmic switch device (48, 12, 46), the additional non-ohmic switch device (48, 12, 46) having a corresponding threshold voltage and including a corresponding primary switch electrode 48, a corresponding secondary switch electrode 46 and a corresponding non-ohmic switch material portion 12 in contact with the corresponding primary switch electrode 48 and the corresponding secondary switch electrode 46. According to aspects of the present disclosure, the threshold voltages of the non-ohmic switch devices (48, 12, 46) may be different from each other.

[0102] In one embodiment, each primary switch electrode 48 and each secondary switch electrode 46 has a top surface located in a horizontal plane, and each non-ohmic switch material portion 12 has a horizontal surface (e.g., a top surface) located in a horizontal plane. In one embodiment, a first sidewall of each non-ohmic switch material portion 12 contacts a sidewall of a corresponding primary switch electrode 48, and a second sidewall of each non-ohmic switch material portion 12 contacts a sidewall of a corresponding secondary switch electrode 46.

[0103] In one embodiment, each of the capacitors 30 (e.g., the first capacitor 30A, the second capacitor 30B, etc.) and each of the non-ohmic switching devices (48, 12, 56) (e.g., the first non-ohmic switching device (48, 12, 56) and the second non-ohmic switching device (48, 12, 56), etc.) is in contact with a corresponding one of the dielectric material layers (650, 660). In one embodiment, each of the non-ohmic switching material portions 12 (e.g., the first non-ohmic switching material portion 12, the second non-ohmic switching material portion 12, etc.) includes a corresponding sidewall in contact with a first dielectric material layer (e.g., the upper connection level dielectric layer 47) selected from the dielectric material layers (650, 660).

[0104] Reference Figure 4E , can be formed by forming an additional capacitor 30D (the additional capacitor 30D is connected in parallel to Figure 4D The capacitor switch assembly connected in parallel as shown in FIG. Figure 4D The second exemplary structure shown in the figure obtains an alternative embodiment of the third structure according to the embodiment of the present disclosure. In this embodiment, a fifth conductive hole structure 662 can be set between the shared node of the parallel-connected capacitor switch assembly (for example, the sixth conductive line structure 668) and the fifth conductive line structure 658 electrically connected to the upper capacitor electrode plate 36 of the additional capacitor 30D. The fifth conductive hole structure 662 is composed of at least one conductive material, thereby providing a conductive path between the shared node of the parallel-connected capacitor switch assembly and the upper capacitor electrode plate 36 of the additional capacitor 30D. In this way, the additional capacitor 30D is always connected to the parallel-connected capacitor switch assembly, and a capacitive coupling path is provided between the two end nodes of the parallel-connected capacitor switch assembly, regardless of the state of the non-ohmic switch device (48, 12, 56).

[0105] Reference Figure 5A , showing a schematic circuit diagram of a first capacitor circuit according to an embodiment of the present disclosure. Figure 5A The circuit diagram shown shows Figure 2F , Figure 3C and Figure 4DThe capacitor circuit shown in FIG. The capacitor circuit includes a plurality of capacitor switch assemblies 60 connected in parallel. Each capacitor switch assembly (60A, 60B, 60C) includes a switch and a capacitor connected in series. For example, the first capacitor switch assembly 60A includes a first switch S1 and a first capacitor C1 connected in series, the second capacitor switch assembly 60B includes a second switch S2 and a second capacitor C2 connected in series, the third capacitor switch assembly 60C includes a third switch S3 and a third capacitor C3 connected in series, and so on.

[0106] In general, the capacitor switch assembly 60 connected in parallel includes a first assembly node AN1, a first end node of the first capacitor switch assembly 60A is connected to a first end node of the second capacitor switch assembly 60B at the first assembly node AN1, and the capacitor switch assembly 60 connected in parallel includes a second assembly node AN2, a second end node of the first capacitor switch assembly 60A is connected to a second end node of the second capacitor switch assembly 60B at the second assembly node AN2. The first end node of the third capacitor switch assembly 60C and the first end node of any additional capacitor switch assembly (not shown) can be connected to the first assembly node AN1. The second end node of the third capacitor switch assembly 60C and the second end node of any additional capacitor switch assembly can be connected to the second assembly node AN2.

[0107] Before any of the switches (S1, S2, S3) is turned on by applying a voltage pulse exceeding the lowest threshold voltage selected from the threshold voltages of the switches (S1, S2, S3), Figure 5A The capacitor circuit shown in has a negligible capacitance. The voltage pulse may be caused by the instantaneous voltage between the two nodes of the capacitor circuit, namely, between the first assembly node AN1 and the second assembly node AN2. As the number of switches (S1, S2, S3) turned on increases, the degree of the instantaneous voltage pulse decreases due to the increase in the capacitance of the capacitor circuit. Given the same level of instantaneous charge pulses during operation of the capacitor circuit disclosed herein, the staggered arrangement of the threshold voltages of the switches (S1, S2, S3) induces a self-limiting turn-on mechanism. In other words, as the total number of switches turned on increases and the total capacitance of the capacitor circuit increases, switches with higher threshold voltages are less likely to turn on. Therefore, Figure 5A The capacitance of the capacitor circuit shown can converge to a default value during operation, and Figure 5A The capacitor circuit shown may provide a self-converging capacitance that compensates for process parameter variations during the manufacturing process.

[0108] Reference Figure 5B , showing a schematic circuit diagram of a second exemplary capacitor circuit according to an embodiment of the present disclosure. Figure 5B The circuit diagram shown shows Figure 2G , Figure 3D and Figure 4E The capacitor circuit shown in FIG. 30 can be automatically connected by connecting the two end nodes of a capacitor such as a fourth capacitor C4 (representing the fourth capacitor 30D) to the first assembly node AN1 and the second assembly node AN2, respectively. Figure 5A The circuit diagram shown in Figure 5B Adding an additional capacitor (e.g., a fourth capacitor C4) will increase the base capacitance of the capacitor circuit from a negligible small capacitance (e.g., Figure 5B ) is converted into a finite capacitance value, which is the capacitance value of the added capacitor. Figure 5B The capacitor circuit shown may also provide a self-converging capacitance that compensates for process parameter variations during the manufacturing process.

[0109] In one embodiment, the additional capacitor (e.g., a fourth capacitor C4) may include a metal-insulator-metal (MIM) capacitor having a first capacitor node and a second capacitor node; the first capacitor node is electrically connected to the first assembly node AN1; and the second capacitor node is electrically connected to the second assembly node AN2.

[0110] Reference Figure 6 , the curve diagram is used as Figure 5A and Figure 5B Current-voltage characteristics of the non-ohmic switch device (48, 12, (46 or 56)) of the present disclosure of switches (S1, S2, S3) in the capacitor circuit shown. In general, the non-ohmic switch device (48, 12, (46 or 56)) behaves as a high resistance resistor until the corresponding threshold voltage (V_th1, V_th2, V_th3). Once the level of the applied external voltage exceeds the corresponding threshold voltage (V_th1, V_th2, V_th3), the non-ohmic switch device (48, 12, (46 or 56)) is transformed to the on state (i.e., the low resistance state), which provides high conductivity and effectively acts as a conductor.

[0111] Various mechanisms may be used for transitioning between the high resistance state and the low resistance state of the non-ohmic switching device (48, 12, (46 or 56)). The present disclosure is not limited by any particular operating mechanism of the non-ohmic switching material. For illustrative purposes, the present application Fig. 7A and Figure 7B Provide an example of such a transformation mechanism. Fig. 7A, a band diagram of a non-ohmic switching material under low electric field bias conditions is shown. Charge carrier transport occurs through local discrete states within the non-ohmic switching material, and therefore, the conductivity of the non-ohmic switching material is low in the high resistivity state. Figure 7B , the energy band diagram of the non-ohmic switching material under high electric field bias conditions is shown. The high electric field induces band bending and allows charge tunneling. Therefore, the conductivity of the non-ohmic switching material is high in the low resistivity state.

[0112] Reference Figure 8 , showing general processing steps for manufacturing a device structure according to an embodiment of the present disclosure.

[0113] Refer to step 810 and Figure 1 , a semiconductor device 701 can be formed on the top surface of the semiconductor substrate 8.

[0114] Refer to step 820 and Figure 1 A first dielectric material layer (601, 610, 620, 630, 640) and a first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) are formed on the semiconductor device 701. The first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) is electrically connected to a corresponding one of the semiconductor devices 701.

[0115] Refer to step 830 and Figures 1 to 5B , a capacitor circuit can be formed on the first dielectric material layer (601, 610, 620, 630, 640). The capacitor circuit includes a capacitor switch assembly 60 connected in parallel. The capacitor switch assembly 60 connected in parallel includes: a first capacitor switch assembly 60A, including a first capacitor 30A and a first non-ohmic switch device (48, 12, (46 or 56)) connected in series, the first non-ohmic switch device (48, 12, (46 or 56)) having a first threshold voltage and including a first primary switch electrode 48, a first secondary switch electrode (46 or 56) and a first non-ohmic switch material portion 12 in contact with the first primary switch electrode 48 and the first secondary switch electrode (46 or 56); And a second capacitor switch assembly 60B, including a second capacitor 30B and a second non-ohmic switching device (48, 12, (46 or 56)) connected in series, the second non-ohmic switching device (48, 12, (46 or 56)) having a second threshold voltage and including a second primary switch electrode 48, a second secondary switch electrode (46 or 56) and a second non-ohmic switching material portion 12 in contact with the second primary switch electrode 48 and the second secondary switch electrode (46 or 56), wherein the second threshold voltage is different from the first threshold voltage.

[0116] With reference to all the drawings and in accordance with various embodiments of the present disclosure, a device structure is provided, the device structure including a capacitor switch assembly 60 connected in parallel on a substrate 8. The capacitor switch assembly 60 includes: a first capacitor switch assembly 60A including a first capacitor 30A connected in series with a first non-ohmic switch device (48, 12, (46 or 56)), the first non-ohmic switch device (48, 12, (46 or 56)) having a first threshold voltage and including a first primary switch electrode 48, a first secondary switch electrode (46 or 56) and a first non-ohmic switch material portion 12 in contact with the first primary switch electrode 48 and the first secondary switch electrode (46 or 56); and a second A capacitor switch assembly 60B includes a second capacitor 30B and a second non-ohmic switch device (48, 12, (46 or 56)) connected in series, the second non-ohmic switch device (48, 12, (46 or 56)) having a second threshold voltage and including a second primary switch electrode 48, a second secondary switch electrode (46 or 56) and a second non-ohmic switch material portion 12 in contact with the second primary switch electrode 48 and the second secondary switch electrode (46 or 56), wherein the second threshold voltage is different from the first threshold voltage.

[0117] In one embodiment, the device structure includes a dielectric material layer (650, 660) located above the substrate 8, wherein each of the first capacitor 30A, the second capacitor 30B, the first non-ohmic switching device (48, 12, (46 or 56)) and the second non-ohmic switching device (48, 12, (46 or 56)) is in contact with a corresponding one of the dielectric material layers (650, 660).

[0118] In one embodiment, each of the first non-ohmic switching material portion 12 and the second non-ohmic switching material portion 12 includes a respective sidewall in contact with a first dielectric material layer selected from the dielectric material layers ( 650 , 660 ).

[0119] In one embodiment, the first primary switch electrode 48 contacts a bottom surface of the first non-ohmic switching material portion 12 ; and the first secondary switch electrode 56 contacts a top surface of the first non-ohmic switching material portion 12 .

[0120] In one embodiment, the first primary switch electrode 48 and the first secondary switch electrode ( 46 or 56 ) have top surfaces that lie within a horizontal plane; and the first non-ohmic switching material portion 12 has a horizontal surface that lies within a horizontal plane.

[0121] In one embodiment, the horizontal surface of the first non-ohmic switching material portion 12 contacts a section of the top surface of the first primary switch electrode 48 and contacts a section of the top surface of the first secondary switch electrode 46 .

[0122] In one embodiment, the first non-ohmic switching material portion 12 contacts a section of a sidewall of the first primary switch electrode 48 and contacts a sidewall of the first secondary switch electrode 46 .

[0123] In one embodiment, each of the first non-ohmic switching material portion 12 and the second non-ohmic switching material portion 12 includes a corresponding bidirectional threshold value material or a corresponding phase change memory material.

[0124] In one embodiment, each of the first capacitor 30A and the second capacitor 30B comprises a respective metal-insulator-metal (MIM) capacitor including a respective lower capacitor electrode plate 32 and a respective upper capacitor electrode plate 36 .

[0125] In one embodiment, the lower capacitor electrode plate 32 of the first capacitor 30A and the lower capacitor electrode plate 32 of the second capacitor 30B are merged into a single conductive electrode plate; the upper capacitor electrode plate 36 of the first capacitor 30A and the upper capacitor electrode plate 36 of the second capacitor 30B are included as discrete conductive electrode plates that do not contact each other; the upper capacitor electrode plate 36 of the first capacitor 30A contacts at least one first conductive hole structure 42 electrically connected to the first primary switch electrode 48; and the upper capacitor electrode plate 36 of the second capacitor 30B contacts at least one second conductive hole structure 42 electrically connected to the second primary switch electrode 48.

[0126] In one embodiment, the capacitor switch assembly 60 connected in parallel includes a first assembly node AN1, a first end node of the first capacitor switch assembly 60A is connected to a first end node of the second capacitor switch assembly 60B at the first assembly node AN1, and the capacitor switch assembly 60 connected in parallel includes a second assembly node AN2, a second end node of the second capacitor switch assembly 60B is connected to a second end node of the second capacitor switch assembly 60B at the second assembly node AN2; the first assembly node AN1 is electrically connected to a power supply node; the device structure includes a semiconductor device located on a substrate 8; and the second assembly node AN2 is electrically connected to at least one node of the semiconductor device.

[0127] In one embodiment, the capacitor switch assembly 60 connected in parallel includes a first assembly node AN1, a first end node of the first capacitor switch assembly 60A is connected to a first end node of the second capacitor switch assembly 60B at the first assembly node AN1, and the capacitor switch assembly 60 connected in parallel includes a second assembly node AN2, a second end node of the second capacitor switch assembly 60B is connected to a second end node of the second capacitor switch assembly 60B at the second assembly node AN2; the device structure further includes a metal-insulator-metal (MIM) capacitor having a first capacitor 30A node and a second capacitor 30B node; the first capacitor 30A node is electrically connected to the first assembly node AN1; and the second capacitor 30B node is electrically connected to the second assembly node AN2.

[0128] According to another aspect of the present disclosure, a device structure is provided, the device structure comprising: a semiconductor device 701, located on a top surface of a semiconductor substrate 8; a first dielectric material layer (601, 610, 620, 630, 640), located on the semiconductor device; a first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648), located in the first dielectric material layer (601, 610, 620, 630, 640) and electrically connected to a corresponding one of the semiconductor devices 701; and a capacitor circuit, located on the first dielectric material layer (601, 610, 620, 630, 640) and comprising a capacitor switch assembly 60 connected in parallel, the capacitor switch assembly 60 connected in parallel comprising: a first capacitor switch assembly 60A, comprising a first capacitor 30A and a first non-ohmic switch device (40A) connected in series; 8, 12, (46 or 56)), a first non-ohmic switch device (48, 12, (46 or 56)) having a first threshold voltage and including a first primary switch electrode 48, a first secondary switch electrode (46 or 56) and a first non-ohmic switch material portion 12 in contact with the first primary switch electrode 48 and the first secondary switch electrode (46 or 56); and a second capacitor switch assembly 60B, including a second capacitor 30B connected in series and a second non-ohmic switch device (48, 12, (46 or 56)), the second non-ohmic switch device (48, 12, (46 or 56)) having a second threshold voltage and including a second primary switch electrode 48, a second secondary switch electrode (46 or 56) and a second non-ohmic switch material portion 12 in contact with the second primary switch electrode 48 and the second secondary switch electrode (46 or 56), wherein the second threshold voltage is different from the first threshold voltage.

[0129] In one embodiment, each of the first non-ohmic switching material portion 12 and the second non-ohmic switching material portion 12 includes a corresponding bidirectional threshold value material or a corresponding phase change memory material.

[0130] In one embodiment, the device structure includes a second dielectric material layer (650, 660), which overlies the first dielectric material layer (601, 610, 620, 630, 640) and laterally surrounds the first capacitor switch assembly 60A and the second capacitor switch assembly 60B, wherein each of the first non-ohmic switching material portion 12 and the second non-ohmic switching material portion 12 includes a corresponding side wall in contact with one of the second dielectric material layers (650, 660).

[0131] According to some embodiments, a method of forming a device structure includes: forming a plurality of semiconductor devices on a top surface of a semiconductor substrate; forming a first dielectric material layer and a first metal interconnect structure over the plurality of semiconductor devices, wherein the first metal interconnect structure is electrically connected to a corresponding one of the plurality of semiconductor devices; and forming a capacitor circuit over the first dielectric material layer, wherein the capacitor circuit includes a plurality of capacitor switch assemblies connected in parallel, the plurality of capacitor switch assemblies connected in parallel including: a first capacitor switch assembly including a first series-connected first capacitor and a first non-ohmic switch device, the first non-ohmic switch device having a first threshold voltage and including a first primary switch electrode, a first secondary switch electrode, and a first non-ohmic switch material portion in contact with the first primary switch electrode and the first secondary switch electrode, and a second capacitor switch assembly including a second series-connected second capacitor and a second non-ohmic switch device, the second non-ohmic switch device having a second threshold voltage and including a second primary switch electrode, a second secondary switch electrode, and a second non-ohmic switch material portion in contact with the second primary switch electrode and the second secondary switch electrode, wherein the second threshold voltage is different from the first threshold voltage.

[0132] In some embodiments, each of the first non-ohmic switching material portion and the second non-ohmic switching material portion includes a corresponding bidirectional threshold value material or a corresponding phase change memory material. In some embodiments, the first non-ohmic switching material portion is formed as a first through-hole structure on the top surface of the first primary switch electrode; and the second non-ohmic switching material portion is formed as a second through-hole structure on the top surface of the second primary switch electrode. In some embodiments, the first non-ohmic switching material portion is formed as a first plate structure, the first plate structure always having a uniform thickness on the top surface of the first primary switch electrode and the top surface of the first secondary switch electrode; and the second non-ohmic switching material portion is formed as a second plate structure, the second plate structure always having the uniform thickness on the top surface of the second primary switch electrode and the top surface of the second secondary switch electrode. In some embodiments, the first non-ohmic switching material portion is formed as a first through-hole structure in contact with the side wall of the first primary switch electrode and in contact with the side wall of the first secondary switch electrode; and the second non-ohmic switching material portion is formed as a second through-hole structure in contact with the side wall of the second primary switch electrode and in contact with the side wall of the second secondary switch electrode.

[0133] Various embodiments of the present disclosure may be used to provide a capacitor circuit that provides capacitance at a predetermined capacitance level without using any actively controlled switches. The non-ohmic switching device of the present disclosure is passive, i.e., does not utilize any other semiconductor device to perform a turn-on operation or a turn-off operation. The passive non-ohmic switching device is turned on sequentially as the magnitude of the transient voltage spike increases. The increase in capacitance of the capacitor circuit of the present disclosure reduces the magnitude of subsequent transient voltage spikes. After several rounds of passive turns-on and passive turns-off, the capacitor circuit of the present disclosure may operate in a steady-state mode in which the capacitance is at an optimal level. Thus, an appropriate level of capacitance may be provided while avoiding excessive capacitance without using any active switching device, such as a field effect transistor.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the embodiments of the utility model.

Claims

1. A semiconductor device structure, characterized in that: A plurality of capacitor switch assemblies connected in parallel are included on a substrate, wherein the plurality of capacitor switch assemblies connected in parallel include: a first capacitor switch assembly including a first capacitor and a first non-ohmic switch device connected in series, the first non-ohmic switch device having a first threshold voltage and including a first primary switch electrode, a first secondary switch electrode, and a first non-ohmic switch material portion in contact with the first primary switch electrode and the first secondary switch electrode; and a second capacitor switch assembly including a second capacitor and a second non-ohmic switch device connected in series, the second non-ohmic switch device having a second threshold voltage and including a second primary switch electrode, a second secondary switch electrode, and a second non-ohmic switch material portion in contact with the second primary switch electrode and the second secondary switch electrode, The second threshold voltage is different from the first threshold voltage.

2. The semiconductor device structure according to claim 1, wherein: Also includes: A plurality of dielectric material layers are located above the substrate, wherein each of the first capacitor, the second capacitor, the first non-ohmic switching device, and the second non-ohmic switching device is in contact with a respective one of the plurality of dielectric material layers.

3. The semiconductor device structure according to claim 2, wherein: Each of the first non-ohmic switching material portion and the second non-ohmic switching material portion includes a respective sidewall in contact with a first dielectric material layer selected from the plurality of dielectric material layers.

4. The semiconductor device structure according to claim 3, wherein: in: The first primary switch electrode and the first secondary switch electrode have top surfaces that lie in a horizontal plane; as well as The first non-ohmic switching material portion has a horizontal surface located within the horizontal plane.

5. The semiconductor device structure according to claim 1, wherein: Each of the first non-ohmic switching material portion and the second non-ohmic switching material portion includes a corresponding bidirectional threshold value material or a corresponding phase change memory material.

6. The semiconductor device structure according to claim 1, wherein: Wherein each of the first capacitor and the second capacitor comprises a respective metal-insulator-metal capacitor including a respective lower capacitor electrode plate and a respective upper capacitor electrode plate.

7. The semiconductor device structure according to claim 1, wherein: in: The plurality of capacitor switch assemblies connected in parallel include a first assembly node, a first end node of the first capacitor switch assembly is connected to a first end node of the second capacitor switch assembly at the first assembly node, and the plurality of capacitor switch assemblies connected in parallel include a second assembly node, a second end node of the first capacitor switch assembly is connected to a second end node of the second capacitor switch assembly at the second assembly node; The first assembly node is electrically connected to a power supply node; The device structure includes a semiconductor device located on the substrate; as well as The second assembly node is electrically connected to at least one node of the semiconductor device.

8. The semiconductor device structure according to claim 1, wherein: in: The plurality of capacitor switch assemblies connected in parallel include a first assembly node, a first end node of the first capacitor switch assembly is connected to a first end node of the second capacitor switch assembly at the first assembly node, and the plurality of capacitor switch assemblies connected in parallel include a second assembly node, a second end node of the first capacitor switch assembly is connected to a second end node of the second capacitor switch assembly at the second assembly node; The device structure further includes a metal-insulator-metal capacitor having a first capacitor node and a second capacitor node; The first capacitor node is electrically connected to the first assembly node; as well as The second capacitor node is electrically connected to the second assembly node.

9. A semiconductor device structure, characterized in that: include: a semiconductor device disposed on a top surface of the semiconductor substrate; A plurality of first dielectric material layers located on the semiconductor device; a first metal interconnect structure disposed in the plurality of first dielectric material layers and electrically connected to a corresponding one of the semiconductor devices; as well as A capacitor circuit is located on the plurality of first dielectric material layers and includes a plurality of capacitor switch assemblies connected in parallel, wherein the plurality of capacitor switch assemblies connected in parallel include: a first capacitor switch assembly including a first capacitor and a first non-ohmic switch device connected in series, the first non-ohmic switch device having a first threshold voltage and including a first primary switch electrode, a first secondary switch electrode, and a first non-ohmic switch material portion in contact with the first primary switch electrode and the first secondary switch electrode, and a second capacitor switch assembly including a second capacitor and a second non-ohmic switch device connected in series, the second non-ohmic switch device having a second threshold voltage and including a second primary switch electrode, a second secondary switch electrode, and a second non-ohmic switch material portion in contact with the second primary switch electrode and the second secondary switch electrode, The second threshold voltage is different from the first threshold voltage.

10. The semiconductor device structure according to claim 9, wherein: Also includes: A plurality of second dielectric material layers overlying the plurality of first dielectric material layers and laterally surrounding the first capacitor switch assembly and the second capacitor switch assembly, wherein each of the first non-ohmic switching material portion and the second non-ohmic switching material portion includes a corresponding side wall in contact with one of the plurality of second dielectric material layers.

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