Image sensor

Abstract

The utility model provides an image sensor. The image sensor comprises a semiconductor substrate, a light detector, an upper passivation layer, a middle passivation layer and a back side isolation structure. The semiconductor substrate has a front side and a back side. And the light detector is positioned in the semiconductor substrate. And the upper passivation layer is located on the back side. The middle passivation layer is located between the upper passivation layer and the back side, and the refractive index of the middle passivation layer is between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer. And a backside isolation structure extending into the backside to laterally surround the light detector, the backside isolation structure including a core body and a dielectric liner located between the core body and the semiconductor substrate. The core body comprises a substrate embedded metal grid, and the substrate embedded metal grid penetrates through the middle passivation layer and extends into the semiconductor substrate.

Description

Technical Field

[0001] The utility model relates to an integrated circuit, and in particular to an image sensor. Background Art

[0002] Integrated circuits (ICs) containing image sensors are widely used in modern electronic devices such as cameras and cellular phones. Complementary metal-oxide semiconductor (CMOS) devices have become a popular IC image sensor. Compared to charge-coupled devices (CCDs), CMOS image sensors (CISs) are increasingly popular due to their low power consumption, small pixel size, fast data processing, and low manufacturing cost. As pixel size becomes smaller, manufacturing becomes more difficult, and limiting crosstalk between pixels becomes more difficult. These are ongoing challenges where unique solutions can improve performance. Utility Model Content

[0003] In an embodiment of the utility model, an image sensor includes a semiconductor substrate, a photodetector, an upper passivation layer, an intermediate passivation layer, and a backside isolation structure. The semiconductor substrate has a front side and a back side. The photodetector is located in the semiconductor substrate. The upper passivation layer is located on the back side. The intermediate passivation layer is located between the upper passivation layer and the back side, wherein the intermediate passivation layer has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer. The backside isolation structure extends into the back side to laterally surround the photodetector, and the backside isolation structure includes a core and a dielectric liner located between the core and the semiconductor substrate. The core includes a substrate-embedded metal grid, which passes through the intermediate passivation layer and extends into the semiconductor substrate.

[0004] In an embodiment of the present invention, an image sensor includes: a semiconductor substrate, a photodetector, and a backside isolation structure. The semiconductor substrate includes a front side and a back side. The photodetectors are arranged in an array in the semiconductor substrate. The backside isolation structure extends between the photodetectors into the back side. The backside isolation structure includes a metal grid and a lower grid, the metal grid is embedded in the semiconductor substrate and extends through the back side of the semiconductor substrate, and the lower grid is located between the metal grid and the front side.

[0005] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A A cross-sectional side view of an IC device according to some aspects of the present invention is shown.

[0008] Figure 1B supply Figure 1A Shown is an enlarged view of a portion of a backside deep trench isolation (BDTI) structure.

[0009] Figure 1C Provide along Figure 1B The cross-sectional plan view is taken along the line CC'.

[0010] Figure 2A A cross-sectional side view of an IC device according to some aspects of the present invention is shown.

[0011] Figure 2B Provide along Figure 2A The cross-sectional plan view is taken along the line CC'.

[0012] Figure 3A A cross-sectional side view of an IC device according to some aspects of the present invention is shown.

[0013] Figure 3B Provide along Figure 3A The cross-sectional plan view is taken along the line CC'.

[0014] Figure 4A A cross-sectional side view of an IC device according to some aspects of the present invention is shown.

[0015] Figure 4B Provide along Figure 4A The cross-sectional plan view is taken along the line CC'.

[0016] Figure 5A A cross-sectional side view of an IC device according to some aspects of the present invention is shown.

[0017] Figure 5B Provide along Figure 5A The cross-sectional plan view is taken along the line CC'.

[0018] Fig. 6AA cross-sectional side view of an IC device according to some aspects of the present invention is shown.

[0019] Figure 6B Provide along Fig. 6A The cross-sectional plan view is taken along the line CC'.

[0020] Figures 7 to 29 is a series of cross-sectional views illustrating a method for forming an IC device according to some aspects of the present invention, wherein the IC device includes a CIS having a BDTI structure according to some embodiments.

[0021] Fig.30 It is a flow chart of a manufacturing process according to some aspects of the utility model. DETAILED DESCRIPTION

[0022] The present invention provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description in which the first feature is formed "above" the second feature or the second feature is "on" may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature illustrated in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0024] Some image sensors designed for backside illumination (BSI) are integrated circuit devices (ICs) that include an array of photodetectors within a semiconductor substrate. The photodetectors may be separated by a backside deep trench isolation (BDTI) structure, which is an isolation structure extending from the backside of the semiconductor substrate into the semiconductor substrate. There may be a passivation layer on the backside. The passivation layer may include an upper passivation layer and an intermediate passivation layer between the upper passivation layer and the semiconductor substrate. The intermediate passivation layer is a transparent material having a refractive index between the refractive index of the upper passivation layer and the refractive index of the semiconductor substrate. The upper passivation layer is often silicon dioxide (SiO 2 ) or similar materials. The intermediate passivation layer may be, for example, tantalum pentoxide (Ta 2 O 5 ) or similar materials.

[0025] The BDTI structure may include a square or ring-shaped component that laterally surrounds and separates the photodetectors. The BDTI structure is formed by etching a trench in the back side of a semiconductor substrate and lining the trench with a dielectric material. A passivation layer is then deposited. A non-conformal deposition process may be used to reduce the extent to which the passivation layer is deposited in the trench. The trench may then be filled with a material that provides optical and electrical isolation between adjacent photodetectors. In some embodiments, the trench is filled with a metal to form a metal grid. In some embodiments, a negative bias voltage is applied to the metal grid to reduce crosstalk.

[0026] As the photodetector pitch becomes smaller, the BDTI structure occupies an increasing proportion of the image sensing area. This trend can be counteracted by making the isolation structure narrower. The extent to which the BDTI structure can be made narrower is generally limited by the tendency of the passivation layer to pinch off at the top of the trench, which ultimately results in the trench being closed at the top, with the void remaining in the trench. In terms of the resulting optical performance characteristics, BDTI structures with voids are generally inferior to BDTI structures without voids.

[0027] According to some aspects of the present invention, a narrower BDTI structure without voids is obtained by using a second mask and etching in the pattern of the BDTI trench structure. The second mask and etching form a second trench. The second trench passes through the passivation layer directly above the area where the first trench is formed. The second trench extends into the first trench. In some embodiments, etching the second trench removes some portions of the passivation layer deposited in the first trench. In some embodiments, an etch stop layer is deposited immediately before the passivation layer to facilitate controlling the endpoint of etching the second trench. The second trench is filled with metal to form a substrate embedded metal grid.

[0028] In some embodiments, the reticle used to pattern the first mask used to define the first trench is used again to pattern the second mask used to define the second trench. In some embodiments, the second trench is wider than the first trench. In some embodiments, the second trench has the same width as the first trench. In some embodiments, the second trench is narrower than the first trench. The trench width can be controlled by varying the patterning conditions (e.g., by varying the photoresist exposure time). Making the second trench wider facilitates filling the trench without creating voids. Making the second trench narrower improves quantum efficiency.

[0029] In some embodiments, the BDTI structure can be further narrowed by filling the bottom portion of the first trench with an underfill material prior to forming the passivation layer. Filling the bottom portion of the first trench in this manner allows the aspect ratio of the substrate-embedded metal grid to remain constant (even if the first trench becomes deeper or narrower). In some embodiments, filling the bottom portion of the first trench with an underfill material includes depositing the underfill material in the first trench followed by an etching process such that the underfill material is recessed in the trench. In some embodiments, the underfill material is a non-metallic material. An etch stop layer may be deposited after depositing the underfill material and recessing the underfill material.

[0030] The image sensor formed by the method of the present invention can have excellent quantum efficiency and unique structural features. One such feature is that the substrate-embedded metal grid cuts through the passivation layer. Although the passivation layer can be formed by a non-conformal deposition process (whereby the passivation layer is only very thinly deposited in the first trench), it is inevitable that at least a thin coating of the passivation layer is deposited in the first trench. Therefore, the passivation layer is typically continuous along the sides of the metal grid and under the substrate-embedded metal grid. According to the second trench of the present invention, the passivation layer is etched through the passivation layer and the passivation layer can be completely removed from the first trench. When the substrate-embedded metal grid is formed, the substrate-embedded metal grid fills the second trench and extends into the semiconductor substrate located below the passivation layer, whereby the metal grid passes through the passivation layer.

[0031] In some embodiments, a unique feature of the BDTI structure is that the BDTI structure has a metal core that undergoes a step-change in width. The step-change in width occurs over the back side of the semiconductor substrate. In some embodiments, the step-change in width occurs below the base of the intermediate passivation layer and over the back side of the semiconductor substrate.

[0032] In some embodiments, a unique feature of the BDTI structure is that the BDTI structure has a core that includes a lower grid directly below a substrate-embedded metal grid. In some embodiments, the substrate-embedded metal grid and the lower grid are separated by an etch stop layer. In some embodiments, the lower grid is completely below the back side of the semiconductor substrate. The sides and bottom of the lower grid can be separated from the semiconductor substrate by a trench liner dielectric. In some embodiments, the lower grid is encapsulated by the trench liner dielectric and the etch stop layer, or if the etch stop layer is omitted, the lower grid is encapsulated by the trench liner dielectric and the metal grid.

[0033] Figure 1A A cross section of an IC device 100A as an image sensor according to some aspects of the present invention is shown. The IC device 100A includes a first semiconductor substrate 107 having a front side 108, a back side 101, an image sensing region 114, a peripheral region 112A, and a peripheral region 112B. A light detector 126 may be disposed in the image sensing region 114, and a contact pad 103 may be disposed in the peripheral region 112B.

[0034] Photodetector 126 may include a photodiode or similar device formed in first semiconductor substrate 107. Floating diffusion 123 may be coupled to photodetector 126 via transfer gate 122. There may be one floating diffusion 123 for each photodetector 126. Alternatively, each floating diffusion 123 may serve two or four adjacent photodetectors 126. Certain transistors may be associated with photodetector 126. Transfer gate 122 is shown. Other transistors that may be associated with photodetector 126 include select gates, reset gates, and the like.

[0035] Microlenses 147 may be disposed directly above photodetector 126. When light travels from microlenses 147 to photodetector 126, the light passes through color filter 146, upper passivation layer 138, and middle passivation layer 137. Upper passivation layer 138 and middle passivation layer 137 suppress reflection. Composite grid 149 at the height of the color filter helps divide the light among photodetector 126.

[0036] BDTI structure 134A disposed directly below composite grid 149 includes segments 135 extending from backside 101 into first semiconductor substrate 107 between adjacent photodetectors 126. BDTI structure 134A includes substrate-embedded metal grid 133A. The term "substrate-embedded" is used to emphasize the distinction from backside metal grid 141, which is a portion of composite grid 149 that is completely above backside 101 of first semiconductor substrate 107. In some embodiments, substrate-embedded metal grid 133A is allowed to float, which simplifies processing. In some embodiments, substrate-embedded metal grid 133A is grounded or connected to a voltage source to provide a bias voltage.

[0037] Figure 1B supply Figure 1A Shown is an expanded view of a portion of BDTI structure 134A. Figure 1C Provide along Figure 1B 1. A plan view taken along line CC' is shown. It should be understood that the illustration exaggerates the size of BDTI structure 134A compared to the size of light detector 126 to show the details of BDTI structure 134A. In some embodiments, BDTI structure 134A occupies about 20% or less of image sensing area 114. In some embodiments, BDTI structure 134A occupies about 10% or less of image sensing area 114.

[0038] BDTI structure 134A includes dielectric liner 131 and core 171. Core 171 includes substrate-embedded metal grid 133A and lower grid 175 located directly below substrate-embedded metal grid 133A. Substrate-embedded metal grid 133A and lower grid 175 each laterally surround photodetector 126. With respect to the orientation used in the drawings, substrate-embedded metal grid 133A is uppermost. In this orientation, backside 101 is facing upward.

[0039] The substrate-embedded metal grid 133A includes an upper portion 179 and a lower portion 177. The lower portion 177 is embedded in the first semiconductor substrate 107. The upper portion 179 is located above the back side 101 and cuts through the intermediate passivation layer 137 and the upper passivation layer 138. The etch stop layer 181 extends above the back side 101 below the intermediate passivation layer 137 and descends into the first semiconductor substrate 107 to below the substrate-embedded metal grid 133A. At or just below the base of the intermediate passivation layer 137, at a height above the back side 101, the substrate-embedded metal grid 133A undergoes a step change from a first width W1 to a second width W2.

[0040] The lower grid 175 is completely embedded in the first semiconductor substrate 107 and is located between the substrate-embedded metal grid 133A and the front side 108. The dielectric liner 131 extends over the back side 101 below the intermediate passivation layer 137 and the etch stop layer 181, descends into the first semiconductor substrate 107, reaches below the substrate-embedded metal grid 133A and the lower grid 175, and laterally separates the substrate-embedded metal grid 133A and the lower grid 175 from the first semiconductor substrate 107. The dielectric liner 131 and the etch stop layer 181 together encapsulate the lower grid 175.

[0041] The dielectric liner 131 is transparent and includes one or more layers formed of any suitable dielectric. In some embodiments, the dielectric liner 131 includes one or more layers formed of a dielectric exhibiting a fixed negative charge. Examples of dielectrics exhibiting a fixed negative charge include hafnium oxide (HfO 2 ), aluminum oxide (AlO) and the like. In some embodiments, the dielectric liner 131 includes a first dielectric layer 128 and a second dielectric layer 129. For example, the first dielectric layer 128 may be aluminum oxide (AlO) or the like, and the second dielectric layer 129 may be hafnium oxide (HfO 2 ) or similar materials. In some embodiments, the first dielectric layer 128 has a thickness ranging from about 20 angstroms to about 100 angstroms, such as about 40 angstroms. In some embodiments, the second dielectric layer 129 has a thickness ranging from about 30 angstroms to about 200 angstroms, such as about 60 angstroms. In some embodiments, the dielectric liner 131 has a thickness generally ranging from about 50 angstroms to about 200 angstroms, such as about 100 angstroms.

[0042] The etch stop layer 181 is also transparent and may include one or more layers of any suitable material. In some embodiments, the etch stop layer 181 includes one or more layers of a dielectric exhibiting a fixed negative charge. In some embodiments, the etch stop layer 181 has the same composition as one of the layers in the dielectric liner 131. For example, the etch stop layer 181 may be aluminum oxide (AlO) or a similar material. In some embodiments, the thickness of the etch stop layer 181 is about 100 angstroms or less.

[0043] The middle passivation layer 137 and the upper passivation layer 138 are much thicker than the dielectric liner 131 or the etch stop layer 181. The upper passivation layer 138 can be any suitable material that is transparent and has a relatively low refractive index. Possible suitable materials include silicon dioxide (SiO 2 ), silicon nitride (SiN), hafnium oxide (HfO 2 ), titanium dioxide (TiO 2) and similar materials. In some embodiments, the upper passivation layer 138 is or includes silicon dioxide (SiO 2 ) or similar materials. In some embodiments, the upper passivation layer 138 has a thickness ranging from about 300 angstroms to about 2500 angstroms, such as about 500 angstroms.

[0044] The middle passivation layer 137 is a transparent material having a refractive index between the refractive index of the upper passivation layer 138 and the refractive index of the first semiconductor substrate 107. Possible suitable materials include tantalum pentoxide, silicon nitride (SiN), hafnium oxide (HfO 2 ), aluminum oxide (AlO), titanium dioxide (TiO 2 ) or similar materials. In some embodiments, the middle passivation layer 137 is tantalum pentoxide or similar materials. In some embodiments, the middle passivation layer 137 has a thickness ranging from about 300 angstroms to about 2500 angstroms, such as about 500 angstroms. The thickness of the middle passivation layer 137 and the thickness of the upper passivation layer 138 can vary relative to the wavelength of light aimed at the IC device 100A.

[0045] The lower grid 175 of the core 171 can be any suitable material. In some embodiments, the lower grid 175 is a metal. The metal can be the same as the metal of the substrate-embedded metal grid 133A. Metal has high reflectivity and can improve quantum efficiency. In some embodiments, the lower grid 175 is a non-metal. Non-metals can be better suited for the process of forming the lower grid 175. In some embodiments, the lower grid 175 is transparent and has a lower refractive index than the first semiconductor substrate 107. In some embodiments, the lower grid 175 is a dielectric. Examples of materials that may be suitable include silicon dioxide (SiO 2 ), silicon nitride (SiN), hafnium oxide (HfO 2 ), aluminum oxide (AlO), titanium dioxide (TiO 2 ) and similar materials. In some embodiments, the lower grid 175 is or includes silicon dioxide (SiO 2 ) or similar materials.

[0046] The substrate embedded metal grid 133A can be any suitable metal. In some embodiments, the substrate embedded metal grid 133A is or includes aluminum (Al), tungsten (W), or a similar material. Aluminum and tungsten have the advantage of being easily deposited in high aspect ratio openings. In some embodiments, the substrate embedded metal grid 133A includes tungsten (W) or a similar material. Tungsten (W) is particularly suitable for deposition in high aspect ratio openings. In some embodiments, the substrate embedded metal grid 133A includes aluminum (Al) or a similar material. Aluminum (Al) has the advantage of high electrical conductivity.

[0047] BDTI structure 134A passes through upper passivation layer 138, through middle passivation layer 137, and into first semiconductor substrate 107 to within a distance D1 of front side 108. In some embodiments, distance D1 is in a range from zero to about 2 microns. In some embodiments, distance D1 is in a range from 0.5 microns to about 1.5 microns, such as about 1 micron. Proximity of BDTI structure 134A to front side 108 reduces crosstalk between photodetectors 126. Spacing BDTI structure 134A from front side 108 allows structures such as floating diffusion region 123 to be formed directly below segment 135.

[0048] First semiconductor substrate 107 has a thickness suitable for light detector 126. In some embodiments, first semiconductor substrate 107 has a thickness ranging from about 2 microns to about 5 microns. In some embodiments, first semiconductor substrate 107 has a thickness ranging from about 3 microns to about 3.5 microns. In some embodiments, BDTI structure 134A extends into first semiconductor substrate 107 to a depth ranging from about 1.5 microns to about 3.5 microns. In some embodiments, BDTI structure 134A extends into first semiconductor substrate 107 to a depth ranging from about 2 microns to about 3 microns.

[0049] The lower grid 175 may have a height selected to limit the aspect ratio of the substrate-embedded metal grid 133A. The lower grid 175 may be located anywhere from no height difference with the core 171 to about 50% of the height of the core 171. In some embodiments, the lower grid 175 is located about 10% to about 30% of the height of the core 171. In some embodiments, the aspect ratio of the substrate-embedded metal grid 133A ranges from about 10:1 to about 30:1. In some embodiments, the aspect ratio of the substrate-embedded metal grid 133A ranges from about 15:1 to about 25:1. The aspect ratio may be calculated as the ratio of the height of the substrate-embedded metal grid 133A to its width at its narrowest point above the back side 101 (e.g., about W2).

[0050] Figure 2A and Figure 2B 1 is a cross-sectional view and a plan view showing an IC device 100B including a BDTI structure 134B. The BDTI structure 134B has a substrate-embedded metal grid 133B having a size similar to that of the substrate-embedded metal grid 133B. Figure 1B and Figure 1C The BDTI structures 134A shown in FIG. 1 are of different sizes. Figure 1B and Figure 1CIn the BDTI structure 134A shown in FIG. 1 , the width W1 of the upper portion 179 is greater than the width W2 of the lower portion 177 and may be similar to the width W3 of the trench in the first semiconductor substrate 107 in which the BDTI structure 134A is formed. Figure 2A and Figure 2B In the BDTI structure 134B shown, the width W1 of the upper portion 179 is less than the width W3 of the lower portion 177 and can be close to the width W2 of the lower portion 177. Making the width W1 of the upper portion 179 smaller increases the quantum efficiency. In some embodiments, the width W1 is within about 10% of the width W2. In some embodiments, the width W1 is within about 5% of the width W2.

[0051] Figure 3A and Figure 3B 1 is a cross-sectional view and a plan view showing an IC device 100C including a BDTI structure 134C. The BDTI structure 134C has a substrate-embedded metal grid 133C having a substrate-embedded metal grid 133C. Figure 2A and Figure 2B 135, but has an asymmetry caused by the manufacturing process. The asymmetry causes the trench 303 in the intermediate passivation layer 137 filled by the upper portion 179 of the substrate-embedded metal grid 133C to be offset relative to the trench 305 in the semiconductor substrate 107 filled by the BDTI structure 134C. Similarly, the upper portion 179 of the substrate-embedded metal grid 133C is offset relative to the lower portion 177 of the substrate-embedded metal grid 133C and other portions of the BDTI structure 134C located within the first semiconductor substrate 107. In some embodiments, the offset is such that a gap 301 exists between the substrate-embedded metal grid 133C and the etch stop layer 181 on one side of the segment 135. The gap 301 may be filled by the intermediate passivation layer 137, whereby a strip of the intermediate passivation layer 137 extends into the first semiconductor substrate 107.

[0052] Figure 4A and Figure 4B 1 is a cross-sectional view and a plan view showing an IC device 100D including a BDTI structure 134D. The BDTI structure 134D has a substrate-embedded metal grid 133D. Figure 2A and Figure 2B Substrate embedded metal grid 133B is shown to be similar, but narrower. The narrowing and alignment allows elongated strips 401 of intermediate passivation layer 137 to extend into first semiconductor substrate 107 on both sides of lower portion 177. Elongated strips 401 may surround photodetector 126.

[0053] Figure 5A and Figure 5B1 is a cross-sectional view and a plan view showing an IC device 100E including a BDTI structure 134E. The BDTI structure 134E is similar to the BDTI structure 134E except that the lower grid 175 of the BDTI structure 134A is completely absent from the BDTI structure 134E. Figure 1B and Figure 1C In contrast, BDTI structure 134E has a substrate-embedded metal grid 133E that extends through the height of BDTI structure 134E down to dielectric liner 131 .

[0054] Fig. 6A and Figure 6B 1 is a cross-sectional view and a plan view showing an IC device 100F including a BDTI structure 134F. The BDTI structure 134F is similar to the BDTI structure 134B except that the lower grid 175 of the BDTI structure 134B is completely absent from the BDTI structure 134F. Figure 4A and Figure 4B In contrast, BDTI structure 134F has a substrate-embedded metal grid 133F that extends through the height of BDTI structure 134F down to dielectric liner 131 .

[0055] return Figure 1A , the contact pads 103 may be disposed in the first semiconductor substrate 107 near the front side 108 and spaced apart from the back side 101 by the pad dielectric 102. The pad dielectric 102 may be covered by the encapsulation layer 145. Access from the back side 101 to the contact pads 103 may be provided by openings 165 extending through the encapsulation layer 145 and the pad dielectric 102. The encapsulation layer 145 may have a concave surface 167 that facilitates bonding to the contact pads 103 through the openings 165.

[0056] The composite grid 149 may be disposed directly above the BDTI structure 134A and between the color filters 146. The composite grid 149 may include a backside metal grid 141, a dielectric grid 142, and a hard mask grid 143. The encapsulation layer 145 may extend over the composite grid 149. The backside metal grid 141 has a grounding bar 141B extending into the first semiconductor substrate 107 in the peripheral region 112A to ground the backside metal grid 141.

[0057] In addition to the first semiconductor substrate 107 and the first metal interconnect 109, the IC device 100A may also include a second semiconductor substrate 111 and a second metal interconnect 110. A plurality of logic gates 113 may be disposed on the second semiconductor substrate 111. The second semiconductor substrate 111, the second metal interconnect 110, and associated devices may be fabricated separately from the first semiconductor substrate 107 and may provide image signal processing (ISP) circuitry, read and / or write circuitry, or other suitable circuitry for operation of the light detector 126.

[0058] The first metal interconnect 109 includes a first wire 121 and a first via 119 in a first interlayer dielectric 120. These may be arranged as a plurality of metallization layers, which may be referred to as M1 metallization layer, M2 metallization layer, etc. in order of distance from the first semiconductor substrate 107. The second metal interconnect 110 includes a second wire 115 and a second via 118 in a second interlayer dielectric 117.

[0059] Figures 7 to 30 is a cross-sectional view illustrating a method of forming an IC device 100A according to the present invention. Figures 7 to 30 , however, it should be understood that Figures 7 to 30 The structures shown in are not limited to the methods described, but can be independently separated from the methods described. Figures 7 to 30 Although described as a series of acts, it should be understood that in other embodiments, the order of the acts may be varied. Figures 7 to 30 Although a particular set of actions is shown and described, some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments. Figures 7 to 30 The illustrated method is described in terms of forming an IC device 100A, but the method and its variations may be used to form other IC devices according to the present invention.

[0060] like Figure 7As shown in the cross-sectional view 700, the method may begin by bonding a partially fabricated IC device 701 and a second IC device 703 together. Each of the IC device 701 and the second IC device 703 may have undergone a front-end-of-line (FEOL) process and a back-end-of-line (BEOL) process. In the IC device 701, the FEOL process provides the photodetector 126, the floating diffusion region 123, and the transfer gate 122. The BEOL process provides the first metal interconnect 109. In the second IC device 703, the FEOL process provides the logic gate 113 and similar structures and the BEOL process provides the second metal interconnect 110. Bonding occurs between the first metal interconnect 109 and the second metal interconnect 110. The bonding process may be a fusion bonding, a hybrid bonding, a similar bonding process, or some other suitable bonding process. After bonding, the first semiconductor substrate 107 may be thinned from the back side 101 to provide a substrate such as Figure 8 The structure shown in the cross-sectional view 800 is shown.

[0061] Each of the first semiconductor substrate 107 and the second semiconductor substrate 111 may be or include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a similar substrate, or some other suitable semiconductor substrate. In some embodiments, an etch stop layer 124 is disposed directly on the front side 108. The etch stop layer 124 is a dielectric and may be an oxide, a carbide, a nitride, or a similar material. Each of the first interlayer dielectric 120 and the second interlayer dielectric 117 may be or include silicon dioxide, a low-k dielectric, an extremely low-k dielectric, or a similar material. The first wiring 121, the first through hole 119, the second wiring 115, the second through hole 118, and the metal pad 163 may be or include copper (Cu), aluminum (Al), a similar material, or some other suitable metal. In some embodiments, the metal pad 163 is copper (Cu) or a similar material. The isolation structure 105 may be a shallow trench isolation structure, a field oxide, or any other suitable type of isolation structure. Photodetector 126, floating diffusion region 123, and transfer gate 122 may constitute an active pixel sensor with a pinned photodiode. More generally, photodetector 126 may be any type of photodetector.

[0062] Figures 9 to 15 The cross-sectional views 900 to 1500 are shown with Figure 8 The cross-sectional view 800 shown corresponds to area D. Fig. 9 As shown in the cross-sectional view 900, a mask 903 may be formed on the back side 101 by photolithography or some other process and the mask 903 may be used to etch a trench 901 having a width W3 in the first semiconductor substrate 107. After etching the trench 901, the mask 903 may be stripped off.

[0063] like Fig.10 As shown in the cross-sectional view 1000, a first dielectric layer 128, a second dielectric layer 129, and a lower fill layer 1001 may be deposited in sequence. The first dielectric layer 128 and the second dielectric layer 129 may be deposited by a conformal deposition process and provide a dielectric liner 131. The conformal deposition process may be physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), a similar process, or some other suitable process. The lower fill layer 1001 may be deposited by a process that effectively fills a high aspect ratio opening. The process may be PVD, CVD, ALD, a similar process, or some other suitable process. In some embodiments, the process is plasma enhanced chemical vapor deposition. In some embodiments, the lower fill layer 1001 is or includes silicon dioxide.

[0064] like Fig.11 As shown in the cross-sectional view 1100, an etching process may be performed to remove the lower fill layer 1001 except for a portion that is recessed in the trench 901 and provides the lower grid 175. The etching process may be any suitable etching process. In some embodiments, the etching process is a wet etch or similar etching process. The wet etch may be advantageous in providing selectivity for removing the material of the lower fill layer 1001 that is located above the second dielectric layer 129.

[0065] like Fig.12 As shown in the cross-sectional view 1200, the etch stop layer 181, the middle passivation layer 137 and the upper passivation layer 138 may be deposited in sequence. The deposition process may include PVD, CVD, ALD, similar deposition processes, or any other suitable process. A portion of the middle passivation layer 137 is deposited in the trench 901. In some embodiments, the upper passivation layer 138 is deposited to a thickness ranging from about 500 angstroms to about 2000 angstroms (e.g., about 1000 angstroms).

[0066] like Fig.13As shown in the cross-sectional view 1300, a mask 1303 is formed and used to etch a trench 1301 having a width W4 through the upper passivation layer 138 and the intermediate passivation layer 137. The trench 1301 extends into the trench 901 in the first semiconductor substrate 107 and stops on the etch stop layer 181. In some embodiments, the etching process removes the intermediate passivation layer 137 from the trench 901. The etching process may be a dry etch (e.g., plasma etch or the like). In some embodiments, the width W4 is greater than the width W3 of the trench 901. In some embodiments, the width W4 is approximately equal to the width W3. In some embodiments, the width W4 is less than the width W3. The trench 1301 may be formed by a photolithography process using the same photomask as the photolithography process used to form the trench 901. By controlling process conditions such as the photoresist exposure time, the relative width W4 of the trench 1301 may be varied relative to the width W3 of the trench 901.

[0067] like Fig.14 As shown in the cross-sectional view 1400, metal 1401 may be deposited in a manner to fill trench 1301 and the portion of trench 901 opened by the previous etching process. The metal may be deposited by PVD, CVD, ALD, electroplating, electroless plating, the like, or any other suitable process. The process may be adapted to fill high aspect ratio openings without creating voids.

[0068] like Fig.15 As shown in the cross-sectional view 1500 , a planarization process may be performed to define the substrate-embedded metal grid 133A from the metal 1401 . The planarization process may be chemical mechanical polishing (CMP), a similar process, or some other suitable process. The planarization process may thin the upper passivation layer 138 .

[0069] like Fig.16 As shown in the cross-sectional view 1600, Fig.15 An etch stop layer 139 is formed over the structure shown in the cross-sectional view 1500 . Fig.16 The cross-sectional view 1600 shown provides a Fig.15 1500 is a cross-sectional view of a wide view shown in FIG. 1500. The etch stop layer 139 may be silicon nitride (SiN), a similar material, or some other suitable transparent material. The etch stop layer 139 may be formed by PVD, CVD, ALD, a similar process, or any other suitable process. In some embodiments, the etch stop layer 139 has a thickness ranging from about 500 angstroms to about 1500 angstroms, for example, about 880 angstroms. The etch stop layer 139 isolates the substrate-embedded metal grid 133A from the backside metal grid 141. Such isolation is not required and the etch stop layer 139 may be omitted.

[0070] like Fig.17As shown in the cross-sectional view 1700, a mask 1703 may be formed and used to etch pad openings 1701 in the first semiconductor substrate 107 within the outer peripheral region 112B. The etching may stop on the isolation structure 105 formed on the front side 108. After etching, the mask 1703 may be stripped.

[0071] like Fig.18 As shown in the cross-sectional view 1800, Fig.17 A pad dielectric liner 104 is deposited over the structure shown in the cross-sectional view 1700. The pad dielectric liner 104 may be an oxide, a similar material, or some other suitable dielectric. In some embodiments, the pad dielectric liner 104 has a thickness ranging from about 2000 angstroms to about 5000 angstroms. The pad dielectric liner may be deposited by PVD, CVD, a similar process, or any other suitable process.

[0072] like Fig.19 As shown in the cross-sectional view 1900, a mask 1903 may be formed and used to etch an opening 1901 within the pad opening 1701. The metal pad 163 is exposed through the opening 1901. After etching, the mask 1903 may be stripped.

[0073] like Fig. 20 As shown in the cross-sectional view 2000, it can be Fig.19 A pad metal 2001 is deposited over the structure shown in the cross-sectional view 1900 (including within the opening 1901). Rather than completely filling the opening 1901, the pad metal 2001 may line the opening 1901, thereby leaving a slit 2003 in the pad metal 2001. The pad metal 2001 may be aluminum (Al), copper (Cu), a similar material, or any other suitable pad metal. The pad metal 2001 may be deposited by ALD, CVD, PVD, electroplating, electroless plating, or a similar process.

[0074] like Fig.21 As shown in the cross-sectional view 2100, a mask 2101 may be formed and used to define the contact pads 103 from the pad metal 2001. After etching, the mask 2101 may be stripped.

[0075] like Fig. 22 As shown in the cross-sectional view 2200, Fig.21A pad dielectric 2201 is deposited on the structure shown in the cross-sectional view 2100 to a thickness sufficient to fill the pad opening 1701. The pad dielectric 2201 can fill the slit 2003. The pad dielectric 2201 can be an oxide, a similar material, or another suitable dielectric. The pad dielectric 2201 can be deposited by PVD, CVD, a similar process, or any other suitable process or combination of processes.

[0076] like Fig.23 As shown in the cross-sectional view 2300, a mask 2301 may be formed and used to thin the pad dielectric 2201 in areas away from the contact pads 103. Fig.24 As shown in the cross-sectional view 2400, the mask 2301 is stripped, followed by planarization and / or additional etching to form the pad dielectric 102 from the pad dielectric 2201. This process advantageously provides a concave surface 167 for the pad dielectric 102. The planarization and / or additional etching may also remove portions of the pad dielectric 102 outside the pad opening 1701 and portions of the pad dielectric liner 104 outside the pad opening 1701.

[0077] like Fig.25 As shown in the cross-sectional view 2500, a mask 2501 may be formed and used to etch ground bar openings 2503 in the first semiconductor substrate 107 within the inner peripheral region 112A. The etching process may be plasma etching or the like. After etching, the mask 2501 may be stripped.

[0078] like Fig.26 As shown in the cross-sectional view 2600, it can be Fig.25 A composite grid stack 2609 is deposited over the structure shown in the cross-sectional view 2500. The composite grid stack 2609 may include a metal layer 2601, a dielectric layer 2603, and a hard mask layer 2605. The metal layer 2601 forms a ground bar 141B within the ground bar opening 2503, and a portion 141A of the backside metal grid 141 that connects the ground bar 141B to the rest of the backside metal grid 141 (see Figure 1A ). Metal layer 2601 may include any suitable metal or combination of metals. In some embodiments, metal layer 2601 is or includes tungsten (W) or a similar material. In some embodiments, metal layer 2601 includes a liner layer formed of titanium nitride (TiN), tantalum nitride (TaN), or a similar material. Dielectric layer 2603 may be silicon dioxide (SiO 2), similar materials, or any suitable dielectric. The hard mask layer 2605 can be a nitride, a carbide, a similar material, a combination thereof, or any other suitable hard mask material. These layers can be deposited by ALD, CVD, PVD, electroplating, electroless plating, a similar process, or a combination of any other suitable processes.

[0079] like Fig. 27 As shown in cross-sectional view 2700, mask 2701 may be formed and used to etch composite grid 149 from composite grid stack 2609. The etching removes the composite grid from above photodetector 126 and from above pad dielectric 102. The etching forms backside metal grid 141 from metal layer 2601, dielectric grid 142 from dielectric layer 2603, and hard mask grid 143 from hard mask layer 2605. After etching, mask 2701 may be stripped.

[0080] like Fig.28 As shown in the cross-sectional view 2800, Fig. 27 An encapsulation layer 145 is formed over the structure shown in the cross-sectional view 2700. The encapsulation layer 145 is conformal to the pad dielectric 102 and to the concave surface 167. The encapsulation layer 145 may be an oxide, a similar material, or some other suitable dielectric. Fig.29 As shown in cross-sectional view 2900 of FIG. 1 , color filter 146 may be formed in composite grid 149 over photodetector 126. Microlens 147 may be formed over color filter 146. Opening 165 may be etched through encapsulation layer 145 and pad dielectric 102 to expose contact pad 103 and generate Figure 1A The structure shown.

[0081] Fig.30 A flow chart of a process 3000 according to the present invention is presented, which process 3000 may be used to form an IC device according to the present invention. Fig.30 The process 3000 is shown and described herein as a series of actions or events, however it should be understood that the order in which such actions or events are shown should not be construed as having a limiting meaning. For example, some actions may occur in a different order and / or simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown are required to implement one or more aspects or embodiments described herein, and one or more of the actions shown herein may be performed in one or more separate actions and / or stages.

[0082] The process 3000 begins at act 3001, which is a FEOL process and a BEOL process. The FEOL process forms a photodetector in a first semiconductor substrate. The BEOL process forms a metal interconnect on the first semiconductor substrate. Figure 7 The illustrated IC device 701 provides an example of the resulting structure.

[0083] Action 3003 is to bond the first semiconductor substrate to the second semiconductor substrate. Figure 7 This process is shown. The process continues to act 3005 by thinning the first semiconductor substrate from the back side. Figure 8 An example of the resulting structure is provided. The second IC device is provided with structural integrity through a thinning process.

[0084] Action 3007 is to etch trenches in the back side of the BDTI structure. Fig. 9 An example is provided by the illustrated cross-sectional view 900. The trenches extend into the semiconductor substrate in the image sensing region and may include one or more trenches extending outside of the image sensing region.

[0085] Action 3009 is to deposit one or more dielectric layers to line the trenches. Fig.10 An example is provided by the cross-sectional view 1000 shown. The dielectric layer may be of a type having a fixed negative charge.

[0086] Actions 3011 and 3013 are optional steps that can be used to fill the lower portion of the trench. Action 3011 is depositing a lower fill material. Fig.10 An example is provided by the cross-sectional view 1000. Action 3013 is to perform an etch to recess the lower fill material within the trench. Fig.11 The cross-sectional view 1100 shown provides an example.

[0087] Action 3015 is depositing an etch stop layer. An etch stop layer is not necessary in some cases, in which case this step can be omitted. Action 3017 is depositing an intermediate passivation layer. Action 3019 is depositing an upper passivation layer. Fig.12 The cross-sectional view 1200 shown provides an example of the resulting structure.

[0088] Action 3021 is to form a second trench on the location of the first trench. The second trench passes through the upper passivation layer, through the middle passivation layer and extends into the first trench. Fig.13 The cross-sectional view 1300 shown provides an example of the resulting structure.

[0089] Action 3023 is to fill the second trench with metal to form a substrate embedded metal grid. The process may include depositing metal followed by planarization. Fig.14 and Fig.15 The cross-sectional views 1400 and 1500 shown provide examples.

[0090] Action 3031 is to form contact pads coupled to the front side conductive structures. Figures 17 to 24 The cross-sectional views 1700 to 2400 shown provide examples.

[0091] Action 3033 is to form a composite grid, color filters, and lenses on the back side. Figure 25 to Figure 29 The cross-sectional views 2500 to 2900 shown provide examples.

[0092] Some aspects of the present invention relate to an image sensor, the image sensor comprising: a photodetector located within a semiconductor substrate; an upper passivation layer located on a back side of the semiconductor substrate; and an intermediate passivation layer located between the upper passivation layer and the back side. The intermediate passivation layer has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer. A backside isolation structure extends into the backside to laterally surround the photodetector and includes a core. A dielectric liner separates the core from the semiconductor substrate. The core includes a substrate-embedded metal grid that passes through the intermediate passivation layer and extends into the semiconductor substrate.

[0093] In some embodiments, the intermediate passivation layer comprises tantalum pentoxide. In some embodiments, the substrate embedded metal grid undergoes a step change in width at the base of the intermediate passivation layer or between the base and the back side of the intermediate passivation layer. In some embodiments, there is an etch stop layer, which is located directly below the intermediate passivation layer and in direct contact with the intermediate passivation layer and is located directly below the substrate embedded metal grid and in direct contact with the substrate embedded metal grid. In some embodiments, the core includes a lower grid located below the substrate embedded metal grid. In some embodiments, the lower grid is separated from the substrate embedded metal grid by the etch stop layer. In some embodiments, the dielectric liner is one or more layers formed of a material exhibiting a fixed negative charge. In some embodiments, the substrate embedded metal grid passes through the upper passivation layer. In some embodiments, the upper portion of the substrate embedded metal grid extends through the upper passivation layer and forms a first grid, the lower portion of the substrate embedded metal grid is located within the semiconductor substrate and forms a second grid, and the first grid is laterally biased relative to the second grid. In some embodiments, the intermediate passivation layer is lowered into the semiconductor substrate, but not as deeply as the substrate-embedded metal grid. In some embodiments, the intermediate passivation layer is lowered into the semiconductor substrate only on one of the two opposite sides of the core in the space between the two photodetectors.

[0094] Some aspects of the present invention relate to an image sensor having photodetectors arranged in an array in a semiconductor substrate. A backside isolation structure extends into the semiconductor substrate between the photodetectors. The backside isolation structure includes a metal grid and a lower grid. The metal grid is embedded in the semiconductor substrate and extends through the back side of the semiconductor substrate. The lower grid is located between the metal grid and the front side. In some embodiments, the lower grid is non-metallic. In some embodiments, the metal grid cuts through a passivation layer located on the back side.

[0095] Some aspects of the present invention relate to a method comprising providing a semiconductor substrate having a peripheral region and light detectors located in an array in an image sensing region. Forming a first trench in a back side of the semiconductor substrate in a pattern of a grid having a plurality of segments located between the light detectors. Lining the first trench with a dielectric. Depositing a first passivation layer and a second passivation layer on the back side. Etching a second trench. The second trench extends through the second passivation layer, through the first passivation layer, and through the back side into the region of the first trench. Filling the second trench with a metal.

[0096] In some embodiments, the method further comprises depositing an etch stop layer on the back side after lining the first trench with the dielectric and before depositing the first passivation layer. The second trench stops on the etch stop layer. In some embodiments, the method further comprises: depositing a lower fill material into the first trench after lining the first trench with the dielectric; and etching to recess the lower fill material in the first trench before depositing the etch stop layer. In some embodiments, the second trench has a pattern of a grid but is smaller in width than the first trench. In some embodiments, forming the first trench comprises photolithographically patterning the first mask using a photomask and forming the second trench comprises photolithographically patterning the second mask using the same photomask. In some embodiments, the first trench and the second trench formed using one photomask have different widths.

[0097] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present invention.

Claims

1. An image sensor, characterized in that: include: A semiconductor substrate having a front side and a back side; a light detector located in the semiconductor substrate; an upper passivation layer located on the back side; an intermediate passivation layer located between the upper passivation layer and the back side, wherein the intermediate passivation layer has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer; as well as a backside isolation structure extending into the back side to laterally surround the photodetector, the backside isolation structure comprising a core and a dielectric liner between the core and the semiconductor substrate, The core includes a substrate-embedded metal grid that passes through the intermediate passivation layer and extends into the semiconductor substrate.

2. The image sensor according to claim 1, characterized in that: The substrate-embedded metal grid undergoes a step change in width at the base of the intermediate passivation layer or between the base and the back side of the intermediate passivation layer.

3. The image sensor according to claim 1, wherein: Also included is an etch stop layer, which is located directly below and in direct contact with the intermediate passivation layer and is located directly below and in direct contact with the substrate embedded metal grid.

4. The image sensor according to claim 1, wherein: The core includes a lower grid located below the substrate-embedded metal grid, wherein the lower grid is separated from the substrate-embedded metal grid by an etch stop layer.

5. The image sensor according to claim 1, wherein: The substrate embedded metal grid passes through the upper passivation layer, and an upper portion of the substrate embedded metal grid extends through the upper passivation layer and forms a first grid; A lower portion of the substrate-embedded metal grid is located within the semiconductor substrate and forms a second grid; and The first grid is laterally offset relative to the second grid.

6. The image sensor according to claim 1, wherein: The intermediate passivation layer descends into the semiconductor substrate, but not as deeply into the semiconductor substrate as the substrate-embedded metal grid.

7. The image sensor according to claim 1, wherein: In the space between two of the photodetectors, the intermediate passivation layer descends into the semiconductor substrate only on one of two opposite sides of the core.

8. An image sensor, characterized in that: include: A semiconductor substrate including a front side and a back side; Photodetectors are arranged in an array in the semiconductor substrate; as well as a backside isolation structure extending into the backside between the light detectors, The backside isolation structure includes a metal grid and a lower grid, wherein the metal grid is embedded in the semiconductor substrate and extends through the backside of the semiconductor substrate, and the lower grid is located between the metal grid and the frontside.

9. The image sensor according to claim 8, characterized in that: The lower grid is non-metallic.

10. The image sensor according to claim 8, wherein: Also included is a passivation layer on the back side, wherein the metal grid cuts through the passivation layer.

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