Electronic paper pixel structure for increasing pixel capacitance, electronic paper and display device

Abstract

The utility model discloses an electronic paper pixel structure capable of increasing pixel capacitance, electronic paper and a display device. A pixel unit comprises a pixel electrode A, a pixel electrode B, a com electrode, a thin film transistor, a grid electrode control line and a source electrode control line. The pixel electrode B is in electric signal connection with the drain terminal of the thin film transistor; the com electrode is communicated with a power ground electric signal; an insulating layer A is arranged between the pixel electrode A and the com electrode, and the pixel electrode A and the com electrode form a capacitor A; an insulating layer B is arranged between the pixel electrode B and the com electrode, and the pixel electrode B and the com electrode form a capacitor B; the insulating layer B comprises a groove, and the pixel electrode B is made of a conductive material covering the groove. By arranging the groove, the distance between the ITO layer and the COM layer is ingeniously reduced, and meanwhile the OC layer is reserved. And through the groove array, the pixel capacitance is increased, and meanwhile, the display driving defect caused by sinking of the ITO layer is avoided.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to an electronic paper pixel structure with increased pixel capacitance, and an electronic paper and a display device. Background Art

[0002] The electronic paper ink screen is a display screen made using electrophoretic display technology. The electronic paper ink screen display has the characteristics of ultra-low power consumption, low-frequency display, and power saving. It has a wide range of applications in price tags, advertising signs, and bus stops.

[0003] TFT electronic paper display screen achieves the effect of displaying images by driving electronic paper particles by continuously applying a driving waveform voltage to each pixel point through a driver IC chip. Each pixel point on the TFT electronic paper display screen is driven by a thin film transistor (Thin Film Transistor) integrated behind the pixel point. The TFT display includes an array substrate (TFTGlass), on which a pixel electrode layer (pixel ITO) corresponding to the electrode layer is arranged. The driving electric field of the electronic paper product is an electric field composed of the TFT capacitor charging and the electronic paper ITO. The size of the capacitance formed by the relative arrangement of the pixel electrode and the com electrode directly affects the performance of the display.

[0004] Conventional electronic paper products implement thin film transistors (TFT) and pixel electrodes (ITO) on glass. If 6-mask technology is used, it includes 6 layers, namely M1, ASI, M2, PV, ITO and OC layers. The M1 layer is metal1, and the M1 layer is used as GATE; ASI (full name in English is Amorphous Silicon; Chinese meaning is amorphous silicon), the ASI layer is used as a semiconductor layer; the M2 layer is metal2, and the M2 layer is used as a source source and a drain; PV (full name in English is Passivation; Chinese meaning is passivation layer), the PV layer is used as an insulating layer; ITO (full name in English is Indium Tin Oxide, Chinese meaning is indium tin oxide) is used as a pixel electrode layer. Among them, the material plated on the M1 layer and the M2 layer can be any one or combination of the existing technologies, such as molybdenum aluminum alloy or copper alloy, which is not limited in this application; generally follow the process of the panel manufacturing factory, so the M1 layer and the M2 layer are collectively referred to as M1 and M2, and they are not called alloy materials.

[0005] The film of the OC (overcoat) layer is a cured film protective layer. Because the OC film is a cured film protective layer of resin material spin-coated on the surface of the color filter film. On the one hand, it is used to improve the flatness and light transmittance of the color filter film surface, and at the same time, it is required to have good heat resistance and strength to protect the filter film from damage and increase its service life. At the same time, on the other hand, the OC (overcoat) layer is used to increase the distance between the pixel electrode and the data line to reduce the parasitic capacitance and improve the pixel voltage stability. There are also some electronic paper products without an OC layer. This type of electronic paper product is an optimized cost reduction solution.

[0006] In the technical solution with OC layer, the distance between ITO layer and COM layer increases due to the existence of OC layer, so the capacitance formed by ITO layer and COM layer will decrease due to the increase of distance. The decrease of capacitance will weaken the electric field effect ability accordingly, and the display effect will also be affected.

[0007] Glossary:

[0008] EPD is the abbreviation of "electronic paper display" in English, which means electronic paper display in Chinese.

[0009] TFT is the abbreviation of "Thin Film Transistor" in English, and its Chinese meaning is (thin film field effect transistor); in this application, it means that each pixel on the display is driven by a thin film transistor integrated therein, so that the screen information can be displayed at high speed, high brightness and high contrast.

[0010] ITO is the abbreviation of "Indium Tin Oxide" in English, and its Chinese meaning is indium tin oxide. In this application, electronic paper ITO refers to the conductive film layer material of the transparent conductive film shielding glass mainly being ITO (indium tin oxide semiconductor) film. Summary of the invention

[0011] The technical problem to be solved by the present invention is to avoid the problem that in the technical solution with an OC layer in the prior art, the distance between the ITO layer and the COM layer becomes larger due to the presence of the OC layer, and the capacitance formed by the two layers of the ITO layer and the COM layer is reduced due to the larger spacing. An electronic paper pixel structure that can increase the pixel capacitance in the presence of the OC layer is proposed. By setting the grooves, the distance between the ITO layer and the COM layer is cleverly reduced, while the OC layer is retained. And by the groove array, while increasing the pixel capacitance, the display drive defects caused by the sinking of the ITO layer are avoided.

[0012] The technical solution of the present application to solve the above-mentioned technical problems is an electronic paper pixel structure for increasing pixel capacitance, wherein the pixel unit includes a pixel electrode A, a pixel electrode B, a com electrode, a thin film transistor, a gate control line, and a source control line; the gate control line is electrically connected to the gate terminal of the thin film transistor; the source control line is electrically connected to the source terminal of the thin film transistor; the pixel electrode A is electrically connected to the drain terminal of the thin film transistor; the pixel electrode B is electrically connected to the drain terminal of the thin film transistor; the com electrode is electrically connected to the power ground; an insulating layer A is included between the pixel electrode A and the com electrode, and the pixel electrode A and the com electrode form a capacitor A; an insulating layer B is included between the pixel electrode B and the com electrode, and the pixel electrode B and the com electrode form a capacitor B; the insulating layer B includes a groove, and the pixel electrode B is composed of a conductive material covering the groove.

[0013] The insulating layer B includes two or more grooves, and the pixel electrode B is made of a conductive material covering the grooves.

[0014] The grooves are arranged in M ​​rows and N columns.

[0015] The pixel electrode A and the com electrode are stacked with the pixel electrode A, and the com electrode is located between the pixel electrode A and the pixel electrode B.

[0016] The pixel electrode A is electrically connected to the pixel electrode B through a via hole.

[0017] The pixel electrode B is composed of an ITO film.

[0018] The electronic paper pixel structure with increased pixel capacitance includes any one of the following technical features: Feature 11: The width range of the groove is less than 20um; Feature 12: The depth range of the groove is set according to the thickness of the OC layer and is consistent with the thickness of the OC layer; Feature 13: The cross-sectional area range of the groove is less than 400um^2. The groove depth range is the OC layer thickness, which is generally 5-6 times the PV layer thickness; different panel factories have different processes, so the depth range is not a fixed value, and the design needs to follow the panel factory process.

[0019] The electronic paper pixel structure with increased pixel capacitance includes any one of the following technical features: Feature 21: the com electrode is made of M2 material; Feature 22: the insulating layer A is made of SINX, i.e. silicon nitride material; Feature 23: the insulating layer B is made of SINX material; Feature 24: the pixel electrode A is made of ITO material.

[0020] The technical solution of the present application to solve the above technical problem may also be an electronic paper, including any of the above electronic paper pixel structures for increasing pixel capacitance.

[0021] The technical solution of the present application to solve the above technical problem may also be a display device, including the above electronic paper.

[0022] One of the beneficial effects of the technical solution in the present application is that the electronic paper pixel structure can increase the pixel capacitance under the condition of the OC layer. By setting the groove, the distance between the ITO layer and the COM layer is cleverly reduced, while the OC layer is retained.

[0023] The second beneficial effect of the technical solution in the present application is that, while increasing the pixel capacitance through a plurality of grooves, display driving defects caused by the sinking of the ITO layer are avoided.

[0024] The third beneficial effect of the technical solution in the present application is that, by means of the groove array, the pixel capacitance is further increased while avoiding display driving defects caused by the depression of the ITO layer.

[0025] One of the beneficial effects of the technical solution in the present application is that the pixel electrode A and the com electrode are arranged in layers with the pixel electrode A, and the com electrode is located between the pixel electrode A and the pixel electrode B. Such a structure is convenient for design and manufacturing.

[0026] One of the beneficial effects of the technical solution in the present application is that the pixel electrode A is connected to the pixel electrode B through the via electrical signal, which can further increase the pixel capacitance and improve the performance of the pixel.

[0027] One of the beneficial effects of the technical solution in the present application is that the pixel electrode B is composed of an ITO film, which is convenient for large-scale manufacturing.

[0028] One of the beneficial effects of the technical solution in the present application is that the width of the groove is set to be less than 20um, so that the width of a single groove is within a suitable range, achieving a balance between increasing the pixel capacitance and preventing the ITO film layer from sinking.

[0029] One of the beneficial effects of the technical solution in the present application is that the depth range of the groove is set according to the thickness of the OC layer and is consistent with the thickness of the OC layer, so that the depth of a single groove is within a suitable range, which can minimize the distance between the ITO film layer and the COM electrode and maximize the pixel capacitance.

[0030] One of the beneficial effects of the technical solution in the present application is that the cross-sectional area of ​​the groove is set within a range of less than 400um^2, and a balance is achieved between increasing the pixel capacitance and preventing the ITO film from sinking in both the horizontal width and the vertical length dimensions, so that the overall pixel capacitance increase effect is maximized and the probability of the ITO film sinking is reduced.

[0031] The beneficial effect 10 of the technical solution in the present application is that the com electrode is made of M2 material; feature 22; the insulating layer A is made of SINX, i.e. silicon nitride material, the insulating layer B is made of SINX material, and the pixel electrode A is made of ITO material. These materials are convenient for large-scale manufacturing, the cost is suitable, and the pixel capacitor performance is stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 1 is a schematic diagram of a top view of an electronic paper pixel structure with increased pixel capacitance;

[0033] Figure 2 1 is a schematic diagram of a cross-sectional structure of an electronic paper pixel structure with increased pixel capacitance;

[0034] Figure 3 This is one of the circuit principle schematic diagrams of the electronic paper pixel structure with increased pixel capacitance;

[0035] Figure 4 2 is a schematic diagram of a cross-sectional structure of an electronic paper pixel structure with increased pixel capacitance;

[0036] Figure 5 It is a schematic diagram of a cross-sectional structure of an electronic paper pixel structure in which the OC layer is hollowed out to increase the pixel capacitance, causing the ITO layer to sink;

[0037] Figure 6 2 is a schematic diagram of a top view of an electronic paper pixel structure with increased pixel capacitance;

[0038] Figure 7 3 is a schematic diagram of a cross-sectional structure of an electronic paper pixel structure with increased pixel capacitance;

[0039] Figure 8 4 is a schematic diagram of a cross-sectional structure of an electronic paper pixel structure with increased pixel capacitance;

[0040] Fig. 9 This is the circuit principle schematic diagram of the electronic paper pixel structure with increased pixel capacitance 2;

[0041] Fig.10 It is a schematic diagram of a top view of an electronic paper pixel structure in the prior art;

[0042] Fig.11 It is a schematic diagram of the cross-sectional structure of an electronic paper pixel structure in the prior art;

[0043] Fig.12 It is a schematic diagram of the cross-sectional structure of an electronic paper pixel structure in the prior art. DETAILED DESCRIPTION

[0044] The embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0045] It should be noted that the following is a description of the preferred embodiments of the present application, which does not constitute any limitation to the present application. The description of the preferred embodiments of the present application is only an explanation of the general principles of the present application. The embodiments described in this application are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0046] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", and technical features numbered with Arabic numerals 1, 2, 3, etc., and numbers such as "A" and "B", are only used for descriptive purposes and are only for the convenience of explanation, and do not represent a sequential relationship in time or space; they cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and numbered with Arabic numerals 1, 2, 3, etc. may explicitly or implicitly include one or more of the features. In the description of the present application, “several” means two or more than two, unless otherwise clearly and specifically defined.

[0047] like Figures 9 to 11 As shown, in the prior art, a pixel structure using 6-mask technology includes 6 layers, namely M1, ASI, M2, PV, ITO and OC layers. The M1 layer is used as GATE and pixel electrode A; the ASI layer is used as a semiconductor layer; the M2 layer is used as the source source, drain and common electrode com; the PV layer is used as an insulating layer; and the ITO layer is used as a pixel electrode layer. The OC layer is arranged below the ITO layer, which greatly increases the distance between the ITO layer and the M2 layer, making the capacitance constructed by the ITO layer and the M2 layer not large enough. In this application, the com electrode is composed of M2 material; the insulating layer A is composed of SINX, i.e., silicon nitride material; the insulating layer B is composed of SINX material; and the pixel electrode A is composed of ITO material.

[0048] like Figures 1 to 4As shown, in an embodiment of an electronic paper pixel structure for increasing pixel capacitance, the pixel unit includes a pixel electrode A, a pixel electrode B, a com electrode, a thin film transistor, a gate control line, and a source control line; the gate control line 1 is electrically connected to the gate terminal 11 of the thin film transistor; the source control line 4 is electrically connected to the source terminal 41 of the thin film transistor; the pixel electrode A is electrically connected to the drain terminal 71 of the thin film transistor; the pixel electrode B is electrically connected to the drain terminal 71 of the thin film transistor; the com electrode is electrically connected to the power ground; an insulating layer A is included between the pixel electrode A and the com electrode, and the pixel electrode A and the com electrode form a capacitor A; an insulating layer B is included between the pixel electrode B and the com electrode, and the pixel electrode B and the com electrode form a capacitor B; the insulating layer B includes a groove, and the pixel electrode B is composed of a conductive material covering the groove.

[0049] like Figure 1 In the figure, label 1 is the gate control line, label 4 is the source control line, label 3 is the com electrode connection line, label 5 is the source control line of the adjacent pixel; label 7 is the semiconductor ASI pattern, and label 20 is the OC hole position.

[0050] like Figure 2 In the figure, the pixel structure from top to bottom is ITO layer, i.e. pixel electrode B, OC layer, PV layer, com electrode, GI layer, pixel electrode A, a total of 6 layers are arranged on PI layer, i.e. glass substrate. Pixel electrode B and com electrode form capacitor B relative to each other, and pixel electrode A and com electrode form capacitor A relative to each other.

[0051] like Figure 3 In the figure, label 1 is the gate control line, label 4 is the source control line, label 11 is the gate terminal of the thin film transistor, label 41 is the source terminal of the thin film transistor, label 71 is the drain terminal of the thin film transistor, label 72 is the pixel electrode A, label 73 is the pixel electrode B, and label 80 is the com electrode; pixel electrode A72 and com electrode 80 form capacitor A, and pixel electrode B73 and com electrode 80 form capacitor B.

[0052] like Figure 4 In the pixel structure, from top to bottom, there are ITO layer, OC layer, PV layer, M2 layer, GI layer, and M1 layer, with a total of 6 layers arranged on the PI layer, i.e., the glass substrate. The ITO layer and the M2 layer relatively form a capacitor Cst2, i.e., capacitor B, and the M1 layer and the M2 layer relatively form a capacitor Cst1, i.e., capacitor A.

[0053] In order to increase the capacitance of the capacitor constructed by the ITO layer and the M2 layer, Figures 1 to 3As shown, the OC layer is hollowed out, that is, a groove is set on the OC layer to reduce the distance between the pixel electrode B and the com electrode, thereby increasing the capacitance of the capacitor B formed by the pixel electrode B and the com electrode. According to the capacitor capacitance determination formula C = εS / 4πkd, where ε is a constant, S is the facing area of ​​the capacitor plates, d is the distance between the capacitor plates, and k is the electrostatic force constant. For common parallel plate capacitors, the capacitance determination formula can be simplified to C = εS / d. ε is the dielectric constant of the medium between the plates, S is the plate area, and d is the distance between the plates. According to the above capacitance determination formula, if the spacing between the plates becomes 1 / 2 of the original, the capacitance of the capacitor B formed by the pixel electrode B and the com electrode becomes twice the original. In the present application, the spacing reduced by hollowing out the OC layer is obviously more than 1 / 2 of the original, and the corresponding capacitance of the capacitor B is also increased by more than 2 times. Such a structure greatly increases the capacitance of the capacitor B. Increasing the pixel capacitance improves the performance of the electronic ink screen.

[0054] The electronic paper pixel structure can also increase the pixel capacitance under the condition of OC layer. By setting the groove, the distance between the ITO layer and the COM layer is cleverly reduced while retaining the OC layer.

[0055] FPL (Front Plane Laminate in English, Front Panel Display in Chinese) refers to an electronic paper film filled with liquid and colored charged particles. When working, the com potential is applied to the upper side of the FPL, and the pixel electrode potential is applied to the lower side. The electric field formed can drive the colored charged particles to move. When particles of a certain color move to the top of the FPL under the action of the electric field, the display is completed. Figure 5 As shown in the figure, due to the hollowing out of the OC layer, the discontinuity in the film structure causes the ITO layer on the FPL to be suspended or deformed there, so the charged particles inside the FPL at that position are not driven by the electric field, and the final color displayed here on the same pixel electrode will be different from the surrounding color. Therefore, when the OC layer is hollowed out over a large area, it will cause a large discontinuity in the film structure of the backplane TFT, thereby affecting the driving of the FPL (the full name in English is Front Plane Laminate, and the Chinese name is Front Panel Display). Figure 5 As shown, when the OC layer is hollowed out over a large area, that is, the groove width on the OC layer is set too wide, it will cause the ITO layer to sink in the groove. Figure 5 The upper middle picture shows the normal state without hollowing out the OC layer; Figure 5 The middle and lower pictures show that after the OC layer is hollowed out, part of the ITO layer sinks into the hollowed-out part.

[0056] In order to further solve the above problems, Figures 6 to 9As shown, in an embodiment of an electronic paper pixel structure for increasing pixel capacitance, the insulating layer B includes two or more grooves, and the pixel electrode B is composed of a conductive material covering the grooves. By providing multiple grooves, the sinking of the ITO layer caused by a single groove can be alleviated, avoiding subsequent problems caused by large-area sinking.

[0057] like Figure 6 and Fig.10 In the figure, label 1 is the gate control line, label 4 is the source control line, label 2 is the gate control line of the adjacent pixel, label 3 is the com electrode connection line, label 5 is the source control line of the adjacent pixel; label 6 is the drain, label 7 is the semiconductor ASI pattern, label 8 is the pixel electrode ITO pattern, and label 9 is the contact hole pattern.

[0058] like Figure 6 In the figure, reference numeral 21 is the first OC hole position, reference numeral 22 is the second OC hole position, reference numeral 23 is the third OC hole position, reference numeral 24 is the fourth OC hole position, reference numeral 25 is the fifth OC hole position, and reference numeral 26 is the sixth OC hole position. Each OC hole position corresponds to a groove. The width range of the groove is less than 20um (micrometer); the depth range of the groove is set according to the thickness of the OC layer and is consistent with the thickness of the OC layer; the cross-sectional area range of the groove is less than 20um×20um.

[0059] like Figures 6 to 9 As shown, in an embodiment of an electronic paper pixel structure for increasing pixel capacitance, the insulating layer B includes two or more grooves, and the pixel electrode B is composed of a conductive material covering the grooves. Multiple grooves are used to increase pixel capacitance while avoiding display driving defects caused by the sinking of the ITO layer.

[0060] like Figures 6 to 9 As shown in the embodiment of the electronic paper pixel structure for increasing pixel capacitance, the grooves are arranged in M ​​rows and N columns. Through the groove array, the pixel capacitance is further increased while avoiding the display driving defects caused by the sinking of the ITO layer.

[0061] like Fig. 9In the figure, reference numeral 1 is a gate control line, reference numeral 4 is a source control line, reference numeral 11 is a gate terminal of a thin film transistor, reference numeral 41 is a source terminal of a thin film transistor, reference numeral 71 is a drain terminal of a thin film transistor, reference numeral 221 is a first capacitor formed by a pixel electrode B on a first OC hole and a com electrode 80; reference numeral 222 is a second capacitor formed by a pixel electrode B on a second OC hole and a com electrode 80; reference numeral 223 is a third capacitor formed by a pixel electrode B on a third OC hole and a com electrode 80; reference numeral 224 is a fourth capacitor formed by a pixel electrode B on a fourth OC hole and a com electrode 80; reference numeral 225 is a fifth capacitor formed by a pixel electrode B on a fifth OC hole and a com electrode 80; reference numeral 226 is a sixth capacitor formed by a pixel electrode B on a sixth OC hole and a com electrode 80. A 2×3 capacitor array such as the first capacitor and the sixth capacitor is connected in parallel to form a comprehensive large-capacitance capacitor B.

[0062] like Figures 1 to 8 As shown, in the embodiment of the electronic paper pixel structure for increasing pixel capacitance, the pixel electrode A and the com electrode and the pixel electrode A are stacked, and the com electrode is located between the pixel electrode A and the pixel electrode B. The pixel electrode A and the com electrode and the pixel electrode A are stacked, and the com electrode is located between the pixel electrode A and the pixel electrode B. Such a structure is convenient for design and manufacturing.

[0063] like Figures 6 to 9 As shown, in the embodiment of the electronic paper pixel structure with increased pixel capacitance, the pixel electrode A is electrically connected to the pixel electrode B through a via hole, which can further increase the pixel capacitance and improve the performance of the pixel.

[0064] like Figures 1 to 8 As shown, in the embodiment of the electronic paper pixel structure for increasing the pixel capacitance, the pixel electrode B is formed by an ITO film, which is convenient for large-scale manufacturing.

[0065] In some embodiments of the electronic paper pixel structure for increasing pixel capacitance that are not shown in the accompanying drawings, the width range of the groove is less than 20um (micrometer); the width of the groove is set in the range of less than 20um (micrometer) so that the width of a single groove is within a suitable range, achieving a balance between increasing the pixel capacitance and preventing the ITO film layer from sinking.

[0066] In some embodiments of the electronic paper pixel structure for increasing pixel capacitance that are not shown in the accompanying drawings, the depth range of the groove is set according to the thickness of the OC layer and is consistent with the thickness of the OC layer; the depth range of the groove is set to be less than 20um×20um, so that the depth of a single groove is within a suitable range, which can minimize the distance between the ITO film layer and the COM electrode and maximize the pixel capacitance.

[0067] In some embodiments of the electronic paper pixel structure for increasing pixel capacitance that are not shown in the accompanying drawings, the cross-sectional area of ​​the groove is less than 400um^2. The cross-sectional area of ​​the groove is set within the range of less than 400um^2, and a balance is achieved between increasing the pixel capacitance and preventing the ITO film from sinking in both the horizontal width and the vertical length, so that the overall pixel capacitance increase benefit is maximized and the probability of the ITO film sinking is reduced.

[0068] In some embodiments of the electronic paper pixel structure for increasing pixel capacitance that are not shown in the accompanying drawings, the com electrode is composed of M2 material; the insulating layer A is composed of SINX, i.e., silicon nitride material; Feature 23: the insulating layer B is composed of SINX material; and the pixel electrode A is composed of ITO material.

[0069] These materials are easy to manufacture on a large scale, are cost-effective, and have stable pixel capacitor performance.

[0070] Some electronic paper embodiments not shown in the drawings include: the electronic paper pixel structure with increased pixel capacitance as described above.

[0071] Some embodiments of the display device not shown in the drawings include the electronic paper described above.

[0072] In the prior art technical solution with an OC layer, the distance between the ITO layer and the COM layer becomes larger due to the presence of the OC layer, and the capacitance formed by the two layers becomes smaller due to the larger distance. The electronic paper pixel structure proposed in this application, which can increase the pixel capacitance while having an OC layer, can solve the above problem well. By setting the groove, the distance between the ITO layer and the COM layer is cleverly reduced, while retaining the OC layer.

[0073] For the design of increasing pixel capacitance by using a three-layer structure for the pixels of the electronic paper panel, in the 6-mask panel, the OC layer is usually hollowed out to achieve the effect of increasing pixel capacitance. However, hollowing out the OC layer over a large area will lead to a large discontinuity in the film layer structure of the backplane TFT, such as Figure 5 As shown. The change in structure will affect the drive of FPL. The driving ability is affected, which in turn causes abnormal display images. The present application also increases the pixel capacitance through the groove array while avoiding the display drive defects caused by the sinking of the ITO layer.

[0074] The invention proposes to dig multiple smaller holes in the OC layer in the CST area, with the diameter of the holes in the OC layer less than 20um and the spacing of the OC holes greater than 20um. Compared with conventional designs, this achieves the goal of both increasing pixel capacitance and ensuring display effects. That is, the width of the groove is less than 20um; the cross-sectional area of ​​the groove is less than 400um^2.

[0075] like Figures 10 to 12 , the conventional design of three-layer pixel capacitor structure, Cst film layer structure such as Fig.12 , the pixel capacitance is Cst1+Cst2. According to the capacitance calculation formula C=εS / d=εS / 4πkd, since the thickness of the OC layer is large, the Cst2 value is small, and the effect of increasing the pixel capacitance is very limited. Figure 1 , Cst film structure such as Figure 4 If the hole in the OC layer is too large, the FPL and OC layers will have a large gap, which may cause the following problems: Figure 5 The condition shown causes the display to be abnormal.

[0076] The new design proposed in the proposal of the present invention digs multiple holes in the OC layer above the pixel capacitor, achieving the purpose of both increasing the pixel capacitance and ensuring the display effect. The schematic diagram of the pixel structure is shown in the figure. Figure 6 , Cst film structure such as Figure 6 , the Cst2 value at the hole is improved. Taking the pixel structure with a size of 135um×135um as an example, the Cst1 formed by the drain M1 and the common electrode M2, and the Cst2 formed by the pixel electrode ITO and the common electrode M2 ​​are both 8100um^2. The new design will dig 6 20um×20um OC holes, so that the Cst2 area with increased capacitance is 2400um^2. If the thickness of the GI layer and the PV layer is set to 3000A, the dielectric constant is 6, the thickness of the OC layer is 1.7um, and the dielectric constant is 3, then the pixel Cst of the conventional design is about 1.55pf, and the pixel Cst of the new design is about 1.94pf, which is an increase of 25.3%.

[0077] like Figures 1 to 9 As shown, the above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An electronic paper pixel structure with increased pixel capacitance, characterized in that: The pixel unit includes a pixel electrode A, a pixel electrode B, a com electrode, a thin film transistor, a gate control line, and a source control line; The gate control line is electrically connected to the gate terminal of the thin film transistor; The source control line is electrically connected to the source terminal of the thin film transistor; The pixel electrode A is electrically connected to the drain terminal of the thin film transistor; The pixel electrode B is electrically connected to the drain terminal of the thin film transistor; The com electrode is in electrical signal communication with the power supply ground; An insulating layer A is included between the pixel electrode A and the com electrode, and the pixel electrode A and the com electrode form a capacitor A; An insulating layer B is included between the pixel electrode B and the com electrode, and the pixel electrode B and the com electrode form a capacitor B; The insulating layer B includes a groove, and the pixel electrode B is made of a conductive material covering the groove.

2. The electronic paper pixel structure with increased pixel capacitance according to claim 1, characterized in that: The insulating layer B includes two or more grooves, and the pixel electrode B is made of a conductive material covering the grooves.

3. The electronic paper pixel structure with increased pixel capacitance according to claim 2, characterized in that: The grooves are arranged in M ​​rows and N columns.

4. The electronic paper pixel structure with increased pixel capacitance according to claim 1, characterized in that: The pixel electrode A and the com electrode are stacked with the pixel electrode A, and the com electrode is located between the pixel electrode A and the pixel electrode B.

5. The electronic paper pixel structure with increased pixel capacitance according to claim 1, characterized in that: The pixel electrode A is electrically connected to the pixel electrode B through a via hole.

6. The electronic paper pixel structure with increased pixel capacitance according to claim 1, characterized in that: The pixel electrode B is composed of an ITO film.

7. The electronic paper pixel structure for increasing pixel capacitance according to claim 1, characterized in that: Include any of the following technical features: Feature 11: The width of the groove is less than 20um; Feature 12: The depth range of the groove is set according to the thickness of the OC layer and is consistent with the thickness of the OC layer; Feature 13: The cross-sectional area of ​​the groove is less than 400um2.

8. The electronic paper pixel structure with increased pixel capacitance according to claim 1, characterized in that: Include any of the following technical features: Feature 21: The com electrode is made of M2 material; Feature 22: The insulating layer A is composed of SINX, i.e., silicon nitride material; Feature 23: The insulating layer B is made of SINX material; Feature 24: The pixel electrode A is made of ITO material.

9. An electronic paper, characterized in that: include: An electronic paper pixel structure with increased pixel capacitance as claimed in any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the electronic paper as claimed in claim 9.

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