Main and standby switching control system for emergency frequency modulation of energy storage supporting power grid

Abstract

The embodiment of the utility model provides a main / standby switching control system for emergency frequency modulation of an energy storage support power grid, which uses two same control panels which are opposite to each other to crossly monitor output signals of the opposite side, automatically completes switching of the main control panel and the standby control panel between the two control panels when a fault occurs, and improves the frequency modulation efficiency of the main control panel and the standby control panel. Or the main control board and the standby control board are manually determined between the two control boards through processor instructions. Based on consideration of fault-tolerant requirements, hardware configuration adopts 1 + 1 redundancy design, when software and hardware faults occur in a main control system, the system still needs to work normally, a main control panel and a standby control panel are arranged, and a double-main-control hot standby fault-tolerant system is constructed. When the main control board breaks down, the system automatically switches the main control board and the standby control board, the standby control board replaces the main control board to work, and normal operation of services is guaranteed.

Description

Technical Field

[0001] The utility model relates to the field of energy storage system fault tolerance, and in particular to a master-slave switching control system for energy storage to support emergency frequency modulation of a power grid. Background Art

[0002] Fault tolerance and high availability are two key technologies for reliable operation of equipment. The former is mainly used in fields that are highly sensitive to equipment failures, such as the aerospace field. It usually uses expensive equipment redundancy and strictly shields the underlying failures. The latter is mainly used in situations where high reliability needs to be guaranteed. Generally, the proportion of time that the equipment operates stably is used as a measurement indicator. Backup and switching are the basic means to ensure high availability of equipment. In order to improve the reliability of the system, the same module is generally connected in parallel. In this way, the system will only fail when all modules that make up the system fail. In actual applications, a 1+1 structure is generally used. When working, one module is active and one module is standby. The system output is active output. When the active module fails, the active and standby modules are switched.

[0003] In the process of implementing the utility model, the applicant found that there are at least the following problems in the prior art:

[0004] When the master fails, seamless, fast and automatic master-slave switchover is performed to achieve hot standby fault tolerance. Utility Model Content

[0005] The present invention provides a master-slave switching control system for energy storage supporting emergency frequency modulation of a power grid, which solves the problem of how to perform seamless, fast and automatic master-slave switching to achieve hot standby fault tolerance when a primary failure occurs.

[0006] To achieve the above-mentioned purpose, on the one hand, the embodiment of the utility model provides a master-standby switching control system for energy storage supporting emergency frequency modulation of power grid, and can also be a master-standby switching control system for energy storage emergency power supply master control, including: two identical control boards that are opposite to each other;

[0007] Each control board includes: a processor, a main-standby switching circuit unit, a reset circuit unit, a board-in-place signal generating circuit unit, a main signal input terminal for the board, a board-in-place signal input terminal, a board-standby main signal input terminal, a board-in-place signal output terminal, a board-in-place main signal output terminal, a board-in-place main signal output terminal, and a board-standby main signal output terminal;

[0008] The main signal input terminal, the in-place signal input terminal and the standby main signal input terminal of each control board are respectively connected to the main signal output terminal, the in-place signal output terminal and the standby main signal output terminal of another control board;

[0009] The board presence signal generating circuit unit of each control board is connected to the board presence signal output terminal of the control board, and is used for outputting the board presence signal of the control board;

[0010] The reset circuit unit of each control board is connected to the processor and the active / standby switching circuit unit, and is used to provide a reset signal of the control board to the processor and the active / standby switching circuit unit;

[0011] The processor of each control board is connected to the active / standby switching circuit unit and is used to output control signals and data bus signals to the active / standby switching circuit unit;

[0012] The master-slave switching circuit unit of each control board is connected with the master signal input terminal of the control board, the board in-place signal input terminal, the master signal input terminal of the board, the master signal output terminal of the current board, and the master signal output terminal of the current board, and is used for inputting the master signal of the current board, the board in-place signal, and the master signal of the current board, and outputting the master signal of the current board and the master signal of the current board;

[0013] The master-slave switching circuit unit of each control board is used to competitively determine the master signal of the control board with the other of the two control boards during the startup and reset of the master-slave switching control system; and, after the startup and reset of the master-slave switching control system is completed, determine the backup master signal and the master signal of the control board according to the instructions represented by the data bus signal output by the processor of the control board; and, after the startup and reset of the master-slave switching control system is completed, when the control board fails, switch the master signal of the control board to the standby state; and, after the startup and reset of the master-slave switching control system is completed, in response to the control board's main signal of the other board being switched to the standby state, switch the master signal of the control board to the master state.

[0014] The above technical solution has the following beneficial effects: by adopting a 1+1 redundant design, two control boards are used to cross-connect signals and monitor each other. When any of the control boards serving as the main control board fails, the system automatically performs a main-standby switch, and the control board currently serving as the standby control board takes over the main control board that currently fails and becomes the new main control board to continue working, thereby ensuring the normal operation of the system business; when it is necessary to manually switch the main and standby control boards, the processor can also issue instructions to manually control the system to switch the main and standby control boards between the two control boards, thereby providing both manual and automatic methods, allowing operation and maintenance personnel to perform flexible control. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 This is an architecture diagram of a master-slave switching control system for energy storage supporting emergency frequency modulation of a power grid according to an embodiment of the present invention;

[0017] Figure 2 It is a circuit principle diagram of the active / standby switching circuit unit according to an embodiment of the present invention.

[0018] The reference numerals are as follows: N1, first NOT gate; N2, second NOT gate; N3, third NOT gate; N4, fourth NOT gate; OR1, first OR gate; AND1, first AND gate; AND2, second AND gate; U1, D register; N5, fifth NOT gate; N6, sixth NOT gate; N7, seventh NOT gate; N8, eighth NOT gate; N9, ninth NOT gate; N10, tenth NOT gate; N11, eleventh NOT gate; N12, twelfth NOT gate; OR2, second OR gate; NOR1, first OR NOT gate; RST, reset signal of this board; rst_a, reset signal of opposite board; A1, in-place signal of opposite board; B1, in-place signal of this board; A2, main signal of opposite board; B2, main signal of this board; A3, main signal of opposite board; B3, main signal of this board. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0020] On the one hand, if Figure 1 As shown, the embodiment of the utility model provides a master-standby switching control system for energy storage supporting emergency frequency modulation of a power grid, comprising: two identical control boards that are opposite to each other;

[0021] Each control board includes: a processor, a main-standby switching circuit unit, a reset circuit unit, a board-in-place signal generating circuit unit, a main signal input terminal for the board, a board-in-place signal input terminal, a board-standby main signal input terminal, a board-in-place signal output terminal, a board-in-place main signal output terminal, a board-in-place main signal output terminal, and a board-standby main signal output terminal;

[0022] The main signal input terminal, the in-place signal input terminal and the standby main signal input terminal of each control board are respectively connected to the main signal output terminal, the in-place signal output terminal and the standby main signal output terminal of another control board;

[0023] The board presence signal generating circuit unit of each control board is connected to the board presence signal output terminal of the control board, and is used for outputting the board presence signal of the control board;

[0024] The reset circuit unit of each control board is connected to the processor and the active / standby switching circuit unit, and is used to provide a reset signal of the control board to the processor and the active / standby switching circuit unit;

[0025] The processor of each control board is connected to the active / standby switching circuit unit and is used to output control signals and data bus signals to the active / standby switching circuit unit;

[0026] The master-slave switching circuit unit of each control board is connected with the master signal input terminal of the control board, the board in-place signal input terminal, the master signal input terminal of the board, the master signal output terminal of the current board, and the master signal output terminal of the current board, and is used for inputting the master signal of the current board, the board in-place signal, and the master signal of the current board, and outputting the master signal of the current board and the master signal of the current board;

[0027] The master-slave switching circuit unit of each control board is used to competitively determine the master signal of the control board with the other of the two control boards during the startup and reset of the master-slave switching control system; and, after the startup and reset of the master-slave switching control system is completed, determine the backup master signal and the master signal of the control board according to the instructions represented by the data bus signal output by the processor of the control board; and, after the startup and reset of the master-slave switching control system is completed, when the control board fails, switch the master signal of the control board to the standby state; and, after the startup and reset of the master-slave switching control system is completed, in response to the control board's main signal of the other board being switched to the standby state, switch the master signal of the control board to the master state.

[0028] In some embodiments, the system includes: two identical control boards that are opposite to each other;

[0029] The input signals of each control board include: the main signal of the board, the in-position signal of the board and the main signal of the standby rise of the board; the output signals of each control board include: the main signal of the board, the in-position signal of the board and the main signal of the standby rise of the board;

[0030] The main signal, in-position signal and standby main signal of each control board are respectively connected to the main signal, in-position signal and standby main signal of another control board;

[0031] Each control board includes: a processor, a master-slave switching circuit unit, a reset circuit unit and a board presence signal generating circuit unit;

[0032] A board presence signal generating circuit unit of each control board, used for providing a board presence signal of the control board;

[0033] The reset circuit unit of each control board is used to output a reset signal as the reset signal of the control board, which is input to the processor and the main standby switching circuit unit of the control board;

[0034] The processor of each control board is used to output control signals and data bus signals to the active / standby switching circuit unit of the control board;

[0035] The input signals of the master-slave switching circuit unit of each control board include: the control board reset signal, the master signal of the opposite board, the in-position signal of the opposite board, the control signal of the processor and the data bus signal;

[0036] The output signal of the main-standby switching circuit unit of each control board includes: the main signal of the control board and the main signal of the standby switch of the control board;

[0037] The master-slave switching circuit unit of each control board is used to competitively determine the master signal of the control board with the other of the two control boards during the startup and reset of the master-slave switching control system; and, after the startup and reset of the master-slave switching control system is completed, determine the backup master signal and the master signal of the control board according to the instructions represented by the data bus signal output by the processor of the control board; and, after the startup and reset of the master-slave switching control system is completed, when the control board fails, switch the master signal of the control board to the standby state; and, after the startup and reset of the master-slave switching control system is completed, in response to the control board's main signal of the other board being switched to the standby state, switch the master signal of the control board to the master state.

[0038] In some embodiments, the master-slave switching circuit is used in occasions such as power and communication networks that have strict requirements on equipment, including but not limited to the field of energy storage emergency power supply master control or energy storage supporting power grid emergency frequency modulation. Single point failure is not allowed during operation. The equipment is generally equipped with two control boards, namely the master control board (Master) and the standby control board (Slave). Among them, the master control board, as the core of the control system, interacts with the outside and the business board to complete the normal functions of each module in the system; while the standby control board is only a backup of the master control board and has no direct interaction with the outside and the business board. When the master control board fails, the system automatically switches between the master and standby, and the standby control board takes over the work of the master control board to ensure the normal operation of the business. Based on the consideration of fault tolerance requirements, the hardware configuration adopts a 1+1 redundant design. When the main control system has a hardware or software failure, the system still needs to work normally. It is equipped with two master and standby control boards to build a dual master hot standby fault-tolerant system. When the master control board fails, the system automatically switches between the master and standby, and the standby control board takes over the work of the master control board to ensure the normal operation of the business. The main and standby switching system architecture diagram is as follows Figure 1 As shown. A1, A2, A3 are the master-slave switching signals input from the other board to this board, and B1, B2, B3 are the master-slave switching signals output from this board to the other board; the output signals are all pulled up on the other board (that is, the input signal of each control board is pulled up). The control board also provides an interface to communicate with the CPU (processor) for the CPU (processor) to detect the master-slave switching status information of the single board (control board) and control the master-slave switching of the single board. The following are the specific signal definitions. A1: Pair board in place signal, B1: This board in place signal; A2: Pair board main signal, B2: This board main signal; A3: Pair board standby upgrade main signal, B3: This board standby upgrade main board signal. The embodiment of the present invention can perform manual master-slave switching by sending instructions by the processor, and can also automatically perform master-slave switching in a fault state. The master-slave switching circuit unit of each control board is used to respond to the reset signal of the board and the master signal of the other board during the startup and reset of the master-slave switching control system, and competitively determine the master signal of the board of the control board with the other of the two control boards; and, after the startup and reset of the master-slave switching control system is completed, determine the backup master signal of the board and the master signal of the board of the control board according to the instructions represented by the data bus signal output by the processor of the control board; and, after the startup and reset of the master-slave switching control system is completed, when the control board fails, switch the master signal of the board of the control board to the standby state; and, after the startup and reset of the master-slave switching control system is completed, respond to the master signal of the other board of the control board switching to the standby state, and switch the master signal of the board of the control board to the master state.

[0039] The embodiment of the present invention has the following technical effects: by adopting a 1+1 redundant design, two control boards are used to cross-connect signals and monitor each other. When any of the control boards that are used as the main control board fails, the system automatically switches between the main and standby control boards, and the control board that is currently used as the standby control board replaces the main control board that is currently faulty and becomes the new main control board to continue working, thereby ensuring the normal operation of the system business. In addition, the two control boards are completely identical, and an inventory can be established, and they can be replaced without distinction, thereby reducing the cost of system maintenance; when it is necessary to manually switch between the main and standby control boards, the manual control system can also switch between the two control boards by issuing instructions through the processor, thereby providing both manual and automatic methods, allowing operation and maintenance personnel to perform flexible control.

[0040] Furthermore, the active / standby switching circuit unit of each control board includes: a control instruction decoding module and an active / standby switching circuit module;

[0041] The control instruction decoding module of the master-slave switching circuit unit of each control board is used to output the master-slave-up signal and the master-slave-down signal of the control board;

[0042] The control instruction decoding module of the master-slave switching circuit unit of each control board is connected to the reset circuit unit of the control board, and is used to respond to the reset signal of the control board and set the master-slave signal and the master-slave signal of the control board to an invalid state;

[0043] The control instruction decoding module of the master-slave switching circuit unit of each control board is connected to the processor of the control board, and is used to input the control signal and data bus signal output by the processor, and determine the state of the master signal of the control board and the master signal of the control board;

[0044] The master-slave switching circuit module of the master-slave switching circuit unit of each control board is connected to the control instruction decoding module of the master-slave switching circuit unit of the control board, and is used to input the master-slave downgrade signal of the control board;

[0045] The master-standby switching circuit module of the master-standby switching circuit unit of each control board is connected to the master signal input terminal of the control board, the board in-place signal input terminal, the master signal input terminal of the board standby rise, the master signal output terminal of the current board, and the master signal output terminal of the current board standby rise, and is used for inputting the master signal of the control board, the board in-place signal, and the master signal of the board standby rise of the control board, and outputting the master signal of the current board of the control board;

[0046] The master-standby switching circuit module of the master-standby switching circuit unit of each control board is used to competitively determine the master signal of the control board with the other of the two control boards during the startup and reset of the master-standby switching control system; and, after the startup and reset of the master-standby switching control system is completed, respond to the control board's master signal, board in-place signal, board standby rise signal, board master fall signal, and board reset signal to determine the control board's master signal.

[0047] In some embodiments, the active / standby switching circuit unit of each control board includes: a control instruction decoding module and an active / standby switching circuit module;

[0048] The input signal of the control instruction decoding module of the master-slave switching circuit unit of each control board includes: the reset signal of the control board, and the control signal and data bus signal output by the processor;

[0049] The output signal of the control instruction decoding module of the master-slave switching circuit unit of each control board includes: the master-slave-up signal and the master-slave-down signal of the control board;

[0050] The control instruction decoding module of the master-standby switching circuit unit of each control board is used to set the master signal of the master board and the master signal of the master board to an invalid state through the reset signal of the master board of the control board during the start-up and reset of the master-standby switching control system; and after the start-up and reset of the master-standby switching control system is completed, determine the master signal of the master board and the master signal of the master board according to the instruction represented by the data bus signal output by the processor of the control board;

[0051] The input signal of the master-standby switching circuit module of the master-standby switching circuit unit of each control board includes: the master signal of the control board, the master signal of the master board, the reset signal of the board, the in-position signal of the board, and the master-standby signal of the board; the output signal of the master-standby switching circuit module of the master-standby switching circuit unit of each control board includes: the master signal of the control board;

[0052] The master-slave switching circuit module of the master-slave switching circuit unit of each control board is used to competitively determine the master signal of the control board with the other of the two control boards during the startup and reset of the master-slave switching control system; and, after the startup and reset of the master-slave switching control system is completed, respond to the input signal of the master-slave switching circuit module to determine the master signal of the control board.

[0053] In some embodiments, the data on the output data bus from the processor is hardware decoded by the control instruction decoding module to determine the signal states of the main standby signal of the current board and the main standby signal of the current board; the main standby signal of the current board is used as the main standby signal of the current board in the input signal of the opposite board. When the main standby signal of the current board is valid, the opposite board will detect that the main standby signal of the current board in the input signal is valid, and the main standby signal of the current board is input to the main standby switching circuit module of the opposite board, causing the main standby switching circuit module to change the main signal of the current board in the output signal of the opposite board to be invalid (i.e., standby state). At this time, the opposite board is downgraded from the main control board to the standby control board, and the current board will detect that the main state of the opposite board in the input signal is invalid (i.e., standby state). ), the master status of the opposite board of this board is input to the master-standby switching circuit module of this board, thereby causing the master-standby switching circuit module of this board to output the master signal of this board as valid (i.e., master status), at which time this board is upgraded from a standby control board to a master control board; the master-standby downgrade signal of this board is used to input to the master-standby switching circuit module of this board, controlling this board to actively downgrade from a master control board to a standby control board, thereby switching the master signal of this board of this board to a standby status, the opposite board detects that the master signal of the opposite board in its input signal is in a standby status, and the master signal of the opposite board of the opposite board is input to the master-standby switching circuit module of the opposite board, and the master-standby switching circuit module of the opposite board switches the master signal of the opposite board of this board to a master status, at which time the opposite board is upgraded from a standby control board to a master control board.

[0054] The embodiment of the present invention has the following technical effects: by adopting 1+1 redundant design, two control boards are used to cross-connect signals and monitor each other. When any of the control boards serving as the main control board fails, the system automatically performs the main-standby switch, and the control board currently serving as the standby control board replaces the main control board currently failing, becomes the new main control board and continues to work, thereby ensuring the normal operation of the system business. In addition, the two control boards are completely identical, and an inventory can be established, and they can be replaced without distinction, thereby reducing the cost of system maintenance; when it is necessary to manually switch the main and standby control boards, the manual control system can also switch the main and standby control boards between the two control boards by issuing instructions through the processor, thereby providing both manual and automatic methods, allowing operation and maintenance personnel to perform flexible control; the control instruction decoding module decodes the data on the processor data bus to obtain the decoded control signal, rather than the processor directly outputting the control signal to directly control the main and standby switching circuit module, thereby allowing the use of more complex processor instruction encoding, which can, to a certain extent, prevent the actions of the subsequent hardware from being accidentally triggered by simple signals, thereby improving the safety of the system.

[0055] Furthermore, if Figure 2 As shown, the master-slave switching circuit module of the master-slave switching circuit unit of each control board includes: a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, a fourth NOT gate N4, a first OR gate OR1, a first AND gate AND1 and a second AND gate AND2;

[0056] The input end of the first NOT gate N1 is connected to the reset circuit unit of the control board, and is used to invert the input reset signal of the control board;

[0057] The input end of the second NOT gate N2 is connected to the main board signal input end of the control board, and is used to invert the input main board signal of the control board;

[0058] The input end of the third NOT gate N3 is connected to the board presence signal input end of the control board;

[0059] The input end of the fourth NOT gate N4 is connected to the input end of the pair board standby main signal of the control board, and is used to invert the input pair board standby main signal of the control board;

[0060] The input end of the first AND gate AND1 is connected to the output end of the second NOT gate N2 and the output end of the first OR gate OR1;

[0061] The input end of the second AND gate AND2 is connected to the output end of the third NOT gate N3;

[0062] The input end of the second AND gate AND2 is also connected to the control instruction decoding module, which is used to input the main board downgrade signal of the control board from the control instruction decoding module;

[0063] The input end of the first OR gate OR1 is connected to the output end of the first NOT gate N1, the output end of the first AND gate AND1, the output end of the second AND gate AND2, and the output end of the fourth NOT gate N4;

[0064] The output end of the first OR gate OR1 is connected to the main signal output end of the control board, and is used to output the main signal of the control board;

[0065] In some embodiments, Figure 2 As shown, the master-slave switching circuit module of the master-slave switching circuit unit of each control board includes: a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, a fourth NOT gate N4, a first OR gate OR1, a first AND gate AND1 and a second AND gate AND2;

[0066] The output signal of the first OR gate OR1 is the main signal of the control board;

[0067] The input signal of the first OR gate OR1 includes: the signal obtained by inverting the reset signal of the control board through the first NOT gate N1, the output signal of the first AND gate AND1, the output signal of the second AND gate AND2, and the signal obtained by inverting the main signal of the control board through the fourth NOT gate N4;

[0068] The input signal of the first AND gate AND1 includes: the signal obtained by inverting the main signal of the control board through the second NOT gate N2, and the output signal of the first OR gate OR1;

[0069] The input signal of the second AND gate AND2 includes: a signal obtained by inverting the pair board presence signal of the control board through the third NOT gate N3, and a master downgrade signal of the control board.

[0070] In some embodiments, when powered on or reset, the reset signal RST of this board is input to the control instruction decoding module. Under the action of the reset signal RST of this board, the control instruction decoding module outputs the main standby signal of this board as a low level, and the main standby signal of this board as a high level. In the specific circuit structure, the reset signal RST of this board can be used as the input signal of the signal clearing terminal or reset terminal of the control instruction decoding module, thereby causing the signal output terminal of the control instruction decoding module to be set to the desired level. Those skilled in the art can select or design a variety of circuits with signal clearing terminal or reset terminal functions under the condition of satisfying the above constraints, which will not be described in detail here. When powered on and reset, if both control boards are in place, there will be a main standby competition relationship between the two control boards. When powered on or reset, under the action of the reset signal RST of this board, the main standby signal of this board is a high level, and the main standby signal of this board is a low level. During the RST reset period, both the board and the opposite board output the standby main signal of the board as a high level through the control instruction decoding module. For example, the opposite board standby main signal in the input signal of the board is a high level at this time, and is output as a low level after passing through the fourth NOT gate N4. The main standby signal of the board is used as the input signal of the second AND gate AND2, resulting in the output signal of the second AND gate AND2 being a low level. At the beginning of the reset, the reset signal RST of the board is a low level, which is reversed by the first NOT gate N1, and the output of the first NOT gate N1 is a high level, which is input to the first OR gate OR1. The output signal of the first OR gate OR1, that is, the main signal B2 of the board, is a high level (invalid state or standby state). Assuming that the reset signal RST of one control board changes to a high level earlier than the reset signal RST of another control board, then the main signal B2 of the control board whose reset signal RST changes to a high level first will change to a low level (valid state or main state) first. At the same time, since the main signal of the control board whose reset signal RST changes to a high level first is connected to the main signal of the opposite board, the opposite board will detect that the main signal of the opposite board in the input signal of the opposite board is a low level, and input it to the second NOT gate N2 on the opposite board. The second NOT gate N2 outputs a high level. At this time, the output of the first OR gate OR1 of the opposite board is a high level, and the output of the first AND gate AND1 of the opposite board is a high level, so that the output signal of the first OR gate OR1 of the opposite board, that is, the main signal B2 of the opposite board on the opposite board, is locked as a high level. Even if the reset signal RST of the opposite board on the opposite board changes to a high level again, the main signal B2 of the opposite board on the opposite board is always high. Therefore, the control board whose reset signal RST changes to a high level first is the main board, and the control board whose reset signal RST changes to a high level later is the standby board.

[0071] When a fault occurs, the processor of the control board in the master state (hereinafter referred to as the faulty board) enters the reset state, and the reset signal RST of the faulty board is in a low-level reset state. The low-level reset signal RST of the faulty board is reversed to a high level through the first NOT gate N1 and then input to the first OR gate OR1, so that the output of the first OR gate OR1 is high, that is, the master signal of the faulty board is high. At this time, the other control board (the opposite board of the faulty board) detects that the opposite board master signal in its input signal is high, which is reversed to a low level through the second NOT gate N2, and outputs a low level through the first AND gate AND1. At this time, the other input signals of the first OR gate OR1 in the opposite board are also low, and finally the first back door OR1 outputs a low level, that is, after the opposite board of the faulty board detects that the faulty board has switched to the standby state, it automatically switches to the master state, completing the automatic switching of the master and standby states during a fault.

[0072] The processor may also send instructions to determine the main standby signal of the board and the main standby signal of the board by the control instruction decoding module, thereby affecting the main standby state of the board or the opposite board. For example, when it is desired to manually upgrade the board (which is in the standby state at this time) to the main control board, a specific instruction is sent through the processor of the board to make the main standby signal of the board and the main standby signal of the board output by the control instruction decoding module of the board both low level; the opposite board (which is in the main state at this time) detects that the main standby signal of the opposite board is low level, which is reversed to high level by the fourth NOT gate N4 of the opposite board and input to the first OR gate OR1, and the first OR gate OR1 of the opposite board outputs high level, that is, the main signal of the opposite board outputs high level (invalid state or standby state). The pair board is switched from the main state to the standby state. The present board detects that the pair board's main signal in the input signal is high, which is reversed to a low level through the second NOT gate N2. The first OR gate OR1 of the present board outputs a low level, and the main signal of the present board is output as a low level. The present board is switched from the standby state to the main state. The pair board detects that the pair board's main signal in the input signal is low, which is reversed to a high level through the second NOT gate N2 of the present board. At this time, the main signal of the present board is already high, and the first AND gate AND1 of the pair board outputs a high level, thereby locking the output of the first OR gate OR1 of the pair board as a high level, that is, completing the promotion of the present board to the main control board, and locking the pair board as the standby control board. For example, when it is desired to manually downgrade the board (at this time, the main control board) to the standby control board, a specific instruction is sent through the processor of the board to make the main standby upgrade signal of the board output by the control instruction decoding module of the board high and the main standby downgrade signal of the board high; at this time, the board in-position signal in the input signal of the board is low (indicating that the board is in position) and is reversed to a high level through the third NOT gate N3, and is input to the second AND gate AND2 of the board together with the main standby downgrade signal of the board (also high at this time), and the second AND gate AND2 of the board outputs a high level, resulting in the first OR gate OR1 The output is high level, that is, the main signal of this board is high level (invalid state or standby state), the opposite board detects that the main state of the opposite board in the input signal is high level, which is reversed to low level by the second non-gate N2, and the output of the first AND gate AND1 of the opposite board is low level, resulting in the output of the first OR gate OR1 of the opposite board being low level, that is, the main signal of the opposite board is low level (valid state or main state), and at the same time, further resulting in the output of the first OR gate OR1 of the opposite board being locked at a high level, completing the switching of this board from the main state to the standby state, and at the same time, the opposite board is switched from the standby state to the main state. In addition, when there is only one control board and there is no opposite board, the opposite board in-position signal in the input signal of this board is high level, which is reversed to low level by the third non-gate N3, resulting in the output of the second AND gate AND2 being low level, thereby prohibiting the change of the main state of this board through the processor.

[0073] The embodiment of the present invention has the following technical effects: through the logic processing of various input signals of simple gate circuits, the master-slave switching function combining automatic switching and manual switching based on the processor is realized, and the switched state can be self-locked. When there is only one control board, the manual switching of the processor can be automatically disabled. The circuit is simple and easy to maintain, and automatic switching is realized in case of failure. Compared with complex circuits, it has the advantage of low failure rate.

[0074] Furthermore, if Figure 2 As shown, the control instruction decoding module of the active / standby switching circuit unit of each control board includes: a D register U1, a fifth NOT gate N5, a sixth NOT gate N6, a seventh NOT gate N7, an eighth NOT gate N8, a ninth NOT gate N9, a tenth NOT gate N10, an eleventh NOT gate N11, a twelfth NOT gate N12, a second OR gate OR2 and a first NOR gate NOR1;

[0075] The data clearing end of the D register U1 of the control board is connected to the reset circuit unit, and is used to respond to the reset signal of the control board. When the reset signal of the control board is reset, the output data bus of the D register U1 is set to a full low level;

[0076] The D register U1 of the control board is also connected to the processor, and is used to input the control signal and data bus signal output by the processor, and latch the data bus signal to the output data bus of the D register U1;

[0077] The input ends of the fifth NOT gate N5, the sixth NOT gate N6, the seventh NOT gate N7, and the eighth NOT gate N8 of the control board are respectively connected to the even-numbered data lines in the output data bus of the D register U1 of the control board;

[0078] The input ends of the ninth NOT gate N9, the tenth NOT gate N10, the eleventh NOT gate N11 and the twelfth NOT gate N12 of the control board are respectively connected to the odd-numbered data lines in the output data bus of the D register U1 of the control board;

[0079] The input end of the second OR gate OR2 is connected to the output ends of the fifth NOT gate N5, the sixth NOT gate N6, the seventh NOT gate N7, and the eighth NOT gate N8, and the odd-numbered data lines in the output data bus of the D register U1;

[0080] The output end of the second OR gate OR2 is connected to the main signal output end of the control board for outputting the main signal of the control board;

[0081] The input end of the first NOR gate NOR1 is connected to the output ends of the ninth NOR gate N9, the tenth NOR gate N10, the eleventh NOR gate N11, and the twelfth NOR gate N12, and the even-numbered data lines in the output data bus of the D register U1;

[0082] The output end of the first NOR gate NOR1 is connected to the master-slave switching circuit module of the master-slave switching circuit unit of the control board, and is used to provide the master-slave switching circuit module of the master-slave switching circuit unit of the control board with the master-slave downgrade signal of the control board.

[0083] In some embodiments, Figure 2 As shown, the control instruction decoding module of the active / standby switching circuit unit of each control board includes: a D register U1, a fifth NOT gate N5, a sixth NOT gate N6, a seventh NOT gate N7, an eighth NOT gate N8, a ninth NOT gate N9, a tenth NOT gate N10, an eleventh NOT gate N11, a twelfth NOT gate N12, a second OR gate OR2 and a first NOR gate NOR1;

[0084] The control board's own board reset signal is input to the data clearing terminal of the D register U1, which is used to set the output data bus of the D register U1 to a full low level when the control board's own board reset signal is reset;

[0085] The control signal and data bus signal output by the processor of the control board are input to the D register U1, and the data bus signal output by the processor of the control board is latched to the output data bus of the D register U1;

[0086] The input signal of the second OR gate OR2 includes: the signals of the even-numbered data lines in the output data bus of the D register U1 obtained by inverting the fifth NOT gate N5, the sixth NOT gate N6, the seventh NOT gate N7, and the eighth NOT gate N8, and the signals of the odd-numbered data lines in the output data bus of the D register U1;

[0087] The output signal of the second OR gate OR2 is the main signal of the control board;

[0088] The input signal of the first NOR gate NOR1 includes: the signals of the odd-numbered data lines in the output data bus of the D register U1 obtained by inverting the ninth NOR gate N9, the tenth NOR gate N10, the eleventh NOR gate N11, and the twelfth NOR gate N12, and the signals of the even-numbered data lines in the output data bus of the D register U1;

[0089] The output signal of the first NOR gate NOR1 is the main board downgrade signal of the control board.

[0090] In some embodiments, manual switching is to manually implement the master-slave switching, and the function of upgrading the standby board to the main board or the main board to the standby board can be realized through software operation. The control of the master-slave switching is realized by writing numbers to the master-slave switching register. Figure 2 The 8-bit D register U1 is the master-slave switch control register. The 8-bit register is used to improve reliability to avoid erroneous operation of the board. If the board is to be upgraded to the master control board, the processor writes 0X55 to the D register U1, so that the master signal of the board is changed to a low level; if the board is to be downgraded to a standby control board, the processor writes 0XAA to the D register U1, and the output of the first NOR gate NOR1 (i.e. the master signal of the board) is changed to a high level, so that the output of the second AND gate AND2 is changed to a high level.

[0091] When the main control board is downgraded to the standby control board, the CPU of the main board (main control board) writes 0XAA to the main-standby switching register (D register U1). At this time, the output of the first NOR gate NOR1 of the main board is high, so the main signal B2 of the main board becomes high. This signal changes the output of the first AND gate AND1 of the standby board (standby control board) to a low level, and the main signal B2 of the standby board becomes low, and the standby board changes to the main state. However, in order to ensure the continued operation of the main-standby switching circuit, after writing 0XAA, the CPU needs to write a value other than 0XAA and 0X55 into the main-standby switching register. In this design, 0X00 is written. If the standby board does not exist, because of the influence of the standby board in-position signal A1, the second AND gate AND2 always outputs a low level, and the written signal is not affected.

[0092] When the standby board is upgraded to the main board, the CPU of the standby board first writes 0X55 into the master-standby switching register. At this time, the second OR gate OR2 of the standby board outputs a low level. The signal reaches the main board's opposite board standby upgrade main signal A3 through the standby upgrade main signal B3 of the board, and is inverted to a high level through the fourth NOT gate N4 of the main board. The high level signal pulls the main board's main signal from a low level to a high level. The main board's main signal is also fed back to the standby board, making the standby board's first AND gate AND1 output a low level. Therefore, the standby board's main signal becomes a low level, and the standby board is upgraded to the main control board. This method of upgrading the standby board to the main is actually achieved by reducing the main board to the standby. Like the main board to the standby, the CPU also needs to write 0X00 after writing 0X55, otherwise the opposite board's main signal will be shielded.

[0093] Furthermore, if Figure 2 As shown, each control board also includes: a reset signal output terminal of the board itself, and a reset signal input terminal of the opposite board;

[0094] The reset signal output terminal of each control board is connected to the reset signal input terminal of another control board;

[0095] The board reset signal input terminal of the control board is connected to the data reset terminal of the D register U1, and is used to reset the D register U1 when the board reset signal is in the reset state, and prohibit the data of the processor's output data bus from being written into the D register U1.

[0096] In some embodiments, Figure 2 As shown, the output signal of each control board also includes: a reset signal of the board; the input signal of each control board also includes: a reset signal of the board;

[0097] The reset signal of each control board corresponds to the reset signal of another control board;

[0098] The control board's board reset signal is input to the data reset terminal of the D register U1, which is used to reset the D register U1 when the board reset signal is in the reset state, and prohibit the data of the processor's output data bus from being written into the D register U1.

[0099] In some embodiments, Figure 2 As shown, the board reset signal rst_a in the input signal of this board is input to the reset pin of the D register U1 of this board. When the main board is downgraded to the standby board and the standby board is upgraded to the main board, if the board is in the reset state, it will cause confusion; therefore, the reset signals of the two boards are interlocked and introduced into the other party's D register U1 respectively. When the other board is in the reset state, the register is locked in the D register U1, and the CPU is prohibited from writing data to the register. In this way, it can be ensured that when a single board is reset, the main board will not be downgraded to the standby board or the standby board will not be upgraded to the main board.

[0100] Furthermore, if Figure 2 As shown, each control panel also includes: dual main control signal input terminals;

[0101] The input end of the first OR gate OR1 is also connected to the dual main control signal input end of the control board, and is used to set the main signal of the board of one of the control boards to the standby state by setting the dual main control signal input to the dual main control signal input end of one of the control boards to a high level when the main signals of the two control boards are both in the main state.

[0102] In some embodiments, Figure 2 As shown, the input signal of each control panel also includes: dual main control signals;

[0103] The input signal of the first OR gate OR1 also includes: dual main control signals of the control board;

[0104] The dual master control signal of the control board is used for setting the main signals of the two control boards to the standby state by setting the dual master control signal of the control board to a high level when the main signals of the two control boards are both in the main state.

[0105] In some embodiments, Figure 2 As shown, when only one single board is in place, the single board is the main board, and its input pair board standby rising main signal A3 is high regardless of whether the standby board is plugged in. In addition, the main signal of the board of the current board is self-locked, that is, regardless of the pair board main signal, the first AND gate AND1 is locked by the feedback low level of the board main signal of the current board and remains at a low level. Therefore, the main signal B2 of the current board is output as a low level. The pair board main signal A2 in the input signal of the later inserted single board is low level, and the feedback input of the board main signal B2 is high level, so the main signal B2 of the current board is output as a high level, and the later inserted single board is a standby board. However, for the single board in place, the self-locking method of the main signal is adopted to ensure that the main state is not changed due to the insertion of another single board, but the greatest danger of using the self-locking circuit is also here. Once a dual master appears, that is, the main and standby boards are both in the main state, it is impossible to automatically let one of the single boards exit the main state, so measures need to be taken to prevent the emergence of dual masters. In this embodiment, the main signals of the two control boards and the slot numbers of the boards on the backplane are detected to prevent the occurrence of dual master. When it is detected that both control boards are in the main state, the board with the slot number 0X0_0111 is immediately downgraded to the standby board, and the main signal of the board with the slot number 0X0_1000 remains unchanged. It is ensured that only one board is in the main state. Since the main-standby switching circuit adopts the self-locking of the main signal state, the dual standby phenomenon will not occur. Once it occurs, it will seize the main state, thereby ensuring that there is always one board in the main state.

[0106] Furthermore, if Figure 2 As shown, each control board also includes: a hot-swap delay control signal input terminal;

[0107] The input end of the first OR gate OR1 is also connected to the hot-swap delay control signal input end of the control board, and is used to keep the hot-swap delay control signal input end as a high-level signal when it is detected that the control board is not stably connected to the backplane during hot-swap of the control board, so that the main signal of the board output by the first OR gate OR1 on the control board is in a standby state, and after the hot-swap of the control board is completed, keep the hot-swap delay control signal input end as a low-level signal;

[0108] Each control board also includes at least one slot number pin; all slot number pins are connected to the processor on the control board, and are used for the processor to sample and read the slot number of the control board on the backplane to determine whether the control board is stably plugged in.

[0109] In some embodiments, Figure 2 As shown, the input signal of each control board also includes: a hot plug delay control signal;

[0110] The input signal of the first OR gate OR1 also includes: a hot plug delay control signal of the control board;

[0111] The hot-swap delay control signal of the control board is used to maintain a high-level signal when the control board is hot-swapped and it is detected that the control board is not stably connected to the backplane, so that the main signal of the board output by the first OR gate OR1 on the control board is in a standby state, and after the hot-swap of the control board is completed, it is maintained as a low-level signal. Each control board also includes at least one slot number pin; all slot number pins are connected to the processor on the control board, and are used for the processor to sample and read the slot number of the control board on the backplane.

[0112] In some embodiments, Figure 2As shown, when one control board is in place and another single board is doing hot-swap experiment, the phenomenon of master-stealing often occurs. After testing, it is found that because the power pin is longer than the signal pin, there are two situations: 1. When the single board is not fully inserted, the master-slave switching circuit has been running, and the single board mistakenly thinks that the existing single board does not exist and enters the master state; 2. Because when the single board is plugged in and out, the moment the connector and the backplane contact, the contact of the pins must have a sequence. If the master signal of the hot-swappable single board is connected before the master signal of the existing single board, and the master-slave switching circuit is implemented by interlocking the master output signals of the master and standby boards, the later inserted single board will pull the master state of the master board in place to the standby state to cause master-stealing. However, this kind of master-stealing is not allowed. In this embodiment, hot-swap delay control is used to prevent the master-stealing phenomenon. The hot-swap delay control time can be generated by detecting the slot number of the backplane. When the single board is inserted into the backplane slot and the corresponding backplane ID number is correctly detected, it means that the single board has been fully connected to the backplane. A 5-bit ID number can be used. The 5 lines are all pulled up on this board. The main and standby board slots are 00111 and 01000. Assuming that the hot-swap single board slot ID is 00111, if the single board detects ID = 11111, it means that the single board is currently only in the power connection state and is not plugged in with the backplane; if ID = 11111 and ID! = 00111, it means that the single board is currently in the moment of being connected to the backplane connector; if ID = 00111, it means that the single board is fully plugged in. In order to prevent jitter, in addition to adding an anti-jitter circuit in the logic, a certain delay is also added (to ensure that the single board is fully plugged in and starts to work normally). During this period, the main signal B2 of the board is forced to maintain a high level. After the delay ends, the main and standby switching circuit starts to work normally. For the single board in place, since the slot number of the single board is stable since power-on, the hot-swap delay control circuit will not work for the single board in place and will not affect the master seizure of the normal single board.

[0113] Furthermore, if Figure 2 As shown, each control board also includes: an odd slot delay signal input terminal;

[0114] The input end of the first OR gate OR1 is also connected to the odd slot delay signal input end of the control board, and is used to maintain the high level signal of the odd slot delay signal input end for a specified time for the control board installed in the odd slot of the backplane during reset, so that within the specified time, the main signal of this board output by the first OR gate OR1 installed in the odd slot of the backplane is in a standby state.

[0115] In some embodiments, Figure 2 As shown, the input signal of each control board also includes: odd slot delay signal;

[0116] The input signal of the first OR gate OR1 also includes: an odd slot delay signal of the control board;

[0117] The odd slot delay signal of the control board is used to maintain a high level signal for a specified time for the control board installed in the odd slot of the backplane during reset, so that the main signal of the board output by the first OR gate OR1 of the control board installed in the odd slot of the backplane is in a standby state within the specified time. After the specified time, the odd slot delay signal is restored to a low level.

[0118] In some embodiments, Figure 2 As shown, when the two boards are powered on and reset, they will compete for the master position, and there will be an uncertain state. Although it will not affect the circuit function, in order to reduce people's illusion, in this embodiment, odd slot delay control is added, that is, the board inserted in the slot ID of 00111 (odd number slot) is delayed for a period of time, so that the board inserted in the slot ID of 01000 has priority to obtain the master right.

[0119] The above technical scheme of the embodiment of the utility model is described in detail below in conjunction with specific application examples. For technical details not introduced during the implementation process, please refer to the relevant description in the previous text.

[0120] In the embodiment of the utility model, based on the consideration of fault tolerance requirements, the hardware configuration adopts a 1+1 redundant design. When the main control system has a hardware or software failure, the system still needs to work normally. It is equipped with two control boards, the main and the backup, to build a dual-main control hot standby fault-tolerant system. When the main control board fails, the system automatically switches to the main and the backup control board to take over the work of the main control board to ensure the normal operation of the business. The main and backup switching circuit architecture diagram is shown in the figure. Figure 1 shown.

[0121] A1, A2, A3 are the master-slave switching signals input from the other board to this board, and B1, B2, B3 are the master-slave switching signals output from this board to the other board; the output signals are all pulled up on the other board. The master-slave switching circuit unit also provides an interface to communicate with the CPU (processor) for the CPU to detect the master-slave switching status information of the single board and control the master-slave switching of the single board. The following are the specific signal definitions. A1: Pair board in-place signal, B1: This board in-place signal; A2: Pair board main signal, B2: This board main signal; A3: Pair board standby rise master signal, B3: This board standby rise master signal.

[0122] According to the following Figure 2 The working principle of the active / standby switching circuit of the embodiment of the present invention is described as follows:

[0123] 1) Both control boards are in place when powering on or resetting

[0124] When power is on or reset, if both control boards are in place, there will be a competition between the two control boards. When power is on or reset, the outputs of the first NOR gate NOR1 and the first AND gate AND1 are low, and the second OR gate OR2 is high. Therefore, the backup main logic auxiliary signal (the backup main signal of this board) B3 of the two boards (control boards) is high, but the reset signal RST of this board is low. After being reversed by the first NOT gate N1, the output of the first NOT gate N1 is high and input to the first OR gate OR1. The output signal of the first OR gate OR1, that is, the main signal B2 of this board, is high (invalid state or standby state). Assuming that the reset signal RST of one control board changes to a high level before the reset signal RST of another control board, then the main signal B2 of the control board whose reset signal RST changes to a high level first will change to a low level (valid state or main state) first. At the same time, since the main signal of the board is connected to the main signal of the opposite board, the opposite board will detect that the main signal of the opposite board in the input signal of the opposite board is low, and input it to the second NOT gate N2 on the opposite board. The second NOT gate N2 outputs a high level. At this time, the output of the first OR gate OR1 of the opposite board is high, and the output of the first AND gate AND1 of the opposite board is high. Therefore, the output signal of the first OR gate OR1 of the opposite board, that is, the main signal B2 of the opposite board, is locked to a high level. Even if the reset signal RST of the opposite board changes to a high level again, the main signal B2 of the opposite board is always high. Therefore, the control board whose reset signal RST changes to a high level first is the main board, and the control board whose reset signal RST changes to a high level later is the standby board.

[0125] 2) Active / standby switchover

[0126] The master-slave switch includes automatic switch and manual switch. Automatic switch means that when both the master and the slave control boards are in place, the master-slave switch can be performed when the master board fails. At this time, the CPU enters the reset state, the reset signal RST of the board is low, the master signal B2 of the failed control board is pulled high, and the master signal of the other control board is pulled low, completing the switch from the slave board to the master board.

[0127] Manual switching is the manual switching of the master and the slave. The software can be used to upgrade the slave board to the master board or the master board to the slave board. The control of the master and the slave switching is achieved by writing numbers to the master and the slave switching register. Figure 2 The 8-bit D register U1 is the master-slave switch control register. The 8-bit register is used to improve reliability to avoid erroneous operation of the board. If the board is to be upgraded to the main board, 0X55 is written to the master-slave switch control register to make the backup upgrade master logic auxiliary signal (the backup upgrade master signal of this board) become low level; if the board is to be downgraded to the backup board, 0XAA is written to the master-slave switch controller, the first NOR gate NOR1 becomes high level, and the second AND gate AND2 becomes high level.

[0128] When the main board is downgraded to the standby board, the CPU of the main board writes 0XAA to the master-slave switching register. At this time, the output of the first NOR gate NOR1 of the main board is high level, so the main board master signal B2 of the main board becomes high level, and this signal changes the output of the first AND gate AND1 of the standby board to low level, and the main board master output signal B2 of the standby board becomes low level, and the standby board is switched to the master state. However, in order to ensure the continued operation of the master-slave switching circuit, after writing 0XAA, the CPU needs to write a value other than 0XAA and 0X55 into the master-slave switching register, and writes 0X00 in this embodiment. If the standby board does not exist, because it is affected by the board presence signal A1 of the main board, the second AND gate AND2 always outputs a low level, and the signal written to the master-slave switching register does not affect the state of the main board master signal of the main board.

[0129] When the standby board is upgraded to the main board, the CPU of the standby board first writes 0X55 into the master-standby switching register. At this time, the second OR gate OR2 of the standby board outputs a low level. The signal reaches the main board through the standby upgrade main signal B3 of the board, and serves as the main board's opposite board standby upgrade main signal. After being inverted by the fourth NOT gate, the signal pulls the main board's main signal from a low level to a high level, and the main board's main signal becomes a high level. At the same time, the main board's main signal is fed back to the standby board as the opposite board's main signal of the backplane, making the output of the first AND gate AND1 of the standby board become a low level. Therefore, the main board's main signal becomes a low level, and the standby board is upgraded to the main state. This method of upgrading the standby board to the main is actually achieved by reducing the main board to the standby. Like the main board to the standby, the CPU also needs to write 0X00 after writing 0X55, otherwise the opposite board's main signal will be shielded.

[0130] When the main board is demoted to the standby board or the standby board is promoted to the main board, if the board is in the reset state, it will cause confusion. Therefore, the reset signals of the two boards are interlocked and introduced into the master-slave switching register of the other party respectively. When the other board is in the reset state, the register in the master-slave switching register is locked, and the CPU is prohibited from writing data to the register. In this way, it can be ensured that when one board is reset, the master will not be demoted to the standby or the standby will not be promoted to the master.

[0131] 3) With one board in place, insert another board

[0132] When only one single board is in place, the single board is the main control board, and its input pair board standby rising main signal A3 is high level regardless of whether the standby board is plugged in. In addition, the main signal of this board is self-locking, that is, regardless of the pair board main signal, the first AND gate AND1 is locked by the feedback low level of the main signal of this board and remains low level. Therefore, the main signal B2 of this board of the single board in place is output as a low level. The pair board main signal A2 in the input signal of the later inserted single board is low level, and the feedback input of the main signal B2 of this board is high level, so its main signal B2 of this board is output as high, and the later inserted single board is a standby board. However, for the single board in place, the self-locking method of the main signal is used to ensure that the main state is not changed due to the insertion of another single board, but the greatest danger of using the self-locking circuit is also here. Once a dual master appears, that is, both the main and standby boards are in the main state, it is impossible to automatically let one of the single boards exit the main state, so measures need to be taken to prevent the emergence of dual masters.

[0133] In this embodiment, the main signals of the two control boards and the slot numbers of the boards on the backplane are detected to prevent the occurrence of dual master. When it is detected that both control boards are in the main state, the board with the slot number 0X0_0111 is immediately downgraded to the standby board, and the main signal of the board with the slot number 0X0_1000 remains unchanged. It is ensured that only one board is in the main state. Since the main-standby switching circuit adopts the self-locking of the main signal state, the dual standby phenomenon will not occur. Once it occurs, it will seize the main state, thereby ensuring that there is always one board in the main state.

[0134] 4) Only one board is in place

[0135] The input end of the first OR gate (OR1) is also connected to a board presence signal generating circuit unit for inputting the board presence signal; when only one single board is in place, there is no control board in the spare board slot, and when power is turned on or reset, the master-slave switching register is reset, and the second OR gate OR2 outputs a high level. At the same time, since the other single board is not in place, the board presence signal A1 is high, so the second AND gate AND2 outputs a low level. At the same time, since all signals are pulled up, the board master signal A2 and the board standby master signal A3 are always high, and the board presence signal is low. Therefore, after the board reset signal RST becomes high, the board master signal B2 outputs a low level, and the board is the master.

[0136] 5) Both control boards are in place, unplug the spare board

[0137] When both control boards are in place, unplug the standby board. For the remaining main board, its main signal is self-locking, so its main state is not affected.

[0138] 6) With both control boards in place, unplug the main board

[0139] When both control boards are in place, when the main board is unplugged, the board master signal A2 in the input signal of the standby board changes from low level to high level, and the output of the first AND gate AND1 changes to low level; at the same time, the board in place signal A1 in the input signal of the standby board changes to high level, and after inversion, AND2 changes to low level; at the same time, the board standby upgrade main signal in the input signal of the standby board remains at a high level, and is reversed to a low level after the fourth NOT gate N4, so the output signal of the standby board, the board master signal B2, changes from high level to low level, and the standby board is upgraded to the main board.

[0140] When one control board is in place and another single board is doing hot-swap experiment, the phenomenon of master-stealing often occurs. After testing, it is found that because the power pin is longer than the signal pin, there are two situations: 1. When the single board is not fully plugged in, the master-slave switching circuit has been running, and the single board mistakenly thinks that the existing single board does not exist and enters the master state; 2. Because when the single board is plugged in and out, the moment the connector and the backplane contact, the contact of the pins must have a sequence. If the master signal of the hot-swappable single board is connected before the master signal of the existing single board, and the master-slave switching circuit is implemented by interlocking the master output signals of the master and standby boards, the later inserted single board will pull the master state of the master board in place to the standby state, causing master-stealing. However, this kind of master-stealing is not allowed. In this embodiment, hot-swap delay control is used to prevent the master-stealing phenomenon. The hot-swap delay control time can be generated by detecting the slot number of the backplane. When the single board is inserted into the backplane slot and the corresponding backplane ID number is correctly detected, it means that the single board has been fully connected to the backplane. A 5-bit ID number can be used. The 5 lines are all pulled up on this board. The main and standby board slots are 00111 and 01000. Assuming that the hot-swap single board slot ID is 00111, if the single board detects ID = 11111, it means that the single board is currently only in the power connection state and is not plugged in with the backplane; if ID = 11111 and ID! = 00111, it means that the single board is currently in the moment of being connected to the backplane connector; if ID = 00111, it means that the single board is fully plugged in. In order to prevent jitter, in addition to adding an anti-jitter circuit in the logic, a certain delay is also added (to ensure that the single board is fully plugged in and starts to work normally). During this period, the main signal B2 of the board is forced to maintain a high level. After the delay ends, the main and standby switching circuit starts to work normally. For the single board in place, since the slot number of the single board is stable since power-on, the hot-swap delay control circuit will not work for the single board in place and will not affect the master seizure of the normal single board.

[0141] When the two boards are powered on and reset, they will compete for the master position, and there will be an uncertain state. Although it will not affect the circuit function, in order to reduce people's illusion, in this embodiment, odd slot delay control is added, that is, the board inserted in the slot ID 00111 is delayed for a period of time, so that the board inserted in the slot ID 01000 has priority to obtain the master right.

[0142] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0143] In the above detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than those clearly stated in each claim. On the contrary, as reflected in the attached claims, the utility model is in a state with less than all the features of the disclosed individual embodiments. Therefore, the attached claims are hereby expressly incorporated into the detailed description, with each claim acting alone as a separate preferred embodiment of the utility model.

[0144] The disclosed embodiments are described above to enable any person skilled in the art to implement or use the present invention. Various modifications of these embodiments are obvious to those skilled in the art, and the general principles defined herein may also be applied to other embodiments without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments given herein, but is consistent with the broadest scope of the principles and novel features disclosed in the present application.

[0145] The above description includes examples of one or more embodiments. Of course, it is impossible to describe all possible combinations of components or methods for the purpose of describing the above embodiments, but it should be recognized by those skilled in the art that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including". In addition, any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

[0146] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the utility model in detail. It should be understood that the above description is only the specific implementation method of the utility model and is not used to limit the protection scope of the utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the utility model should be included in the protection scope of the utility model.

Claims

1. A master-standby switching control system for energy storage supporting emergency frequency modulation of power grid, characterized in that: include: Two identical control boards that are opposite to each other; Each control board includes: a processor, a main-standby switching circuit unit, a reset circuit unit, a board-in-place signal generating circuit unit, a main signal input terminal for the board, a board-in-place signal input terminal, a board-standby main signal input terminal, a board-in-place signal output terminal, a board-in-place main signal output terminal, a board-in-place main signal output terminal, and a board-standby main signal output terminal; The main signal input terminal, the in-place signal input terminal and the standby main signal input terminal of each control board are respectively connected to the main signal output terminal, the in-place signal output terminal and the standby main signal output terminal of another control board; The board presence signal generating circuit unit of each control board is connected to the board presence signal output terminal of the control board, and is used for outputting the board presence signal of the control board; The reset circuit unit of each control board is connected to the processor and the active / standby switching circuit unit, and is used to provide a reset signal of the control board to the processor and the active / standby switching circuit unit; The processor of each control board is connected to the active / standby switching circuit unit and is used to output control signals and data bus signals to the active / standby switching circuit unit; The master-slave switching circuit unit of each control board is connected with the master signal input terminal of the control board, the board in-place signal input terminal, the master signal input terminal of the board, the master signal output terminal of the current board, and the master signal output terminal of the current board, and is used for inputting the master signal of the current board, the board in-place signal, and the master signal of the current board, and outputting the master signal of the current board and the master signal of the current board; The master-slave switching circuit unit of each control board is used to competitively determine the master signal of the control board with the other of the two control boards during the startup and reset of the master-slave switching control system; and, after the startup and reset of the master-slave switching control system is completed, determine the backup master signal and the master signal of the control board according to the instructions represented by the data bus signal output by the processor of the control board; and, after the startup and reset of the master-slave switching control system is completed, when the control board fails, switch the master signal of the control board to the standby state; and, after the startup and reset of the master-slave switching control system is completed, in response to the control board's main signal of the other board being switched to the standby state, switch the master signal of the control board to the master state.

2. The main-standby switching control system for emergency frequency modulation of power grid supported by energy storage according to claim 1, characterized in that: The main and standby switching circuit unit of each control board includes: a control instruction decoding module and a main and standby switching circuit module; The control instruction decoding module of the master-slave switching circuit unit of each control board is used to output the master-slave-up signal and the master-slave-down signal of the control board; The control instruction decoding module of the master-slave switching circuit unit of each control board is connected to the reset circuit unit of the control board, and is used to respond to the reset signal of the control board and set the master-slave signal and the master-slave signal of the control board to an invalid state; The control instruction decoding module of the master-slave switching circuit unit of each control board is connected to the processor of the control board, and is used to input the control signal and data bus signal output by the processor, and determine the state of the master signal of the control board and the master signal of the control board; The master-slave switching circuit module of the master-slave switching circuit unit of each control board is connected to the control instruction decoding module of the master-slave switching circuit unit of the control board, and is used to input the master-slave downgrade signal of the control board; The master-standby switching circuit module of the master-standby switching circuit unit of each control board is connected to the master signal input terminal of the control board, the board in-place signal input terminal, the master signal input terminal of the board standby rise, the master signal output terminal of the current board, and the master signal output terminal of the current board standby rise, and is used for inputting the master signal of the control board, the board in-place signal, and the master signal of the board standby rise of the control board, and outputting the master signal of the current board of the control board; The master-standby switching circuit module of the master-standby switching circuit unit of each control board is used to competitively determine the master signal of the control board with the other of the two control boards during the startup and reset of the master-standby switching control system; and, after the startup and reset of the master-standby switching control system is completed, respond to the control board's master signal, board in-place signal, board standby rise signal, board master fall signal, and board reset signal to determine the control board's master signal.

3. The main-standby switching control system for emergency frequency modulation of power grid supported by energy storage according to claim 2, characterized in that: The master-slave switching circuit module of the master-slave switching circuit unit of each control board includes: a first NOT gate (N1), a second NOT gate (N2), a third NOT gate (N3), a fourth NOT gate (N4), a first OR gate (OR1), a first AND gate (AND1) and a second AND gate (AND2); The input end of the first NOT gate (N1) is connected to the reset circuit unit of the control board, and is used to invert the input reset signal of the control board; The input end of the second NOT gate (N2) is connected to the main board signal input end of the control board, and is used to invert the input main board signal of the control board; The input end of the third NOT gate (N3) is connected to the board-in-place signal input end of the control board; The input end of the fourth NOT gate (N4) is connected to the input end of the pair board standby main signal of the control board, and is used to invert the input pair board standby main signal of the control board; The input end of the first AND gate (AND1) is connected to the output end of the second NOT gate (N2) and the output end of the first OR gate (OR1); The input end of the second AND gate (AND2) is connected to the output end of the third NOT gate (N3); The input end of the second AND gate (AND2) is also connected to the control instruction decoding module, and is used to input the main board downgrade signal of the control board from the control instruction decoding module; The input end of the first OR gate (OR1) is connected to the output end of the first NOT gate (N1), the output end of the first AND gate (AND1), the output end of the second AND gate (AND2), and the output end of the fourth NOT gate (N4); The output end of the first OR gate (OR1) is connected to the main signal output end of the control board for outputting the main signal of the control board.

4. The main-standby switching control system for emergency frequency modulation of power grid supported by energy storage according to claim 2, characterized in that: The control instruction decoding module of the master-slave switching circuit unit of each control board includes: a D register (U1), a fifth NOT gate (N5), a sixth NOT gate (N6), a seventh NOT gate (N7), an eighth NOT gate (N8), a ninth NOT gate (N9), a tenth NOT gate (N10), an eleventh NOT gate (N11), a twelfth NOT gate (N12), a second OR gate (OR2) and a first NOR gate (NOR1); The data clearing end of the D register (U1) of the control board is connected to the reset circuit unit, and is used to respond to the reset signal of the control board. When the reset signal of the control board is reset, the output data bus of the D register (U1) is set to a full low level; The D register (U1) of the control board is also connected to the processor, and is used to input the control signal and data bus signal output by the processor, and latch the data bus signal to the output data bus of the D register (U1); The input ends of the fifth NOT gate (N5), the sixth NOT gate (N6), the seventh NOT gate (N7), and the eighth NOT gate (N8) of the control board are respectively connected to the even-numbered data lines in the output data bus of the D register (U1) of the control board; The input ends of the ninth NOT gate (N9), the tenth NOT gate (N10), the eleventh NOT gate (N11), and the twelfth NOT gate (N12) of the control board are respectively connected to the odd-numbered data lines in the output data bus of the D register (U1) of the control board; The input end of the second OR gate (OR2) is connected to the output ends of the fifth NOT gate (N5), the sixth NOT gate (N6), the seventh NOT gate (N7), and the eighth NOT gate (N8), and the odd-numbered data lines in the output data bus of the D register (U1); The output end of the second OR gate (OR2) is connected to the main signal output end of the control board for outputting the main signal of the control board; The input end of the first NOR gate (NOR1) is connected to the output ends of the ninth NOR gate (N9), the tenth NOR gate (N10), the eleventh NOR gate (N11), and the twelfth NOR gate (N12), and the even-numbered data lines in the output data bus of the D register (U1); The output end of the first NOR gate (NOR1) is connected to the master-slave switching circuit module of the master-slave switching circuit unit of the control board, and is used to provide the master-slave switching circuit module of the master-slave switching circuit unit of the control board with the master-slave downgrade signal of the control board.

5. The main-standby switching control system for emergency frequency modulation of power grid supported by energy storage according to claim 4, characterized in that: Each control board also includes: a reset signal output terminal of the board itself, and a reset signal input terminal of the opposite board; The reset signal output terminal of each control board is connected to the reset signal input terminal of another control board; The board reset signal input terminal of the control board is connected to the data reset terminal of the D register (U1), and is used to put the D register (U1) in a reset state when the board reset signal is in a reset state, and prohibit the data of the processor's output data bus from being written into the D register (U1).

6. The main-standby switching control system for emergency frequency modulation of power grid supported by energy storage according to claim 3, characterized in that: Each control panel also includes: dual main control signal input terminals; The input end of the first OR gate (OR1) is also connected to the dual main control signal input end of the control board, and is used for setting the main signal of the board of one of the control boards to the standby state by setting the dual main control signal input to the dual main control signal input end of one of the control boards to a high level when the main signals of the board of two control boards are both in the main state.

7. The main-standby switching control system for emergency frequency modulation of power grid supported by energy storage according to claim 3, characterized in that: Each control board also includes: a hot-swap delay control signal input terminal; The input end of the first OR gate (OR1) is also connected to the hot-swap delay control signal input end of the control board, and is used to keep the hot-swap delay control signal input end as a high-level signal when it is detected that the control board is not stably connected to the backplane during hot-swap operation of the control board, so that the main signal of the board output by the first OR gate (OR1) on the control board is in a standby state, and keep the hot-swap delay control signal input end as a low-level signal after the hot-swap of the control board is completed; Each control board also includes at least one slot number pin; all slot number pins are connected to the processor on the control board, and are used for the processor to sample and read the slot number of the control board on the backplane to determine whether the control board is stably plugged in.

8. The main-standby switching control system for emergency frequency modulation of power grid supported by energy storage according to claim 3, characterized in that: Each control board also includes: an odd slot delay signal input terminal; The input end of the first OR gate (OR1) is also connected to the odd slot delay signal input end of the control board, and is used to maintain the high level signal of the odd slot delay signal input end for a specified time for the control board installed in the odd slot of the backplane during reset, so that within the specified time, the main signal of the board output by the first OR gate (OR1) installed in the odd slot of the backplane is in a standby state.

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