Overvoltage and undervoltage surge voltage suppression circuit
By designing the overvoltage and undervoltage surge voltage suppression circuit of logic control circuit and shutdown circuit, the problems of insufficient sensitivity and slow boost response in the prior art are solved, and effective suppression of overvoltage and undervoltage surges are achieved. Stable power supply of the later stage power system.
Patent Information
- Application Number
- CN202420716876.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-09
- Publication Date
- 2025-02-18
- Estimated Expiration
- 2034-04-09
AI Technical Summary
The prior art has problems such as insufficient sensitivity, slow boost response and power failure in the overvoltage and undervoltage surge suppression.
An overvoltage undervoltage surge voltage suppression circuit including a logic control circuit and a shutdown circuit is designed. When the input end is over or undervoltage, the logic control circuit controls the shutdown circuit to turn off and the discharge circuit is turned on to achieve voltage suppression.
Through the coordination of the logic control circuit and the shutdown circuit, effective suppression of overvoltage and undervoltage surges is achieved, power loss of the later power supply system is avoided, and the sensitivity of the power supply is improved.
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Figure CN222509106U_ABST
Abstract
Description
Background Art
[0002] Most of the existing overvoltage surge suppression is designed based on the voltage stabilization and limiting principle, which places high requirements on the limiting tube. Most of the undervoltage surge is designed based on the boost method. The power supply switching has a large undershoot and the boost response is slow, which causes the subsequent power supply system to lose power, and places high requirements on the sensitivity of the power supply. Summary of the invention
[0003] The present application provides an overvoltage and undervoltage surge voltage suppression circuit for realizing overvoltage and undervoltage surge voltage suppression functions.
[0004] The present application provides an overvoltage, undervoltage and surge voltage suppression circuit, comprising: a logic control circuit and a shutdown circuit, wherein:
[0005] The logic control circuit is used to perform logic judgment and edit a control signal to the shutdown circuit;
[0006] The shut-off circuit is used to turn on and off the discharge circuit.
[0007] In the above technical solution, the logic control circuit is used to perform logic judgment and edit control signals to the shutdown circuit; the shutdown circuit is used to open and close the discharge circuit. When the input end is over-voltage or under-voltage, the logic control circuit controls the shutdown circuit to close and the discharge circuit to open, thereby realizing the over-voltage or under-voltage surge voltage suppression function.
[0008] In a specific implementation scheme, the logic control circuit includes a first comparator U2A and a second comparator U2B, wherein:
[0009] The non-inverting input terminal of the first comparator U2A is electrically connected to the output terminal of the first sampling bias circuit, and the inverting input terminal of the first comparator U2A is electrically connected to the voltage regulator U9;
[0010] The non-inverting input terminal of the second comparator U2B is electrically connected to the output terminal of the second sampling bias circuit, and the inverting input terminal of the second comparator U2B is electrically connected to the voltage regulator U9;
[0011] The output end of the first comparator U2A and the output end of the second comparator U2B are both electrically connected to the input end of the shutdown circuit.
[0012] In a specific implementation scheme, the shutdown circuit includes a second MOS transistor Q2 and a fourth MOS transistor Q4, wherein:
[0013] The G terminal of the fourth MOS tube Q4 is electrically connected to the output terminal of the first comparator U2A and the output terminal of the second comparator U2B;
[0014] The D terminal of the fourth MOS transistor Q4 is electrically connected to the G terminal of the second MOS transistor Q2, and the S terminal of the fourth MOS transistor Q4 is grounded;
[0015] The S terminal of the second MOS tube Q2 is electrically connected to the input terminal of the discharge circuit;
[0016] The D terminal of the second MOS transistor Q2 is electrically connected to the voltage input terminal VI.
[0017] In a specific implementation scheme, the shutdown circuit further includes a third diode D3 and a fourth resistor R4, wherein:
[0018] The conduction end of the third diode D3 is electrically connected to the G end of the second MOS transistor Q2, and the cut-off end of the third diode D3 is electrically connected to the D end of the second MOS transistor Q2.
[0019] The fourth resistor R4 is connected in parallel with the third diode D3.
[0020] In a specific implementation scheme, the discharge circuit includes a third MOS transistor Q3 and a fifth MOS transistor Q5, wherein:
[0021] The G terminal of the fifth MOS tube Q5 is electrically connected to the output terminal of the first comparator U2A and the output terminal of the second comparator U2B;
[0022] The D terminal of the fifth MOS transistor Q5 is electrically connected to the G terminal of the third MOS transistor Q3, and the S terminal of the fifth MOS transistor Q5 is grounded;
[0023] The D terminal of the third MOS transistor Q3 is electrically connected to the S terminal of the second MOS transistor Q2;
[0024] The S terminal of the third MOS transistor Q3 is electrically connected to the voltage output terminal VO.
[0025] In a specific implementation scheme, the discharge circuit further includes a fourth diode D4 and a sixth resistor R6, wherein:
[0026] The conducting end of the fourth diode D4 is electrically connected to the G end of the third MOS transistor Q3, and the blocking end of the fourth diode D4 is electrically connected to the D end of the third MOS transistor Q3.
[0027] The sixth resistor R6 is connected in parallel with the fourth diode D4.
[0028] In a specific embodiment, a sixth diode D6 is further included, wherein:
[0029] The conduction end of the sixth diode D6 is electrically connected to the S end of the second MOS transistor Q2 , and the cut-off end of the sixth diode D6 is electrically connected to the voltage output end VO.
[0030] In a specific implementation scheme, an inverter U3 is also included, wherein:
[0031] The input end of the inverter U3 is electrically connected to the output end of the first comparator U2A and the output end of the second comparator U2B;
[0032] The inverting output terminal of the inverter U3 is electrically connected to the G terminal of the fifth MOS tube Q5;
[0033] The positive phase output terminal of the inverter U3 is electrically connected to the D terminal of the third MOS transistor Q3 through a power supply circuit.
[0034] In a specific implementation scheme, it also includes a storage capacitor C1, a seventh diode D7 and an eighth resistor R8, wherein:
[0035] The first capacitor plate of the energy storage capacitor C1 is electrically connected to the conduction end of the seventh diode D7, the cut-off end of the seventh diode D7 is electrically connected to the D end of the third MOS tube Q3, and the first capacitor plate of the energy storage capacitor C1 is grounded;
[0036] The eighth resistor R8 is connected in parallel with the seventh diode D7.
[0037] In a specific implementation scheme, a fifth diode D5 is further included, wherein a conducting end of the fifth diode D5 is electrically connected to the S end of the third MOS transistor Q3 , and a cutting end of the fifth diode D5 is electrically connected to the voltage output end VO. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 A circuit diagram of an overvoltage, undervoltage, and surge voltage suppression circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0039] The present application is further described in detail below through the accompanying drawings and embodiments. Through these descriptions, the characteristics and advantages of the present application will become clearer and more specific.
[0040] The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise noted.
[0041] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0042] To facilitate understanding of the overvoltage and undervoltage surge voltage suppression circuit provided in the embodiment of the present application, its application scenario is first explained. The overvoltage and undervoltage surge voltage suppression circuit provided in the embodiment of the present application is used to realize the over- and undervoltage surge voltage suppression functions. Most of the existing overvoltage surge suppression adopts the voltage stabilization and limiting principle design, and has high requirements for the limiting tube. Most of the undervoltage surge adopts the boost method, and the power supply switching has a large undershoot, and the boost response is slow, resulting in power failure of the subsequent power supply system, and has high requirements for the sensitivity of the power supply. For this reason, the embodiment of the present application provides an overvoltage and undervoltage surge voltage suppression circuit to realize the overvoltage and undervoltage surge voltage suppression functions. The following is a detailed description of it with specific drawings and embodiments.
[0043] refer to Figure 1 , Figure 1 This is a circuit diagram of an overvoltage, undervoltage, surge voltage suppression circuit provided by an embodiment of the present application. Figure 1 In the embodiment of the present application, an overvoltage and undervoltage surge voltage suppression circuit is disclosed, including: a logic control circuit and a shutdown circuit, wherein:
[0044] The logic control circuit is used to perform logic judgment and edit a control signal to the shutdown circuit;
[0045] The shut-off circuit is used to turn on and off the discharge circuit.
[0046] In the above technical solution, the logic control circuit is used to perform logic judgment and edit control signals to the shutdown circuit; the shutdown circuit is used to open and close the discharge circuit. When the input end is over-voltage or under-voltage, the logic control circuit controls the shutdown circuit to close and the discharge circuit to open, thereby realizing the over-voltage or under-voltage surge voltage suppression function.
[0047] In a specific implementation scheme, the logic control circuit includes a first comparator U2A and a second comparator U2B, wherein:
[0048] The non-inverting input terminal of the first comparator U2A is electrically connected to the output terminal of the first sampling bias circuit, and the inverting input terminal of the first comparator U2A is electrically connected to the voltage regulator U9;
[0049] The non-inverting input terminal of the second comparator U2B is electrically connected to the output terminal of the second sampling bias circuit, and the inverting input terminal of the second comparator U2B is electrically connected to the voltage regulator U9;
[0050] The output end of the first comparator U2A and the output end of the second comparator U2B are both electrically connected to the input end of the shutdown circuit.
[0051] In a specific implementation scheme, the shutdown circuit includes a second MOS transistor Q2 and a fourth MOS transistor Q4, wherein:
[0052] The G terminal of the fourth MOS tube Q4 is electrically connected to the output terminal of the first comparator U2A and the output terminal of the second comparator U2B;
[0053] The D terminal of the fourth MOS transistor Q4 is electrically connected to the G terminal of the second MOS transistor Q2, and the S terminal of the fourth MOS transistor Q4 is grounded;
[0054] The S terminal of the second MOS tube Q2 is electrically connected to the input terminal of the discharge circuit;
[0055] The D terminal of the second MOS transistor Q2 is electrically connected to the voltage input terminal VI.
[0056] In a specific implementation scheme, the shutdown circuit further includes a third diode D3 and a fourth resistor R4, wherein:
[0057] The conduction end of the third diode D3 is electrically connected to the G end of the second MOS transistor Q2, and the cut-off end of the third diode D3 is electrically connected to the D end of the second MOS transistor Q2.
[0058] The fourth resistor R4 is connected in parallel with the third diode D3.
[0059] The shutdown circuit further includes a fifth resistor R5, one end of which is electrically connected to the D end of the fourth MOS transistor Q4, and the other end of which is electrically connected to the G end of the second MOS transistor Q2.
[0060] In a specific implementation scheme, the discharge circuit includes a third MOS transistor Q3 and a fifth MOS transistor Q5, wherein:
[0061] The G terminal of the fifth MOS tube Q5 is electrically connected to the output terminal of the first comparator U2A and the output terminal of the second comparator U2B;
[0062] The D terminal of the fifth MOS transistor Q5 is electrically connected to the G terminal of the third MOS transistor Q3, and the S terminal of the fifth MOS transistor Q5 is grounded;
[0063] The D terminal of the third MOS transistor Q3 is electrically connected to the S terminal of the second MOS transistor Q2;
[0064] The S terminal of the third MOS transistor Q3 is electrically connected to the voltage output terminal VO.
[0065] In a specific implementation scheme, the discharge circuit further includes a fourth diode D4 and a sixth resistor R6, wherein:
[0066] The conducting end of the fourth diode D4 is electrically connected to the G end of the third MOS transistor Q3, and the blocking end of the fourth diode D4 is electrically connected to the D end of the third MOS transistor Q3.
[0067] The sixth resistor R6 is connected in parallel with the fourth diode D4.
[0068] The discharge circuit further includes a seventh resistor R7, one end of which is electrically connected to the D end of the fifth MOS transistor Q5, and the other end of which is electrically connected to the G end of the third MOS transistor Q3.
[0069] In a specific embodiment, a sixth diode D6 is further included, wherein:
[0070] The conduction end of the sixth diode D6 is electrically connected to the S end of the second MOS transistor Q2 , and the cut-off end of the sixth diode D6 is electrically connected to the voltage output end VO.
[0071] In a specific implementation scheme, an inverter U3 is also included, wherein:
[0072] The input end of the inverter U3 is electrically connected to the output end of the first comparator U2A and the output end of the second comparator U2B;
[0073] The inverting output terminal of the inverter U3 is electrically connected to the G terminal of the fifth MOS tube Q5;
[0074] The positive phase output terminal of the inverter U3 is electrically connected to the D terminal of the third MOS transistor Q3 through a power supply circuit.
[0075] The power supply circuit includes a first power supply circuit and a second power supply circuit, wherein:
[0076] The first power supply circuit includes a first transistor Q1, a first diode D1, a second diode D2 and a first resistor R1, wherein:
[0077] The collector of the first transistor Q1 is electrically connected to the voltage input terminal VI.
[0078] The emitter of the first transistor Q1 is electrically connected to the conduction end of the second diode D2, and the cut-off end of the second diode D2 is electrically connected to the VCC voltage output end;
[0079] The VCC voltage output terminal is electrically connected to the VCC input terminal of the first comparator U2A and the VCC input terminal of the second comparator U2B respectively;
[0080] The base of the first diode D1 is electrically connected to the cut-off end of the first diode D1, and the conduction end of the first diode D1 is grounded;
[0081] One end of the first resistor R1 is electrically connected to the base of the first diode D1, and the other end of the first resistor R1 is electrically connected to the voltage input terminal VI.
[0082] It also includes a boost circuit; the voltage output end of the boost circuit is electrically connected to the D end of the third MOS tube Q3.
[0083] The second power supply circuit includes a seventh transistor Q7, an eighth diode D8, a ninth diode D9 and a ninth resistor R9, wherein:
[0084] The collector of the seventh transistor Q7 is electrically connected to the voltage output terminal of the boost circuit.
[0085] The emitter of the seventh transistor Q7 is electrically connected to the conduction end of the ninth diode D9, and the cut-off end of the ninth diode D9 is electrically connected to the VCC voltage output end;
[0086] The base of the eighth diode D8 is electrically connected to the cut-off end of the eighth diode D8, and the conduction end of the eighth diode D8 is grounded;
[0087] One end of the ninth resistor R9 is electrically connected to the base of the eighth diode D8, and the other end of the ninth resistor R9 is electrically connected to the voltage output end of the boost circuit.
[0088] In a specific implementation scheme, it also includes a storage capacitor C1, a seventh diode D7 and an eighth resistor R8, wherein:
[0089] The first capacitor plate of the energy storage capacitor C1 is electrically connected to the conduction end of the seventh diode D7, the cut-off end of the seventh diode D7 is electrically connected to the D end of the third MOS tube Q3, and the first capacitor plate of the energy storage capacitor C1 is grounded;
[0090] The eighth resistor R8 is connected in parallel with the seventh diode D7.
[0091] The device further comprises a fifth diode D5, wherein a conducting end of the fifth diode D5 is electrically connected to the S end of the third MOS transistor Q3, and a cutting end of the fifth diode D5 is electrically connected to the voltage output end VO.
[0092] In this embodiment, an invention is designed to address the shortcomings of existing over-voltage and under-voltage surge suppression circuits; an over-voltage and under-voltage surge voltage suppression circuit is provided, which mainly includes a power supply circuit, a logic control circuit, a first sampling bias circuit and a second sampling bias circuit, a shutdown circuit, a boost circuit, and a discharge circuit. Its working principle is: when the input end is over-voltage or under-voltage, the logic control circuit controls the shutdown circuit to shut down, the discharge circuit to open, and the energy storage capacitor to discharge to maintain the normal operation of the subsequent power supply system, thereby realizing the over-voltage and under-voltage surge voltage suppression function. The specific implementation process is:
[0093] In normal operation, the first sampling bias circuit is greater than the reference voltage 2.5V, the first comparator U2A outputs a high level, the second sampling bias circuit is less than the reference voltage 2.5V, the second comparator U2B outputs a high level, so the logic control circuit outputs a high level, controls the fourth MOS tube Q4 to be turned on, and the input circuit generates a bias in the fourth resistor R4 and the fifth resistor R5 to drive the second MOS tube Q2 to be turned on. The input voltage passes through the second MOS tube Q2, while supplying power to the power supply system at the output VO end through the sixth diode D6, and charging the first energy storage capacitor C1 through the boost circuit. Since the logic control circuit outputs a high level, it is a low level after passing through the inverter U3. At this time, the signal fifth MOS tube Q5 is not turned on, and the discharge third MOS tube Q3 is turned off, and the discharge circuit is in a closed state;
[0094] When the undervoltage 8V / 50mS surge voltage occurs, the first sampling bias circuit is less than the reference voltage 2.5V, the first comparator U2A outputs a low level, so the logic control circuit outputs a low level, the signal fourth MOS tube Q4 is turned off, the gate voltage of the power second MOS tube Q2 is equal to the source voltage, the power second MOS tube Q2 is turned off, the logic control circuit outputs a low level and outputs a high level through the inverter U3 to turn on the fifth MOS tube Q5, the voltage on the first energy storage capacitor C1 generates a bias to turn on the power third PMOS tube Q3 through the sixth resistor R6 and the seventh resistor R7, the voltage on the first energy storage capacitor C1 passes through the third MOS tube Q3, and the fifth diode D5 supplies power to the power system of the post-VO;
[0095] When the overvoltage 80V / 50mS surge voltage occurs, the second sampling bias circuit is greater than the reference voltage 2.5V, the second comparator U2B outputs a low level, so the logic control circuit outputs a low level, the signal fourth MOS tube Q4 is turned off, the gate voltage of the power second MOS tube Q2 is equal to the source voltage, the power second MOS tube Q2 is turned off, the logic control circuit outputs a low level and outputs a high level through the inverter U3 to turn on the fifth MOS tube Q5, the voltage on the first energy storage capacitor C1 generates a bias to turn on the power third MOS tube Q3 through the sixth resistor R6 and the seventh resistor R7, the voltage on the first energy storage capacitor C1 passes through the third MOS tube Q3, and the fifth diode D5 supplies power to the power supply system of the VO back stage. The above whole process realizes over-voltage and under-voltage surge suppression, meeting the requirements of GJB181.
[0096] Those skilled in the art will appreciate that the present application may be implemented as a system, method or computer program product.
[0097] Therefore, the present disclosure may be specifically implemented in the following forms, namely: it may be completely hardware, it may be completely software (including firmware, resident software, microcode, etc.), or it may be a combination of hardware and software, generally referred to herein as a "circuit", "module" or "system". In addition, in some embodiments, the present application may also be implemented in the form of a computer program product in one or more computer-readable media, and the computer-readable medium may contain computer-readable program code.
[0098] Any combination of one or more computer-readable media can be used. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.
[0099] Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art can change, modify, replace and modify the above embodiments within the scope of the present application. On this basis, a variety of replacements and improvements can be made to the present application, all of which fall within the scope of protection of the present application.
Claims
1. An overvoltage, undervoltage and surge voltage suppression circuit, characterized in that: include: Logic control circuit and shutdown circuit, where The logic control circuit is used to perform logic judgment and edit a control signal to the shutdown circuit; The shutoff circuit is used to turn on and off the discharge circuit; The logic control circuit includes a first comparator U2A and a second comparator U2B, wherein: The non-inverting input terminal of the first comparator U2A is electrically connected to the output terminal of the first sampling bias circuit, and the inverting input terminal of the first comparator U2A is electrically connected to the voltage regulator U9; The non-inverting input terminal of the second comparator U2B is electrically connected to the output terminal of the second sampling bias circuit, and the inverting input terminal of the second comparator U2B is electrically connected to the voltage regulator U9; The output end of the first comparator U2A and the output end of the second comparator U2B are both electrically connected to the input end of the shutdown circuit.
2. The overvoltage and undervoltage surge voltage suppression circuit according to claim 1, characterized in that: The shutdown circuit includes a second MOS transistor Q2 and a fourth MOS transistor Q4, wherein: The G terminal of the fourth MOS tube Q4 is electrically connected to the output terminal of the first comparator U2A and the output terminal of the second comparator U2B; The D terminal of the fourth MOS transistor Q4 is electrically connected to the G terminal of the second MOS transistor Q2, and the S terminal of the fourth MOS transistor Q4 is grounded; The S terminal of the second MOS tube Q2 is electrically connected to the input terminal of the discharge circuit; The D terminal of the second MOS transistor Q2 is electrically connected to the voltage input terminal VI.
3. The overvoltage and undervoltage surge voltage suppression circuit according to claim 2, characterized in that: The shutdown circuit further includes a third diode D3 and a fourth resistor R4, wherein: The conduction end of the third diode D3 is electrically connected to the G end of the second MOS transistor Q2, and the cut-off end of the third diode D3 is electrically connected to the D end of the second MOS transistor Q2. The fourth resistor R4 is connected in parallel with the third diode D3.
4. The overvoltage and undervoltage surge voltage suppression circuit according to claim 3, characterized in that: The discharge circuit includes a third MOS tube Q3 and a fifth MOS tube Q5, wherein: The G terminal of the fifth MOS tube Q5 is electrically connected to the output terminal of the first comparator U2A and the output terminal of the second comparator U2B; The D terminal of the fifth MOS transistor Q5 is electrically connected to the G terminal of the third MOS transistor Q3, and the S terminal of the fifth MOS transistor Q5 is grounded; The D terminal of the third MOS transistor Q3 is electrically connected to the S terminal of the second MOS transistor Q2; The S terminal of the third MOS transistor Q3 is electrically connected to the voltage output terminal VO.
5. The overvoltage and undervoltage surge voltage suppression circuit according to claim 4, characterized in that: The discharge circuit further includes a fourth diode D4 and a sixth resistor R6, wherein: The conducting end of the fourth diode D4 is electrically connected to the G end of the third MOS transistor Q3, and the blocking end of the fourth diode D4 is electrically connected to the D end of the third MOS transistor Q3. The sixth resistor R6 is connected in parallel with the fourth diode D4.
6. The overvoltage and undervoltage surge voltage suppression circuit according to claim 5, characterized in that: Also includes a sixth diode D6, wherein, The conduction end of the sixth diode D6 is electrically connected to the S end of the second MOS transistor Q2 , and the cut-off end of the sixth diode D6 is electrically connected to the voltage output end VO.
7. The overvoltage and undervoltage surge voltage suppression circuit according to claim 6, characterized in that: Also included is an inverter U3, wherein The input end of the inverter U3 is electrically connected to the output end of the first comparator U2A and the output end of the second comparator U2B; The inverting output terminal of the inverter U3 is electrically connected to the G terminal of the fifth MOS tube Q5; The positive phase output terminal of the inverter U3 is electrically connected to the D terminal of the third MOS transistor Q3 through a power supply circuit.
8. The overvoltage and undervoltage surge voltage suppression circuit according to claim 7, characterized in that: It also includes a storage capacitor C1, a seventh diode D7 and an eighth resistor R8, wherein: The first capacitor plate of the energy storage capacitor C1 is electrically connected to the conduction end of the seventh diode D7, the cut-off end of the seventh diode D7 is electrically connected to the D end of the third MOS tube Q3, and the first capacitor plate of the energy storage capacitor C1 is grounded; The eighth resistor R8 is connected in parallel with the seventh diode D7.
9. The overvoltage and undervoltage surge voltage suppression circuit according to claim 8, characterized in that: The device further comprises a fifth diode D5, wherein a conducting end of the fifth diode D5 is electrically connected to the S end of the third MOS transistor Q3, and a cutting end of the fifth diode D5 is electrically connected to the voltage output end VO.