Transverse voltage-resistant planar gate silicon carbide MOSFET

Abstract

The utility model provides a transverse voltage-resistant planar gate silicon carbide MOSFET, which is characterized in that the lower side surface of a P-type well region is connected to the upper side surface of a silicon carbide insulating substrate, the P-type well region is provided with an N-type voltage-resistant region, a P-type source region and a first N-type source region, and the P-type source region is connected to the first N-type source region; the lower side surface of the N-type well region is connected to the upper side surface of the silicon carbide insulating substrate, the left side surface of the N-type well region is connected to the right side surface of the P-type well region, and the N-type well region is provided with a second N-type source region and a P-type voltage-resistant region; the gate dielectric layer is respectively connected with the P-type well region, the N-type well region, the N-type voltage-withstanding region and the P-type voltage-withstanding region; the source metal layer is respectively connected with the P-type source region and the first N-type source region; the drain metal layer is connected to the second N-type source region; the gate metal layer is connected to the gate dielectric layer, the voltage endurance capability of the device is improved, and the thickness of the epitaxial layer does not need to be increased.

Description

Technical Field

[0001] The utility model relates to a planar gate silicon carbide MOSFET with lateral voltage resistance. Background Art

[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. The vertical withstand voltage capability of existing silicon carbide MOSFET is directly related to the thickness of its epitaxial layer. However, the process stability of the epitaxial layer of silicon carbide MOSFET devices decreases after exceeding 2μm, and the device cost increases sharply, so it is difficult to achieve the high vertical withstand voltage capability of silicon carbide MOSFET at a low cost. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a planar gate silicon carbide MOSFET with lateral voltage resistance, so as to improve the voltage resistance of the device without increasing the thickness of the epitaxial layer.

[0004] The utility model is implemented as follows: a lateral pressure-resistant planar gate silicon carbide MOSFET, comprising:

[0005] Silicon carbide insulating substrate,

[0006] A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the silicon carbide insulating substrate, an N-type voltage-withstand region, a P-type source region and a first N-type source region are provided on the P-type well region, and the P-type source region is connected to the first N-type source region;

[0007] An N-type well region, wherein the lower side of the N-type well region is connected to the upper side of the silicon carbide insulating substrate, the left side of the N-type well region is connected to the right side of the P-type well region, and a second N-type source region and a P-type voltage-resistant region are provided on the N-type well region;

[0008] A gate dielectric layer, wherein the gate dielectric layer is respectively connected to the P-type well region, the N-type well region, the N-type voltage-resistant region, and the P-type voltage-resistant region;

[0009] A source metal layer, the source metal layer is respectively connected to the P-type source region and the first N-type source region;

[0010] a drain metal layer, the drain metal layer being connected to the second N-type source region;

[0011] and a gate metal layer connected to the gate dielectric layer.

[0012] The advantages of the utility model are:

[0013] 1. The device adopts a lateral device structure and five pn junction structures to improve the device's withstand voltage level;

[0014] Second, the gate of the device can control all areas from the P-type source region to the second N-type source region to achieve control of the channel region;

[0015] 3. The device is provided with a P-type source region and a second N-type source region, which ensures that the device forms a good ohmic contact. When the device is not turned on, a single pn junction structure is formed from the P-type source region to the P-type well region, then to the N-type well region, and finally to the second N-type source region during the device continuous current flow, thereby reducing the body diode voltage of the device;

[0016] 4. The device substrate adopts silicon carbide insulating substrate, which has high compatibility in device preparation process and avoids leakage of the device to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0018] Figure 1 The utility model is a schematic diagram of a lateral pressure-resistant planar gate silicon carbide MOSFET.

[0019] Figure 2 The utility model is a flow chart of a method for preparing a lateral voltage-resistant planar gate silicon carbide MOSFET.

[0020] Figure 3 This is a cross-sectional view of the process of a lateral pressure-resistant planar gate silicon carbide MOSFE of the utility model. Figure 1 .

[0021] Figure 4 This is a cross-sectional view of the process of a lateral pressure-resistant planar gate silicon carbide MOSFE of the utility model. Figure 2 .

[0022] Figure 5 This is a cross-sectional view of the process of a lateral pressure-resistant planar gate silicon carbide MOSFE of the utility model. Figure 3 .

[0023] Figure 6 This is a cross-sectional view of the process of a lateral pressure-resistant planar gate silicon carbide MOSFE of the utility model. Figure 4 .

[0024] Figure 7 This is a cross-sectional view of the process of a lateral pressure-resistant planar gate silicon carbide MOSFE of the utility model. Figure 5 .

[0025] Figure 8 This is a cross-sectional view of the process of a lateral pressure-resistant planar gate silicon carbide MOSFE of the utility model. Figure 6 .

[0026] Fig. 9This is a cross-sectional view of the process of a lateral pressure-resistant planar gate silicon carbide MOSFE of the utility model. Figure 7 .

[0027] Fig.10 This is a cross-sectional view of the process of a lateral pressure-resistant planar gate silicon carbide MOSFE of the utility model. Figure 8 .

[0028] Fig.11 This is a cross-sectional view of the process of a lateral pressure-resistant planar gate silicon carbide MOSFE of the utility model. Figure 9 . DETAILED DESCRIPTION

[0029] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0032] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0033] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] like Figures 1 to 10 As shown, the embodiment of the present application provides a lateral voltage-resistant planar gate silicon carbide MOSFET, comprising:

[0035] Silicon carbide insulating substrate 1,

[0036] A P-type well region 2, wherein the lower side of the P-type well region 2 is connected to the upper side of the silicon carbide insulating substrate 1, and an N-type voltage-resistant region 21, a P-type source region 22 and a first N-type source region 23 are provided on the P-type well region 2, and the P-type source region 22 is connected to the first N-type source region 23;

[0037] An N-type well region 3, wherein the lower side of the N-type well region 3 is connected to the upper side of the silicon carbide insulating substrate 1, the left side of the N-type well region 3 is connected to the right side of the P-type well region 2, and a second N-type source region 31 and a P-type withstand voltage region 32 are provided on the N-type well region 3;

[0038] A gate dielectric layer 4, the gate dielectric layer is respectively connected to the P-type well region 2, the N-type well region 3, the N-type voltage-resistant region 21 and the P-type voltage-resistant region 32;

[0039] A source metal layer 5, wherein the source metal layer 5 is respectively connected to the P-type source region 22 and the first N-type source region 23;

[0040] a drain metal layer 6, wherein the drain metal layer 6 is connected to the second N-type source region 31;

[0041] and a gate metal layer 7 , wherein the gate metal layer 7 is connected to the gate dielectric layer 4 .

[0042] The thickness of the P-type well region 2 and the N-type well region 3 are both 1 micron.

[0043] The thickness of the P-type source region 22 , the first N-type source region 23 , the second N-type source region 31 , the P-type voltage-resistant region 32 and the N-type voltage-resistant region 21 are all 300 nm.

[0044] like Figures 2 to 11 As shown, the method for preparing the above MOSFET comprises the following steps:

[0045] Step 1, depositing and growing an N-type well region 3 on a silicon carbide insulating substrate 1, wherein the thickness of the N-type well region 3 is 1 μm;

[0046] Step 2, forming a barrier layer a above the N-type well region 3, etching the barrier layer a to form a through hole, and performing ion implantation on the N-type well region 3 to form a P-type well region 2, the ion implantation energy is 10-330kev, the depth is 0nm-1000nm, and the thickness of the P-type well region 2 is 1μm;

[0047] Step 3, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the P-type well region 2 and the N-type well region 3, respectively form a first N-type source region 23 and a second N-type source region 31, the ion implantation energy is 10-100kev, and the depth is 300nm;

[0048] Step 4, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the P-type well region 2, form a P-type source region 22, the implantation energy is 10-100kev, and the depth is 300nm;

[0049] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the P-type well region 2, and form an N-type withstand voltage region 21; the implantation energy is 10-100kev, and the depth is 300nm;

[0050] Step 6, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the N-type well region 3, form a P-type withstand voltage region 32, the implantation energy is 10-100kev, and the depth is 300nm;

[0051] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a, forming a through hole, and performing deposition to form a gate dielectric layer 4;

[0052] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a, forming a through hole, performing metal deposition, and forming a gate metal layer 7;

[0053] Step 9, remove the original barrier layer a, re-form the barrier layer a, etch to form two through holes, perform metal deposition to form a source metal layer 5 and a drain metal layer 6 respectively, remove the barrier layer a, and complete the preparation.

[0054] The thickness of the P-type well region 2 and the N-type well region 3 are both 1 micron, and the thickness of the P-type source region 22, the first N-type source region 23, the second N-type source region 31, the P-type voltage-resistant region 32 and the N-type voltage-resistant region 21 are all 300nm. This thickness structure is to form a field limiting ring through the npnpnp structure of the device to withstand the voltage when the drain of the device is subjected to a high voltage, and to form a single pn junction structure of the P-type source region 22-P-type well region 2-N-type well region 3-second N-type source region 31 when the body diode of the device is continuous, and the gate can complete the device close to the gate dielectric part when the device is turned on. The device is controlled to be turned on and off, thereby reducing the on-resistance of the device; there is only a second N-type source region 31 under the drain metal layer of the device, and a P-type source region 22 and a second N-type source region 23 are included under the source metal layer 5. This is because the doping in the second N-type source region 23 makes the carriers of the device conductive channel all electrons, which have high mobility and low on-resistance, thereby avoiding the reduction of on-resistance caused by the single P-type source region 22. At the same time, when the body diode is required for freewheeling, the P-type source region 22 and the P-type well region 2 have the same doping type and do not constitute a pn junction. Only a pn junction is formed in the P-type well region 2 and the N-type well region 3, and the body diode freewheeling loss is small.

[0055] In principle, the silicon carbide insulating substrate 1 is not doped. Due to the influence of the substrate process, the maximum doping concentration shall not exceed 1e12cm -3 The doping concentration of the N-type well region 3 is 6e16cm -3 The doping concentrations of the first N-type source region 23 and the second N-type source region 31 are both 2e18cm -3 The doping concentration of the P-type voltage-withstanding region 32 is 6e16cm -3 The doping concentration of the P-type well region 2 is 6e16cm -3 The doping concentration of the P-type source region 22 is 1e19cm -3 The doping concentration of the N-type voltage-sustaining region 21 is 6e16cm -3The gate dielectric layer 4 is silicon dioxide, and the highest doping concentration of the silicon carbide insulating substrate 1 is to ensure that the substrate leakage is small enough to suppress the leakage loss of the device. The doping concentrations of the N-type well region 3, the P-type voltage-resistant region 32, the P-type well region 2, and the N-type voltage-resistant region 21 are the same, so that when the drain is subjected to a high voltage, the four regions share the voltage equally, avoiding the electric field concentration under the gate dielectric and reducing the gate reliability of the device. The doping concentration of the second N-type source region 31 is to form a low-resistance ohmic contact to the drain, and the P-type source region 22 and the first N-type source region 23 are to form a low-resistance ohmic contact to the source.

[0056] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A lateral voltage-resistant planar gate silicon carbide MOSFET, characterized in that: include: Silicon carbide insulating substrate, A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the silicon carbide insulating substrate, an N-type voltage-withstand region, a P-type source region and a first N-type source region are provided on the P-type well region, and the P-type source region is connected to the first N-type source region; An N-type well region, wherein the lower side of the N-type well region is connected to the upper side of the silicon carbide insulating substrate, the left side of the N-type well region is connected to the right side of the P-type well region, and a second N-type source region and a P-type voltage-resistant region are provided on the N-type well region; A gate dielectric layer, wherein the gate dielectric layer is respectively connected to the P-type well region, the N-type well region, the N-type voltage-resistant region, and the P-type voltage-resistant region; A source metal layer, the source metal layer is respectively connected to the P-type source region and the first N-type source region; a drain metal layer, the drain metal layer being connected to the second N-type source region; and a gate metal layer connected to the gate dielectric layer.

2. A lateral voltage-resistant planar gate silicon carbide MOSFET according to claim 1, characterized in that: The thickness of the P-type well region and the N-type well region are both 1 micron.

3. A lateral voltage-resistant planar gate silicon carbide MOSFET according to claim 1, characterized in that: The thicknesses of the P-type source region, the first N-type source region, the second N-type source region, the P-type voltage-resistant region and the N-type voltage-resistant region are equal.

4. A lateral voltage-resistant planar gate silicon carbide MOSFET according to claim 3, characterized in that: The thickness of the P-type source region, the first N-type source region, the second N-type source region, the P-type voltage-resistant region and the N-type voltage-resistant region are all 300 nm.

Images