Voltage conversion circuit

Abstract

The voltage conversion circuit comprises a logic circuit, a drive control circuit, an upper bridge switch, a lower bridge switch and a discharge switch. The logic circuit receives a pulse width modulation signal from an input node and outputs a first control signal and a second control signal according to the pulse width modulation signal. The driving control circuit receives the first control signal and the second control signal and outputs an upper bridge switch control signal and a lower bridge switch control signal according to the first control signal and the second control signal. The upper bridge switch and the lower bridge switch respectively receive the upper bridge switch control signal and the lower bridge switch control signal and output a phase output signal according to the signals. The discharge switch is coupled between the input node and a ground terminal. The discharge switch is controlled by at least one of the pulse width modulation signal, the first control signal, the inverted phase of the second control signal, the inverted phase of the upper bridge switch control signal, the inverted phase of the lower bridge switch control signal, and the phase output signal. According to the utility model, an accelerated discharge path is formed in the process of converting the pulse width modulation signal from a high logic mode to a high impedance logic mode, so as to avoid the damage of the upper bridge switch.

Description

Technical Field

[0001] The utility model relates to a voltage conversion circuit. Background Art

[0002] A conventional voltage conversion circuit receives a pulse-width modulation (PWM) signal, and provides a first gate drive signal to an upper bridge switch and a second gate drive signal to a lower bridge switch according to the PWM signal. The upper bridge switch is turned on and off alternately according to the first gate drive signal, and the lower bridge switch is turned on and off alternately according to the second gate drive signal, so that the upper bridge switch and / or the lower bridge switch output a voltage signal accordingly. However, when the PWM signal is to be converted from a high logic mode to a high impedance logic mode, the upper bridge switch may be turned on too long due to the slow voltage drop of the PWM signal, resulting in the output voltage signal of the upper bridge switch being too high, which may cause the upper bridge switch to be damaged. Utility Model Content

[0003] The utility model aims to provide a voltage conversion circuit, comprising a logic circuit, a drive control circuit, an upper bridge switch, a lower bridge switch and a discharge switch. The logic circuit is coupled to an input node to receive a pulse width modulation signal and output a first control signal and a second control signal accordingly. The drive control circuit is coupled to the logic circuit to receive the first control signal and the second control signal, and outputs an upper bridge switch control signal and a lower bridge switch control signal accordingly, wherein the drive control circuit also receives a bootstrap power supply signal for driving the drive control circuit. The control end of the upper bridge switch is coupled to the drive control circuit to receive the upper bridge switch control signal. The control end of the lower bridge switch is coupled to the drive control circuit to receive the lower bridge switch control signal. The first end of the lower bridge switch and the second end of the upper bridge switch are coupled to a switching node, and a phase output signal is generated at the switching node. The discharge switch is coupled between the input node and the ground terminal. The discharge switch is controlled by at least one of the following: a pulse width modulation signal, a first control signal, an inversion of the second control signal, a bootstrap power supply signal, an upper bridge switch control signal, an inversion of the lower bridge switch control signal and a phase output signal.

[0004] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following detailed description in conjunction with the accompanying drawings will provide a better understanding of the present invention. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased at will to make the discussion clearer.

[0006] Figure 1 is a circuit diagram of a voltage conversion circuit according to an illustrative example of the present utility model;

[0007] Figure 2 It is the timing diagram of various signals of the voltage conversion circuit;

[0008] Figure 3 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0009] Figure 4 is a circuit diagram of a logic circuit according to an embodiment of the utility model;

[0010] Figure 5 is a timing diagram of various signals of a voltage conversion circuit according to an embodiment of the utility model;

[0011] Figure 6 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0012] Figure 7 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0013] Figure 8 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0014] Fig. 9 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0015] Fig.10 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0016] Fig.11 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0017] Fig.12 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0018] Fig.13 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0019] Fig.14 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0020] Fig.15 is a timing diagram of various signals of a voltage conversion circuit according to another embodiment of the utility model;

[0021] Fig.16 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0022] Fig.17 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0023] Fig.18 is a circuit diagram of a voltage conversion circuit according to an embodiment of the utility model;

[0024] Fig.19 is a circuit diagram of a switch control circuit according to an embodiment of the utility model;

[0025] Fig. 20 is a timing diagram of various signals of a voltage conversion circuit according to another embodiment of the utility model;

[0026] Fig.21 is a flow chart of a voltage conversion method according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0027] The following is a detailed discussion of the embodiments of the present invention. However, it is understood that the embodiments provide many applicable concepts that can be implemented in a variety of specific contexts. The embodiments discussed and disclosed are for illustration only and are not intended to limit the scope of the present invention. The terms "first", "second", etc. used herein do not specifically refer to order or sequence, but are only used to distinguish between elements or operations described in the same technical terms.

[0028] Figure 1 1 is a circuit diagram of a voltage conversion circuit 100 according to an illustrative example of the present invention. The voltage conversion circuit 100 includes a logic circuit 110, a drive control circuit 120, an upper bridge switch 130, a lower bridge switch 140, a current source 150, a current sink 160, an output inductor Lout and an output capacitor Cout. Figure 2 is a timing chart of various signals of the voltage conversion circuit 100 .

[0029] The logic circuit 110 is coupled to the input node IN to receive the pulse width modulation signal PWM and output the first control signal PWMH, the second control signal PWML and the third control signal HiZ accordingly. It is worth mentioning that the pulse width modulation signal PWM is generated by the front stage circuit ( Figure 1When the pulse width modulation signal PWM is driven by the previous stage circuit and is in a high logic mode, the first control signal PWMH is at a high level and the second control signal PWML and the third control signal HiZ are at a low level. When the pulse width modulation signal PWM is driven by the previous stage circuit and is in a low logic mode, the second control signal PWML is at a high level and the first control signal PWMH and the third control signal HiZ are at a low level. When the pulse width modulation signal PWM is not driven by the previous stage circuit and is in a high impedance logic mode (or tri-state mode), the third control signal HiZ is at a high level and the first control signal PWMH and the second control signal PWML are at a low level.

[0030] The driving control circuit 120 is coupled to the logic circuit 110 to receive the first control signal PWMH, the second control signal PWML and the third control signal HiZ, and outputs the upper bridge switch control signal UG and the lower bridge switch control signal LG accordingly, wherein the driving control circuit 120 also receives a bootstrap power signal BOOT for driving the driving control circuit 120. The upper bridge switch control signal UG is positively correlated with the first control signal PWMH and negatively correlated with the lower bridge switch control signal LG. The utility model does not limit the circuit composition of the driving control circuit 120, as long as it can be constituted to receive the first control signal PWMH, the second control signal PWML and the third control signal HiZ and output the upper bridge switch control signal UG and the lower bridge switch control signal LG accordingly, it can be applied to the utility model.

[0031] The control end of the upper bridge switch 130 is coupled to the driving control circuit 120 to receive the upper bridge switch control signal UG. The control end of the lower bridge switch 140 is coupled to the driving control circuit 120 to receive the lower bridge switch control signal LG. The first end of the upper bridge switch 130 is coupled to the voltage source VIN, the second end of the lower bridge switch 140 is coupled to the ground terminal GND, the first end of the lower bridge switch 140 and the second end of the upper bridge switch 130 are coupled to the switching node SW, and the upper bridge switch 130 and the lower bridge switch 140 are used to output the phase output signal PHASE at the switching node SW. In other words, the phase output signal PHASE is generated at the switching node SW. In an embodiment of the present invention, the upper bridge switch 130 and the lower bridge switch 140 are, for example, N-type metal oxide semiconductor field effect transistors (MOSFETs), but the present invention is not limited thereto. When the upper bridge switch 130 is implemented by an N-type MOSFET, the gate, drain and source of this N-type MOSFET correspond to the control end, the first end and the second end of the upper bridge switch 130 respectively; when the lower bridge switch 140 is implemented by an N-type MOSFET, the gate, drain and source of this N-type MOSFET correspond to the control end, the first end and the second end of the lower bridge switch 140 respectively.

[0032] The output inductor Lout is coupled between the switch node SW and the load node NL. The output inductor Lout and the output capacitor Cout form a filter for filtering the phase output signal PHASE to generate an output voltage Vout at the load node NL.

[0033] Current stage circuit ( Figure 1 The current source 150 (not shown) does not drive the pulse width modulation signal PWM, the current source 150 pulls up the voltage value of the pulse width modulation signal PWM through the voltage source VCC, and the current sink 160 pulls down the voltage value of the pulse width modulation signal PWM through the ground terminal GND. Specifically, the current source 150 and the current sink 160 cooperate with each other to control the pulse width modulation signal PWM to have a desired voltage level, such as a high impedance logic level.

[0034] like Figure 2 As shown, in time period t1, the pulse width modulation signal PWM is in high logic mode (Hi mode); in time period t3, the pulse width modulation signal PWM is in tri-state mode (or high impedance logic mode). Time period t2 is the process of the pulse width modulation signal PWM changing from high logic mode to high impedance logic mode. To be more specific, in time period t2, the voltage value of the pulse width modulation signal PWM is pulled down by the current sink 160 in a fixed sink current manner. However, the sink current of the above-mentioned current sink 160 is not large enough, resulting in Figure 2 The voltage drop speed of the pulse width modulation signal PWM in the time period t2 is too slow, which will cause the upper bridge switch 130 to be continuously turned on because the upper bridge switch control signal UG is at a high level, causing the output voltage Vout to continue to rise. However, if the output voltage Vout is too high and the current of the output inductor Lout is too high, there is a risk of damage to the upper bridge switch 130.

[0035] Therefore, the purpose of the present invention is to form an accelerated discharge path for the pulse width modulation signal PWM when the pulse width modulation signal PWM is about to change from the high logic mode to the high impedance logic mode, so that the output voltage Vout and the current of the output inductor Lout will not be too high, thereby avoiding damage to the upper bridge switch 130.

[0036] Figure 3is a circuit diagram of a voltage conversion circuit 200A according to an embodiment of the present utility model. The voltage conversion circuit 200A is similar to the voltage conversion circuit 100, except that the voltage conversion circuit 200A further includes a resistor R1 and a discharge switch SW1. The discharge switch SW1 is coupled between the input node IN and the ground terminal GND. Specifically, the resistor R1 and the discharge switch SW1 are connected in series and coupled between the input node IN and the ground terminal GND. The discharge switch SW1 is controlled by a switch control signal SW_CTRL. Figure 3 In the embodiment of the present invention, the first control signal PWMH is used as the switch control signal SW_CTRL to control the discharge switch SW1 (i.e., the switch control signal SW_CTRL of the discharge switch SW1 is the first control signal PWMH). When the first control signal PWMH is at a high level, the discharge switch SW1 will be turned on to form a discharge path between the input node IN and the ground terminal GND as an accelerated discharge path of the pulse width modulation signal PWM. In detail, Figure 3 As shown, the first control signal PWMH is used to directly control the on-off of the discharge switch SW1, that is, the discharge switch SW1 is directly controlled by the first control signal PWMH. In the embodiment of the present invention, the discharge switch SW1 is, for example, a transistor or a MOSFET, but the present invention is not limited thereto.

[0037] Figure 4 1 is a circuit diagram of a logic circuit 110 according to an embodiment of the present utility model. The logic circuit 110 includes a first comparator CP1, a second comparator CP2 and a NOR gate NOR1. The positive input terminal (+) of the first comparator CP1 and the negative input terminal (-) of the second comparator CP2 are used to receive the pulse width modulation signal PWM, the negative input terminal of the first comparator CP1 receives the first high input threshold voltage VPWM_H, and the positive input terminal of the second comparator CP2 receives the first low input threshold voltage VPWM_L. The first comparator CP1 is used to compare the pulse width modulation signal PWM with the first high input threshold voltage VPWM_H and output the first control signal PWMH accordingly. The second comparator CP2 is used to compare the pulse width modulation signal PWM with the first low input threshold voltage VPWM_L and output the second control signal PWML accordingly. The two input terminals of the NOR gate NOR1 are respectively coupled to the output terminal of the first comparator CP1 and the output terminal of the second comparator CP2 to receive the first control signal PWMH and the second control signal PWML respectively, and output the third control signal HiZ accordingly.

[0038] Figure 5 2 is a timing diagram of various signals of the voltage conversion circuit 200A (also applicable to the voltage conversion circuits 200B, 200C, 300, 400, 500, 600, 700 and 800). Figure 5As shown, the high impedance logic level V_HiZ is between a first high input threshold voltage VPWM_H and a first low input threshold voltage VPWM_L. The first high input threshold voltage VPWM_H is lower than the high logic level V_H of the pulse width modulation signal PWM and higher than the high impedance logic level V_HiZ of the pulse width modulation signal PWM. The first low input threshold voltage VPWM_L is lower than the high impedance logic level V_HiZ of the pulse width modulation signal PWM and higher than the low logic level V_L of the pulse width modulation signal PWM.

[0039] Specifically, if Figure 4 As shown, when the pulse width modulation signal PWM is higher than the first high input threshold voltage VPWM_H, the first control signal PWMH is at a high level and the second control signal PWML and the third control signal HiZ are at a low level, that is, the logic circuit 110 determines that the pulse width modulation signal PWM is in a high logic mode; when the pulse width modulation signal PWM is lower than the first low input threshold voltage VPWM_L, the second control signal PWML is at a high level and the first control signal PWMH and the third control signal HiZ are at a low level, that is, the logic circuit 110 determines that the pulse width modulation signal PWM is in a low logic mode; when the pulse width modulation signal PWM is lower than the first high input threshold voltage VPWM_H and higher than the first low input threshold voltage VPWM_L, the third control signal HiZ is at a high level and the first control signal PWMH and the second control signal PWML are at a low level, that is, the logic circuit 110 determines that the pulse width modulation signal PWM is in a high impedance logic mode. Therefore, according to the level of the third control signal HiZ, it can be known that the third control signal HiZ can indicate whether the pulse width modulation signal PWM is in a high impedance logic mode.

[0040] like Figure 5 As shown, in time period t1, the pulse width modulation signal PWM is driven by the previous stage circuit and is in high logic mode; in time period t3, the pulse width modulation signal PWM is not driven by the previous stage circuit and is in high impedance logic mode. Time period t2 is the process of the pulse width modulation signal PWM not being driven by the previous stage circuit and changing from high logic mode to high impedance logic mode. Figure 3 and Figure 5 As shown, in time period t2, since the first control signal PWMH is at a high level, the discharge switch SW1 will be turned on to form an accelerated discharge path of the pulse width modulation signal PWM. Specifically, when the pulse width modulation signal PWM is higher than the first high input threshold voltage VPWM_H, the first control signal PWMH is at a high level, so the discharge switch SW1 will be turned on to form an accelerated discharge path of the pulse width modulation signal PWM.

[0041] In other words, in the time period t2, the voltage value of the pulse width modulation signal PWM is not only pulled down by the current drawn by the current drawer 160, but also pulled down by the accelerated discharge path formed by the discharge switch SW1. Figure 2 and Figure 5 As shown, the voltage drop speed of the pulse width modulation signal PWM of the voltage conversion circuit 200A in the time period t2 is accelerated, and the duration of the time period t2 is shortened (that is, the conduction time of the upper bridge switch 130 is shortened), so that the output voltage Vout and the current of the output inductor Lout will not be too high, so as to avoid damage to the upper bridge switch 130. Specifically, as Figure 5 As shown in the time period t2, when the pulse width modulation signal PWM is not driven by the previous stage circuit and is in the process of changing from the high logic mode to the high impedance logic mode (i.e., the time period t2), the discharge switch SW1 is turned on (the switch control signal SW_CTRL is at a high level) to form an accelerated discharge path of the pulse width modulation signal PWM, thereby increasing the falling speed of the pulse width modulation signal PWM. Specifically, Figure 5 As shown in the time period t3, when the pulse width modulation signal PWM is in the high impedance logic mode (ie, the time period t3), the discharge switch SW1 is turned off (the switch control signal SW_CTRL is at a low level).

[0042] Figure 6 2 is a circuit diagram of a voltage conversion circuit 200B according to an embodiment of the present invention. The voltage conversion circuit 200B is similar to the voltage conversion circuit 200A, except that the discharge switch SW1 of the voltage conversion circuit 200B is connected in series with the current sink IS1 and coupled between the input node IN and the ground terminal GND.

[0043] Figure 7 2 is a circuit diagram of a voltage conversion circuit 200C according to an embodiment of the present invention. The voltage conversion circuit 200C is similar to the voltage conversion circuit 200A and / or 200B, except that the discharge switch SW1 of the voltage conversion circuit 200C is directly coupled between the input node IN and the ground terminal GND. Specifically, Figure 7 The discharge switch SW1 of the voltage conversion circuit 200C shown is a switch with built-in impedance. Therefore, in the time period t2, when the discharge switch SW1 of the voltage conversion circuit 200C is turned on, the pulse width modulation signal PWM can also form an accelerated discharge path through the built-in impedance of the discharge switch SW1 to pull down the voltage value of the pulse width modulation signal PWM.

[0044] Figure 8is a circuit diagram of a voltage conversion circuit 300 according to an embodiment of the present invention. The voltage conversion circuit 300 is similar to the voltage conversion circuit 200C, except that the upper bridge switch control signal UG is used as the switch control signal SW_CTRL to control the discharge switch SW1 (i.e., the switch control signal SW_CTRL of the discharge switch SW1 is the upper bridge switch control signal UG). When the upper bridge switch control signal UG is at a high level, the discharge switch SW1 will be turned on to form a discharge path between the input node IN and the ground terminal GND, which serves as an accelerated discharge path for the pulse width modulation signal PWM. In detail, as Figure 8 As shown, the upper bridge switch control signal UG is used to directly control the on-off of the discharge switch SW1, that is, the discharge switch SW1 is directly controlled by the upper bridge switch control signal UG. Figure 5 As shown, the upper bridge switch control signal UG is positively correlated with the first control signal PWMH. Therefore, if the discharge switch SW1 is controlled by the upper bridge switch control signal UG, an accelerated discharge path of the pulse width modulation signal PWM can also be formed when the pulse width modulation signal PWM is about to change from the high logic mode to the high impedance logic mode (i.e., time period t2).

[0045] Fig. 9 is a circuit diagram of a voltage conversion circuit 400 according to an embodiment of the present utility model. The voltage conversion circuit 400 is similar to the voltage conversion circuit 200C, except that the bootstrap power signal BOOT is used as the switch control signal SW_CTRL to control the discharge switch SW1 (i.e., the switch control signal SW_CTRL of the discharge switch SW1 is the bootstrap power signal BOOT), and when the bootstrap power signal BOOT is at a high level, the discharge switch SW1 will be turned on to form a discharge path between the input node IN and the ground terminal GND, serving as an accelerated discharge path for the pulse width modulation signal PWM. It is worth mentioning that the bootstrap power signal BOOT is a signal generated by boost coupling of the phase output signal PHASE of the switching node SW (the bootstrap power signal BOOT may be generated by the phase output signal PHASE through some known signal processing, but the present utility model is not limited here), therefore, Figure 5 As shown in FIG. 1 , the waveforms of the bootstrap power supply signal BOOT and the phase output signal PHASE are substantially consistent. Fig. 9 As shown in FIG. 1 , the bootstrap power signal BOOT is used to directly control the on / off of the discharge switch SW1 , that is, the discharge switch SW1 is directly controlled by the bootstrap power signal BOOT. Specifically, Figure 5As shown, the bootstrap power signal BOOT is positively correlated with the first control signal PWMH. Therefore, if the discharge switch SW1 is controlled by the bootstrap power signal BOOT, an accelerated discharge path of the pulse width modulation signal PWM can also be formed when the pulse width modulation signal PWM is about to change from the high logic mode to the high impedance logic mode (i.e., time period t2).

[0046] Fig.10 is a circuit diagram of a voltage conversion circuit 500 according to an embodiment of the present invention. The voltage conversion circuit 500 is similar to the voltage conversion circuit 200C, except that the phase output signal PHASE is used as the switch control signal SW_CTRL to control the discharge switch SW1 (i.e., the switch control signal SW_CTRL of the discharge switch SW1 is the phase output signal PHASE). When the phase output signal PHASE is at a high level, the discharge switch SW1 will be turned on to form a discharge path between the input node IN and the ground terminal GND, which serves as an accelerated discharge path for the pulse width modulation signal PWM. In detail, Fig.10 As shown in FIG. 1 , the phase output signal PHASE is used to directly control the on-off of the discharge switch SW1 , that is, the discharge switch SW1 is directly controlled by the phase output signal PHASE. Figure 5 As shown, the phase output signal PHASE is positively correlated with the first control signal PWMH. Therefore, if the discharge switch SW1 is controlled by the phase output signal PHASE, an accelerated discharge path of the pulse width modulation signal PWM can also be formed when the pulse width modulation signal PWM is about to change from the high logic mode to the high impedance logic mode (i.e., time period t2).

[0047] Fig.11 is a circuit diagram of a voltage conversion circuit 600 according to an embodiment of the present utility model. The voltage conversion circuit 600 is similar to the voltage conversion circuit 200C, except that the inverse of the second control signal PWML is used as the switch control signal SW_CTRL to control the discharge switch SW1. Specifically, Figure 5 As shown, the second control signal PWML is negatively correlated with the first control signal PWMH during the time period t2 and before the time period t2 (i.e., before the pulse width modulation signal PWM switches to the high impedance logic mode). Therefore, if the discharge switch SW1 is controlled by the inverse phase of the second control signal PWML (i.e., the control signal PWMLb), an accelerated discharge path of the pulse width modulation signal PWM can also be formed during the process of the pulse width modulation signal PWM switching from the high logic mode to the high impedance logic mode (i.e., the time period t2). It should be noted that, Fig.11As shown, the voltage conversion circuit 600 further includes a first AND gate AND1, which is coupled to the discharge switch SW1 and is used to perform an AND logic operation on the inverse of the second control signal PWML (i.e., the control signal PWMLb) and the inverse of the third control signal HiZ (i.e., the control signal HiZb), thereby outputting a switch control signal SW_CTRL to the discharge switch SW1 to control the on-off of the discharge switch SW1.

[0048] Please refer to Fig.11 and Figure 5 In the time periods t1 and t2, the second control signal PWML and the third control signal HiZ are both at low levels, so the result of the AND logic operation of the inverse of the second control signal PWML (i.e., the control signal PWMLb) and the inverse of the third control signal HiZ (i.e., the control signal HiZb) is high (i.e., the switch control signal SW_CTRL is high), and the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM. Therefore, it can be seen that when the pulse width modulation signal PWM is not driven by the previous circuit and is in the process of changing from a high logic mode to a high impedance logic mode (i.e., the time period t2), the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM, thereby increasing the falling speed of the pulse width modulation signal PWM.

[0049] On the other hand, during the time period t3, the second control signal PWML is still at a low level, but the third control signal HiZ has changed to a high level, so the result of the logical AND operation of the inverse of the second control signal PWML (i.e., the control signal PWMLb) and the inverse of the third control signal HiZ (i.e., the control signal HiZb) is a low level (i.e., the switch control signal SW_CTRL is a low level), and the discharge switch SW1 is turned off to close the accelerated discharge path of the pulse width modulation signal PWM. Specifically, in the time period t3, the inverse of the second control signal PWML (i.e., the control signal PWMLb) is still at a high level, but it is designed to disconnect the discharge switch SW1 in the time period t3 so that the pulse width modulation signal PWM can be maintained in the high impedance logic mode. Therefore, the voltage conversion circuit 600 performs an AND logic operation on the inverse of the second control signal PWML (i.e., the control signal PWMLb) and the inverse of the third control signal HiZ (i.e., the control signal HiZb), so that in the time period t3, the switch control signal SW_CTRL is at a low level, thereby disconnecting the discharge switch SW1.

[0050] Fig.12is a circuit diagram of a voltage conversion circuit 700 according to an embodiment of the present utility model. The voltage conversion circuit 700 is similar to the voltage conversion circuit 600, except that one of the input signals of the first AND gate AND1 is replaced by the inverse of the second control signal PWML (i.e., the control signal PWMLb) with the inverse of the lower bridge switch control signal LG (i.e., the control signal LGb), and the inverse of the lower bridge switch control signal LG is used as the switch control signal SW_CTRL to control the discharge switch SW1. Specifically, as Figure 5 As shown, the lower bridge switch control signal LG is positively correlated with the second control signal PWML. Therefore, if the discharge switch SW1 is controlled by the inverse of the lower bridge switch control signal LG (i.e., the control signal LGb), an accelerated discharge path of the pulse width modulation signal PWM can also be formed during the process of the pulse width modulation signal PWM changing from the high logic mode to the high impedance logic mode (i.e., the time period t2). It should be noted that, Fig.12 As shown, the voltage conversion circuit 700 also includes a first AND gate AND1, which is coupled to the discharge switch SW1 and is used to perform an AND logic operation on the inverted phase of the lower bridge switch control signal LG (i.e., the control signal LGb) and the inverted phase of the third control signal HiZ (i.e., the control signal HiZb), thereby outputting a switch control signal SW_CTRL to the discharge switch SW1 to control the on and off of the discharge switch SW1.

[0051] Please refer to Fig.12 and Figure 5 In the time periods t1 and t2, the lower bridge switch control signal LG and the third control signal HiZ are both at low level, so the result of the AND logic operation of the inverse of the lower bridge switch control signal LG (i.e., the control signal LGb) and the inverse of the third control signal HiZ (i.e., the control signal HiZb) is high level (i.e., the switch control signal SW_CTRL is at high level), and the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM. Therefore, it can be seen that when the pulse width modulation signal PWM is not driven by the previous stage circuit and is in the process of changing from the high logic mode to the high impedance logic mode (i.e., the time period t2), the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM, thereby increasing the falling speed of the pulse width modulation signal PWM.

[0052] On the other hand, in the time period t3, the inverse of the lower bridge switch control signal LG (i.e., the control signal LGb) is still at a high level, but it is designed to disconnect the discharge switch SW1 in the time period t3 so that the pulse width modulation signal PWM can be maintained in the high impedance logic mode. Therefore, the voltage conversion circuit 700 performs an AND logic operation on the inverse of the lower bridge switch control signal LG (i.e., the control signal LGb) and the inverse of the third control signal HiZ (i.e., the control signal HiZb), so that in the time period t3, the switch control signal SW_CTRL is at a low level, thereby disconnecting the discharge switch SW1.

[0053] Fig.13 8 is a circuit diagram of a voltage conversion circuit 800 according to an embodiment of the present invention. The voltage conversion circuit 800 is similar to the voltage conversion circuit 200C, except that the inverse of the third control signal HiZ is used as the switch control signal SW_CTRL to control the discharge switch SW1. Fig.13 As shown, the inverse phase of the third control signal HiZ is used to directly control the on-off of the discharge switch SW1, that is, the discharge switch SW1 is directly controlled by the inverse phase of the third control signal HiZ. Figure 5 As shown, the third control signal HiZ is negatively correlated with the first control signal PWMH in time periods t1, t2 and t3. Therefore, if the discharge switch SW1 is controlled by the inverse phase of the third control signal HiZ (i.e., the control signal HiZb), an accelerated discharge path of the pulse width modulation signal PWM can also be formed when the pulse width modulation signal PWM is about to change from the high logic mode to the high impedance logic mode (i.e., time period t2).

[0054] Please refer to Fig.13 and Figure 5 , in time periods t1 and t2, the third control signal HiZ is at a low level, so the inverse of the third control signal HiZ is at a high level (i.e., the switch control signal SW_CTRL is at a high level), and the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM. Therefore, it can be seen that when the pulse width modulation signal PWM is not driven by the previous circuit and is in the process of changing from a high logic mode to a high impedance logic mode (i.e., time period t2), the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM, thereby increasing the falling speed of the pulse width modulation signal PWM. On the other hand, in time period t3, the inverse of the third control signal HiZ (i.e., the control signal HiZb) has changed to a low level (i.e., the switch control signal SW_CTRL is at a low level), thereby turning off the discharge switch SW1.

[0055] Fig.14is a circuit diagram of a voltage conversion circuit 900 according to an embodiment of the present utility model. The voltage conversion circuit 900 is similar to the voltage conversion circuit 200C, except that the discharge switch SW1 of the voltage conversion circuit 900 is controlled by a pulse width modulation signal PWM. Specifically, Figure 5 As shown, the pulse width modulation signal PWM is positively correlated with the first control signal PWMH (from the perspective of digital signals) in the time period t1 and the time period t2. Therefore, if the discharge switch SW1 is controlled by the pulse width modulation signal PWM, an accelerated discharge path of the pulse width modulation signal PWM can also be formed when the pulse width modulation signal PWM is about to change from the high logic mode to the high impedance logic mode (i.e., the time period t2).

[0056] It should be noted that if Fig.14 As shown, the voltage conversion circuit 900 further includes a level generating circuit GEN1. The level generating circuit GEN1 is coupled to the input node IN and is used to receive the pulse width modulation signal PWM and output a switch conduction signal DFF_Q according to the level of the pulse width modulation signal PWM, that is, the output switch conduction signal DFF_Q is associated with the level of the pulse width modulation signal PWM. Fig.14 In the embodiment of the present invention, the switch conduction signal DFF_Q is used as the switch control signal SW_CTRL of the discharge switch SW1. The level generating circuit GEN1 includes a third comparator CP3, a fourth comparator CP4 and a set-reset trigger (SR trigger) SR1. The negative input terminal (-) of the third comparator CP3 and the negative input terminal of the fourth comparator CP4 are used to receive the pulse width modulation signal PWM, the positive input terminal (+) of the third comparator CP3 receives the second high input threshold voltage VPWM_SWH, and the positive input terminal of the fourth comparator CP4 receives the second low input threshold voltage VPWM_SWL. The third comparator CP3 is used to compare the pulse width modulation signal PWM with the second high input threshold voltage VPWM_SWH and output the first comparison signal DFF_S accordingly. The fourth comparator CP4 is used to compare the pulse width modulation signal PWM with the second low input threshold voltage VPWM_SWL and output the second comparison signal DFF_R accordingly. The set terminal (S) of the SR flip-flop SR1 is coupled to the output terminal of the third comparator CP3 to receive the first comparison signal DFF_S, and the reset terminal (R) of the SR flip-flop SR1 is coupled to the output terminal of the fourth comparator CP4 to receive the second comparison signal DFF_R. The SR flip-flop SR1 outputs the switch-on signal DFF_Q at the output terminal (Q) according to the first comparison signal DFF_S and the second comparison signal DFF_R. Therefore, it can be known that Fig.14 As shown, the switch-on signal DFF_Q is used to directly control the on-off of the discharge switch SW1 , that is, the discharge switch SW1 is directly controlled by the switch-on signal DFF_Q.

[0057] Fig.15 is a timing diagram of various signals of the voltage conversion circuit 900 (also applicable to the voltage conversion circuits 1000 and 1100). Fig.15 As shown, the second high input threshold voltage VPWM_SWH is lower than the high logic level V_H of the pulse width modulation signal PWM and higher than the first high input threshold voltage VPWM_H, and the second low input threshold voltage VPWM_SWL is lower than the first high input threshold voltage VPWM_H and higher than the high impedance logic level V_HiZ of the pulse width modulation signal PWM. Within the above voltage range, the second high input threshold voltage VPWM_SWH and the second low input threshold voltage VPWM_SWL can be determined according to system requirements.

[0058] like Fig.14 and Fig.15 As shown, in time periods t1 and t2, the pulse width modulation signal PWM is higher than the second high input threshold voltage VPWM_SWH and the second low input threshold voltage VPWM_SWL, the first comparison signal DFF_S and the second comparison signal DFF_R are both low, so the switch conduction signal DFF_Q is also low (i.e., the switch control signal SW_CTRL is low), the discharge switch SW1 is disconnected, and at this time, the pulse width modulation signal PWM is determined to be in a high logic mode. In time period t5, the pulse width modulation signal PWM is lower than the second high input threshold voltage VPWM_SWH and higher than the second low input threshold voltage VPWM_SWL, the first comparison signal DFF_S and the second comparison signal DFF_R are both high, so the switch conduction signal DFF_Q is low (i.e., the switch control signal SW_CTRL is low), the discharge switch SW1 is disconnected, and at this time, the pulse width modulation signal PWM is in a high impedance logic mode. See. Fig.15 In the time period t5, the pulse width modulation signal PWM drops from the second low input threshold voltage VPWM_SWL to the high impedance logic level V_HiZ and maintains at the high impedance logic level V_HiZ. Since the second low input threshold voltage VPWM_SWL is defined as being lower than the first high input threshold voltage VPWM_H and higher than the high impedance logic level V_HiZ of the pulse width modulation signal PWM, the pulse width modulation signal PWM is in the high impedance logic mode in the time period t5.

[0059] During time periods t3 and t4, since the pulse width modulation signal PWM is lower than the second high input threshold voltage VPWM_SWH and higher than the second low input threshold voltage VPWM_SWL, the first comparison signal DFF_S is at a high level and the second comparison signal DFF_R is at a low level, the switch conduction signal DFF_Q is turned to a high level (i.e., the switch control signal SW_CTRL is at a high level), and the discharge switch SW1 will be turned on to form an accelerated discharge path of the pulse width modulation signal PWM.

[0060] In other words, during the time periods t3 and t4, the voltage value of the pulse width modulation signal PWM is not only pulled down by the current drawn by the current drawer 160, but also pulled down by the accelerated discharge path formed by the discharge switch SW1. Fig.14 and Fig.15 As shown, the voltage drop speed of the pulse width modulation signal PWM of the voltage conversion circuit 900 in the time period t3 and t4 is accelerated (that is, the drop slope of the pulse width modulation signal PWM in the time period t3 and t4 is greater than the drop slope of the pulse width modulation signal PWM in the time period t2 and t5), shortening the duration of the time period t3 and t4 (that is, the conduction time of the upper bridge switch 130 is shortened), so that the output voltage Vout and the current of the output inductor Lout will not be too high, so as to avoid damage to the upper bridge switch 130. It should be noted that Fig.15 As shown, when the pulse width modulation signal PWM is in the process of changing from the high logic mode to the high impedance logic mode (i.e., time period t3), the discharge switch SW1 is turned on according to the switch control signal SW_CTRL to form an accelerated discharge path of the pulse width modulation signal PWM. In time period t4, the pulse width modulation signal PWM drops below the first high input threshold voltage VPWM_H, so the pulse width modulation signal PWM enters the high impedance logic mode. Fig.15 As shown in the time period t5, the pulse width modulation signal PWM is in the high impedance logic mode. In addition, after the pulse width modulation signal PWM drops to the second low input threshold voltage VPWM_SWL, the discharge switch SW1 is switched off (the switch control signal SW_CTRL is switched to a low level).

[0061] Fig.161 is a circuit diagram of a voltage conversion circuit 1000 according to an embodiment of the present utility model. The voltage conversion circuit 1000 is similar to the voltage conversion circuit 600, except that one of the input signals of the first AND gate AND1 is replaced by the inverse of the third control signal HiZ (i.e., the control signal HiZb) with the switch conduction signal DFF_Q. The first AND gate AND1 is used to perform a logical AND operation on the inverse of the second control signal PWML (i.e., the control signal PWMLb) and the switch conduction signal DFF_Q, thereby outputting a switch control signal SW_CTRL to the discharge switch SW1 to control the on and off of the discharge switch SW1.

[0062] Please refer to Fig.16 and Fig.15 In the time periods t1 and t2, the second control signal PWML and the switch conduction signal DFF_Q are both at low levels, so the result of the logical AND operation of the inverse of the second control signal PWML (i.e., the control signal PWMLb) and the switch conduction signal DFF_Q is low (i.e., the switch control signal SW_CTRL is low), and the discharge switch SW1 is turned off. In the time periods t3 and t4, the second control signal PWML is at a low level and the switch conduction signal DFF_Q is at a high level, so the result of the logical AND operation of the inverse of the second control signal PWML (i.e., the control signal PWMLb) and the switch conduction signal DFF_Q is high (i.e., the switch control signal SW_CTRL is high), and the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM. In other words, in the time periods t3 and t4, the second control signal PWML is at a low level, and the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM.

[0063] On the other hand, in the time period t5, the second control signal PWML is still at a low level, but the switch-on signal DFF_Q has changed to a low level, so the result of the logical operation of the inverse phase of the second control signal PWML (i.e., the control signal PWMLb) and the switch-on signal DFF_Q is a low level (i.e., the switch control signal SW_CTRL is a low level), and the discharge switch SW1 is turned off to close the accelerated discharge path of the pulse width modulation signal PWM. Specifically, in the time period t5, the inverse phase of the second control signal PWML (i.e., the control signal PWMLb) is still at a high level, but it is desired to turn off the discharge switch SW1 in the time period t5 in design so that the pulse width modulation signal PWM can be maintained in the high impedance logic mode, so the voltage conversion circuit 1000 performs a logical operation of the inverse phase of the second control signal PWML (i.e., the control signal PWMLb) and the switch-on signal DFF_Q, so that in the time period t5, the switch control signal SW_CTRL is a low level, thereby turning off the discharge switch SW1.

[0064] In another embodiment, the first AND gate AND1 can receive the inverse of the second control signal PWML (i.e., the control signal PWMLb), the inverse of the third control signal HiZ (i.e., the control signal HiZb), and the switch-on signal DFF_Q, and perform an AND logic operation on the inverse of the second control signal PWML (i.e., the control signal PWMLb), the inverse of the third control signal HiZ (i.e., the control signal HiZb), and the switch-on signal DFF_Q. Therefore, it can be seen that when the pulse width modulation signal PWM enters the high-impedance logic mode, once the inverse of the third control signal HiZ (i.e., the control signal HiZb) or the switch-on signal DFF_Q is switched to a low level, the first AND gate AND1 outputs a low-level switch control signal SW_CTRL to disconnect the discharge switch SW1.

[0065] Fig.17 1 is a circuit diagram of a voltage conversion circuit 1100 according to an embodiment of the present utility model. The voltage conversion circuit 1100 is similar to the voltage conversion circuit 700, except that one of the input signals of the first AND gate AND1 is replaced by the inverted third control signal HiZ (i.e., control signal HiZb) with the switch conduction signal DFF_Q. The first AND gate AND1 is used to perform a logical AND operation on the inverted lower bridge switch control signal LG (i.e., control signal LGb) and the switch conduction signal DFF_Q, thereby outputting a switch control signal SW_CTRL to the discharge switch SW1 to control the on and off of the discharge switch SW1.

[0066] Please refer to Fig.17 and Fig.15 In the time periods t1 and t2, the lower bridge switch control signal LG and the switch conduction signal DFF_Q are both at low levels, so the result of the logical AND operation of the inverse of the lower bridge switch control signal LG (i.e., the control signal LGb) and the switch conduction signal DFF_Q is low (i.e., the switch control signal SW_CTRL is low), and the discharge switch SW1 is turned off. In the time periods t3 and t4, the lower bridge switch control signal LG is low and the switch conduction signal DFF_Q is high, so the result of the logical AND operation of the inverse of the lower bridge switch control signal LG (i.e., the control signal LGb) and the switch conduction signal DFF_Q is high (i.e., the switch control signal SW_CTRL is high), and the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM. In other words, in the time periods t3 and t4, the lower bridge switch control signal LG is at a low level, and the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM.

[0067] On the other hand, in the time period t5, the lower bridge switch control signal LG is still at a low level, but the switch conduction signal DFF_Q has changed to a low level, so the result of the logical operation of the inverse phase of the lower bridge switch control signal LG (i.e., the control signal LGb) and the switch conduction signal DFF_Q is a low level (i.e., the switch control signal SW_CTRL is a low level), and the discharge switch SW1 is turned off to close the accelerated discharge path of the pulse width modulation signal PWM. Specifically, in the time period t5, the inverse phase of the lower bridge switch control signal LG (i.e., the control signal LGb) is still at a high level, but it is desired to turn off the discharge switch SW1 in the time period t5 in design so that the pulse width modulation signal PWM can be maintained in the high impedance logic mode, so the voltage conversion circuit 1000 performs a logical operation of the inverse phase of the lower bridge switch control signal LG (i.e., the control signal LGb) and the switch conduction signal DFF_Q, so that in the time period t5, the switch control signal SW_CTRL is a low level, thereby turning off the discharge switch SW1.

[0068] In another embodiment, the first AND gate AND1 can receive the inverse of the lower bridge switch control signal LG (i.e., the control signal LGb), the inverse of the third control signal HiZ (i.e., the control signal HiZb), and the switch conduction signal DFF_Q, and perform an AND logic operation on the same. Therefore, it can be seen that when the pulse width modulation signal PWM enters the high impedance logic mode, once the inverse of the third control signal HiZ (i.e., the control signal HiZb) or the switch conduction signal DFF_Q is switched to a low level, the first AND gate AND1 outputs a low-level switch control signal SW_CTRL to disconnect the discharge switch SW1.

[0069] Fig.18 1 is a circuit diagram of a voltage conversion circuit 1200 according to an embodiment of the present utility model. The voltage conversion circuit 1200 is similar to the voltage conversion circuit 900, except that: Fig.18 The voltage conversion circuit 1200 further includes a switch control circuit 170 , which is coupled to the discharge switch SW1 and configured to output a switch control signal SW_CTRL to the discharge switch SW1 to control the on-off of the discharge switch SW1 .

[0070] Fig.19: is a circuit diagram of a switch control circuit 170 according to an embodiment of the present utility model. The switch control circuit 170 includes an OR gate OR1 and a second AND gate AND2. The OR gate OR1 is used to receive the first control signal PWMH, the inverted phase of the third control signal HiZ (i.e., the control signal HiZb), the inverted phase of the second control signal PWML (i.e., the control signal PWMLb), the bootstrap power signal BOOT, the upper bridge switch control signal UG, the inverted phase of the lower bridge switch control signal LG (i.e., the control signal LGb), the phase output signal PHASE and the switch conduction signal DFF_Q, and performs an OR logic operation on the above signals to output an enable signal EN accordingly. It is worth mentioning that, Fig.19 The input signal composition of the OR gate OR1 is shown for illustration only, and the present invention is not limited thereto, and the input signal composition of the OR gate OR1 may be omitted according to actual needs. The second AND gate AND2 is coupled to the OR gate OR1 to receive the enable signal EN, and performs an AND logic operation on the enable signal EN, the inverse of the third control signal HiZ (i.e., the control signal HiZb), and the switch conduction signal DFF_Q, thereby outputting the switch control signal SW_CTRL.

[0071] Please refer to Fig.18 , Fig.19 and Fig. 20In the time periods t1 and t2, the enable signal EN outputted by the OR gate OR1 of the switch control circuit 170 has a high level, for example, because the control signal PWMLb is at a high level. However, since the switch-on signal DFF_Q is at a low level, the switch control signal SW_CTRL outputted by the second AND gate AND2 of the switch control circuit 170 is at a low level, and the discharge switch SW1 is turned off. In the time period t3, the enable signal EN outputted by the OR gate OR1 of the switch control circuit 170 has a high level, for example, because the control signal PWMLb is at a high level, and since the switch-on signal DFF_Q is at a high level and the control signal HiZb is at a high level (as described above, in the time period t3, the pulse width modulation signal PWM is higher than the first high input threshold voltage VPWM_H, so the third control signal HiZ is at a low level), the switch control signal SW_CTRL outputted by the second AND gate AND2 of the switch control circuit 170 is at a high level, and the discharge switch SW1 is turned on to form an accelerated discharge path of the pulse width modulation signal PWM. During the time periods t4 and t5, the enable signal EN outputted by the OR gate OR1 of the switch control circuit 170 has a high level, for example, because the control signal PWMLb is at a high level. However, since at least one of the switch conduction signal DFF_Q and the control signal HiZb is at a low level (as described above, during the time period t4, the pulse width modulation signal PWM drops to be lower than the first high input threshold voltage VPWM_H and higher than the first low input threshold voltage VPWM_L, the third control signal HiZ is switched to a high level at the time point between the time periods t3 and t4, that is, the control signal HiZb is switched to a low level), the switch control signal SW_CTRL outputted by the second AND gate AND2 of the switch control circuit 170 is at a low level, and the discharge switch SW1 is turned off. Specifically, during the time period t4, the control signal HiZb is at a low level; during the time period t5, the switch conduction signal DFF_Q and the control signal HiZb are both at a low level. Therefore, during the time periods t4 and t5 , based on the operation of the second AND gate AND2 , since at least one of the switch conduction signal DFF_Q and the control signal HiZb is at a low level, the switch control signal SW_CTRL is at a low level.

[0072] according to Figures 18 to 20 In the embodiment of the present invention, the second AND gate AND2 is coupled to the OR gate OR1 to receive the enable signal EN, the inverse of the third control signal HiZ (i.e., the control signal HiZb) and the switch conduction signal DFF_Q to perform an AND operation. Therefore, it can be seen that when the pulse width modulation signal PWM enters the high impedance logic mode, once the inverse of the third control signal HiZ (i.e., the control signal HiZb) or the switch conduction signal DFF_Q is switched to a low level, the second AND gate AND2 outputs a low-level switch control signal SW_CTRL to disconnect the discharge switch SW1.

[0073] Fig.21 It is a flow chart of a voltage conversion method according to an embodiment of the utility model, comprising steps S1 to S5. In step S1, a pulse width modulation signal PWM is provided through an input node IN. In step S2, the pulse width modulation signal PWM is received by a logic circuit 110 and a first control signal PWMH and a second control signal PWML are outputted accordingly. In other words, step S2 generates the first control signal PWMH and the second control signal PWML according to the pulse width modulation signal PWM. In step S3, the first control signal PWMH and the second control signal PWML are received by a drive control circuit 120 and an upper bridge switch control signal UG and a lower bridge switch control signal LG are outputted accordingly. In other words, step S3 generates the upper bridge switch control signal UG and the lower bridge switch control signal LG according to the first control signal PWMH and the second control signal PWML, wherein the drive control circuit 120 also receives a bootstrap power supply signal BOOT for driving the drive control circuit 120. A supplementary explanation for the above steps S2 and S3 is that in some embodiments, the upper bridge switch control signal UG and the lower bridge switch control signal LG may not be generated via the third control signal HiZ, so the third control signal HiZ may be omitted. In step S4, the upper bridge switch control signal UG is received through the control end of the upper bridge switch 130, the lower bridge switch control signal LG is received through the control end of the lower bridge switch 140, and the phase output signal PHASE is output through the first end of the lower bridge switch 140 and the second end of the upper bridge switch 130. In other words, step S4 generates the phase output signal PHASE according to the upper bridge switch control signal UG and the lower bridge switch control signal LG. In step S5, the on-off of the discharge switch SW1 is controlled, wherein the discharge switch SW1 is coupled between the input node IN and the ground terminal GND, wherein the discharge switch SW1 is controlled by at least one of the following: the pulse width modulation signal PWM, the first control signal PWMH, the inverse of the second control signal PWML, the bootstrap power signal BOOT, the upper bridge switch control signal UG, the inverse of the lower bridge switch control signal LG and the phase output signal PHASE. In other words, step S5 controls the on-off of the discharge switch SW1 according to the pulse width modulation signal PWM, the first control signal PWMH, the inverse of the second control signal PWML, the bootstrap power signal BOOT, the upper bridge switch control signal UG, the inverse of the lower bridge switch control signal LG and / or the phase output signal PHASE.

[0074] According to some embodiments of the present invention, Figure 8 The voltage conversion circuit 300 shown in FIG. Fig. 9 The voltage conversion circuit 400 shown, Fig.10 The voltage conversion circuit 500 shown, Fig.11 The voltage conversion circuit 600 shown in FIG. Fig.12 The voltage conversion circuit 700 shown, Fig.13 The voltage conversion circuit 800 shown, Fig.14 The voltage conversion circuit 900 shown, Fig.16 The voltage conversion circuit 1000 shown in FIG. Fig.17 The voltage conversion circuit 1100 shown, and Fig.18 The discharge switch SW1 of at least one of the voltage conversion circuits 1200 shown in FIG. 1 may also refer to FIG. Figure 3 The voltage conversion circuit 200A shown has a discharge switch SW1 , such that the discharge switch SW1 and the resistor R1 are connected in series and coupled between the input node IN and the ground terminal GND.

[0075] According to other embodiments of the present invention Figure 8 The voltage conversion circuit 300 shown in FIG. Fig. 9 The voltage conversion circuit 400 shown, Fig.10 The voltage conversion circuit 500 shown, Fig.11 The voltage conversion circuit 600 shown in FIG. Fig.12 The voltage conversion circuit 700 shown, Fig.13 The voltage conversion circuit 800 shown, Fig.14 The voltage conversion circuit 900 shown, Fig.16 The voltage conversion circuit 1000 shown in FIG. Fig.17 The voltage conversion circuit 1100 shown, and Fig.18 The discharge switch SW1 of at least one of the voltage conversion circuits 1200 shown in FIG. 1 may also refer to FIG. Figure 6 The discharge switch SW1 of the voltage conversion circuit 200B is shown, so that the discharge switch SW1 and the current sink IS1 are connected in series and coupled between the input node IN and the ground terminal GND.

[0076] In summary, the utility model proposes a voltage conversion circuit, which is used to form an accelerated discharge path of a pulse width modulation signal when the pulse width modulation signal is converted from a high logic mode to a high impedance logic mode, so that the output voltage and the current of the output inductor will not be too high, thereby avoiding damage to the upper bridge switch.

[0077] The features of several embodiments are summarized above, so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures to achieve the same goals and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present invention.

[0078]

Explanation of symbols

[0079] 110:Logic Circuit

[0080] 120: drive control circuit

[0081] 130: Upper bridge switch

[0082] 140: Lower bridge switch

[0083] 150: Current source

[0084] 160,IS1: Current Drain

[0085] 170: switch control circuit

[0086] 100,200A,200B,200C,300,400,500,600,700,800,900,1000,1100,1200: Voltage conversion circuit

[0087] AND1: The first AND gate

[0088] AND2: Second AND gate

[0089] BOOT: Bootstrap power supply signal

[0090] Cout: output capacitance

[0091] CP1: First comparator

[0092] CP2: Second comparator

[0093] CP3: The third comparator

[0094] CP4: Fourth comparator

[0095] DFF_Q: switch on signal

[0096] DFF_R: Second comparison signal

[0097] DFF_S: First comparison signal

[0098] EN: Enable signal

[0099] GEN1: Level generation circuit

[0100] GND: Ground terminal

[0101] HiZ: The third control signal

[0102] HiZb,LGb,PWMLb: control signal

[0103] IN: Input node

[0104] LG: Lower bridge switch control signal

[0105] Lout: output inductance

[0106] NL: Load Node

[0107] NOR1:NAND gate

[0108] OR1: OR gate

[0109] PHASE: Phase output signal

[0110] PWM: Pulse Width Modulation Signal

[0111] PWMH: first control signal

[0112] PWML: Second control signal

[0113] R1: Resistor

[0114] S1, S2, S3, S4, S5: Steps

[0115] SR1:SR trigger

[0116] SW: Switch Node

[0117] SW_CTRL: switch control signal

[0118] SW1: discharge switch

[0119] t1,t2,t3,t4,t5: time period

[0120] UG: Upper bridge switch control signal

[0121] V_H: High logic level

[0122] V_HiZ: High impedance logic level

[0123] V_L: Low logic level

[0124] VCC, VIN: voltage source

[0125] Vout: output voltage

[0126] VPWM_H: First high input threshold voltage

[0127] VPWM_L: First low input threshold voltage

[0128] VPWM_SWH: Second highest input threshold voltage

[0129] VPWM_SWL: Second lower input threshold voltage.

Claims

1. A voltage conversion circuit, characterized in that: include: A logic circuit coupled to the input node to receive the pulse width modulation signal and output a first control signal and a second control signal accordingly; A drive control circuit coupled to the logic circuit to receive the first control signal and the second control signal and output an upper bridge switch control signal and a lower bridge switch control signal accordingly, wherein the drive control circuit also receives a bootstrap power supply signal for driving the drive control circuit; An upper bridge switch, wherein a control end of the upper bridge switch is coupled to the drive control circuit to receive the upper bridge switch control signal; a lower bridge switch, wherein a control end of the lower bridge switch is coupled to the drive control circuit to receive the lower bridge switch control signal, wherein a first end of the lower bridge switch and a second end of the upper bridge switch are coupled to a switching node, and a phase output signal is generated at the switching node; and A discharge switch coupled between the input node and a ground terminal; The discharge switch is controlled by at least one of the following: the pulse width modulation signal, the first control signal, the inverse of the second control signal, the bootstrap power signal, the upper bridge switch control signal, the inverse of the lower bridge switch control signal and the phase output signal.

2. The voltage conversion circuit according to claim 1, characterized in that: A resistor is also included, wherein the discharge switch is connected in series with the resistor and coupled between the input node and the ground terminal.

3. The voltage conversion circuit according to claim 1, characterized in that: A current sink is also included, wherein the discharge switch is connected in series with the current sink and is coupled between the input node and the ground terminal.

4. The voltage conversion circuit according to claim 1, characterized in that: One of the first control signal, the bootstrap power signal, the upper bridge switch control signal and the phase output signal is used to directly control the on-off of the discharge switch.

5. The voltage conversion circuit according to claim 1, characterized in that: The logic circuit includes: A first comparator, configured to compare the pulse width modulation signal with a first high input threshold voltage and output the first control signal accordingly; and A second comparator, used for comparing the pulse width modulation signal with a first low input threshold voltage and outputting the second control signal accordingly; The positive input terminal of the first comparator and the negative input terminal of the second comparator are used to receive the pulse width modulation signal; The first high input threshold voltage is lower than the high logic level of the pulse width modulation signal and higher than the high impedance logic level of the pulse width modulation signal, and the first low input threshold voltage is lower than the high impedance logic level and higher than the low logic level of the pulse width modulation signal.

6. The voltage conversion circuit according to claim 5, characterized in that: The logic circuit also includes: The NAND gate is coupled to the first comparator and the second comparator to receive the first control signal and the second control signal and output a third control signal accordingly.

7. The voltage conversion circuit according to claim 6, characterized in that: Also includes: The first AND gate is coupled to the discharge switch and is used to perform a logical AND operation on the inverse of the second control signal and the inverse of the lower bridge switch control signal with the inverse of the third control signal, thereby outputting a switch control signal to the discharge switch to control the on and off of the discharge switch.

8. The voltage conversion circuit according to claim 5, characterized in that: Also includes: A level generating circuit is coupled to the input node and is used to receive the pulse width modulation signal and output a switch conduction signal accordingly, wherein the level generating circuit comprises: A third comparator, used for comparing the pulse width modulation signal with a second high input threshold voltage and outputting a first comparison signal accordingly; a fourth comparator, configured to compare the pulse width modulation signal with a second low input threshold voltage and output a second comparison signal accordingly; and a set-reset trigger coupled to the third comparator and the fourth comparator to receive the first comparison signal and the second comparison signal and output the switch-on signal accordingly; The negative input terminal of the third comparator and the negative input terminal of the fourth comparator are used to receive the pulse width modulation signal.

9. The voltage conversion circuit according to claim 8, characterized in that: Also includes: The first AND gate is coupled to the discharge switch and is used to perform a logic operation of AND on one of the inverse of the second control signal and the inverse of the lower bridge switch control signal and the switch conduction signal, thereby outputting a switch control signal to the discharge switch to control the on-off of the discharge switch.

10. The voltage conversion circuit according to claim 1, characterized in that: Also includes: A switch control circuit is coupled to the discharge switch and is used to output a switch control signal to the discharge switch to control the on and off of the discharge switch, wherein the switch control circuit includes: an OR gate for receiving the first control signal, the inverse of the third control signal, the inverse of the second control signal, the bootstrap power signal, the upper bridge switch control signal, the inverse of the lower bridge switch control signal, the phase output signal and the switch conduction signal, and performing an OR logic operation on the above signals to output an enable signal accordingly; and a second AND gate coupled to the OR gate to receive the enable signal, and perform an AND logic operation on the enable signal, the inverse of the third control signal, and the switch conduction signal, thereby outputting the switch control signal; The third control signal indicates whether the pulse width modulation signal is in a high impedance logic mode, and the switch conduction signal is associated with a level of the pulse width modulation signal.

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