Semiconductor device and semiconductor die

Abstract

The utility model provides a semiconductor assembly. The semiconductor assembly comprises a first grid electrode, a second grid electrode arranged on the first grid electrode, a first contact conductor, a second contact conductor, a third contact conductor arranged between the first grid electrode and the second grid electrode, a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is disposed between the first gate and the third contact conductor. The first semiconductor layer includes a first channel region, a first source region, and a first drain region, and the first channel region extends laterally between the first drain region and the first contact conductor. The second semiconductor layer is disposed between the second gate and the third contact conductor. The second semiconductor layer includes a second channel region, a second source region, and a second drain region, and the second channel region extends laterally between the second drain region and the second contact conductor.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor component and a semiconductor crystal grain. Background Art

[0002] The semiconductor components used to generate logic functions are commonly known as complementary metal oxide semiconductor (CMOS) inverters. CMOS inverters are basic building blocks in semiconductor die manufacturing. CMOS inverters are field effect transistors (FETs) that include a metal gate that is located on an insulating oxide layer on a semiconductor material. CMOS inverters are used and manufactured in most electronic components to generate data. CMOS inverters are used to invert the applied input signal. In digital logic circuits, binary operations and mathematical operations of switching or logic functions are performed using symbols 0 and 1. When the input logic is LOW (e.g., 0), the output of the CMOS inverter is HIGH (e.g., 1); when the input logic is HIGH (e.g., 1), the output of the CMOS inverter is LOW (e.g., 0).

[0003] Currently, the quality of CMOS inverters can be evaluated by measuring the voltage transfer characteristic (VTC) of the CMOS inverter. Due to the difference in materials and mobility between the p-type channel and the n-type channel of the CMOS inverter, the VTC will shift and the performance of the CMOS inverter will deteriorate. Therefore, it is necessary to improve the reliability of the CMOS inverter. Utility Model Content

[0004] According to some embodiments of the utility model, a semiconductor component is provided, which includes a first gate, a second gate configured on the first gate, a first contact conductor, a second contact conductor, a third contact conductor configured between the first gate and the second gate, a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is configured between the first gate and the third contact conductor. The first semiconductor layer includes a first channel region, a first source region laterally contacting the first contact conductor, and a first drain region in contact with the third contact conductor, and the first channel region extends laterally between the first drain region and the first contact conductor. The second semiconductor layer is configured between the second gate and the third contact conductor. The second semiconductor layer includes a second channel region, a second source region laterally contacting the second contact conductor, and a second drain region in contact with the third contact conductor, and the second channel region extends laterally between the second drain region and the second contact conductor.

[0005] According to some other embodiments of the utility model, a semiconductor crystal grain is provided, which includes a semiconductor substrate, an interconnect structure configured on the semiconductor substrate, and an inverter embedded in the interconnect structure. The inverter includes a first contact conductor, a second contact conductor laterally separated from the first contact conductor, a first thin film transistor, a second thin film transistor, and a third contact conductor. The second thin film transistor is stacked on the first thin film transistor, wherein the first thin film transistor and the second thin film transistor are configured in a region between the first contact conductor and the second contact conductor. The third contact conductor is configured in a region between the first contact conductor and the second contact conductor, wherein the first thin film transistor and the second thin film transistor are configured on opposite sides of the third contact conductor, the first semiconductor layer of the first thin film transistor extends laterally from the bottom surface of the third contact conductor to the first side wall of the first contact conductor, and the second semiconductor layer of the second thin film transistor extends laterally from the top surface in the third contact conductor to the second side wall of the second contact conductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A circuit diagram of an inverter according to some embodiments of the present disclosure is schematically illustrated.

[0008] Figure 2 A three-dimensional view of a semiconductor die according to some embodiments of the present disclosure is schematically depicted.

[0009] Figures 3 to 13 A cross-sectional view of a process flow for fabricating an inverter embedded in an interconnect structure of a semiconductor die according to some embodiments of the present disclosure is schematically illustrated.

[0010] FIG. 14A to FIG. 14G The diagram schematically illustrates the layout of various thin films in an inverter according to some embodiments of the present disclosure.

[0011] [Description of Figure Numbers]

[0012] 101: Semiconductor Substrate

[0013] 102: Interconnection Structure

[0014] 102D1, 102D2, 102D4, 102D5: Dielectric layer

[0015] 102D3: Dielectric Pattern

[0016] 102V1, 102V2, 102V3, 102V4: Contact through-hole

[0017] 102W1, 102W2, 102W3, 102W4: Interconnection wiring

[0018] 103: Inverter

[0019] 110: n-type field effect transistor

[0020] 112: First semiconductor layer

[0021] 112C: First channel region

[0022] 112D: First drain region

[0023] 112R: First offset area

[0024] 112S: First source region

[0025] 120: p-type field effect transistor

[0026] 122, 212: Second semiconductor layer

[0027] 122C: Second channel region

[0028] 122D: Second drain region

[0029] 122R: Second offset area

[0030] 122S: Second source region

[0031] 130: First contact conductor

[0032] 135: District

[0033] 140: Second contact conductor

[0034] 150: Third contact conductor

[0035] 160: Conductive materials

[0036] D1: First drain

[0037] D2: Second drain

[0038] ESL: Etch Stop Layer

[0039] G1: First gate

[0040] G2: Second gate

[0041] GI1: First gate insulation layer

[0042] GI2: Second gate insulation layer

[0043] GND: Low voltage level

[0044] L1: First level

[0045] L2: Second level

[0046] L3: The third level

[0047] L4: The fourth level

[0048] L5: Fifth level

[0049] LD1: First lateral distance

[0050] LD2: Second lateral distance

[0051] O1, O2, O3, O4: Through hole

[0052] R: Concave

[0053] Vout: output voltage

[0054] Vin: input voltage

[0055] VDD: High voltage level

[0056] S1: First source

[0057] S2: Second source DETAILED DESCRIPTION

[0058] The following disclosure provides many different embodiments or examples for implementing the different features of the utility model. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are just examples and are not intended to be restrictive. For example, in the following description, a first member formed above or on a second member may include an embodiment in which the first member and the second member are formed in direct contact, and may also include an embodiment in which an additional member may be formed between the first member and the second member so that the first member and the second member may not be in direct contact. In addition, the disclosure may repeat the figure numbers and / or letters in each example. This repetition is for the purpose of simplification and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0059] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "overlying," "upper," and the like may be used herein to describe the relationship of one component or member to another component(s) or member(s) as shown in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0060] Figure 1A circuit diagram of an inverter according to some embodiments of the present disclosure is schematically illustrated.

[0061] refer to Figure 1 According to some embodiments of the present disclosure, the inverter 103 includes an n-type field effect transistor (FET) 110 and a p-type field effect transistor 120 electrically connected to the n-type field effect transistor 110. The first drain D1 of the n-type field effect transistor 110 is electrically connected to the second drain D2 of the p-type field effect transistor 120, and the first gate G1 of the n-type field effect transistor 110 is electrically connected to the second gate G2 of the p-type field effect transistor 120. Figure 1 As shown, the first drain D1 and the second drain D2 are electrically connected to the output terminal to output an output voltage Vout, the first gate G1 and the second gate G2 are electrically connected to the input terminal to receive an input voltage Vin, and the first source S1 of the n-type field effect transistor 110 is electrically connected to the high voltage level VDD (e.g., the supply voltage VDD), and the second source S2 of the p-type field effect transistor 120 is electrically connected to the low voltage level GND (e.g., electrical ground). When a low input voltage Vin (e.g., Vin=0V) is applied to the first gate G1 and the second gate G2 in the inverter 103, the p-type field effect transistor 120 is switched to "ON" and the n-type field effect transistor 110 is switched to "OFF", so that the inverter 103 outputs a high output voltage Vout (i.e., Vout=VDD). Similarly, when a high input voltage Vin (e.g., Vin=5V) is applied to the first gate G1 and the second gate G2 in the inverter 103, the p-type field effect transistor 120 is switched “OFF” and the n-type field effect transistor 110 is switched “ON”, so the inverter 103 outputs a low output voltage Vout (i.e., Vout=GND).

[0062] Figure 2 A three-dimensional view of a semiconductor die according to some embodiments of the present disclosure is schematically depicted.

[0063] Reference Figure 1 and Figure 2, which depicts a semiconductor die 100, and the semiconductor die 100 includes a semiconductor component (e.g., an inverter 103) embedded therein. The semiconductor die 100 includes a semiconductor substrate 101, an interconnect structure 102 configured on the semiconductor substrate 101, and an inverter 103 embedded in the interconnect structure 102. In some embodiments, the semiconductor substrate 101 includes a metal oxide semiconductor field effect transistor (MOSFET), such as a P-type metal oxide semiconductor field effect transistor (PMOSFET), an N-type metal oxide semiconductor field effect transistor (NMOSFET), a complementary metal oxide semiconductor field effect transistor (CMOSFET), or a combination thereof formed thereon; and an embedded inverter 103 electrically connected to the MOSFET through the interconnect structure 102. The inverter 103 integrated in the interconnect structure 102 of the semiconductor die 100 may include a first thin film transistor (e.g., Figure 1 n-type field effect transistor shown) 110, a second thin film transistor (eg, Figure 1 1 , a p-type field effect transistor (FET) 120, a first contact conductor 130, a second contact conductor 140 laterally separated from the first contact conductor 130, and a third contact conductor 150. The second thin film transistor 120 is stacked on the first thin film transistor 110, wherein the first thin film transistor 110 and the second thin film transistor 120 are arranged in a region 135 between the first contact conductor 130 and the second contact conductor 140. The third contact conductor 150 is arranged in a region 135 between the first contact conductor 130 and the second contact conductor 140, wherein the first thin film transistor 110 and the second thin film transistor 120 are arranged on opposite sides of the third contact conductor 150. In addition, the first thin film transistor 110 and the second thin film transistor 120 are electrically connected to the MOSFET formed on the semiconductor substrate 101 through the interconnect structure 102. In some embodiments, the first thin film transistor 110 and the second thin film transistor 120 are separated from the semiconductor substrate 101 by at least one dielectric layer 102D1 of the interconnect structure 102.

[0064] The first thin film transistor 110 may include a first gate G1 and a first semiconductor layer 112. The second thin film transistor 120 may include a second gate G2 and a second semiconductor layer 122. The second gate G2 is disposed on the first gate G1, and the third contact conductor 150 is disposed between the first gate G1 and the second gate G2. The first semiconductor layer 112 is disposed between the first gate G1 and the third contact conductor 150. The first semiconductor layer 112 is laterally spaced from the second contact conductor 140, and the second semiconductor layer 122 is laterally spaced from the first contact conductor 130. The first semiconductor layer 112 of the first thin film transistor 110 extends laterally from a bottom surface of the third contact conductor 150 to a first sidewall of the first contact conductor 130, and the second semiconductor layer 122 of the second thin film transistor 120 extends laterally from a top surface of the third contact conductor 150 to a second sidewall of the second contact conductor 140. Figure 2 As shown in FIG. 1 , a portion of the top surface of the first semiconductor layer 112 contacts the bottom surface of the third contact conductor 150, and a side wall (e.g., the side wall on the right side) of the first semiconductor layer 112 contacts the first side wall of the first contact conductor 130. In addition, a portion of the bottom surface of the second semiconductor layer 212 contacts the top surface of the third contact conductor 150, and a side wall (e.g., the side wall on the left side) of the second semiconductor layer 212 contacts the second side wall of the second contact conductor 140.

[0065] The first semiconductor layer 112 may be an n-type doped semiconductor layer, and the second semiconductor layer 122 may be a p-type doped semiconductor layer. The first semiconductor layer 112 includes a first channel region 112C, a first source region 112S laterally contacting the first contact conductor 130, and a first drain region 112D contacting the third contact conductor 150. The first channel region 112C extends laterally from the first drain region 112D to the first contact conductor 130. The first channel region 112C and the first drain region 112D overlap with the first gate G1 below, and the first drain region 112D is vertically sandwiched between the first gate G1 and the third contact conductor 150. The second semiconductor layer 122 is disposed between the second gate G2 and the third contact conductor 150. The second semiconductor layer 122 includes a second channel region 122C laterally contacting the second contact conductor 140 and a second drain region 122D contacting the third contact conductor 150, and the second channel region 122C extends laterally from the second drain region 122D to the second contact conductor 140. In addition, the second channel region 122C and the second drain region 122D overlap with the overlying second gate G2, and the second drain region 122D is vertically sandwiched between the second gate G2 and the third contact conductor 150.

[0066] like Figure 2As shown, the first gate G1 and the second gate G2 are disposed between the first contact conductor 130 and the second contact conductor 140. In some embodiments, the first gate G1 is located at a first level L1, the second gate G2 is located at a second level L2 different from the first level L1, and the third contact conductor 150 is located at a third level L3 between the first level L1 and the second level L2. The first contact conductor 130 may extend vertically from the first level L1 to the second level L2. The first semiconductor layer 112 is located at a fourth level L4 between the first level L1 and the third level L3, and the second semiconductor layer 122 is located at a fifth level L5 between the second level L2 and the third level L3. In some embodiments, the first semiconductor layer 112 is laterally spaced from the second contact conductor 140, and the second semiconductor layer 122 is laterally spaced from the first contact conductor 130. Specifically, the first semiconductor layer 112 is laterally separated from the second contact conductor 140 by a dielectric layer 102D2 in the interconnect structure 102 , and the second semiconductor layer 122 is laterally separated from the first contact conductor 130 by another dielectric layer 102D3 in the interconnect structure 102 .

[0067] The inverter 103 may further include a first gate insulating layer GI1 and a second gate insulating layer GI2, wherein the first gate insulating layer GI1 is disposed between the first gate G1 and the first semiconductor layer 112, and the second gate insulating layer GI2 is disposed between the second gate G2 and the second semiconductor layer 122. The first gate insulating layer GI1 extends laterally between the first contact conductor 130 and the second contact conductor 130. The second gate insulating layer GI2 is disposed above the first gate insulating layer GI1 and extends laterally between the first contact conductor 130 and the second contact conductor 140. The first gate G1 is disposed below the first gate insulating layer GI1. The second gate G2 is disposed above the second gate insulating layer GI2. The first semiconductor layer 112, the second semiconductor layer 122, and the third contact conductor 150 are disposed between the first gate insulating layer GI1 and the second gate insulating layer GI2. The first semiconductor layer 112 extends laterally from the third contact conductor 150 to the first contact conductor 130, and the second semiconductor layer 122 extends laterally from the third contact conductor 150 to the second contact conductor 140.

[0068] The third contact conductor 150, the first gate G1, the first semiconductor layer 112, the first gate insulating layer GI1, the second gate G2, the second semiconductor layer 212 and the second gate insulating layer GI2 are located at different levels. Figure 2As shown, multiple ends (or side walls) of the first gate insulating layer GI1 are in contact with the first contact conductor 130 and the second contact conductor 140, and multiple ends (or side walls) of the second gate insulating layer GI2 are in contact with the first contact conductor 130 and the second contact conductor 140. In other words, the first gate insulating layer GI1 and the second gate insulating layer GI2 extend laterally and continuously between the first contact conductor 130 and the second contact conductor 140, respectively. Specifically, multiple ends (or side walls) of the first gate insulating layer GI1 and multiple ends (or side walls) of the second gate insulating layer GI2 are in contact with the side walls of the first contact conductor 130 and the side walls of the second contact conductor 140.

[0069] In some embodiments, the first semiconductor layer 112, the second semiconductor layer 122, and the third contact conductor 150 are disposed between the first gate insulating layer GI1 and the second gate insulating layer GI2. The first contact conductor 130 and the third contact conductor 150 are laterally separated by a first lateral distance LD1, and the second contact conductor 140 and the third contact conductor 150 are laterally separated by a second lateral distance LD2, and the first lateral distance LD1 may be different from the second lateral distance LD2. For example, the first lateral distance LD1 between the first contact conductor 130 and the third contact conductor 150 is greater than 150 nanometers, and the second lateral distance LD2 between the second contact conductor 140 and the third contact conductor 150 is greater than 150 nanometers.

[0070] Figures 3 to 13 A cross-sectional view of a process flow for fabricating an inverter embedded in an interconnect structure of a semiconductor die according to some embodiments of the present disclosure is schematically illustrated. FIG. 14A to FIG. 14G The diagram schematically illustrates the layout of various thin films in an inverter according to some embodiments of the present disclosure.

[0071] Reference Figure 3 and Fig.14A, a semiconductor substrate 101 is provided, and the semiconductor substrate 101 has at least one dielectric layer 102D1 formed thereon. The semiconductor substrate 101 may include an elemental semiconductor (e.g., silicon or germanium in a crystalline, polycrystalline, or amorphous structure), a compound semiconductor (e.g., SiC, GaAs, GaP, InP, InAs, and / or InSb, etc.), an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, etc.), a combination of the foregoing, or other suitable materials. In some embodiments, the semiconductor substrate 101 is a semiconductor substrate having a multilayer structure or any suitable substrate. In some embodiments, semiconductor components are formed in the semiconductor substrate 101 and may include active components (e.g., transistors, diodes, etc.) and / or passive components (e.g., capacitors, resistors, inductors, etc.), or other suitable electrical components. The at least one dielectric layer 102D1 may be a portion of the above-mentioned interconnect structure 102 (e.g., Figure 2 In some embodiments, the interconnect structure 102 (eg Figure 2 102D1 includes stacked dielectric layers and interconnect wiring embedded in the stacked dielectric layers, and the dielectric layer 102D1 is one of the stacked dielectric layers. The material of the dielectric layer 102D1 can be or include silicon dioxide, silicon nitride, silicon oxynitride or other inorganic dielectric materials.

[0072] A patterning process is performed to form a recess R in the dielectric layer 102D1. In some embodiments, the patterning process performed on the dielectric layer 102D1 includes a photolithography process and an etching process performed after the photolithography process. The depth of the recess R formed in the dielectric layer 102D1 may be less than or substantially equal to the thickness of the dielectric layer 102D1. After the recess R is formed in the dielectric layer 102D1, a conductive material is formed on the dielectric layer 102D1 to fill the recess R and cover the top surface of the dielectric layer 102D1. The material of the conductive material may be or include copper or other metal materials. The conductive material may be formed on the dielectric layer 102D1 by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other suitable deposition processes. After depositing the conductive material on the top surface of the dielectric layer 102D1, a removal process is performed to remove portions of the conductive material until the top surface of the dielectric layer 102D1 is exposed, thereby forming the first gate G1 in the recess R of the dielectric layer 102D1. The removal process for removing the excess portion of the conductive material may be or include a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, a combination of the foregoing processes, or other suitable removal processes.

[0073] like Figure 3, the top surface of the first gate G1 is substantially flush with the top surface of the dielectric layer 102D1. In some other embodiments, due to the grinding selectivity of the CMP process, the grinding selectivity of the mechanical grinding process, or the etching selectivity of the etching process, the top surface of the first gate G1 may be slightly lower than the top surface of the dielectric layer 102D1. In some alternative embodiments, due to the grinding selectivity of the CMP process, the grinding selectivity of the mechanical grinding process, or the etching selectivity of the etching process, the top surface of the first gate G1 may be slightly higher than the top surface of the dielectric layer 102D1.

[0074] refer to Figure 4 and Fig. 14B , a first gate insulating layer GI1 is deposited to cover the top surface of the first gate G1 and the top surface of the dielectric layer 102D1. The material of the first gate insulating layer GI1 may be or include silicon dioxide, silicon nitride, silicon oxynitride, or other insulating materials. The first gate insulating layer GI1 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other suitable deposition processes.

[0075] After forming the first gate insulating layer GI1, a first semiconductor layer 112 is formed on the first gate insulating layer GI1. The material of the first semiconductor layer 112 may be or include n-type doped indium gallium zinc oxide (IGZO), indium titanium nitride zinc oxide (ITZO), indium zinc oxide (IZO) or other suitable semiconductor oxide materials. The first semiconductor layer 112 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process or other suitable deposition process. Figure 4 and Fig. 14B As shown, the first semiconductor layer 112 includes a first channel region 112C, a first source region 112S, and a first drain region 112D, wherein the first channel region 112C extends laterally from the first drain region 112D to the first source region 112S. The first channel region 112C and the first drain region 112D vertically overlap with the first gate G1 below, and the first source region 112S does not vertically overlap with the first gate G1 below. In addition, the first channel region 112C, the first source region 112S, and the first drain region 112D are separated from the first gate G1 by the first gate insulating layer GI1.

[0076] like Figure 4 and Fig. 14BAs shown, the first semiconductor layer 112 may further include a first offset region 112R in contact with the first drain region 112D, wherein the first offset region 112R vertically overlaps the first gate G1 below, and the first drain region 112D extends laterally from the first offset region 112R to the first channel region 112C. That is, the first drain region 112D and the first offset region 112R are located on a first side (e.g., the left side) of the first channel region 112C, and the first source region 112S is located on a second side (e.g., the right side) of the first channel region 112C, and the first side is opposite to the second side.

[0077] Reference Figure 5 , a dielectric layer 102D2 is formed to cover the first semiconductor layer 112 and the portion of the first gate insulating layer GI1 not covered by the first semiconductor layer 112. The dielectric layer 102D2 is one of the stacked dielectric layers of the interconnect structure 102 (eg, Figure 2 As shown). The material of the dielectric layer 102D2 may be or include silicon dioxide, silicon nitride, silicon oxynitride or other inorganic dielectric materials. Figure 5 As shown, the dielectric layer 102D2 is separated from the dielectric layer 102D1 by the first gate insulating layer GI1.

[0078] Reference Figure 6 and Fig. 14C , a patterning process is performed to form a through hole O1 in the dielectric layer 102D2. In some embodiments, the patterning process performed on the dielectric layer 102D2 includes a photolithography process and an etching process performed after the photolithography process. The through hole O1 penetrates the dielectric layer 102D2, and the through hole O1 reveals the first drain region 112D of the first semiconductor layer 112. After the through hole O1 is formed in the dielectric layer 102D2, a conductive material is formed on the dielectric layer 102D2 to fill the through hole O1 and cover the top surface of the dielectric layer 102D2. The material of the conductive material may be or include copper or other metal materials. The conductive material may be formed on the dielectric layer 102D2 by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other suitable deposition processes. After depositing the conductive material on the top surface of the dielectric layer 102D2, a removal process is performed to remove a portion of the conductive material until the top surface of the dielectric layer 102D2 is exposed, thereby forming a third contact conductor 150 in the through hole O1 of the dielectric layer 102D2. The removal process for removing the excess portion of the conductive material may be or include a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, a combination of the foregoing processes, or other suitable removal processes. An ohmic contact interface is formed between the bottom surface of the third contact conductor 150 and the top surface of the first drain region 112D.

[0079] like Figure 6, the top surface of the third contact conductor 150 is substantially flush with the top surface of the dielectric layer 102D2. In some other embodiments, due to the grinding selectivity of the CMP process, the grinding selectivity of the mechanical grinding process, or the etching selectivity of the etching process, the top surface of the third contact conductor 150 is slightly lower than the top surface of the dielectric layer 102D2. In some alternative embodiments, due to the grinding selectivity of the CMP process, the grinding selectivity of the mechanical grinding process, or the etching selectivity of the etching process, the top surface of the third contact conductor 150 is slightly higher than the top surface of the dielectric layer 102D2.

[0080] In addition, the boundary between the first drain region 112D and the first offset region 112R is substantially aligned with the sidewall (e.g., the left sidewall) of the third contact conductor 150, and the boundary between the first drain region 112D and the first channel region 112C is aligned with the other sidewall (e.g., the right sidewall) of the third contact conductor 150. In other words, the boundary of the first drain region 112D of the first semiconductor layer 112 is defined by the sidewall of the third contact conductor 150. Figure 6 As shown, the third contact conductor 150 vertically overlaps the first drain region 112D. In addition, the first offset region 112R, the first channel region 112C, and the first source region 112S do not vertically overlap the third contact conductor 150.

[0081] Only the first drain region 112D vertically overlaps the third contact conductor 150 and the first gate G1 below. In other words, the first drain region 112D is vertically sandwiched between the third contact conductor 150 and the first gate G1 below. In addition, only the first source region 112S does not vertically overlap the third contact conductor 150 and the first gate G1 below.

[0082] refer to Figure 7 and Fig.14D , forming a second semiconductor layer 122 to cover the dielectric layer 102D2 and the third contact conductor 150. The material of the second semiconductor layer 122 may be or include p-type doped indium gallium zinc oxide (IGZO), indium titanium nitride zinc oxide (ITZO), indium zinc oxide (IZO) or other suitable semiconductor oxide materials. The second semiconductor layer 122 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process or other suitable deposition process. Figure 7 and Fig.14D As shown, the second semiconductor layer 122 includes a second channel region 122C, a second source region 122S, and a second drain region 122D, wherein the second channel region 122C extends laterally from the second drain region 122D to the second source region 122S. An ohmic contact interface is formed between the top surface of the third contact conductor 150 and the bottom surface of the second drain region 122D of the second semiconductor layer 122.

[0083] The second semiconductor layer 122 may further include a second offset region 122R in contact with the second drain region 122D, wherein the second drain region 122D extends laterally from the second offset region 122R to the second channel region 122C. That is, the second drain region 122D and the second offset region 122R are located on a first side (e.g., right side) of the second channel region 122C, and the second source region 122S is located on a second side (e.g., left side) of the second channel region 122C, and the first side is opposite to the second side.

[0084] The boundary between the second drain region 122D and the second offset region 112R is substantially aligned with a sidewall (e.g., a right sidewall) of the third contact conductor 150, and the boundary between the second drain region 122D and the second channel region 122C is substantially aligned with another sidewall (e.g., a left sidewall) of the third contact conductor 150. In other words, the boundary of the second drain region 122D of the second semiconductor layer 122 is defined by the sidewall of the third contact conductor 150. Figure 7 As shown, the third contact conductor 150 vertically overlaps the first drain region 112D and the second drain region 122D. In addition, the second offset region 122R, the second channel region 122C, and the second source region 122S do not vertically overlap the third contact conductor 150.

[0085] refer to Figure 8 After forming the second semiconductor layer 122, a dielectric pattern 102D3 is formed on the exposed portion of the dielectric layer 102D2. The dielectric pattern 102D3 is one of the stacked dielectric layers of the interconnect structure 102 (eg, Figure 2 102D3). The material of the dielectric pattern 102D3 may be or include silicon dioxide, silicon nitride, silicon oxynitride or other inorganic dielectric materials. The exposed portion of the dielectric layer 102D2 is not covered by the second semiconductor layer 122, and the exposed portion of the dielectric layer 102D2 is in contact with the dielectric pattern 102D3. The top surface of the dielectric layer 102D2 is substantially flush with the top surface of the dielectric pattern 102D3, which may facilitate the execution of subsequent processes. In other words, the dielectric pattern 102D3 may act as a planarization layer and may enhance the step coverage of a subsequently formed thin film. In some other embodiments, the formation of the dielectric pattern 102D3 may be omitted.

[0086] After forming the second semiconductor layer 122, a second gate insulating layer GI2 is deposited to cover the top surface of the second semiconductor layer 122 and the top surface of the dielectric pattern 102D3. The material of the second gate insulating layer GI2 may be or include silicon dioxide, silicon nitride, silicon oxynitride, or other insulating materials. The second gate insulating layer GI2 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other suitable deposition processes.

[0087] A dielectric layer 102D4 and an etch stop layer ESL are successively formed on the second gate insulating layer GI2. The dielectric layer 102D4 is one of the stacked dielectric layers of the interconnect structure 102 (eg, Figure 2 As shown). The material of the dielectric layer 102D4 may be or include silicon dioxide, silicon nitride, silicon oxynitride or other inorganic dielectric materials. Figure 8 As shown, the dielectric layer 102D4 is separated from the dielectric pattern 102D3 and the second semiconductor layer 122 by the second gate insulating layer GI2. In addition, the etch stop layer ESL is also one of the stacked dielectric layers of the interconnect structure 102 (eg, Figure 2 As shown). The material of the etch stop layer ESL may be or include silicon nitride or other etch stop materials. Figure 8 As shown, the etch stop layer ESL is separated from the dielectric pattern 102D3 and the second semiconductor layer 122 by the second gate insulating layer GI2 and the dielectric layer 102D4. In some other embodiments, the formation of the etch stop layer ESL may be omitted.

[0088] refer to Fig. 9 and Fig.14E , a patterning process is performed to form a through hole O2 in the dielectric layer 102D4 and the etch stop layer ESL. In some embodiments, the patterning process performed on the dielectric layer 102D4 and the etch stop layer ESL includes a photolithography process and an etching process after the photolithography process. The depth of the through hole O2 formed in the dielectric layer 102D4 and the etch stop layer ESL may be substantially equal to the sum of the thicknesses of the dielectric layer 102D4 and the etch stop layer ESL. After the through hole O2 is formed in the dielectric layer 102D4 and the etch stop layer ESL, a conductive material is formed on the etch stop layer ESL to fill the through hole O2 and cover the top surface of the etch stop layer ESL. The material of the conductive material may be or include copper or other metal materials. The conductive material may be formed on the etch stop layer ESL by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other suitable deposition processes. After depositing the conductive material on the top surface of the etch stop layer ESL, a removal process is performed to remove a portion of the conductive material until the top surface of the etch stop layer ESL is exposed, thereby forming a second gate G2 in the dielectric layer 102D4 and the through hole O2 of the etch stop layer ESL. The removal process for removing the excess portion of the conductive material may be or include a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, a combination of the aforementioned processes, or other suitable removal processes.

[0089] like Fig. 9, the top surface of the second gate G2 and the top surface of the etch stop layer ESL are substantially aligned. In some other embodiments, due to the grinding selectivity of the CMP process, the grinding selectivity of the mechanical grinding process, or the etching selectivity of the etching process, the top surface of the second gate G2 is slightly lower than the top surface of the etch stop layer ESL. In some alternative embodiments, due to the grinding selectivity of the CMP process, the grinding selectivity of the mechanical grinding process, or the etching selectivity of the etching process, the top surface of the second gate G2 is slightly higher than the top surface of the etch stop layer ESL.

[0090] The second channel region 122C and the second drain region 122D vertically overlap with the overlying second gate G2, and the second source region 122S does not vertically overlap with the overlying second gate G2. In addition, the second channel region 122C, the second source region 122S and the second drain region 122D are separated from the overlying second gate G2 by the second gate insulating layer GI2.

[0091] After forming the second gate G2, a first field effect transistor (e.g., an n-type field effect transistor) 110 and a second field effect transistor (e.g., a p-type field effect transistor) 120 stacked on the first field effect transistor 110 and electrically connected to the first field effect transistor 110 are manufactured. The first field effect transistor 110 includes a first gate G1, a first gate insulating layer GI1, and a first semiconductor layer 112. The second field effect transistor 120 includes a second gate G2, a second gate insulating layer GI2, and a second semiconductor layer 122. The third contact conductor 150 is vertically sandwiched between the first field effect transistor 110 and the second field effect transistor 120. Both the first semiconductor layer 112 and the second semiconductor layer 122 are in contact with the third contact conductor 150. A first ohmic contact interface is formed between the top surface of the first semiconductor layer 112 and the bottom surface of the third contact conductor 150, and a second ohmic contact interface is formed between the bottom surface of the second semiconductor layer 122 and the top surface of the third contact conductor 150.

[0092] refer to Fig.10, a patterning process is performed to form a through hole O3 and a through hole O4. The through hole O3 penetrates the etch stop layer ESL, the dielectric layer 102D4, the second gate insulating layer GI2, the dielectric pattern 102D3, the dielectric layer 102D2, the first semiconductor layer 112, and the first gate insulating layer GI1. The through hole O3 further extends downward into the dielectric layer 102D1. The bottom of the through hole O3 can be substantially flush with the bottom surface of the first gate G1. The through hole O4 penetrates the etch stop layer ESL, the dielectric layer 102D4, the second gate insulating layer GI2, the second semiconductor layer 122, the dielectric pattern 102D3, the dielectric layer 102D2, and the first gate insulating layer GI1. The through hole O4 further extends downward into the dielectric layer 102D1. The bottom of the opening O4 can be substantially flush with the bottom surface of the first gate G1. In some embodiments, the patterning process for simultaneously forming the through hole O3 and the through hole O4 includes a photolithography process and an etching process performed after the photolithography process.

[0093] After forming the through hole O3 and the through hole O4, a conductive material 160 is formed on the etch stop layer ESL and the second gate G2 to fill the through hole O3 and the through hole O4. The material of the conductive material 160 may be or include copper or other metal materials. The conductive material 160 may be formed on the etch stop layer ESL and the second gate G2 by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other suitable deposition processes.

[0094] refer to Fig.10 , Fig.11 and Fig.14F After depositing the conductive material 160 on the top surface of the etch stop layer ESL and the second gate G2, a removal process is performed to remove a portion of the conductive material 160 until the top surface of the etch stop layer ESL and the second gate G2 are exposed, thereby forming the first contact conductor 130 and the second contact conductor 140 in the through hole O3 and the through hole O4, respectively. The removal process for removing the excess portion of the conductive material 160 may be or include a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, a combination of the foregoing processes, or other suitable removal processes.

[0095] The first contact conductor 130 and the second contact conductor 140 define a region 135, and the first gate G1, the first gate insulating layer GI1, the first semiconductor layer 112, the third contact conductor 150, the second semiconductor layer 122, the second gate insulating layer GI2, and the second gate G2 are distributed in the region 135 between the first contact conductor 130 and the second contact conductor 140. The top surfaces of the first contact conductor 130 and the second contact conductor 140 are substantially flush with the top surface of the etch stop layer ESL. In some other embodiments, due to the grinding selectivity of the CMP process, the grinding selectivity of the mechanical grinding process, or the etching selectivity of the etching process, the top surfaces of the first contact conductor 130 and the second contact conductor 140 are slightly lower than the top surface of the etch stop layer ESL. In some alternative embodiments, due to the grinding selectivity of the CMP process, the grinding selectivity of the mechanical grinding process, or the etching selectivity of the etching process, the top surfaces of the first contact conductor 130 and the second contact conductor 140 are slightly higher than the top surface of the etch stop layer ESL.

[0096] like Fig.11 As shown in , the first gate G1 is laterally separated from the first contact conductor 130 and the second contact conductor 140 by different portions of the dielectric layer 102D1. The first gate G1 is electrically insulated from the first contact conductor 130 and the second contact conductor 140. Two opposite ends (or sidewalls) of the first gate insulating layer GI1 are in contact with the first contact conductor 130 and the second contact conductor 140, respectively. In other words, the first gate insulating layer GI1 extends laterally and continuously between the first contact conductor 130 and the second contact conductor 140. In addition, one end of the first semiconductor layer 112 (i.e., the first source region 112S) is in contact with the first contact conductor 130 and is electrically connected. The first semiconductor layer 112 is laterally separated from the second contact conductor 140 by the dielectric layer 102D2. The first semiconductor layer 112 is electrically insulated from the second contact conductor 140.

[0097] The third contact conductor 150 is laterally separated from the first contact conductor 130 and the second contact conductor 140 by the dielectric layer 102D2. The third contact conductor 150 is electrically insulated from the first contact conductor 130 and the second contact conductor 140.

[0098] The second semiconductor layer 122 is laterally separated from the first contact conductor 130 by the dielectric pattern 102D3. The second semiconductor layer 122 is electrically insulated from the first contact conductor 130. In addition, one end of the second semiconductor layer 122 (i.e., the second source region 122S) is in contact with and electrically connected to the second contact conductor 140. Two opposite ends (or side walls) of the second gate insulating layer GI2 are in contact with the side walls of the first contact conductor 130 and the side walls of the second contact conductor 140, respectively. In other words, the second gate insulating layer GI2 extends laterally and continuously between the first contact conductor 130 and the second contact conductor 140. The second gate G2 is laterally separated from the first contact conductor 130 and the second contact conductor 140 by different portions of the dielectric layer 102D4 and different portions of the etch stop layer ESL. The second gate G2 is electrically insulated from the first contact conductor 130 and the second contact conductor 140.

[0099] refer to Fig.12 , a dielectric layer 102D5 is formed to cover the second gate G2, the etch stop layer ESL, the first contact conductor 130 and the second contact conductor 140. The dielectric layer 102D5 may be a part of the above-mentioned interconnect structure 102 (eg, Figure 2 In some embodiments, the interconnect structure 102 (eg Figure 2 ) includes stacked dielectric layers and interconnect wiring embedded in the stacked dielectric layers, and the dielectric layer 102D5 is one of the stacked dielectric layers. The material of the dielectric layer 102D5 can be or include silicon dioxide, silicon nitride, silicon oxynitride or other inorganic dielectric materials.

[0100] refer to Fig.13 and Figure 14G , contact vias 102V1, 102V2, and 102V3 are formed through the dielectric layer 102D5. The contact via 102V1 is located on the first contact conductor 130 and is electrically connected to the first contact conductor 130, the contact via 102V2 is located on the second contact conductor 140 and is electrically connected to the second contact conductor 140, and the contact via 102V3 is located on the first gate G1 and the second gate G2 and is electrically connected to the first gate G1 and the second gate G2. In addition, a contact via 102V4 is formed on the third contact conductor 150, penetrating the dielectric layer 102D5, the etch stop layer ESL, the dielectric layer 102D4, and the second gate insulating layer GI2. The contact via 102V4 is located on the third contact conductor 150 and is electrically connected to the third contact conductor 150. The height of the contact via 102V4 may be greater than the heights of the contact vias 102V1, 102V2, and 102V3. In some embodiments, the contact vias 102V1 , 102V2 , 102V3 , and 102V4 are formed by a photolithography process and an etching process performed subsequent to the photolithography process.

[0101] like Figure 2 , Fig.13 and Figure 14G As shown, interconnection wirings 102W1, 102W2, 102W3, and 102W4 of the interconnection structure 102 are formed. Interconnection wiring 102W1 is formed on and electrically connected to contact via 102V1, interconnection wiring 102W2 is formed on and electrically connected to contact via 102V2, interconnection wiring 102W3 is formed on and electrically connected to contact via 102V3, and interconnection wiring 102W4 is formed on and electrically connected to contact via 102V4. Through interconnection wiring 102W1, first contact conductor 130 is electrically connected to a low voltage level GND (e.g., electrical ground). Through interconnection wiring 102W2, second contact conductor 140 is electrically connected to a high voltage level VDD (e.g., supply voltage VDD). Through the interconnection wiring 102W3, the first gate G1 and the second gate G2 are electrically connected to each other, and the input voltage Vin can be applied to the first gate G1 and the second gate G2. In addition, through the interconnection wiring 102W4 formed on the third contact conductor 150, the third contact conductor 150 can output a high output voltage Vout according to the input voltage Vin applied to the first gate G1 and the second gate G2.

[0102] In the above embodiment, the VTC offset problem of the inverter 103 can be improved by freely adjusting the lateral size and position of the output contact (i.e., the third contact conductor 150), so that the inverter 103 can have a symmetrical VTC. In addition, the manufacturing process of the inverter 103 is compatible with the existing process, and the inverter 103 can be easily integrated into the interconnection structure of the semiconductor die.

[0103] According to some embodiments of the utility model, a semiconductor component is provided, which includes a first gate, a second gate configured on the first gate, a first contact conductor, a second contact conductor, a third contact conductor configured between the first gate and the second gate, a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is configured between the first gate and the third contact conductor. The first semiconductor layer includes a first channel region, a first source region laterally contacting the first contact conductor, and a first drain region contacting the third contact conductor, and the first channel region extends laterally between the first drain region and the first contact conductor. The second semiconductor layer is configured between the second gate and the third contact conductor. The second semiconductor layer includes a second channel region, a second source region laterally contacting the second contact conductor, and a second drain region contacting the third contact conductor, and the second channel region extends laterally between the second drain region and the second contact conductor. In some embodiments, the first gate and the second gate are configured between the first contact conductor and the second contact conductor. In some embodiments, the first gate is located at a first level, the second gate is located at a second level different from the first level, and the third contact conductor is located at a third level between the first level and the second level. In some embodiments, the first contact conductor extends from a first level to a second level. In some embodiments, the first semiconductor layer is located at a fourth level between the first level and the third level, and the second semiconductor layer is located at a fifth level between the second level and the third level. In some embodiments, the first semiconductor layer is separated from the second contact conductor, and the second semiconductor layer is separated from the first contact conductor. In some embodiments, the semiconductor component further includes a first gate insulating layer configured between the first gate and the first semiconductor layer; and a second gate insulating layer configured between the second gate and the second semiconductor layer. In some embodiments, multiple ends of the first gate insulating layer contact the first contact conductor and the second contact conductor, and multiple ends of the second gate insulating layer contact the first contact conductor and the second contact conductor. In some embodiments, the first semiconductor layer, the second semiconductor layer, and the third contact conductor are configured between the first gate insulating layer and the second gate insulating layer. In some embodiments, the first contact conductor and the third contact conductor are separated by a first lateral distance, the second contact conductor and the third contact conductor are separated by a second lateral distance, and the first lateral distance is different from the second lateral distance.

[0104] According to some other embodiments of the utility model, a semiconductor crystal grain is provided, which includes a semiconductor substrate, an interconnection structure configured on the semiconductor substrate, and an inverter embedded in the interconnection structure. The inverter includes a first contact conductor, a second contact conductor laterally separated from the first contact conductor, a first thin film transistor, a second thin film transistor, and a third contact conductor. The second thin film transistor is stacked on the first thin film transistor, wherein the first thin film transistor and the second thin film transistor are configured in a region between the first contact conductor and the second contact conductor. The third contact conductor is configured in a region between the first contact conductor and the second contact conductor, wherein the first thin film transistor and the second thin film transistor are configured on opposite sides of the third contact conductor, the first semiconductor layer of the first thin film transistor extends laterally from the bottom surface of the third contact conductor to the first side wall of the first contact conductor, and the second semiconductor layer of the second thin film transistor extends laterally from the top surface in the third contact conductor to the second side wall of the second contact conductor. In some embodiments, the semiconductor substrate includes a metal oxide semiconductor field effect transistor (MOSFET), and the first thin film transistor and the second thin film transistor are electrically connected to the MOSFET through the interconnection structure. In some embodiments, the first thin film transistor and the second thin film transistor are separated from the semiconductor substrate by a dielectric layer of the interconnection structure. In some embodiments, the third contact conductor, the first gate of the first thin film transistor, the first semiconductor layer, the first gate insulating layer of the first thin film transistor, the second gate of the second thin film transistor, the second semiconductor layer, and the second gate insulating layer of the second thin film transistor are respectively located at different levels. In some embodiments, the first semiconductor layer is separated from the second contact conductor, and the second semiconductor layer is separated from the first contact conductor. In some embodiments, the first contact conductor is separated from the third contact conductor by a first lateral distance, and the second contact conductor is separated from the third contact conductor by a second lateral distance, and the first lateral distance is different from the second lateral distance.

[0105] According to some other embodiments of the utility model, a semiconductor component is provided, which includes a first contact conductor, a second contact conductor, a first gate insulating layer, a second gate insulating layer, a first gate, a second gate, a first semiconductor layer, a second semiconductor layer and a third contact conductor. The second contact conductor is laterally separated from the first contact conductor. The first gate insulating layer extends laterally between the first contact conductor and the second contact conductor. The second gate insulating layer is arranged above the first gate insulating layer and extends laterally between the first contact conductor and the second contact conductor. The first gate is arranged below the first gate insulating layer. The second gate is arranged above the second gate insulating layer. The first semiconductor layer, the second semiconductor layer and the third contact conductor are arranged between the first gate insulating layer and the second gate insulating layer. The first semiconductor layer extends laterally from the third contact conductor to the first contact conductor, and the second semiconductor layer extends laterally from the third contact conductor to the second contact conductor. In some embodiments, the first end of the first gate insulating layer and the second end of the second gate insulating layer are in contact with the first sidewall of the first contact conductor and the second sidewall of the second contact conductor. In some embodiments, the first semiconductor layer is laterally separated from the second contact conductor, and the second semiconductor layer is laterally separated from the first contact conductor. In some embodiments, the semiconductor die further includes an etch stop layer contacting the second gate, the first contact conductor, and the second contact conductor.

[0106] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and / or obtaining the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor component, characterized in that: include: a first gate; A second gate, disposed above the first gate; a first contact conductor; a second contact conductor; A third contact conductor is disposed between the first gate and the second gate; a first semiconductor layer disposed between the first gate and the third contact conductor, wherein the first semiconductor layer comprises a first channel region, a first source region laterally contacting the first contact conductor, and a first drain region contacting the third contact conductor, and the first channel region laterally extends between the first drain region and the first contact conductor; as well as A second semiconductor layer is arranged between the second gate and the third contact conductor, wherein the second semiconductor layer includes a second channel region, a second source region laterally contacting the second contact conductor, and a second drain region contacting the third contact conductor, and the second channel region extends laterally between the second drain region and the second contact conductor.

2. The semiconductor component according to claim 1, characterized in that The first gate is located at a first level, the second gate is located at a second level different from the first level, and the third contact conductor is located at a third level between the first level and the second level.

3. The semiconductor component according to claim 2, characterized in that The first contact conductor extends from the first level to the second level.

4. The semiconductor component according to claim 2, characterized in that The first semiconductor layer is located at a fourth level between the first level and the third level, and the second semiconductor layer is located at a fifth level between the second level and the third level.

5. The semiconductor component according to claim 1, characterized in that The first semiconductor layer is separated from the second contact conductor, and the second semiconductor layer is separated from the first contact conductor.

6. The semiconductor component according to claim 1, characterized in that The first contact conductor is separated from the third contact conductor by a first lateral distance, the second contact conductor is separated from the third contact conductor by a second lateral distance, and the first lateral distance is different from the second lateral distance.

7. A semiconductor crystal grain, characterized in that: include: Semiconductor substrate; An interconnect structure, disposed on the semiconductor substrate; An inverter is embedded in the interconnect structure, and the inverter comprises: a first contact conductor; a second contact conductor laterally spaced apart from the first contact conductor; a first thin film transistor; a second thin film transistor stacked above the first thin film transistor, wherein the first thin film transistor and the second thin film transistor are arranged in a region between the first contact conductor and the second contact conductor; and A third contact conductor is arranged in the area between the first contact conductor and the second contact conductor, wherein the first thin film transistor and the second thin film transistor are arranged on opposite sides of the third contact conductor, the first semiconductor layer of the first thin film transistor extends laterally from the bottom surface of the third contact conductor to the first side wall of the first contact conductor, and the second semiconductor layer of the second thin film transistor extends laterally from the top surface of the third contact conductor to the second side wall of the second contact conductor.

8. The semiconductor crystal grain according to claim 7, characterized in that: The first thin film transistor and the second thin film transistor are separated from the semiconductor substrate by a dielectric layer of the interconnect structure.

9. The semiconductor crystal grain according to claim 7, characterized in that: The third contact conductor, the first gate of the first thin film transistor, the first semiconductor layer, the first gate insulating layer of the first thin film transistor, the second gate of the second thin film transistor, the second semiconductor layer and the second gate insulating layer of the second thin film transistor are respectively located at different levels.

10. The semiconductor crystal grain according to claim 7, characterized in that: The first contact conductor is separated from the third contact conductor by a first lateral distance, the second contact conductor is separated from the third contact conductor by a second lateral distance, and the first lateral distance is different from the second lateral distance.

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