PD power supply parallel adapter

Abstract

The utility model discloses a PD power supply parallel adapter, which comprises at least two protocol chips and an output interface, and each protocol chip is in one-to-one correspondence with a PD power supply and is connected with the PD power supply through a corresponding input interface. The voltage anode pin of each input interface and the power supply voltage pin of the corresponding protocol chip are connected with the anode pin of the output interface through a diode, and the voltage cathode pin of each input interface and the cathode pin of the output interface are grounded. And the first configuration channel pin and the second configuration channel pin of the input interface are respectively connected with the first configuration channel pin and the second configuration channel pin of the corresponding protocol chip. According to the utility model, the plurality of protocol chips which are electrically connected with the output interfaces and are in one-to-one correspondence and connection with the PD power supplies through the corresponding input interfaces are arranged, when the output voltages of the power supplies passing through the protocol chips are equal, the output current and power of the output interfaces are the superposition of the current and power of the power supplies, so that the parallel connection of the power supplies is realized; and the high-power requirement is met.

Description

Technical Field

[0001] The utility model relates to the technical field of charging circuits, in particular to a PD power parallel adapter. Background Art

[0002] PD (Power Delivery) protocol is a charging protocol and a fast charging technology based on USB interface, which can achieve a maximum power output of up to 100W and provide a faster and more efficient charging method for various devices. However, in actual use, some electronic devices may require a power supply of 140W or higher for charging, and traditional PD power supplies cannot meet this demand. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a PD power parallel adapter to meet the demand for high-power power supply.

[0004] To solve the above technical problems, the purpose of the utility model is achieved through the following technical solutions: a PD power parallel adapter is provided, comprising at least two protocol chips and an output interface, each of the protocol chips corresponds to and is connected to a PD power supply one by one, each of the PD power supply is electrically connected to the corresponding protocol chip through an input interface, the voltage positive pin of each input interface and the power supply voltage pin of the corresponding protocol chip are connected to the positive pin of the output interface after a diode, the voltage negative pin of the input interface and the negative pin of the output interface are both grounded, and the first configuration channel pin and the second configuration channel pin of the input interface are respectively connected to the first configuration channel pin and the second configuration channel pin of the corresponding protocol chip.

[0005] A further technical solution is: the anode of the diode is connected to the positive voltage pin of the corresponding input interface and the power supply voltage pin of the corresponding protocol chip, and the cathode of the diode is connected to the positive pin of the output interface.

[0006] Its further technical solution is: the positive pin of the output interface is connected to the cathode of the diode through a switch tube, the PD power parallel adapter also includes an output protocol chip, the control end of the switch tube is connected to the control pin of the output protocol chip, the cathode of the diode is connected to the input end of the switch tube and the power supply voltage pin of the output protocol chip, the output end of the switch tube is connected to the positive pin of the output interface, and the first configuration channel pin and the second configuration channel pin of the output protocol chip are respectively connected to the first configuration channel pin and the second configuration channel pin of the output interface.

[0007] Its further technical solution is: the number of the protocol chips is two, namely the first protocol chip and the second protocol chip, and the empty pins of the first protocol chip and the empty pins of the second protocol chip are respectively connected to the first configuration channel pin and the second configuration channel pin of the output interface.

[0008] Its further technical solution is: the switch tube is an NMOS tube, the gate of the switch tube is connected to the control pin of the output protocol chip, the cathode of the diode is connected to the drain of the switch tube and the power supply voltage pin of the output protocol chip, and the source of the switch tube is connected to the positive pin of the output interface.

[0009] A further technical solution is: the anode of the diode is electrically connected to a ground polarity capacitor.

[0010] The beneficial technical effect of the present invention is that the PD power parallel adapter of the present invention is provided with multiple protocol chips electrically connected to the output interface, and each protocol chip is respectively in one-to-one correspondence and connected with the PD power through the corresponding input interface, so that each protocol chip can obtain the voltage of the corresponding PD power and output it to the output interface after being combined through the corresponding diode. The protocol chip can automatically identify and control the output voltage according to the voltage required by the terminal, and the PD power supplies connected to each protocol chip are isolated through the diode to prevent mutual influence between the PD power supplies; when the output voltages of each PD power supply after passing through the corresponding protocol chip are equal, the output current and power of the output interface are the superposition of the current and power between the PD power supplies connected to each protocol chip, so as to realize the parallel connection of the PD power supplies and obtain higher power to meet the demand of high-power power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1 A circuit diagram of a PD power parallel adapter provided by the first embodiment of the utility model;

[0013] Figure 2 This is a circuit diagram of a PD power parallel adapter provided in the second embodiment of the utility model. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0015] See also Figure 1 , Figure 1 The circuit diagram of the PD power parallel adapter provided for the first embodiment of the utility model, the PD power parallel adapter includes two protocol chips and an output interface, the two protocol chips can be a first protocol chip U1 and a second protocol chip U2 respectively, each of the protocol chips corresponds to and is connected to a PD power supply one by one, then the number of PD power supplies is two, the first protocol chip U1 corresponds to and is connected to one of the PD power supplies, the second protocol chip U2 corresponds to and is connected to the other PD power supply, each of the PD power supplies is electrically connected to the corresponding protocol chip through an input interface, then one PD power supply is electrically connected to the first protocol chip U1 through the first input interface USB1, and the other power supply can be electrically connected to the second protocol chip U2 through the second input interface USB2, the voltage positive pin of each input interface and the power supply voltage pin of the corresponding protocol chip are connected to the positive pin of the output interface after a diode, then the voltage positive pin V+ of the first input interface USB1 and the power supply voltage pin VCC of the first protocol chip U1 are connected to the output interface after a first diode D1. The positive pin of the second input interface USB2 is connected to the positive pin of the output interface, the voltage positive pin V+ of the second input interface USB2 and the power supply voltage pin VCC of the second protocol chip U2 are connected to the positive pin of the output interface after passing through the second diode D2, the voltage negative pin of the input interface and the negative pin of the output interface are grounded, then the voltage negative pin V- of the first input interface USB1, the voltage negative pin V- of the second input interface USB2 and the negative pin of the output interface are grounded, the first configuration channel pin and the second configuration channel pin of the input interface are respectively connected to the first configuration channel pin and the second configuration channel pin of the protocol chip corresponding thereto, then the first configuration channel pin CC1 and the second configuration channel pin CC2 of the first input interface USB1 are respectively connected to the first configuration channel pin CC1 and the second configuration channel pin CC2 of the first protocol chip U1, and the first configuration channel pin CC1 and the second configuration channel pin CC2 of the second input interface USB2 are respectively connected to the first configuration channel pin CC1 and the second configuration channel pin CC2 of the second protocol chip U2.

[0016] Among them, the protocol chip is a PD protocol chip, the fourth pin of the protocol chip is connected to a grounding capacitor, the ground pin of the protocol chip is grounded, the input interface can be a TYPE C interface, and the output interface can be a DC head output interface. The PD power parallel adapter is provided with multiple protocol chips electrically connected to the output interface, and each protocol chip is respectively connected to the PD power supply through the corresponding input interface, so as to obtain the voltage of the corresponding PD power supply by using each protocol chip and merge and output it to the output interface after passing through the corresponding diode. The protocol chip can automatically identify and control the output voltage according to the voltage required by the terminal, and the isolation between the PD power supplies connected to each protocol chip is realized through the diode to prevent mutual influence between the PD power supplies, and avoid damage to other power supplies when one power supply is abnormal; when the output voltage of each PD power supply is equal after passing through the corresponding protocol chip, the output current and power of the output interface are the superposition of the current and power between the PD power supplies connected to each protocol chip, and the parallel connection of the PD power supply is realized, and higher power can be obtained to meet the needs of high-power power supply. Of course, in some embodiments, the number of protocol chips can be three or more, and the remaining structures and functions are similar to the first embodiment, which will not be repeated here.

[0017] Specifically, in the first embodiment, the anode of the diode is connected to the positive voltage pin of the corresponding input interface and the power supply voltage pin of the corresponding protocol chip, and the cathode of the diode is connected to the positive pin of the output interface. Correspondingly, the anode of the first diode D1 is connected to the positive voltage pin V+ of the first input interface USB1 and the power supply voltage pin VCC of the first protocol chip U1, and the cathode of the first diode D1 is connected to the positive pin of the output interface; the anode of the second diode D2 is connected to the positive voltage pin V+ of the second input interface USB2 and the power supply voltage pin VCC of the second protocol chip U2, and the cathode of the second diode D2 is connected to the positive pin of the output interface.

[0018] Specifically, in the first embodiment, the anode of the diode is electrically connected to a ground polarity capacitor. Accordingly, the anode of the first diode D1 is electrically connected to a first ground polarity capacitor EC1, and the anode of the second diode D2 is electrically connected to a second ground polarity capacitor EC2.

[0019] See also Figure 2 , Figure 2The circuit diagram of the PD power parallel adapter provided by the second embodiment of the utility model is shown. In the second embodiment, the input interface can be a TYPE C interface, and the output interface can be a TYPE C interface. The positive pin of the output interface is connected to the cathode of the diode through a switch tube Q1. The PD power parallel adapter also includes an output protocol chip U3. The control end of the switch tube Q1 is connected to the control pin G of the output protocol chip U3. The cathode of the diode is connected to the input end of the switch tube Q1 and the power supply voltage pin VCC of the output protocol chip U3. The output end of the switch tube Q1 is connected to the positive pin of the output interface. The first configuration channel pin CC1 and the second configuration channel pin CC2 of the output protocol chip U3 are respectively connected to the first configuration channel pin and the second configuration channel pin of the output interface. The output protocol chip U3 is a PD protocol chip.

[0020] Specifically, in this embodiment, the number of the protocol chips is two, namely a first protocol chip U1 and a second protocol chip U2. The empty pin NC of the first protocol chip U1 and the empty pin NC of the second protocol chip U2 are respectively connected to the first configuration channel pin and the second configuration channel pin of the output interface.

[0021] Specifically, in this embodiment, the switch tube Q1 is an NMOS tube, the gate of the switch tube Q1 is connected to the control pin G of the output protocol chip U3, the cathode of the diode is connected to the drain of the switch tube Q1 and the power supply voltage pin VCC of the output protocol chip U3, and the source of the switch tube Q1 is connected to the positive pin of the output interface. The remaining structures and functions are similar to those of the first embodiment and will not be repeated here.

[0022] Based on the above design, when working, each protocol chip obtains the voltage of the corresponding PD power supply through the corresponding input interface, and then the voltage obtained by each protocol chip is combined after passing through the corresponding diode, so that high-power power can be obtained according to demand.

[0023] To summarize, the PD power parallel adapter of the present invention is provided with a plurality of protocol chips electrically connected to the output interface, and each protocol chip corresponds to and is connected to the PD power supply through the corresponding input interface, so that each protocol chip can obtain the voltage of the corresponding PD power supply and output it to the output interface after merging through the corresponding diode. The protocol chip can automatically identify and control the output voltage according to the voltage required by the terminal, and isolate the PD power supplies connected to each protocol chip through the diode to prevent mutual influence between the PD power supplies; when the output voltage of each PD power supply is equal after passing through the corresponding protocol chip, the output current and power of the output interface are the superposition of the current and power between the PD power supplies connected to each protocol chip, so as to realize the parallel connection of the PD power supplies and obtain higher power to meet the demand of high-power power supply.

[0024] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the utility model, and these modifications or replacements should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A PD power parallel adapter, characterized in that: The invention comprises at least two protocol chips and an output interface, each of the protocol chips corresponds to and is connected to a PD power supply one by one, each of the PD power supply is electrically connected to the corresponding protocol chip through an input interface, the positive voltage pin of each input interface and the power supply voltage pin of the corresponding protocol chip are connected to the positive pin of the output interface through a diode, the negative voltage pin of the input interface and the negative voltage pin of the output interface are both grounded, and the first configuration channel pin and the second configuration channel pin of the input interface are respectively connected to the first configuration channel pin and the second configuration channel pin of the corresponding protocol chip.

2. The PD power parallel adapter according to claim 1, characterized in that: The anode of the diode is connected to the positive voltage pin of the corresponding input interface and the power supply voltage pin of the corresponding protocol chip, and the cathode of the diode is connected to the positive pin of the output interface.

3. The PD power parallel adapter according to claim 2, characterized in that: The positive pin of the output interface is connected to the cathode of the diode through a switch tube. The PD power parallel adapter also includes an output protocol chip. The control end of the switch tube is connected to the control pin of the output protocol chip. The cathode of the diode is connected to the input end of the switch tube and the power supply voltage pin of the output protocol chip. The output end of the switch tube is connected to the positive pin of the output interface. The first configuration channel pin and the second configuration channel pin of the output protocol chip are respectively connected to the first configuration channel pin and the second configuration channel pin of the output interface.

4. The PD power parallel adapter according to claim 3, characterized in that: There are two protocol chips, namely a first protocol chip and a second protocol chip. The empty pins of the first protocol chip and the empty pins of the second protocol chip are respectively connected to the first configuration channel pin and the second configuration channel pin of the output interface.

5. The PD power parallel adapter according to claim 3, characterized in that: The switch tube is an NMOS tube, the gate of the switch tube is connected to the control pin of the output protocol chip, the cathode of the diode is connected to the drain of the switch tube and the power supply voltage pin of the output protocol chip, and the source of the switch tube is connected to the positive pin of the output interface.

6. The PD power parallel adapter according to claim 2, characterized in that: The anode of the diode is electrically connected to a grounded polarity capacitor.

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