HEMT device

Abstract

The utility model relates to an HEMT (High Electron Mobility Transistor) device, comprising a body provided with a top surface and a heterostructure; a gate region including a semiconductor material disposed on the top surface of the body, the gate region having a first lateral sidewall and a second lateral sidewall opposite the first lateral sidewall; a sealing layer of a non-conductive material extending on and in contact with the first and second lateral sidewalls of the gate region; a passivation layer of a non-conductive material having a surface portion extending laterally to the first lateral sidewall of the gate region on the top surface of the body, the sealing layer and the passivation layer having different geometric parameters; and a spacer region of a non-conductive material between the passivation layer and the sealing layer, the spacer region separating the sealing layer from the passivation layer at a location where the passivation layer is not on the top surface of the body.

Description

Technical Field

[0001] The present disclosure relates to a high electron mobility transistor (HEMT) with improved on-state performance and a process for manufacturing the same. Background Art

[0002] As is known, HEMT devices, also called heterostructure field effect transistors (HFETs), have gained wide popularity due to the possibility of operating at high voltages and due to their high breakdown voltage and high density and high charge carrier mobility.

[0003] In HEMT devices, semiconductor heterostructures (usually based on AlGaN / GaN layers) allow the spontaneous generation of a so-called two-dimensional electron gas (2DEG) in the device, which forms a channel path for charges. The spontaneous channel can be modulated by applying a suitable voltage at the gate region above the channel path.

[0004] AlGaN / GaN HEMTs are usually depletion mode. However, for practical applications, enhancement mode (normally off) devices are preferred for safe operation and drive circuit simplification.

[0005] Several methods have been proposed to realize normally-off HEMTs based on AlGaN / GaN layers, including forming a recessed gate transistor, performing specific manufacturing steps such as incorporating a fluorine plasma under the gate, or forming the gate region of p-GaN. The latter solution is used, for example, in products available on the market and is considered below.

[0006] For example, Figure 1 A HEMT device 1 formed on a semiconductor body 2 is shown, where the semiconductor body 2 comprises a substrate layer 3, a first layer 4 and a second layer 6 (hereinafter also referred to as a channel layer 4 and a barrier layer 6).

[0007] The substrate layer 3 may include Figure 1 The silicon substrate and gallium nitride (GaN) buffer layer are not shown separately.

[0008] The channel layer 4 is made of a first semiconductor material such as, for example, a first semiconductor alloy of elements of Group III and Group V of the periodic table; for example, the channel layer 4 may be made of gallium nitride (GaN).

[0009] The barrier layer 6 overlies the channel layer 4 and is in direct contact with the channel layer 4, and is made of a second semiconductor material, such as, for example, a second semiconductor alloy of Group III-Group V elements of the periodic table, which is different from the first semiconductor alloy. For example, the barrier layer 6 can be made of aluminum gallium nitride (AlGaN).

[0010] The channel layer 4 and the barrier layer 6 are, for example, of N-type.

[0011] The gate region 7 extends on the barrier layer 6. The gate region 7 is formed of, for example, a third semiconductor material such as, for example, a third semiconductor alloy of elements of Group III and Group V of the periodic table; in particular, here the gate region 7 is formed of P conductivity type gallium nitride (pGaN).

[0012] A first insulating region 9 of, for example, silicon oxide, extends on the barrier layer 6 , on the side surfaces and on the upper surface of the gate region 7 .

[0013] An opening 11 extends through the first insulating region 9 on top of the gate region 7 , and a gate metal region 10 , for example TiN / AlCu / TiN, is in direct electrical contact with the gate region 7 and extends in the opening 11 and partially over the first insulating region 9 .

[0014] A second insulating region 12 , for example silicon oxide, extends over the first insulating region 9 and the gate metal region 10 .

[0015] A field plate 13 of a conductive material may extend on the first insulating region 9, laterally to the gate metal region 10, and below the second insulating region 12. The field plate 13 may be formed of the same metal layer as the gate metal region 10.

[0016] The source metal region 15, for example Ti / AlCu / TiN, extends on and laterally of the second insulating region 12 and is in direct electrical contact with the barrier layer 6. In the HEMT device 1, the source metal region 15 has a portion extending over the gate metal region 10 and over the field plate region 13 and has a shielding function.

[0017] A drain metal region 16 of, for example, Ti / AlCu / TiN, is on and extends laterally from the second insulating region 12 (on the opposite side of the gate region 7 relative to the source metal region 15 ), on the barrier layer 6 and in direct electrical contact therewith.

[0018] In this type of HEMT transistor, etching of the layers above the semiconductor body 2 is critical and may affect the barrier layer 6. Indeed, such etching may damage the barrier layer 6 and cause an increase in its sheet resistance, thus causing an increase in the on-resistance (Ron) of the HEMT device 1. Utility Model Content

[0019] To avoid this severity, it has been suggested to change the parameters of the barrier layer 6 (thickness, percentage of Al); however, this solution has the disadvantage of reducing the pinch-off voltage Vpo, thereby reducing the threshold voltage of the device; in addition, it also reduces the gate current Igon. Therefore, the choice of the parameters of the barrier layer 6 means a compromise between Ron, Vpo / Vth and Igon.

[0020] Therefore, one object of the present disclosure is to overcome the disadvantages and limitations of the prior art.

[0021] According to one aspect of the present disclosure, a HEMT device is provided, comprising: a body having a top surface and a heterostructure; a gate region comprising a semiconductor material, arranged on the top surface of the body, the gate region having a first lateral sidewall and a second lateral sidewall opposite to the first lateral sidewall; a sealing layer of a non-conductive material, extending on and contacting the first lateral sidewall and the second lateral sidewall of the gate region; a passivation layer of a non-conductive material, having a surface portion extending on the top surface of the body laterally to the first lateral sidewall of the gate region, the sealing layer and the passivation layer having different geometric parameters; and a spacer region of a non-conductive material, located between the passivation layer and the sealing layer, the spacer region separating the sealing layer from the passivation layer at a position where the passivation layer is not on the top surface of the body.

[0022] In some embodiments, the HEMT device further comprises: a first current conducting terminal of conductive material on the top surface of the body at a distance from and extending laterally to the first lateral sidewall of the gate region; a second current conducting terminal of conductive material on the top surface of the body at a distance from and extending laterally to the second lateral sidewall of the gate region, wherein a surface portion of the passivation layer is arranged between the gate region and the first current conducting terminal, and wherein the passivation layer does not extend on the top surface of the body between the gate region and the second current conducting terminal.

[0023] In some embodiments, the HEMT device further comprises: a first current conducting terminal of conductive material on the top surface of the body at a distance from and extending laterally to the first lateral sidewall of the gate region; and a second current conducting terminal of conductive material on the top surface of the body at a distance from and extending laterally to the second lateral sidewall of the gate region, wherein the surface portion of the passivation layer is a first surface portion arranged between the gate region and the first current conducting terminal, and the passivation layer further has a second surface portion extending on the top surface of the body, laterally to the second lateral sidewall of the gate region and arranged between the gate region and the second current conducting terminal.

[0024] In some embodiments, the sealing layer is made of an oxide selected from the group consisting of Al2O3, HfO2, and AlON.

[0025] In some embodiments, the sealing layer has a thickness between 2 nm and 10 nm.

[0026] In some embodiments, the passivation layer is made of nitride.

[0027] In some embodiments, the passivation layer has a thickness of 5 nm.

[0028] In some embodiments, the passivation layer has a greater thickness than the sealing layer.

[0029] In some embodiments, the sealing layer further extends partially over a top surface of the gate region, and the passivation layer further has a raised portion extending over and contacting the spacer region.

[0030] In some embodiments, the HEMT device further includes a field plate region of conductive material, which is lateral to the first lateral sidewall or the second lateral sidewall of the gate region and extends a distance from the gate region and is located above the top surface of the body.

[0031] In some embodiments, the heterostructure includes a channel layer and a barrier layer extending on the channel layer, the barrier layer forming a top surface of the body, wherein a surface portion of the passivation layer extends directly on the barrier layer and has a single crystalline structure.

[0032] According to one aspect of the present disclosure, a high electron mobility transistor (HEMT) device is provided, comprising: a heterostructure having a first surface; a gate region comprising a semiconductor material on the first surface, the gate region having a first lateral sidewall and a second lateral sidewall opposite to the first lateral sidewall, the gate region having a second surface opposite to the first surface, and the second surface traversing the lateral sidewall; a sealing layer of non-conductive material, on and in contact with the first and second lateral sidewalls of the gate region; a passivation layer, on the first surface, lateral to the first lateral sidewall of the gate region, the passivation layer on the second surface; and a spacer region of non-conductive material, between the passivation layer and the sealing layer.

[0033] In some embodiments, the passivation layer has a greater thickness than the sealing layer.

[0034] According to the present disclosure, a HEMT device and a manufacturing process thereof are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to understand the present disclosure, embodiments thereof will now be described, purely as non-limiting examples, with reference to the accompanying drawings, in which:

[0036] Figure 1 is the cross section of a known HEMT device;

[0037] Figure 2 is a cross section of a HEMT device according to an embodiment;

[0038] Figure 3A-3G yes Figure 2 A cross section of a semiconductor wafer in a subsequent manufacturing step of a HEMT device;

[0039] Figure 4A-4C is a cross section of a semiconductor wafer during a subsequent manufacturing step of some embodiments of a HEMT device;

[0040] Figure 5 is a cross-section of a HEMT device according to another embodiment; and

[0041] Figure 6 is a cross-section of a HEMT device according to another embodiment. DETAILED DESCRIPTION

[0042] The following description refers to the arrangements shown in the accompanying drawings; therefore, expressions such as "above", "below", "upper", "lower", "top", "bottom", "right", "left", etc. are relative to the drawings and should not be interpreted in a limiting manner.

[0043] Figure 2 A HEMT device 50 is shown comprising a body 52 having a top surface 52A and formed by a substrate 53 and a heterostructure, here comprising a channel layer 54 and a barrier layer 56 .

[0044] The substrate 53 may include Figure 2 The silicon layer and the gallium nitride (GaN) buffer layer are shown separately.

[0045] The channel layer 54 is made of a first semiconductor material such as a first semiconductor alloy of Group III and Group V elements of the periodic table; for example, the channel layer 54 may be made of gallium nitride (GaN) or an alloy including GaN such as InGaN, particularly GaN.

[0046] The barrier layer 56 overlies and directly contacts the channel layer 54 and is made of a second semiconductor material, such as a second semiconductor alloy of Group III-Group V elements of the periodic table, which is different from the first semiconductor alloy. For example, the barrier layer 56 may be made of a material such as Al x Ga 1-x N, AlInGaN, In x Ga 1-x N、Al x In1-x A ternary or quaternary alloy of gallium nitride such as Al, AlScN, in particular AlGaN.

[0047] The channel layer 54 and the barrier layer 56 are, for example, of N-type.

[0048] The gate region 57 extends on and is in contact with the barrier layer 56. In a manner not shown, the gate region 57 is strip-shaped and extends along a first horizontal axis Y of the Cartesian reference system XYZ.

[0049] exist Figure 2 In the embodiment, the gate region 57 includes a channel modulation region 58 (here, pGaN (P-conductivity type gallium nitride)) and an interlayer region 59.

[0050] The channel modulation region 58 serves to modulate a channel formed at an interface between the channel layer 56 and the barrier layer 56 below the channel modulation region 58 based on a voltage applied thereto.

[0051] In detail, in this embodiment, the HEMT device 50 is a normally-off HEMT.

[0052] The interlayer region 59 is used to facilitate the turn-on of the channel modulation region 58 and to form a barrier to the diffusion of contaminants from the upper layers, as described later. The interlayer region 59 may be made of a material such as TiN.

[0053] exist Figure 2 In the embodiment of FIG. 5 , along the second horizontal axis X of the Cartesian reference system XYZ, the interlayer region 59 has a smaller width than the channel modulation region 58 .

[0054] The interlayer regions 59 are optional.

[0055] The HEMT device 50 includes a source region 61 and a drain region 62 of a conductive material (eg, Ti / AlCu / TiN) that form a source terminal S and a drain terminal D of the HEMT device 50 , respectively.

[0056] The source region 61 and the drain region 62 each include a respective contact portion 63 extending over the top surface 52A of the body 52 , where they are in direct contact with the barrier layer 56 .

[0057] The contact portions 63 of the source region 61 and the drain region 62 form an ohmic contact with the heterostructure, in particular, with the 2DEG disposed at the interface between the channel layer 54 and the barrier layer 56 .

[0058] In practice, the contact portion 63 of the source region 61 and the contact portion 63 of the drain region 62 form part of the source current conducting terminal and the drain current conducting terminal, respectively, of the HEMT device.

[0059] The gate region 57 is arranged along the axis X between the contact portion 63 of the source region 61 and the contact portion 63 of the drain region 62 .

[0060] In other words, the gate region 57 is on the source side ( Figure 2 The left side in FIG. 1 faces the contact portion 63 of the source region 62, and the ... drain region 62. Figure 2 The right side in FIG. 1 faces the contact portion 63 of the drain region 62.

[0061] In detail, the gate region 57 has a source lateral sidewall 65 facing the contact portion 63 of the source region 61 and a drain lateral sidewall 66 opposite to the source lateral sidewall 65 and facing the contact portion 63 of the drain region 62 .

[0062] In this embodiment, the source lateral sidewall 65 and the drain lateral sidewall 66 of the gate region 57 include the lateral sidewalls of both the channel modulation region 58 and the interlayer region 59 .

[0063] On the source side, the gate region 57 is arranged at a distance W parallel to the axis X from the contact portion 63 of the source region 61. s , and on the drain side, arranged at a distance W parallel to the axis X from the contact portion 63 of the drain region 62 d . Distance W s and W d It may be comprised between, for example, 0.5 μm and 20 μm, depending on the specific application of the HEMT device 50 , and in particular on the specific voltage rating of the HEMT device 50 (eg, the maximum voltage that the HEMT device 50 needs to withstand during use).

[0064] In detail, in this embodiment, the distance W s Less than distance W d ; For example, the distance W s can be from 0.5 μm to 1 μm, and the distance W d can be from 1.8 μm to 20 μm, in particular, the ratio W s / W d It can be about 1 / 4.

[0065] In other words, the gate region 57 is arranged along the axis X closer to the contact portion 63 of the source region 61 than to the contact portion 63 of the drain region 62 .

[0066] A sealing layer 67 of an insulating material (here particularly Al2O3), for example an oxide such as Al2O3, HfO2 or AlON, covers the source lateral side walls 65 and the drain lateral side walls 66 of the channel modulation region 58 and the interlayer region 59 and partially covers the upper side of the channel modulation region 58 and the upper side of the interlayer region 59.

[0067] The sealing layer 67 has a thickness comprised between 2 nm and 10 nm, for example 2.5 nm.

[0068] In this embodiment, the sealing layer 67 has a surface portion that continuously extends from the source lateral sidewall 65 and the drain lateral sidewall 66 of the gate region 57 along the axis X on the top surface 52A of the body 52 .

[0069] In detail, the sealing layer 67 extends on the source side of the gate region 57 up to the contact portion 63 of the source region 61, that is, extends the entire distance W s .

[0070] On the drain side of gate region 57, the surface portion of sealing layer 67 extends only a distance W above top surface 52A. d part, especially much smaller than the distance W d A portion of, for example, comprised between 0.1 μm and 0.3 μm.

[0071] The sealing layer 67 also extends along the axis Y in a manner not shown here.

[0072] A spacer region 70 of insulating material such as oxide or nitride, particularly silicon oxide, extends over the sealing layer 67 .

[0073] In detail, the spacer region 70 overlies the sealing layer 67 and is in direct contact therewith.

[0074] A passivation layer 75 of an insulating material such as an oxide or a nitride, here particularly AlN, extends over the spacer region 70 and, on the drain side of the gate region 57 , also over a portion of the top surface 52A of the body 52 .

[0075] In detail, the material of the passivation layer 75 may have a small lattice mismatch with the barrier layer 56; for example, if the barrier layer 56 includes AlGaN or is entirely formed of AlGaN, the passivation layer 75 may be made of AlN.

[0076] The thickness of the passivation layer 75 may be comprised, for example, between 2 nm and 10 nm, for example 5 nm.

[0077] In this embodiment, the passivation layer 75 has a greater thickness than the sealing layer 67 .

[0078] In detail, the passivation layer 75 has a surface portion 75A extending on a portion of the top surface 52A of the body 52 on the drain side of the gate region 57 and a convex portion 75B extending on the spacer region 70 .

[0079] The surface portion 75A extends in direct contact with the barrier layer 56 .

[0080] Surface portion 75A extends along axis X at a distance from drain-lateral sidewall 66 of gate region 57 .

[0081] In detail, the surface portion 75A extends adjacent to a surface portion of the sealing layer 67 between the sealing layer 67 and the contact portion 63 of the drain region 62 .

[0082] In more detail, in this embodiment, the surface portion 75A extends over the entire width between the surface portion of the sealing layer 67 and the contact portion 63 of the drain region 62 .

[0083] The surface portion 75A of the passivation layer 75 may be epitaxial with respect to the barrier layer 56 ; thus, the surface portion 75A may have a monocrystalline structure.

[0084] The single crystal structure can be detected by known techniques such as energy dispersive X-ray (EDX) spectroscopy or electron energy loss (EELS) spectroscopy.

[0085] The raised portion 75B of the passivation layer 75 extends over the spacer region 70 , and in particular overlies and contacts the spacer region 70 .

[0086] The convex portion 75B may have a polycrystalline structure or an amorphous structure.

[0087] A first insulating layer 78 , for example an oxide or a nitride, in particular silicon oxide, extends over the passivation layer 75 .

[0088] In detail, the first insulating layer 78 overlies the passivation layer 75 and is in direct contact therewith.

[0089] The first insulating layer 78 , the passivation layer 75 , the spacer region 70 , and the sealing layer 67 are opened on the interlayer region 59 , thereby forming a gate opening 79 .

[0090] A multi-layer gate metal 80 , such as TiN / AlCu / TiN, extends in gate opening 79 , in direct electrical contact with interlayer region 59 , and in this embodiment, partially extends over first insulating layer 78 .

[0091] A second insulating layer 82 , for example an oxide or a nitride, in particular silicon nitride here, extends on the drain side of the gate region 57 on the first insulating layer 78 .

[0092] The fact that the second insulating layer 82 is made of a different material relative to the first insulating layer 78 allows for a simplified manufacturing process, as discussed further below.

[0093] The second insulating layer 82 has a thickness comprised, for example, between 50 nm and 100 nm.

[0094] In detail, the second insulating region 82 partially faces the surface portion 75A of the passivation layer 75 .

[0095] A third insulating layer 83 , for example an oxide or a nitride, in particular silicon oxide, extends over the first insulating layer 78 , over the gate metal 68 and over the second insulating layer 82 .

[0096] The source opening 84 and the drain opening 85 extend vertically, parallel to the axis Z, on the source side and the drain side of the gate region 57 , respectively, up to the top surface 52A of the body 52 .

[0097] The contact portion 63 of the source region 61 and the contact portion 63 of the drain region 62 extend in the source opening 84 and the drain opening 85 , respectively.

[0098] In this embodiment, the source region 61 further has a shielding portion 86 extending over the gate metal 68 and having a shielding function.

[0099] In this embodiment, field plate 87 extends at a distance from gate region 57 on the drain side of gate region 57, partially on first insulating layer 78 and partially on second insulating layer 82, below second insulating layer 69. Field plate 87 may be formed from the same metal layer used to form gate metal 80.

[0100] In other words, the field plate 87 has a non-planar structure and extends along the axis X at different distances from the barrier layer 56 measured along the axis Z. In detail, a portion of the contact portion 63 of the field plate 87 that is closer to the drain region 62 is arranged at a greater distance (measured along the axis Z) from the barrier layer 56 .

[0101] The non-planar structure of the field plate 87 allows for effectively having a double field plate, thereby allowing for greater design freedom to modulate the electric field in the body 52 .

[0102] Here too, the shielding part 86 of the source region 61 extends over the field plate 87 .

[0103] exist Figure 2In the HEMT device 50 , the fact that the sealing layer 67 has different properties (different materials and / or different thicknesses) relative to the surface portion 75A of the passivation layer 75 on the drain side of the gate region 57 allows different 2DEGs to be formed below the gate region 57 and below the surface portion 75A.

[0104] That is, a first 2DEG (hereinafter also referred to as gate 2DEG) is formed at the interface between the channel layer 54 and the barrier layer 56 below the gate region 57, and a second 2DEG (hereinafter also referred to as access 2DEG) is formed at the interface between the channel layer 54 and the barrier layer 56 below the surface portion 75A of the passivation layer 75.

[0105] By tailoring and optimizing the parameters / characteristics of the sealing layer 67 and the passivation layer 75 , the density of the gate 2DEG and the access 2DEG can thus be tailored and optimized according to the desired characteristics.

[0106] In particular, using Figure 2 The structure can have a high sheet resistance Rsh below and around the gate region 57, resulting in a high threshold voltage and low electric field at the corner between the channel modulation region 58 and the blocking layer 56 (at the gate 2DEG), and a low sheet resistance Rsh below the passivation layer 75, resulting in a low on-resistance Ron (at the access 2DEG).

[0107] The HEMT device 50 thus allows a good compromise to be obtained between gate current, threshold voltage and on-resistance.

[0108] Furthermore, the fact that surface portion 75A of passivation layer 75 may have epitaxial properties of barrier layer 56 will allow reconstruction of possible defects of barrier layer 56 at top surface 52A of body 52 generated during fabrication. Thus, HEMT device 50 may achieve good electrical performance.

[0109] Furthermore, when the passivation layer 75 includes AlN and the barrier layer 56 includes AlGaN, the passivation layer 75 may allow the interface state density to be reduced, and the 2DEG carrier density and drift mobility to be increased by suppressing a trapping effect.

[0110] The HEMT device 50 may be Figure 3A-3G As shown in the manufacture, Figure 3A-3G The wafer is shown before dicing. Figure 3A-3G The manufacturing steps of the HEMT 50 are shown with respect to a portion of the HEMT device 50 including the gate region 57 and the corresponding source and drain sides, ie the manufacturing steps for forming the source and drain regions are not shown.

[0111] Figure 3A A wafer 100 is shown having a top surface 100A and comprising a stack of layers including a substrate 53, a channel layer 54 and a barrier layer 56. On the barrier layer 56 a gate region 57 has been formed.

[0112] For example, the channel modulation region 58 and the interlayer region 59 can be formed by sputtering a TiN layer on a pGaN layer epitaxially grown on the barrier layer 56 and photolithographically defining the TiN layer and the pGaN layer by side etching using a single mask (not shown) to obtain a smaller width of the interlayer region 59; however, any other manufacturing steps are possible, such as by using two different masks.

[0113] exist Figure 3B In the embodiment, a working sealing layer 101 for forming the sealing layer 67 is formed on the exposed barrier layer 56 and the gate region 57 , and a spacer layer 102 for forming the spacer region 70 is formed on the working sealing layer 101 .

[0114] For example, the working sealing layer 101 is thermally deposited or plasma deposited using ALD (Atomic Layer Deposition) technology in a H 2 O-based environment at 300° C. to a thickness of, for example, 2.5 nm.

[0115] The spacer layer 102 may be deposited, for example, by PECVD (Plasma Enhanced Chemical Vapor Deposition) in a SiO 2 SiH 4 based environment to a thickness of, for example, 200 nm.

[0116] exist Figure 3C In the process, a mask 104 of, for example, a polymer material is formed on the spacer layer 102.

[0117] Mask 104 exposes a portion of spacer layer 102 on the drain side of gate region 57 that extends over a portion of top surface 100A on which surface portion 75A of passivation layer 75 is intended to be formed.

[0118] exist Figure 3C In the embodiment of the present invention, by using the mask 104, an opening 106 is also formed through the spacer layer 102 and the working sealing layer 101.

[0119] The exposed portions of the spacer layer 102 are anisotropically etched (eg, by dry etching) to expose the underlying working sealing layer 101. The exposed working sealing layer 101 is etched, for example, by wet etching using an etchant that is selective to the material of the barrier layer 56.

[0120] If the barrier layer 56 is made of AlGaN, the etchant may be, for example, a product from DuPont TM Production of EKC265 TM .

[0121] The selective etchant may allow for minimization of the possibility of damaging the underlying barrier layer 56. Thus, access to the 2DEG is not affected by this etch and, therefore, the sheet resistance Rsh is not negatively affected.

[0122] Then, Figure 3D , the mask 104 is removed, and a working passivation layer 110 (intended to form the passivation layer 75 ) is formed, for example, from AlN and using an ALD technique at about 370° C. with a thickness of, for example, 5 nm.

[0123] Working passivation layer 110 has surface portion 110A extending over the exposed portion of top surface 100A and forming surface portion 75A of passivation layer 75 , and raised portion 110B extending over the remaining portion of spacer layer 102 and forming raised portion 75B of passivation layer 75 .

[0124] The surface portion 110A may be grown layer by layer on the barrier layer 56. This allows the crystal structure of the barrier layer 56 to be reconstructed at the top surface 100A, which may have been formed during initial manufacturing steps, such as during an etching step to form the channel modulation region 58 and / or during the reference Figure 3C The working sealing layer 101 is damaged during the removal described.

[0125] The surface portion 110A may follow the epitaxial characteristics of the barrier layer 56 and have a single crystal structure.

[0126] exist Figure 3E In the embodiment, a first insulating layer 78 and a second insulating layer 82 are formed on the working passivation layer 110 .

[0127] The first insulating layer 78, for example silicon oxide, is deposited, for example, by PECVD in a SiO 2 SiH 4 based environment to a thickness of, for example, 50 nm.

[0128] The second insulating layer 82, for example silicon nitride, can be deposited by PECVD to a thickness of, for example, 80 nm. The second insulating layer 82 can be formed by blanket deposition and subsequent patterning.

[0129] The fact that the first insulating layer 78 can be made of a different material than the second insulating layer 82 allows for a simplified integration of the second insulating layer 82 in the process flow. In fact, the first insulating layer 78 and the second insulating layer 82 will have different etching rates from each other. Thus, while patterning the second insulating layer 82, the remaining thickness of the underlying first insulating layer 78 can be better controlled. Therefore, the distance of the field plate 87 from the surface 100A can be accurately controlled.

[0130] exist Figure 3FIn the embodiment, the first insulating layer 78 , the passivation layer 110 , the spacer layer 102 , and the working sealing layer 101 are etched using a mask (not shown) to form a gate opening 79 , thereby exposing a top surface of the gate region 57 .

[0131] exist Figure 3G In the embodiment, a gate metal layer is deposited and defined to form a gate metal 80 in the gate opening 79 and a field plate 87 at its side. The gate metal layer may be a multilayer of TiN / AlCu / TiN.

[0132] Then, in a manner not shown, a third insulating layer 83 is deposited; a source opening 84 and a drain opening 85 are formed; and a source / drain metal layer is deposited and defined to form the source region 61 and the drain region 62 .

[0133] The final manufacturing steps then include depositing an outer passivation layer; forming electrical contacts on the gate metal 80 and on the source region 61 and the drain region 62; and dicing the wafer 100 to obtain Figure 2 HEMT device 50.

[0134] Figure 4A-4C Manufacturing steps of a HEMT device according to various embodiments are shown, wherein the field plate has a planar structure.

[0135] Figure 4A Shows Figure 3E Here, only the first insulating layer 78 is formed, and the second insulating region 82 is not formed.

[0136] Then, Figure 4B , similar to reference Figure 3F The gate opening 79 is formed as described, and Figure 4C , depositing and defining the gate metal layer.

[0137] Thus, a gate metal 80 is formed in the gate opening 79 , and a field plate 87 ′ is formed on the first insulating layer 78 .

[0138] In this embodiment, the field plate 87 ′ extends only on top of the first insulating layer 78 and is in direct contact therewith. In practice, the field plate 87 ′ extends along the axis X at a substantially constant distance from the barrier layer 56 .

[0139] The final manufacturing steps are then performed as described above.

[0140] Figure 5 A HEMT device, indicated here by 150 , according to various embodiments is shown.

[0141] The HEMT device 150 has Figure 2The HEMT device 50 has a similar overall structure; therefore, common elements are indicated by the same reference numerals and are not described in further detail.

[0142] In this embodiment, the sealing layer indicated by 167 extends on the top surface 52A of the body 52 on the source side of the gate region 57 only a distance W between the gate region 57 and the contact portion 63 of the source region 61. d part of.

[0143] Figure 5 The spacer region indicated by 170 here also overlies the sealing layer 167, being in direct contact therewith.

[0144] In this embodiment, Figure 5 The passivation layer indicated by 175 in FIG. 5 extends over spacer region 170 and over portions of top surface 52A on both the drain side of gate region 57 and the source side of gate region 57 .

[0145] In detail, the passivation layer 175 has a surface portion 175A extending on the top surface 52A on the drain side of the gate region 57 and a surface portion 175C extending on the top surface 52A on the source side of the gate region 57 .

[0146] The raised portion 175B of the passivation layer 175 extends over the spacer region 170 , and in particular overlies and contacts the spacer region 170 .

[0147] The surface portions 175A, 175C may have a single crystal structure, while the raised portion 175B may have a polycrystalline structure, as shown in FIG. Figure 2 As discussed in sections 75A, 75B.

[0148] The discussion regarding the passivation layer 75 of the HEMT device 50 also applies to the passivation layer 175 of the HEMT 150 .

[0149] Thus, the presence of surface portion 175C of passivation layer 175 allows the density of the 2DEG to be tailored and optimized also on the source side of gate region 57 .

[0150] The HEMT device 150 can therefore achieve a good trade-off between gate current, threshold voltage, and on-resistance.

[0151] Here, too, the passivation layer 175 may allow possible defects of the barrier layer 56 to be reconstructed at the top surface 52A also on the source side of the gate region 57 .

[0152] It will be appreciated by those skilled in the art that the HEMT device 150 can be connected to Figure 3A-3G The steps for the HEMT device 50 are similar to those shown in FIG. 5 . For example, in this case, Figure 3CThe mask 104 may also have a second opening on the source side of the gate region 57 so as to remove portions of the working spacer layer 102 and the working sealing layer 101 also on the source side, thereby also allowing Figure 3D Surface portion 175C is formed during the deposition step of .

[0153] Figure 6 A HEMT device 200 is shown in which the source metal region and the drain metal region are formed before the gate metal region.

[0154] exist Figure 6 In, with Figure 5 The common elements of the HEMT device 150 have been indicated using the same reference numerals. After forming the first insulating layer 78 ( Figure 3E or Figure 4A , depending on whether a second insulating region 82 is to be formed).

[0155] After forming the first insulating layer 78, a source opening, indicated herein by 84', and a drain opening, indicated herein by 85', are formed.

[0156] Then, source and drain regions, indicated here by 201 and 202 , are formed by depositing and defining the same metal layer or stack (eg Ti / AlCu / TiN).

[0157] The field plate 203 may be formed together with the source region 201 and the drain region 202 .

[0158] Thereafter, another insulating layer 205 corresponding to the third insulating layer 83 and made of, for example, oxide or nitride is deposited on the first insulating layer 78 and on the source region 201 and the drain region 202 .

[0159] The gate opening 206 therefore also extends through the insulating layer 205 here.

[0160] The gate metal 210 extends within the gate opening 206 and partially over the insulating layer 205 .

[0161] In a manner not shown here, the shielding region may be formed from the same metal layer that forms the gate metal 210 , or from a different metal layer that is deposited later.

[0162] Finally, it is evident that numerous changes and modifications may be made to the HEMT devices and processes described and illustrated herein, all of which fall within the scope of the present disclosure as defined in the appended claims.

[0163] For example, the passivation layer 75 , 175 may be made of a different insulating material having a small lattice mismatch with respect to the barrier layer 56 , so that the surface portion 75A, 175A, 175C may be grown layer by layer and have a single crystal structure.

[0164] In general, the passivation layer 75 , 175 may have the same, lesser, or greater thickness than the sealing layer 67 , 167 .

[0165] Generally speaking, the source lateral sidewall 65 and the drain lateral sidewall 66 may correspond to the lateral sidewall of the channel modulation region 58 only, or to the lateral sidewalls of both the channel modulation region 58 and the interlayer region 59, depending on the specific structure of the gate region 57 and the specific manufacturing steps used to manufacture the HEMT device.

[0166] In general, surface portions 75A, 175A, 175C of passivation layers 75, 175 may each extend between respective lateral sidewalls 65, 66 of gate region 57 and respective source or drain contact portion 63 and extend along axis X from respective lateral sidewalls 65, 66 to an entire portion (e.g., an entire distance W) of top surface 52A of respective contact portion 63. d and / or W s For example, the surface portions 75A, 175A, 175C of the passivation layer 75, 175 may extend a certain distance between the respective lateral sidewalls 65, 66 of the gate region 57 and the respective source contact portion or drain contact portion 63, but do not reach the respective contact portion 63.

[0167] For example, the distance W d , W s Can be equal to each other, or at a distance W s Can be greater than the distance W d .

[0168] For example, the heterostructure may also include other layers besides the channel layer 54 and the barrier layer 56. For example, the heterostructure may include other semiconductor layers or insulating layers below the channel layer or above the barrier layer, depending on the specific application of the HEMT device and the specific manufacturing steps used to manufacture the corresponding body.

[0169] Finally, the embodiments shown and described may be combined to provide other solutions.

[0170] The HEMT device (50; 150; 200) can be summarized as comprising: a body (52) having a top surface (52A) and a heterostructure (54, 56); a gate region (57) comprising a semiconductor material, arranged on the top surface (52A) of the body (52), the gate region having a first lateral sidewall (66) and a second lateral sidewall (65) opposite the first lateral sidewall; a sealing layer (67; 167) of a non-conductive material, disposed on the gate region (52); 7) and extending on and contacting the first lateral sidewall and the second lateral sidewall (65, 66) of the gate region (57); and a passivation layer (75; 175) of non-conductive material, having a surface portion (75A; 175A, 175C) extending laterally to the first lateral sidewall (66) of the gate region (57) on the top surface (52A) of the body (52), the sealing layer (67; 167) and the passivation layer (75; 175) having different geometric parameters and / or being made of different materials.

[0171] The HEMT device may further include: a first current conducting terminal (63, 62) of conductive material on the top surface (52A) of the body (52) at a distance from and extending laterally to a first lateral sidewall (66) of the gate region (57); a second current conducting terminal (63, 61) of conductive material on the top surface (52A) of the body (52) at a distance from and extending laterally to a second lateral sidewall (65) of the gate region (57), wherein a surface portion (75A) of the passivation layer (75) is arranged between the gate region and the first current conducting terminal (63, 62), and wherein the passivation layer (75) does not extend on the top surface (52A) of the body (52) between the gate region and the second current conducting terminal (63, 61).

[0172] The HEMT device may further include: a first current conducting terminal (62; 202) of conductive material, which is on the top surface (52A) of the body (52) at a distance from the first lateral sidewall (66) of the gate region (57) and extends laterally to the first lateral sidewall (66); and a second current conducting terminal (61; 201) of conductive material, which is on the top surface (52A) of the body (52) at a distance from the second lateral sidewall (65) of the gate region (57) and extends laterally to the second lateral sidewall (65), wherein the surface portion of the passivation layer (175) is a first surface portion (175A) arranged between the gate region and the first current conducting terminal (62; 202), and the passivation layer also has a second surface portion (175C) extending on the top surface (52A) of the body (52), laterally to the second lateral sidewall (65) of the gate region and arranged between the gate region and the second current conducting terminal (61; 201).

[0173] The sealing layer (67; 167) may be made of an oxide, for example selected from: Al2O3, HfO2 and AlON.

[0174] The thickness of the sealing layer (67; 167) may be comprised between 2 nm and 10 nm, for example 2.5 nm.

[0175] The passivation layer (75; 175) may be made of a nitride, in particular AlN.

[0176] The thickness of the passivation layer (75; 175) may be comprised between 2 nm and 10 nm, for example 5 nm.

[0177] The passivation layer (75; 175) may have a greater thickness than the sealing layer (75; 175).

[0178] The sealing layer (67; 167) may also partially extend over the top surface of the gate region (57), the HEMT device further comprising a spacer region (70; 170) of a non-conductive material extending over and in contact with the sealing layer (67; 167), and the passivation layer (75; 175) further comprising a raised portion (75B; 175B) extending over and in contact with the spacer region (70; 170).

[0179] The HEMT device may further include a field plate region (87; 87'; 203) of conductive material extending laterally to the first lateral sidewall or the second lateral sidewall of the gate region and at a distance from the gate region, located above the top surface (52A) of the body (52).

[0180] The heterostructure may include a channel layer (54) and a barrier layer (56) extending over the channel layer, the barrier layer forming a top surface (52A) of the body, wherein a surface portion (75A; 175A, 175C) of a passivation layer (75; 175) may extend directly over the barrier layer and have a single crystalline structure.

[0181] A process for manufacturing a HEMT device (50; 150; 200), the process can be summarized as comprising: forming a gate region (57) on a wafer (80) having a top surface (80A) and a heterostructure (54, 56), the gate region comprising a semiconductor material and arranged on the top surface of a body, the gate region having a first lateral sidewall (66) and a second lateral sidewall (65) opposite the first lateral sidewall; forming a sealing layer (67; 167) of a non-conductive material, the sealing layer being disposed on the top surface of a body; The invention relates to a sealing layer (67; 167) and a passivation layer (75; 175) formed of a non-conductive material, the passivation layer having a surface portion (75A; 175A, 175C) extending laterally to the first lateral sidewall (66) of the gate region (57) on the top surface (52A) of the body (52), the sealing layer (67; 167) and the passivation layer (75; 175) having different geometric parameters and / or being made of different materials.

[0182] Forming a sealing layer (67; 167) may include: depositing a working sealing layer (101) on the gate region (57) and on the top surface (52A) of the body (52); depositing a working spacer layer (102) on the working sealing layer; forming a mask (104) above the working spacer layer, the mask having an opening above a portion of the top surface of the wafer, the opening being arranged at a certain distance from the gate region and lateral to a first lateral sidewall (66) of the gate region; and selectively removing the working sealing layer (101) and the working spacer layer by using the mask (104), wherein forming a passivation layer includes depositing a working passivation layer (110) after selectively removing the working sealing layer and the working spacer layer.

[0183] A process may also include: forming an insulating structure (78, 82, 83; 78, 205) on the passivation layer (75; 175); forming a gate opening (79; 206) that at least partially exposes the top surface of the gate region (57) and extends at least partially through the insulating structure; forming a gate control terminal (68) of conductive material on the gate region within the gate opening (79); forming a first current conduction terminal (62; 202) of conductive material, the first current conduction terminal extending laterally to the first lateral sidewall (66) of the gate region (57) on the top surface of the body (52) and in contact with it; and forming a second current conduction terminal (61; 201) of conductive material, the second current conduction terminal extending laterally to the second lateral sidewall (65) of the gate region (57) on the top surface of the body (52) and in contact with it.

[0184] The first current conducting terminal and the second current conducting terminal (61, 62) may be formed after forming the gate control terminal (80).

[0185] In an embodiment, a process for manufacturing a HEMT device includes: forming a gate region on a wafer having a top surface and a heterostructure, the gate region including a semiconductor material and arranged on the top surface of a body, the gate region having a first lateral sidewall and a second lateral sidewall opposite to the first lateral sidewall; forming a sealing layer of non-conductive material, the sealing layer extending on and contacting the first lateral sidewall and the second lateral sidewall of the gate region; forming a spacer region of non-conductive material, the spacer region extending on and contacting the sealing layer; and forming a passivation layer of non-conductive material, the passivation layer having a surface portion extending on the top surface of the body laterally to the first lateral sidewall of the gate region, the sealing layer and the passivation layer having different geometric parameters and / or being made of different materials, the spacer region being located between the sealing layer and the passivation layer, the spacer region separating the sealing layer from the passivation layer at a position where the passivation layer is not on the top surface of the body.

[0186] In some embodiments, forming a sealing layer includes: depositing a working sealing layer on the gate region and on the top surface of the body; depositing a working spacer layer on the working sealing layer; forming a mask above the working spacer layer, the mask having an opening above a portion of the top surface of the wafer, the opening being arranged to be a certain distance away from the gate region and lateral to a first lateral sidewall of the gate region; and selectively removing the working sealing layer and the working spacer layer by using the mask, wherein forming a passivation layer includes depositing the working passivation layer after selectively removing the working sealing layer and the working spacer layer.

[0187] In some embodiments, the process also includes: forming an insulating structure on the passivation layer; forming a gate opening that at least partially exposes the top surface of the gate region and extends at least partially through the insulating structure; forming a gate control terminal of a conductive material on the gate region within the gate opening; forming a first current conduction terminal of the conductive material, the first current conduction terminal extending laterally to and in contact with a first lateral sidewall of the gate region on the top surface of the body; and forming a second current conduction terminal of the conductive material, the second current conduction terminal extending laterally to and in contact with a second lateral sidewall of the gate region on the top surface of the body.

[0188] In some embodiments, the first current conducting terminal and the second current conducting terminal are formed after forming the gate control terminal.

[0189] In some embodiments, the spacer region is formed after forming the sealing layer.

[0190] In some embodiments, the spacer regions are formed before forming the passivation layer.

[0191] In some embodiments, the process further includes forming a field plate region of conductive material laterally to the first lateral sidewall or the second lateral sidewall of the gate region and extending a distance from the gate region, above the top surface of the body.

[0192] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide further embodiments.

[0193] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalent forms to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A HEMT device, characterized in that: include: a body having a top surface and a heterogeneous structure; a gate region including a semiconductor material disposed on the top surface of the body, the gate region having a first lateral sidewall and a second lateral sidewall opposite the first lateral sidewall; a sealing layer of non-conductive material extending over and contacting the first lateral sidewall and the second lateral sidewall of the gate region; A passivation layer of non-conductive material having a surface portion extending laterally from a first lateral sidewall of the gate region on a top surface of the body, the sealing layer and the passivation layer having different geometric parameters; as well as A spacer region of non-conductive material is located between the passivation layer and the sealing layer, the spacer region separating the sealing layer from the passivation layer at a location where the passivation layer is not on the top surface of the body.

2. The HEMT device according to claim 1, further comprising: a first current conducting terminal of conductive material on the top surface of the body at a distance from and extending laterally to the first lateral sidewall of the gate region; a second current conducting terminal of conductive material, on the top surface of the body, at a distance from and extending laterally to the second lateral sidewall of the gate region, wherein a surface portion of the passivation layer is arranged between the gate region and the first current conducting terminal, and Wherein the passivation layer does not extend over the top surface of the body between the gate region and the second current conducting terminal.

3. The HEMT device according to claim 1, further comprising: a first current conducting terminal of conductive material on the top surface of the body at a distance from and extending laterally to the first lateral sidewall of the gate region; as well as a second current conducting terminal of conductive material, on the top surface of the body, at a distance from and extending laterally to the second lateral sidewall of the gate region, wherein the surface portion of the passivation layer is a first surface portion arranged between the gate region and the first current conducting terminal, and The passivation layer also has a second surface portion extending above the top surface of the body, lateral to a second lateral sidewall of the gate region and arranged between the gate region and the second current conducting terminal. The HEMT device of claim 1 , wherein the sealing layer has a thickness between 2 nm and 10 nm. The HEMT device according to claim 1 , wherein the passivation layer is made of nitride. The HEMT device according to claim 1 , wherein the passivation layer has a thickness of 5 nm. 7 . The HEMT device of claim 1 , wherein the passivation layer has a greater thickness than the sealing layer.

8. The HEMT device of claim 1, wherein the sealing layer further extends partially over a top surface of the gate region, and the passivation layer further has a raised portion extending over and contacting the spacer region.

9. The HEMT device of claim 1 , further comprising a field plate region of conductive material, which is lateral to the first lateral sidewall or the second lateral sidewall of the gate region and extends at a distance from the gate region, and is located above the top surface of the body.

10. The HEMT device of claim 1, wherein the heterostructure comprises a channel layer and a barrier layer extending on the channel layer, the barrier layer forming a top surface of the body, wherein a surface portion of the passivation layer extends directly on the barrier layer and has a single crystalline structure.

11. A HEMT device, characterized in that: include: a heterostructure having a first surface; a gate region on the first surface including a semiconductor material, the gate region having a first lateral sidewall and a second lateral sidewall opposite the first lateral sidewall, the gate region having a second surface opposite the first surface, and the second surface traverses the lateral sidewall; a sealing layer of non-conductive material on and in contact with the first lateral sidewall and the second lateral sidewall of the gate region; A passivation layer on the first surface, lateral to a first lateral sidewall of the gate region, and the passivation layer on the second surface; as well as A spacer region of non-conductive material is between the passivation layer and the sealing layer. 12 . The HEMT device of claim 11 , wherein the passivation layer has a greater thickness than the sealing layer.

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