Comparator circuit beneficial to ultra-low input voltage DCDC boosting device
By improving the voltage comparator circuit in the reference reference module, using a higher VREF0 instead of VREF, outputting PFM logic high-level signal at ultra-low input voltage, solving the problem that the existing DCDC booster device cannot start normally at low input voltage, realizing the startup and normal operation of the booster device, and reducing production costs.
Patent Information
- Application Number
- CN202322759288.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-13
- Publication Date
- 2025-03-11
- Estimated Expiration
- 2033-10-13
AI Technical Summary
The existing DCDC booster devices cannot start normally at low input voltages, limiting the application range of lower input voltages, and the use of special devices increases production costs.
By improving the voltage comparator circuit in the reference reference module, the higher VREF0 is preferred instead of VREF, and the PFM logic high-level signal is output at an ultra-low input voltage, so that the boost system switch drive control module works normally, and the alternating turn-on or turn-off of transistors Q1 and Q2 is realized.
The startup and normal operation of the booster device at ultra-low input voltage avoids the inconvenience of using higher voltage batteries or multiple batteries and reduces production costs.
Smart Images
Figure CN222602398U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of integrated circuit (IC) automatic test equipment (ATE for short), and relates to a comparator circuit that is beneficial to an ultra-low input voltage DCDC boost device. Background Art
[0002] DCDC boost devices are commonly used in power supply applications such as alkaline batteries, NiMH rechargeable batteries, lithium manganese batteries or lithium ion rechargeable batteries. Figure 1 , Figure 1 The figure shows a schematic diagram of the structure of a comparator circuit of a DCDC boost device using the prior art. Figure 1 As shown, the circuit mainly includes a reference comparison module, a boost system switch drive control module, an inductor L0, a feedback resistor R1, a feedback resistor R2, a sampling resistor R3, a capacitor CIN, a capacitor COUT, a transistor Q1, a transistor Q2 and other components. The reference comparison module includes a PFM comparator unit PFMCMP, a bandgap reference unit BANDGAP and a bias current unit BIAS; the boost system switch drive control module includes a zero-crossing detection comparator unit ZCDCMP, a current limiting detection comparator unit OCLCMP, a drive unit DRIVER, a current limiting detection logic control unit OCLCTRL and an oscillator unit OSC.
[0003] Please combine Figure 1 See also Figure 2 , Figure 2 for Figure 1 FIG. 1 is a schematic diagram of a PFM comparator unit PFMCMP in a boost device system. Figure 2 As shown, the PFM comparator unit PFMCMP includes N-type transistors MN0, MN1, MN2, MN3, MN4, P-type transistors MP0, MP1, MP2 and a logic Schmitt trigger SMIT.
[0004] When the circuit is started, the external input VIN power supply is powered on, and the current from VIN charges the capacitor COUT through the inductor L0 and the transistor Q1, and the output voltage VOUT rises to a voltage value close to the external input VIN. The power supply of the internal modules is provided by the external input VIN. When the external input VIN meets the voltage that the system can work, the bias current unit IBIAS is started first to provide the bias current IB for the PFM comparator unit PFMCMP, the zero-crossing detection comparator unit ZCDCMP, and the current-limiting detection comparator unit OCLCMP. At the same time, the bandgap reference unit BANDGAP is started, and the output VREF is used to provide the reference voltage for the PFM comparator unit PFMCMP. The output voltage VOUT is compared with the reference voltage VREF by the voltage divider VFB of the resistor R1 and the resistor R2 to the PFM comparator unit PFMCMP. When the PFM comparator unit PFMCMP detects that VREF>VFB, the PFM comparator unit PFMCMP outputs an enable control signal of a logic high level for PFM. At this time, the oscillator unit OSC starts to oscillate and output a fixed-period clock signal CLK. Under the premise that the enable signals of PZCD and NOCL are invalid, the drive unit DRIVER receives the CLK signal and outputs VPG and VNG to connect the gates of transistor Q1 and transistor Q2, so as to turn on or off transistor Q1 and transistor Q2.
[0005] When transistor Q1 is turned off and transistor Q2 is turned on, the external input VIN, inductor L0, and N-type transistor Q2 form a charging loop, and inductor L0 begins to store energy; when transistor Q1 is turned on and transistor Q2 is turned off, the current across L0 does not change suddenly immediately, and a discharge loop is formed between VIN and VOUT. The energy of inductor L0 is slowly released and transmitted to the VOUT terminal through transistor Q1, thereby increasing the VOUT voltage.
[0006] When VFB>VREF, it means that VOUT is greater than the target voltage. At this time, the PFM comparator unit PFMCMP outputs a logic low signal to control the oscillator unit OSC to stop working. At this time, the clock signal CLK is always at a low level. After passing through the drive unit DRIVER, the VNG signal continues to output a low level, and the transistor Q2 cannot be turned on. During the energy release process of the inductor L0, the zero-crossing detection comparator unit ZCDCMP compares the voltages of SW and VOUT. When VOUT>SW, it means that the current of the inductor L0 is released to nearly 0, and the output ZCD is a logic low signal. The ZCD signal passes through the zero-crossing detection logic control unit ZCDCTRL to output PZCD and is transmitted to the switch drive logic control unit DRIVER, and the output VPG signal turns off the Q1 transistor to prevent the current of the inductor L0 from flowing back to the input end.
[0007] When VFB<VREF, it means that VOUT is less than the target voltage. At this time, PFMCMP outputs a logic high signal to control the oscillator unit OSC to work and continuously output a fixed-cycle clock signal CLK. The driving unit DRIVER receives the CLK signal and outputs VPG and VNG to control the transistor Q1 and the transistor Q2 to turn on or off. In the process of the continuous increase of the current of the inductor L0, the current limiting detection comparator unit OCLCMP compares the size of VB and VS. When VS>VB, it means that the current of the inductor L0 exceeds the set current limiting value, and the output OCL is a logic low level. The OCL signal is transmitted to the switch drive logic control unit DRIVER through the current limiting detection logic control unit OCLCTRL output NOCL, and the output VNG signal turns off the transistor Q2 until the next CLK cycle starts, and the transistor Q2 will be turned on again, thereby limiting the peak value of the inductor current.
[0008] In the prior art, the power supply of the internal module, i.e., VOUT, must reach a relatively high voltage value in order to enable the internal module to work normally and the boost device system to start normally. The premise for the normal startup of the boost device is that VREF must be greater than VFB so that the oscillator module can output the CLK clock signal, thereby driving the switch drive logic control unit DRIVER to realize the alternate opening or closing of the transistor Q1 and the transistor Q2.
[0009] For example, the bandgap reference unit BANDGAP of the traditional BJT architecture requires a power supply voltage of at least 1.5V to generate VREF for normal operation. Therefore, the input voltage VIN must be at least higher than 1.5V for the system to start normally, which limits the application scope of lower input voltages.
[0010] Nowadays, electronic devices on the market are generally small and light. There are many applications that use a dry cell battery to power the boost device. However, the input voltage is too low, which greatly limits the system boost. If a higher voltage battery or multiple batteries are used to power the device, the device can work normally, but there will be many problems such as large size and inconvenience in carrying.
[0011] Of course, if a BANDAGAP module with other special device architectures is used, although it is possible to achieve normal output VREF at a lower input power supply voltage, allowing the system to work normally at a lower input voltage and start the boost device system, special devices have higher requirements for process selection, which will increase production costs and is not conducive to the economy of the product. Utility Model Content
[0012] In order to solve the above technical problems, the utility model proposes a comparator circuit that is beneficial to an ultra-low input voltage DCDC boost device. By improving the voltage comparator circuit in the reference module, the boost device can be started and operate normally under ultra-low input voltage.
[0013] To achieve the above purpose, the technical solution of the utility model is as follows:
[0014] A comparator circuit for an ultra-low input voltage DCDC boost device, comprising a reference comparison module, a boost system switch drive control module, a P-type transistor Q1 and an N-type transistor Q2; the reference comparison module comprises a PFM comparator unit PFMCMP, a bandgap reference unit BANDGAP and a bias current unit IBIAS; the boost system switch drive control module comprises a zero-crossing detection comparator unit ZCDCMP, a zero-crossing detection logic control unit ZCDCTRL, a current limiting detection comparator unit OCLCMP, a switch drive logic control unit DRIVER, a current limiting detection logic control unit OCLCTRL and an oscillator unit OSC; wherein the bias current unit IBIAS provides a bias current IB for the PFM comparator unit PFMCMP, the zero-crossing detection comparator unit ZCDCMP and the current limiting detection comparator unit OCLCMP; the bandgap reference unit BANDGAP provides a bias current IB for the PFM comparator unit PFMCMP and the current limiting detection comparator unit OCLCMP provides a reference voltage; the PFM comparator unit PFMCMP compares the reference voltage VREF with the divided voltage VFB of the output terminal VOUT, and outputs an enable control signal PFM; the oscillator unit OSC outputs a fixed-period clock signal to supply the switch drive logic control unit DRIVER of the subsequent stage; the zero-crossing detection comparator unit ZCDCMP compares the SW signal with the voltage of the output terminal VOUT, and outputs a ZCD signal; the zero-crossing detection logic control unit ZCDCTRL receives the ZCD signal and outputs a PZCD signal; the current limiting detection comparator unit OCLCMP compares the VS signal with the voltage of the output terminal VB, and outputs an OCL signal; the current limiting detection logic control unit OCLCTRL receives the OCL signal and outputs a NOCL signal; the switch drive logic control unit DRIVER receives the clock signal, the PZCD signal and the NOCL signal to control the gates of the P-type transistor Q1 and the N-type transistor Q2;
[0015] The PFM comparator unit PFMCMP includes an N-type transistor MN0, an N-type transistor MN1, an N-type transistor MN2, an N-type transistor MN3, an N-type transistor MN4, an N-type transistor MN5, a P-type transistor MP0, a P-type transistor MP1, a P-type transistor MP2 and a logic Schmitt trigger SMIT;
[0016] The logic Schmitt trigger SMIT is connected between the output terminal VOUT and the ground terminal GND, the output terminal is PFM, and the input terminal is connected to the drain of the P-type transistor MP2 and the N-type transistor MN4; the gate of the P-type transistor MP2, the drain of the P-type transistor MP1 and the drain of the N-type transistor MN1 are connected, the source of the P-type transistor MP0, the source of the P-type transistor MP1, the source of the P-type transistor MP2 and the source of the P-type transistor MP3 are connected to the output terminal VOUT; the gate of the N-type transistor MN4, the gate and drain of the N-type transistor MN2, and the N-type transistor MN5 are connected to the output terminal VOUT; The gate of the N-type transistor MN2 and the gate of the N-type transistor MN3 are connected to the voltage terminal IB; the source of the N-type transistor MN2, the source of the N-type transistor MN3 and the source of the N-type transistor MN4 are connected to the ground terminal GND, the drain of the N-type transistor MN3 is connected to the source of the N-type transistor MN5, the source of the N-type transistor MN0 and the source of the N-type transistor MN1; the gate of the N-type transistor MN1 is connected to VFB, and the gate of the N-type transistor MN0 is connected to VREF; the drain of the N-type transistor MN5, the gate and drain of the P-type transistor MP0, the drain of the N-type transistor MN0 and the gate of the P-type transistor MP1 are connected.
[0017] Furthermore, the comparator circuit for the ultra-low input voltage DCDC boost device further includes a feedback resistor R1 and a feedback resistor R2, which are connected in series between the output terminal VOUT and the ground terminal GND to generate the divided voltage VFB.
[0018] Furthermore, the comparator circuit for the ultra-low input voltage DCDC boost device further includes an inductor L0, a capacitor COUT and a capacitor CIN, one end of the capacitor CIN is connected to the external input voltage VIN and one end of the inductor L0, and the other end is connected to the ground terminal GND, and the other end of the inductor L0 is connected to the connection point of the SW signal terminal, the P-type transistor Q1 and the drain of the N-type transistor Q2.
[0019] It can be seen from the above technical scheme that the utility model is beneficial to the comparator circuit of the ultra-low input voltage DCDC boost device. By improving the input circuit of the PFM comparator unit PFMCMP, when the bandgap reference unit BANDGAP cannot work normally at a relatively low voltage, VREF0 with a higher voltage is preferably used to replace VREF. When VREF0 is greater than VFB, a PFM logic high level signal can be output, so that the boost system switch drive control module can work normally and drive transistor Q1 and transistor Q2 to be turned on alternately to transmit energy to the output terminal VOUT, thereby realizing the startup of the boost system at an ultra-low input voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1The schematic diagram of the structure of the booster system using the prior art is shown.
[0021] Figure 2 for Figure 1 Schematic diagram of the PFM comparator unit PFMCMP in the boost device system shown in FIG.
[0022] Figure 3 FIG. 1 is a schematic diagram of a preferred embodiment of a comparator circuit for an ultra-low input voltage DCDC boost device according to an embodiment of the present invention.
[0023] Figure 4 for Figure 3 Schematic diagram of the PFM comparator unit PFMCMP in the boost device system shown in FIG.
[0024] Figure 5 The figure shows a voltage comparison diagram of the boost device system in the embodiment of the utility model and the boost device system in the prior art during the boost process. DETAILED DESCRIPTION
[0025] The following is combined with Figure 3-5 , the specific implementation methods of the utility model are further described in detail.
[0026] See also Figure 3 , Figure 3 The figure shows a schematic diagram of a preferred embodiment of a comparator circuit for an ultra-low input voltage DCDC boost device in the embodiment of the present utility model. Figure 3 As shown, the improved boost system mainly includes a reference comparison module, a boost system switch drive control module, a boost module, a voltage divider module, an external input voltage terminal VIN, an output terminal VOUT, a P-type transistor Q1, an N-type transistor Q2, resistors, capacitors, inductors and transistor devices.
[0027] The voltage dividing module is connected between the voltage output terminal VOUT and the ground terminal, and is used to generate a divided voltage VFB of the voltage output terminal VOUT.
[0028] The reference comparison module includes a PFM comparator unit PFMCMP, a bandgap reference unit BANDGAP and a bias current unit IBIAS, wherein the voltage of the voltage input terminal VIN is less than the normal operating voltage of the reference comparison module and the boost system switch drive control module; the boost system switch drive control module includes a zero-crossing detection comparator unit ZCDCMP, a zero-crossing detection logic control unit ZCDCTRL, a current limiting detection comparator unit OCLCMP, a switch drive logic control unit DRIVER, a current limiting detection logic control unit OCLCTRL and an oscillator unit OSC.
[0029] When the external input voltage VIN power supply is powered on, the boost module causes the voltage of the voltage output terminal VOUT to rise to a voltage value close to the external input voltage VIN; the bandgap reference unit BANDGAP does not work. Among them, the bias current unit IBIAS provides bias current for the PFM comparator unit PFMCMP, the zero-crossing detection comparator unit ZCDCMP and the current-limiting detection comparator unit OCLCMP; the bandgap reference unit BANDGAP provides a reference voltage for the PFM comparator unit PFMCMP and the current-limiting detection comparator unit OCLCMP; the PFM comparator unit PFMCMP compares the reference voltage VREF with the divided voltage VFB of the output terminal VOUT, and outputs an enable control signal PFM; the oscillator unit OSC outputs a fixed-period clock signal to supply the switch drive logic control unit DRIVER of the subsequent stage; the The zero-crossing detection comparator unit ZCDCMP compares the SW signal with the voltage of the output terminal VOUT and outputs a ZCD signal; the zero-crossing detection logic control unit ZCDCTRL receives the ZCD signal and outputs a PZCD signal; the current-limiting detection comparator unit OCLCMP compares the VS signal with the voltage of the output terminal VB and outputs an OCL signal; the current-limiting detection logic control unit OCLCTRL receives the OCL signal and outputs a NOCL signal; the switch drive logic control unit DRIVER receives a clock signal, a PZCD signal and a NOCL signal to control the gates of the transistors Q1 and Q2.
[0030] In addition, the voltage division module in the comparator circuit further includes a feedback resistor R1 and a feedback resistor R2, which are connected in series between the output terminal VOUT and the ground terminal GND to generate the divided voltage VFB.
[0031] The boost module includes an inductor L0, a P-type transistor Q1, an N-type transistor Q2, an N-type transistor Q3 and R3; the external input voltage VIN is connected to one end of the inductor L0, and the other end of the inductor L0 is connected to the connection point of the drains of the P-type transistor Q1 and the N-type transistor Q2; the connection point of the drains of the P-type transistor Q1 and the N-type transistor Q2 is the SW signal terminal; the source of the P-type transistor Q1 is connected to the output terminal VOUT, and the source of the N-type transistor Q2 is connected to the ground terminal GND; the gate of the N-type transistor Q3 is connected to the gate of the N-type transistor Q2, its source is connected to the ground terminal GND through the resistor R3, and its drain is connected to the drain of the N-type transistor Q2; the connection point of its source and the resistor R3 is the VS signal terminal.
[0032] The comparator circuit also includes an inductor L0 and a capacitor CIN, one end of the capacitor CIN is connected to the input voltage VIN and one end of the inductor L0, and the other end is connected to the ground terminal GND, and the other end of the inductor L0 is connected to the connection point of the SW signal terminal, the P-type transistor Q1 and the drain of the N-type transistor Q2.
[0033] See also Figure 4 , Figure 4 for Figure 3 FIG. 1 is a schematic diagram of a PFM comparator unit PFMCMP in a boost device system. Figure 4 As shown, the PFM comparator unit PFMCMP includes N-type transistors MN0, MN1, MN2, MN3, MN4, MN5, P-type transistors MP0, MP1, MP2 and a logic Schmitt trigger SMIT.
[0034] In the embodiment of the present invention, the PFM comparator unit PFMCMP is used to generate a comparator reference voltage substitute signal VREF0 to compare with the divided voltage VFB of the output terminal VOUT voltage when the input voltage is relatively low, and normally output a PFM high level signal.
[0035] The logic Schmitt trigger SMIT is connected between the output terminal VOUT and the ground terminal GND, the output terminal is PFM, and the input terminal is connected to the drain of the P-type transistor MP2 and the N-type transistor MN4; the gate of the P-type transistor MP2, the drain of the P-type transistor MP1 and the drain of the N-type transistor MN1 are connected, the source of the P-type transistor MP0, the source of the P-type transistor MP1 and the source of the P-type transistor MP2 are connected to the output terminal VOUT; the gate of the N-type transistor MN4, the gate and drain of the N-type transistor MN2, the gate of the N-type transistor MN5, and the N-type transistor MN6 are connected to the output terminal VOUT; The gate of the body transistor MN3 is connected to the voltage terminal IB; the source of the N-type transistor MN2, the source of the N-type transistor MN3 and the source of the N-type transistor MN4 are connected to the ground terminal GND, the drain of the N-type transistor MN3 is connected to the source of the N-type transistor MN5, the source of the N-type transistor MN0 and the source of the N-type transistor MN1; the gate of the N-type transistor MN1 is connected to VFB, and the gate of the N-type transistor MN0 is connected to VREF; the drain of the N-type transistor MN5, the gate and drain of the P-type transistor MP0, the drain of the N-type transistor MN0 and the gate of the P-type transistor MP1 are connected.
[0036] Please combine Figure 3 and 4 See also Figure 5 , Figure 5The figure shows a voltage comparison diagram of the boosting device system in the embodiment of the utility model and the boosting device system in the prior art during the boosting process. Figure 5 As shown,
[0037] When the ultra-low input voltage is started, the external input voltage VIN power supply is powered on, and the current from the external input voltage VIN charges the capacitor COUT through the inductor L0 and the P-type transistor Q1, and the voltage of the output terminal VOUT rises to a voltage value close to the external input voltage VIN.
[0038] The power supply of the internal modules is provided by the voltage of the output terminal VOUT. Since the external input voltage VIN is low, the voltage of the output terminal VOUT is also low and insufficient to ensure that all internal modules can work normally. At this time, the bias current unit IBIAS is started first, and the bias current unit IBIAS provides the bias current IB for the PFM comparator unit PFMCMP, the zero crossing detection comparator unit ZCDCMP and the current limiting detection comparator unit OCLCMP.
[0039] However, the bandgap reference unit BANDGAP cannot work properly to output the correct reference voltage VREF, so the PFM comparator unit PFMCMP uses the bias current provided by the bias current IB to generate a relatively high reference voltage VREF0 through the N-type transistor MN2.
[0040] At this time, the PFM comparator unit PFMCMP will select a relatively high reference voltage VREF0 to compare with the divided voltage VFB of VOUT, and detect that the reference voltage VREF0>reference voltage VFB, and the PFM comparator unit PFMCMP outputs an enable control signal of PFM with a logic high level; at the same time, the oscillator unit OSC starts to oscillate and output a clock signal CLK with a fixed period. Under the premise that the enable signals of PZCD and NOCL are invalid, the switch drive logic control unit DRIVER receives the CLK signal and outputs VPG and VNG to connect the gates of the P-type transistor Q1 and the N-type transistor Q2, thereby turning on or off the P-type transistor Q1 and the N-type transistor Q2.
[0041] When the P-type transistor Q1 is turned off and Q2 is turned on, the external input VIN, the inductor L0 and the N-type transistor Q2 form a charging loop, and the inductor L0 begins to store energy; when the P-type transistor Q1 is turned on and Q2 is turned off, the current across L0 will not change suddenly immediately, and a discharge loop will be formed between VIN and VOUT. The energy of the inductor L0 is slowly released and transmitted to the VOUT end through the P-type transistor Q1, thereby increasing the VOUT voltage.
[0042] As the voltage at the output terminal VOUT continues to rise, if it rises to a level where the bandgap reference unit BANDGAP can work normally and generate a reference voltage VREF greater than VREF0, the input end of the PFM comparator unit PFMCMP will switch to compare VREF with VFB, and the boost system will start to reach a preset output voltage value.
[0043] When VFB>VREF, it means that VOUT is greater than the target voltage. At this time, the PFM comparator unit PFMCMP outputs a logic low signal to control the oscillator unit OSC to stop working. At this time, the clock signal CLK is always at a low level. After the switch drive logic control unit DRIVER, the VNG signal continues to output a low level, and the N-type transistor Q2 cannot be turned on. During the energy release process of the inductor L0, the zero-crossing detection comparator unit ZCDCMP compares the SW and VOUT voltages.
[0044] When the voltage VOUT of the output terminal VOUT>SW, it means that the current of the inductor L0 is released to close to 0, and the output ZCD is a logic low level signal. The ZCD signal passes through the zero-crossing detection logic control unit ZCDCTRL to output PZCD and is transmitted to the switch drive logic control unit DRIVER, and the output VPG signal turns off the P-type transistor Q1 to prevent the current of the inductor L0 from flowing back to the input terminal.
[0045] When VFB<VREF, it means that the voltage of the output terminal VOUT is less than the target voltage. At this time, the PFM comparator unit PFMCMP outputs a logic high level signal to control the oscillator unit OSC to work and continuously output a fixed-cycle clock signal CLK. The switch drive logic control unit DRIVER receives the CLK signal and outputs VPG and VNG to control the P-type transistor Q1 and the N-type transistor Q2 to turn on or off. In the process of the continuous increase of the current of the inductor L0, the current limiting detection comparator unit OCLCMP compares the size of VB and VS; when VS>VB, it means that the current of the inductor L0 exceeds the set current limiting value, and the output OCL is a logic low level. The OCL signal is transmitted to the switch drive logic control unit DRIVER through the current limiting detection logic control unit OCLCTRL output NOCL, and the output VNG signal turns off the N-type transistor Q2 until the next CLK cycle starts, and the N-type transistor Q2 will be turned on again, thereby limiting the peak value of the inductor current.
[0046] The above-described embodiments are only preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, all equivalent structural changes made using the description and drawings of the present invention should also be included in the protection scope of the present invention.
Claims
1. A comparator circuit for an ultra-low input voltage DCDC boost device, characterized in that: It includes a reference comparison module, a boost system switch drive control module, an external input voltage terminal VIN, an output terminal VOUT, a boost module and a voltage divider module; the voltage divider module is connected between the voltage output terminal VOUT and the ground terminal, and is used to generate a divided voltage VFB of the voltage output terminal VOUT; the reference comparison module includes a PFM comparator unit PFMCMP, a bandgap reference unit BANDGAP and a bias current unit IBIAS; wherein the voltage of the voltage input terminal VIN is less than the normal working voltage of the reference comparison module and the boost system switch drive control module; When the external input voltage VIN power supply is powered on, the boost module causes the voltage of the voltage output terminal VOUT to rise to a voltage value close to the external input voltage VIN; the bandgap reference unit BANDGAP does not work; the bias current unit IBIAS provides a bias current IB for the PFM comparator unit PFMCMP; the PFM comparator unit PFMCMP generates a reference voltage VREF0 using the bias current provided by the bias current unit IBIAS; when the reference voltage VREF0> the divided voltage VFB, the PFM comparator unit PFMCMP outputs an enable control signal PFM that is a logic high level enable control signal; at the same time, the boost system switch drive control module controls the boost module to continue to increase the voltage of the output terminal VOUT; When the voltage of the voltage output terminal VOUT rises to the point where the bandgap reference unit BANDGAP starts working, the bandgap reference unit BANDGAP generates a reference voltage VREF greater than the reference voltage VREF0, and the input end of the PFM comparator unit PFMCMP is switched to compare the reference voltage VREF with the divided voltage VFB, and outputs an enable control signal PFM that is a logic high level enable control signal; the boost system switch drive control module controls the boost module to continue to increase the voltage of the voltage output terminal VOUT until the target voltage is output.
2. The comparator circuit for an ultra-low input voltage DCDC boost device according to claim 1, characterized in that: The PFM comparator unit PFMCMP includes an N-type transistor MN0, an N-type transistor MN1, an N-type transistor MN2, an N-type transistor MN3, an N-type transistor MN4, an N-type transistor MN5, a P-type transistor MP0, a P-type transistor MP1, a P-type transistor MP2 and a logic Schmitt trigger SMIT; The logic Schmitt trigger SMIT is connected between the output terminal VOUT and the ground terminal GND, the output terminal of which outputs the PFM signal, and the input terminal is connected to the drain of the P-type transistor MP2 and the N-type transistor MN4; the gate of the P-type transistor MP2, the drain of the P-type transistor MP1 and the N-type transistor MN1 are connected, the source of the P-type transistor MP0, the source of the P-type transistor MP1 and the source of the P-type transistor MP2 are connected to the output terminal VOUT; the gate of the N-type transistor MN4, the gate and drain of the N-type transistor MN2, the gate of the N-type transistor MN5, and the gate of the N-type transistor MN3 are connected to the reference voltage VRE generated by the bias current IB F0 terminal; the source of the N-type transistor MN2, the source of the N-type transistor MN3 and the source of the N-type transistor MN4 are connected to the ground terminal GND, the drain of the N-type transistor MN3 is connected to the source of the N-type transistor MN5, the source of the N-type transistor MN0 and the source of the N-type transistor MN1; the gate of the N-type transistor MN1 is connected to VFB, and the gate of the N-type transistor MN0 is connected to VREF; the drain of the N-type transistor MN5, the gate and drain of the P-type transistor MP0, the drain of the N-type transistor MN0 and the gate of the P-type transistor MP1 are connected; the drain of the P-type transistor MP1, the gate of the N-type transistor MN2 and the drain of the N-type transistor MN1 are connected.
3. The comparator circuit for an ultra-low input voltage DCDC boost device according to claim 1, characterized in that: The voltage divider module includes a feedback resistor R1 and a feedback resistor R2, which are connected in series between the output terminal VOUT and the ground terminal GND, and are used to generate the divided voltage VFB.
4. The comparator circuit for an ultra-low input voltage DCDC boost device according to claim 1, characterized in that: The boost system switch drive control module includes a voltage zero-crossing detection comparator unit ZCDCMP powered by the output terminal VOUT, a zero-crossing detection logic control unit ZCDCTRL, a current-limiting detection comparator unit OCLCMP, a switch drive logic control unit DRIVER, a current-limiting detection logic control unit OCLCTRL and an oscillator unit OSC; wherein, The oscillator unit OSC receives the enable control signal PFM and outputs a fixed-cycle clock signal CLK to supply to the switch drive logic control unit DRIVER of the subsequent stage; The bias current unit IBIAS provides a bias current IB for the zero-crossing detection comparator unit ZCDCMP and the current-limiting detection comparator unit OCLCMP; the bandgap reference unit BANDGAP provides a voltage VB for the current-limiting detection comparator unit OCLCMP; the negative input terminal of the zero-crossing detection comparator unit ZCDCMP is connected to the output terminal VOUT; The boost module includes an inductor L0, a P-type transistor Q1, an N-type transistor Q2, an N-type transistor Q3 and a resistor R3; the external input voltage VIN is connected to one end of the inductor L0, and the other end of the inductor L0 is connected to the connection point of the drains of the P-type transistor Q1 and the N-type transistor Q2; the connection point of the drains of the P-type transistor Q1 and the N-type transistor Q2 is the SW signal terminal; the source of the P-type transistor Q1 is connected to the output terminal VOUT, and the source of the N-type transistor Q2 is connected to the ground terminal GND; The gate of the N-type transistor Q3 is connected to the gate of the N-type transistor Q2, the source thereof is connected to the ground terminal GND through the resistor R3, and the drain thereof is connected to the drain of the N-type transistor Q2; the connection point between the source thereof and the resistor R3 is the VS signal terminal; The positive input terminal of the zero-crossing detection comparator unit ZCDCMP is connected to the SW signal terminal; The zero-crossing detection comparator unit ZCDCMP compares the voltage of the SW signal terminal with the voltage of the output terminal VOUT, and outputs a ZCD signal; the zero-crossing detection logic control unit ZCDCTRL receives the ZCD signal and outputs a PZCD signal; the current-limiting detection comparator unit OCLCMP compares the voltage of the VS signal with the voltage of the output terminal VB, and outputs an OCL signal; the current-limiting detection logic control unit OCLCTRL receives the OCL signal and outputs a NOCL signal; the switch drive logic control unit DRIVER receives the clock signal CLK, the PZCD signal and the NOCL signal to control the gates of the P-type transistor Q1 and the N-type transistor Q2.