Network-on-chip structure, processor and electronic equipment
By setting up boundary routers in each bare core structure router and enabling communication between the bare core groups through these routers, the problem of data transmission between multiple bare core structures is solved, and data transmission across bare core structures without deadlock is achieved.
Patent Information
- Application Number
- CN202421265635.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-04
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2034-06-04
AI Technical Summary
The prior art is prone to deadlock problems in data transmission between multiple die structures. The X-Y routing strategy can only solve the deadlock problem inside the die structure and cannot effectively solve the deadlock between multiple die structures.
At least one boundary router is provided in each core structure router, and communication between core groups is achieved through these boundary routers. The two die structures in each die group are interconnected by a pair of proprietary boundary routers, ensuring that data transmission does not pass through other die structures, thereby avoiding deadlocks.
The interconnection between the die sets is achieved through a proprietary boundary router, ensuring that data transmission across the die structure does not need to pass through other die structures, thereby avoiding the occurrence of deadlock problems.
Smart Images
Figure CN222621040U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of computers, and in particular to an on-chip network structure, a processor and an electronic device. Background Art
[0002] On-chip network is a key technology of multi-processor architecture. It is the interconnection path and communication network inside the processor, responsible for message transmission, and is the basis for processor collaboration.
[0003] At present, the on-chip network includes multiple bare core structures, each of which is composed of multiple nodes arranged in an array. The nodes are processor cores, caches or other IP cores. Each node is associated with a router, and the nodes communicate through the router. When transmitting data between multiple bare core structures, an XY routing strategy can be used to reduce the probability of deadlock. The XY routing strategy means that data can only be transmitted between routers arranged in an array in the bare core structure in a horizontal and vertical transmission direction. When data is transmitted between any two routers in the bare core structure, a change in the transmission direction will occur at most once. When there is a knotted ring between the paths of multiple messages, the transmission of the message is blocked, and deadlock will occur. However, the XY routing strategy in the related art can only solve the deadlock problem during internal transmission of the bare core structure. For transmission between multiple bare core structures, there is still a high probability of deadlock. Utility Model Content
[0004] In view of the above problems, embodiments of the present utility model are proposed to provide a network-on-chip structure, a processor, and an electronic device that overcome the above problems or at least partially solve the above problems.
[0005] In a first aspect, an embodiment of the utility model discloses a network-on-chip structure, the network-on-chip structure comprising:
[0006] A plurality of bare core structures; the bare core structure comprises a plurality of routers arranged in an array; each of the bare core structures comprises at least one border router; any two bare core structures constitute a bare core group;
[0007] For any bare core group, a border router included in one bare core structure itself is connected to a border router included in another bare core structure itself in the bare core group to realize communication between the two bare core structures in the bare core group; different bare core groups use different border routers when communicating.
[0008] In a second aspect, an embodiment of the utility model discloses a processor, wherein the processor includes an on-chip network structure.
[0009] In a third aspect, an embodiment of the utility model further discloses an electronic device, comprising a processor.
[0010] In an embodiment of the utility model, at least one border router can be set in the router included in each bare core structure, and for any bare core group, a border router included in one bare core structure itself is connected to a border router included in another bare core structure itself in the bare core group to realize communication between the two bare core structures in the bare core group, and different bare core groups use different border routers for communication, and the transmission between the routers inside the bare core structure still follows the XY routing strategy. Under such a structural design, each two bare core structures can be interconnected through a pair of dedicated border routers, and data transmission does not need to pass through other bare core structures, so that data transmission across bare core structures will not cause deadlock problems. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 It is a schematic diagram of a network-on-chip structure provided by an embodiment of the utility model;
[0012] Figure 2 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;
[0013] Figure 3 It is a schematic diagram comparing transmission directions of on-chip networks provided by a related technology;
[0014] Figure 4 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;
[0015] Figure 5 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;
[0016] Figure 6 It is a partial structural diagram of an on-chip network structure provided by an embodiment of the utility model;
[0017] Figure 7 is a schematic diagram of a processor provided by an embodiment of the utility model;
[0018] Figure 8 It is a schematic diagram of an electronic device provided by an embodiment of the utility model. DETAILED DESCRIPTION
[0019] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.
[0020] refer to Figure 1 , which shows a schematic diagram of an on-chip network structure provided by an embodiment of the utility model, including: multiple bare core structures 10; the bare core structure 10 includes a processor core (or other IP), and multiple array-arranged routers 11, each processor core is associated with a router; the router 11 included in each bare core structure 10 has at least one border router 12; any two bare core structures 10 constitute a bare core group; for any bare core group, a border router 12 included in one bare core structure 10 itself is connected to a border router 12 included in another bare core structure 10 in the bare core group, so as to realize communication between the two bare core structures 10 in the bare core group; different bare core groups use different border routers 12 when communicating.
[0021] In practical applications, although the multiple processor cores in a multi-core processor chip each execute their own code, data needs to be shared and synchronized between the processor cores. Therefore, the hardware structure of the multi-core processor must support efficient inter-core communication, and the performance of the on-chip communication structure will directly affect the performance of the processor.
[0022] Therefore, the Network on Chip (NoC) aims to solve the communication problem within the multi-core processor. The NoC is an integrated circuit on a communication subsystem based on a router network. The NoC is a packet switching network based on routers between systems on chip. The NoC technology draws on the interconnection network structure of parallel computers, integrating a large number of computing resources and an on-chip communication network connecting these resources on a single chip. Each processor core has an independent router and its private cache, and is connected together through an on-chip communication network. The processor cores use a message communication mechanism, and use routers and packet switching technology to replace the on-chip bus of related technologies to complete the communication task, thereby solving various bottleneck problems caused by bus interconnection in related technologies.
[0023] After determining the topology of the on-chip network, the routing algorithm can be used to determine the path that the message takes through the network to reach the destination. The goal of the routing algorithm is to evenly distribute traffic in the paths provided by the network topology, avoid hot spots, minimize contention, and improve network latency and throughput. While achieving these performance goals, design constraints must be observed to avoid critical paths that are too long and too large in area.
[0024] The bare core structure is also called a chiplet, which refers to a pre-manufactured chip with specific functions that can be combined and integrated. The bare core structure can divide the processor into multiple independent dies, and then manufacture large chips through advanced packaging technology. This technology can reduce the manufacturing cost of large-scale chips, improve the reuse of a single die, and reduce development costs.
[0025] Specifically, Figure 1 The figure shows a network-on-chip structure including two bare core structures 10, each bare core structure 10 includes a router 11 of 4×4 specification, and an XY routing strategy can be used to solve the deadlock problem for data transmission between the routers 11 included in each bare core structure 10. That is, the XY routing strategy avoids the occurrence of deadlock by limiting the transmission of data to be carried out along the longitudinal and transverse transmission directions.
[0026] For example, refer to Figure 2 , in a bare core structure 10, an XY routing strategy is implemented. Assuming that data is transmitted from router A to router B, there are two transmission paths: transmission path m1, first horizontal transmission and then vertical transmission; transmission path m2, first vertical transmission and then horizontal transmission. Regardless of the transmission path, the transmission direction will change (turn) at most once, thus avoiding the deadlock problem.
[0027] However, the XY routing strategy can only solve the deadlock problem during transmission within the bare core structure 10, and cannot avoid the deadlock problem for transmission between multiple bare core structures 10. The deadlock problem refers to the blocking of message transmission when there are knotted loops between the paths of multiple messages.
[0028] For example, refer to Figure 3 , data is transmitted between two bare core structures 10, and the XY routing strategy is executed. Assuming that data is exchanged between router C in one bare core structure 10 and router D in another bare core structure 10, the transmission path includes n1 and n2, which makes the data transmission produce a circular dependency, resulting in a deadlock problem, thereby blocking the data transmission.
[0029] In order to solve the above problems, in the embodiment of the present utility model, based on Figure 1 design, any two bare core structures 10 in all bare core structures 10 in the on-chip network can form a bare core group ( Figure 1A bare core group is shown in the figure), each bare core structure 10 includes a router 11 which may have at least one border router 12, and the border router 12 is used for data transmission between bare core structures 10, that is, the routers in the bare core structure 10 except the border router 12 can only perform data transmission within the bare core structure 10, while the border router 12 can perform data transmission across the bare core structure 10. In addition, for a bare core group, a border router 12 included in one bare core structure 10 itself is connected to a border router 12 included in another bare core structure 10 in the bare core group, so as to realize the communication between the two bare core structures 10 in the bare core group, and the border routers 12 used for communication between different bare core groups are different.
[0030] Based on the above design, it can be ensured that there is only one pair of interconnected border routers 12 between any two bare core structures 10. Every two bare core structures 10 can be interconnected through a pair of dedicated border routers 12, so that data transmission does not need to pass through other bare core structures. In this way, data transmission across bare core structures will not cause deadlock problems.
[0031] For example, refer to Figure 4 For the communication between two bare core structures 10, assuming that the router E in one bare core structure 10 sends data to the router F in another bare core structure 10, the transmission paths include f1 and f2 (there are two other paths not shown), and the transmission is realized based on a pair of dedicated boundary routers 12 between the two bare core structures 10, thereby avoiding the occurrence of deadlock problems.
[0032] It should be noted that the number of routers included in each bare core structure may also be n×m, and n and m may be different, which is not limited in the embodiment of the present utility model.
[0033] In summary, the solution of the utility model can set at least one border router in the router included in each bare core structure, and for any bare core group, a border router included in one bare core structure itself is connected to a border router included in another bare core structure itself in the bare core group, so as to realize the communication between the two bare core structures in the bare core group, and different bare core groups use different border routers for communication, and the transmission between the routers inside the bare core structure still follows the XY routing strategy. Under such a structural design, each two bare core structures can be interconnected through a pair of dedicated border routers, and data can be transmitted without passing through other bare core structures, so that the data transmission across the bare core structures will not cause deadlock problems.
[0034] Optional, see Figure 1 , the number of edge routers 12 included in each bare core structure 10 is m-1; m is the number of bare core structures 10.
[0035] Based on this limiting rule, Figure 1 In the case of two bare core structures 10 , m=2, and the number of border routers 12 included in each bare core structure 10 is 2−1=1.
[0036] Reference Figure 5 , Figure 5 The on-chip network including four bare core structures 10 is shown, then m=4, and the number of border routers 12 included in each bare core structure 10 is 4-1=3. It can be seen that any two bare core structures 12 are still interconnected through a pair of dedicated border routers 12, and different bare core groups use different border routers 12 for communication, thereby solving the deadlock problem.
[0037] exist Figure 5 In the figure, assuming that a router G in a bare chip structure 10 transmits data to a router H in another bare chip structure 10, the achievable transmission paths include but are not limited to path h1; assuming that a router I in a bare chip structure 10 transmits data to a router G in another bare chip structure 10, the achievable transmission paths include but are not limited to path h2.
[0038] Optional, see Figure 1 and Figure 5 The bare core structure 10 includes routers 11 arranged in an array to form a grid structure. The routers 11 are located at the corner points of the grid in the grid structure, so that the data forwarded by the routers 11 are transmitted horizontally or vertically in the grid structure.
[0039] Specifically, refer to Figure 6 , which shows a partial structural diagram of an on-chip network structure, which shows a grid structure 50 formed by four routers 11 in the on-chip network structure. The grid structure 50 has four corner points 51, and a corresponding router 11 is arranged at each corner point.
[0040] In an embodiment of the utility model, the array-arranged routers 11 included in the bare core structure 10 can be formed into a grid structure, and each router 11 can be placed at a corner point of the grid in the grid structure, so that the horizontal transmission direction and the vertical transmission direction are realized in the bare core structure 10, that is, the transmission direction between the routers in the bare core structure is only horizontal and vertical, which provides a structural basis for the implementation of the XY routing strategy.
[0041] Optional, see Figure 1 and Figure 5 , the border router 12 is located at the periphery of the bare core structure 10 .
[0042] In the embodiment of the present utility model, preferably, the border router 12 can be located at the periphery of the bare core structure 10, so as to reduce the communication distance between the border routers.
[0043] Of course, the border router can also be located at any router position in the bare core structure. As long as it is ensured that for any bare core group, a border router included in one bare core structure itself is connected to a border router included in another bare core structure itself in the bare core group, and the border routers used for communication between different bare core groups are different, the deadlock problem can be solved.
[0044] Optionally, the border router is located at an endpoint position on the periphery of the bare core structure.
[0045] In the embodiment of the present invention, preferably, the border router is located at an end point of the periphery of the bare core structure, so as to ensure that the distance between two interconnected border routers is the shortest.
[0046] Optionally, the number of bare core structures is an even number.
[0047] In the embodiment of the present invention, preferably, the number of bare core structures is an even number, so that the on-chip network structure can form a symmetrical structure that is easy to process and produce. Of course, the number of bare core structures can also be an odd number, and the embodiment of the present invention does not limit this.
[0048] Optional, see Figure 5 When the bare core structure 10 includes a plurality of edge routers 12 , the plurality of edge routers 12 are arranged in series.
[0049] In the embodiment of the utility model, when the bare core structure 10 includes a plurality of boundary routers 12, the plurality of boundary routers 12 can be arranged continuously, so that the boundary routers can be centrally arranged, thereby facilitating processing and production.
[0050] In addition, for the network-on-chip structure of the embodiment of the utility model, only a single virtual channel is used, that is, Figure 1 , Figure 5 The physical channel reflected by the connection between routers in the on-chip network structure is the virtual channel. The virtual channel is a virtual channel divided from the physical channel by time-division multiplexing. It has an independent buffer and does not interfere with each other, but shares a physical link. From the perspective of the data packet, there are multiple virtual channels between the two routers, but the actual physical links are the same. One of the purposes of the utility model is to solve the deadlock problem by designing the position of the border router under the premise of using only a single virtual channel. A single virtual channel can reduce power consumption, reduce area, and reduce design complexity. By constraining the number, position, and connection relationship of the border routers, the purpose of deadlock-free under a single channel is achieved.
[0051] Reference Figure 7 , which shows a schematic diagram of a processor provided by an embodiment of the utility model, and the processor includes the on-chip network structure provided by the above embodiment.
[0052] Reference Figure 8 , which shows a schematic diagram of an electronic device provided by an embodiment of the utility model, the electronic device may include Figure 7 processor.
[0053] In summary, the solution of the utility model can set at least one border router in the router included in each bare core structure, and for any bare core group, a border router included in one bare core structure itself is connected to a border router included in another bare core structure itself in the bare core group, so as to realize the communication between the two bare core structures in the bare core group, and different bare core groups use different border routers for communication, and the transmission between the routers inside the bare core structure still follows the XY routing strategy. Under such a structural design, each two bare core structures can be interconnected through a pair of dedicated border routers, and data can be transmitted without passing through other bare core structures, so that the data transmission across the bare core structures will not cause deadlock problems.
[0054] Those skilled in the art will readily come up with other embodiments of the present invention after considering the specification and practicing the utility model disclosed herein. The present invention is intended to cover any variation, use or adaptation of the present invention, which follows the general principles of the present invention and includes common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.
[0055] It should be understood that the present invention is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.
Claims
1. A network-on-chip structure, characterized in that: The network-on-chip structure comprises: A plurality of bare core structures; the bare core structure comprises a plurality of routers arranged in an array; each of the bare core structures comprises at least one border router; any two bare core structures constitute a bare core group; For any bare core group, a border router included in one bare core structure itself is connected to a border router included in another bare core structure itself in the bare core group to realize communication between the two bare core structures in the bare core group; different bare core groups use different border routers when communicating.
2. The network-on-chip structure according to claim 1, characterized in that: The number of edge routers included in each bare core structure is m-1, where m is the number of bare core structures.
3. The network-on-chip structure according to claim 1, characterized in that: The border router is located at a peripheral position of the bare core structure.
4. The network-on-chip structure according to claim 1, characterized in that: The bare core structure includes routers arranged in an array to form a grid structure. The routers are located at corner points of the grid in the grid structure, so that data forwarded by the routers are transmitted horizontally or vertically in the grid structure.
5. The network-on-chip structure according to claim 3, characterized in that: The border router is located at an end point of the periphery of the bare core structure.
6. The network-on-chip structure according to claim 1, characterized in that: The number of the bare core structures is an even number.
7. The network-on-chip structure according to claim 1, characterized in that: When the bare core structure includes a plurality of edge routers, the plurality of edge routers are arranged consecutively.
8. A processor, characterized in that: The processor comprises: a network-on-chip structure as described in any one of claims 1-7.
9. An electronic device, characterized in that: The method comprises a processor as claimed in claim 8.