Semiconductor device

Abstract

Some embodiments of the present disclosure describe a semiconductor device having an artificial field plate. The semiconductor device includes a first gallium nitride layer on a substrate, an aluminum gallium nitride layer on the first gallium nitride layer, and a second gallium nitride layer on the aluminum gallium nitride layer. The first and second gallium nitride layers include different types of dopants. The semiconductor device further includes a gate contact structure in contact with the second gallium nitride layer, first and second source / drain contact structures in contact with the aluminum gallium nitride layer, and one or more artificial field plates between the gate contact structure and the first source / drain contact structure. First and second source / drain contact structures are disposed on opposite sides of the gate contact structure. One or more artificial field plates are separated from the first and second source / drain contact structures and on the aluminum gallium nitride layer.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a semiconductor device. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to increase. To meet these demands, the semiconductor industry continues to shrink the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs), and gallium nitride (GaN) high electron mobility transistors (HEMTs). This downsizing increases the complexity of semiconductor manufacturing processes and increases the difficulty of defect control in semiconductor devices. Utility Model Content

[0003] According to some embodiments of the present disclosure, a semiconductor device includes a gate structure on a substrate, a first source / drain region and a second source / drain region, a gate contact structure electrically connected to the gate structure, a first source / drain contact structure and a second source / drain contact structure electrically connected to the first source / drain region and the second source / drain region, respectively, and one or more artificial field plates disposed between the gate contact structure and the first source / drain contact structure. The one or more artificial field plates are electrically separated from the first source / drain contact structure and the second source / drain contact structure.

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a first gallium nitride layer on a substrate, an aluminum gallium nitride layer on the first gallium nitride layer, a second gallium nitride layer on the aluminum gallium nitride layer, a gate contact structure in contact with the second gallium nitride layer, a first source / drain contact structure and a second source / drain contact structure in contact with the aluminum gallium nitride layer, and one or more artificial field plates disposed on the aluminum gallium nitride layer and between the gate contact structure and the first source / drain contact structure. The first and second source / drain contact structures are disposed on opposite sides of the gate contact structure. The one or more artificial field plates are separated from the first source / drain contact structure and the second source / drain contact structure.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a first gallium nitride layer on a substrate, an aluminum gallium nitride layer on the first gallium nitride layer, a second gallium nitride layer on the aluminum gallium nitride layer, a gate contact structure in contact with the second gallium nitride layer, a first source / drain contact structure and a second source / drain contact structure in contact with the aluminum gallium nitride layer, one or more artificial field plates disposed between the gate contact structure and the first source / drain contact structure, a first field plate adjacent to the gate contact structure and disposed between the gate contact structure and the first source / drain contact structure, and a second field plate disposed on the first field plate. The first source / drain contact structure and the second source / drain contact structure are disposed on opposite sides of the gate contact structure. The one or more artificial field plates are separated from the first source / drain contact structure and the second source / drain contact structure. The first field plate and the second field plate are electrically connected to the second source / drain contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Some aspects of the present disclosure are described in the accompanying Figure 1 It is best understood from the following detailed description when read together.

[0007] Figure 1 illustrates a plan view of a gallium nitride (GaN) device with an artificial field plate according to some embodiments;

[0008] Figure 2 illustrates a cross-sectional view of a GaN device with an artificial field plate according to some embodiments;

[0009] Figure 3 A schematic diagram illustrating a GaN device in a circuit context according to some embodiments of the present disclosure;

[0010] Figure 4 is a flow chart of a method for manufacturing a GaN device with an artificial field plate according to some embodiments of the present disclosure;

[0011] Figures 5 to 18 FIG. 1 illustrates plan views and cross-sectional views of a GaN device with an artificial field plate at various stages of its fabrication process according to some embodiments of the present disclosure.

[0012] Illustrative embodiments will now be described with reference to the accompanying drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements.

[0013]

Explanation of symbols

[0014] 100:GaN Device

[0015] 102:Substrate

[0016] 104: Transition layer

[0017] 104A: Nucleation layer

[0018] 104B: Gradient buffer layer

[0019] 104C: Superlattice layer

[0020] 106: first GaN layer

[0021] 108: AlGaN layer

[0022] 108D: Drain region

[0023] 108S: Source region

[0024] 110: Quarantine

[0025] 114D: First S / D contact structure

[0026] 114S: Second S / D contact structure

[0027] 116: Second GaN layer

[0028] 116w: Width

[0029] 116*: Second GaN layer

[0030] 120: Gate contact structure

[0031] 121: Interface layer

[0032] 122: passivation layer

[0033] 124: Nitride layer

[0034] 126: Oxide layer

[0035] 128:ILD layer

[0036] 130: First board

[0037] 130d: Distance

[0038] 130w: Width

[0039] 132: Artificial field board

[0040] 134: Second board

[0041] 134d: Distance

[0042] 136:Metal through hole

[0043] 138A: Third board

[0044] 138B:Metal wiring

[0045] 138d: Distance

[0046] 150: Circuit

[0047] 152: Driver level

[0048] 400:Method

[0049] 410~460: Operation

[0050] 740: Implantation Process

[0051] 2DEG: Two-dimensional electron gas

[0052] d1: first distance

[0053] d2: second distance

[0054] Vss: Source voltage

[0055] V out :Output voltage

[0056] X,Y,Z: axis DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify some embodiments of the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used in some embodiments of the present disclosure, the formation of a first feature on a second feature means that the first feature is formed in direct contact with the second feature. In addition, some embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0058] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used in some embodiments of the present disclosure to describe the relationship of one element or feature to another element or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in some embodiments of the present disclosure may be similarly interpreted accordingly.

[0059] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include the particular feature, structure, or characteristic. In addition, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0060] It should be understood that the phrases or terms in some embodiments of the present disclosure are for the purpose of description rather than limitation, and thus the terms or phrases of the specification will be interpreted by those skilled in the art based on the teachings of some embodiments of the present disclosure.

[0061] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one skilled in the art based on the teachings of some embodiments of the present disclosure.

[0062] Compared to silicon-based power devices, GaN high electron mobility transistor (HEMT) power devices can have lower on-resistance, higher operating frequency, and ultra-high breakdown voltage, thereby achieving better performance. In addition, compared to vertical GaN HEMT power devices, GaN-on-silicon lateral HEMT power devices can have higher integration, lower cost, and easier mass production. However, compared to the device failure rate requirement of about 1 to about 5 ppm for automotive-grade GaN power devices, GaN-on-silicon lateral HEMT power devices can have their challenges, such as high device failure rate (e.g., about 600 to about 800 parts per million (ppm)).

[0063] In lateral GaN power devices, a GaN layer can be grown on a silicon (Si) substrate. Since GaN and Si have different lattice constants, epitaxial growth defects and mismatch defects can be formed in the GaN layer. In addition, metal particles and etching defects can also be introduced in the back-end process. In high-temperature reliability testing, these defects can cause the device to fail after hundreds of hours, thereby reducing the performance of lateral GaN power devices and increasing the failure rate of the device. Various tests, such as wafer acceptance test (WAT), chip probing (CP), and final test (FT), can be implemented to monitor defects in GaN power devices. The dimension of the defect can be about 1μm 2 to about 6 μm 2 Therefore, these defects may not be detected during these tests. Line scanning tools and microscopes can monitor these defects on the intermetal dielectric layer, field plate, and drift region of lateral GaN power devices. However, manufacturing time and cost may increase with line scanning and microscope imaging on each GaN power device.

[0064] Various embodiments disclosed herein provide example methods for forming one or more artificial field plates in lateral GaN HEMT devices and / or other semiconductor devices in integrated circuits (ICs). The GaN device may include a first GaN layer on a substrate, an aluminum gallium nitride (AlGaN) layer on the first GaN, and a second GaN layer on the AlGaN layer. The first and second source / drain (S / D) contact structures of the GaN device may contact the AlGaN layer. The gate contact structure of the GaN device may contact the second GaN layer. The one or more artificial field plates may be located between the gate and the first S / D contact structure and may be separated from the first and second S / D structures. In some embodiments, the one or more artificial field plates may improve the defect detection sensitivity during testing and may help evaluate the impact of defects in the intermetallic dielectric layer and the drift region on device performance. In some embodiments, the one or more artificial field plates may improve the electric field uniformity between the gate and the first S / D contact structure and improve device performance. In some embodiments, the one or more artificial field plates may reduce GaN device manufacturing costs and improve defect control.

[0065] Figure 1 A plan view of a GaN device 100 with one or more artificial field plates is shown in accordance with some embodiments. Figure 2 A cross-sectional view of a GaN device 100 with one or more artificial field plates is shown in accordance with some embodiments. Figure 3 A schematic diagram of a GaN device 100 in the context of a circuit 150 is shown according to some embodiments of the present disclosure. Figures 1 to 3 A single GaN HEMT transistor is shown, but the GaN device 100 may have any number of GaN HEMT transistors. In addition, the GaN device 100 may be incorporated into an IC using other structural components such as conductive vias, wires, dielectric layers, and interconnects, which are not shown for simplicity. Unless otherwise noted, the discussion of the elements of the GaN device 100 with the same annotations applies to each figure. And similar reference numbers generally represent identical, functionally similar, and / or structurally similar elements.

[0066] refer to Figures 1 to 3 , the GaN device 100 may include a substrate 102, a transition layer 104, a first GaN layer 106, an AlGaN layer 108, an isolation region 110, a first S / D contact structure 114D and a second S / D contact structure 114S, a second GaN layer 116, and a gate contact structure 120. In some embodiments, the GaN device 100 may further include a passivation layer 122, a nitride layer 124, an oxide layer 126, an inter-layer dielectric (ILD) layer 128, a first field plate 130, a second field plate 134 and a third field plate 138A, an artificial field plate 132, a metal via 136, and a metal wiring 138B.

[0067] refer to Figure 2, the GaN device 100 may be fabricated on a substrate 102. As used in some embodiments of the present disclosure, the term "substrate" describes a material on which subsequent material layers are added. The substrate 102 may be patterned. The material added to the substrate 102 may be patterned or may remain unpatterned. The substrate 102 may be a bulk semiconductor wafer or a top semiconductor layer (not shown) of a semiconductor-on-insulator (SOI) wafer. In some embodiments, the substrate 102 may include a crystalline semiconductor layer whose top surface is parallel to the (111) crystal plane. The substrate 102 may be made of a semiconductor material such as, but not limited to, silicon (Si). In some embodiments, the substrate 102 may include (i) an elemental semiconductor, such as germanium (Ge); (ii) a compound semiconductor, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium aluminum arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) a combination thereof. Alternatively, the substrate 102 may be made of a non-conductive material, such as a glass wafer, a sapphire wafer, and a plastic material.

[0068] In some embodiments, Figure 2 As shown in FIG. 1 , the transition layer 104 may include a nucleation layer 104A, a gradient buffer layer 104B, and a superlattice layer 104C. In some embodiments, the nucleation layer 104A may include an epitaxially grown layer of aluminum nitride (AlN) on the substrate 102. The nucleation layer 104A may facilitate the formation of subsequent AlGaN and GaN layers. In some embodiments, the nucleation layer 104A may have a thickness ranging from about 100 to about 100. to about In some embodiments, the gradient buffer layer 104B may include Al 1-x Ga xN, wherein x may be in the range of about 0 to about 1. In some embodiments, the gradient buffer layer 104B may include an AlGaN layer having a high Al concentration formed on the nucleation layer 104A and an AlGaN layer having a lower Al concentration formed thereon. The gradient buffer layer 104B may minimize the lattice mismatch between the subsequently grown GaN layer and the substrate 102. In some embodiments, the gradient buffer layer 104B may have a thickness ranging from about 300 nm to about 1500 nm. In some embodiments, the superlattice layer 104C may include a carbon-doped GaN layer for the subsequently grown first GaN layer 106. In some embodiments, the superlattice layer 104C may have a thickness ranging from about 1 μm to about 2 μm. In some embodiments, the transition layer 104 may include any number of alternating layers of AlN, AlGaN, and GaN. In some embodiments, the transition layer 104 may have the same crystal orientation as the top surface of the substrate 102. In some embodiments, the transition layer 104 may have a total thickness ranging from about 3 μm to about 6 μm.

[0069] refer to Figure 2 , the first GaN layer 106 may be disposed on the transition layer 104. In some embodiments, the first GaN layer 106 may be an epitaxial growth layer of GaN having a thickness of about 1 μm to about 2 μm. In some embodiments, the first GaN layer 106 may be doped with n-type dopants such as carbon and Si.

[0070] refer to Figure 2 , the AlGaN layer 108 may be disposed on the first GaN layer 106. In some embodiments, the AlGaN layer 108 may be epitaxially grown on the first GaN layer 106. Alternatively, the material of the AlGaN layer 108 may be replaced with AlInN. In some embodiments, the AlGaN layer 108 may have a thickness between about 10 nm and about 50 nm. In some embodiments, the AlGaN layer 108 may be Al 1- x Ga x N, and the value of x may be in the range of about 0.8 to about 0.85, or about 80% to about 85%. In some embodiments, the AlGaN layer 108 may include a source region 108S, a drain region 108D, and a channel region between the source region 108S and the drain region 108D.

[0071] The interface between the AlGaN layer 108 and the first GaN layer 106, or the AlGaN / GaN heterojunction, can induce a two-dimensional electron gas (2DEG) 2DEG to form in the upper region of the first GaN layer 106. In some embodiments, the two-dimensional electron gas 2DEG can be a polarization-induced sheet charge formed at the interface of the AlGaN layer and the GaN layer. Both piezoelectric polarization and spontaneous polarization effects contribute to the formation of the two-dimensional electron gas 2DEG. The two-dimensional electron gas 2DEG in the GaN device 100 can have high electron mobility, and for this reason, the GaN device 100 can be referred to as a "GaN HEMT device".

[0072] In some embodiments, the second GaN layer 116 may include a p-type GaN (pGaN) layer that serves as a gate structure for the GaN device 100. The pGaN layer may be deposited and patterned to form the second GaN layer 116. In some embodiments, the second GaN layer 116 may have a thickness of about 50 nm to about 200 nm. In some embodiments, the second GaN layer 116 may be doped with a p-type dopant, such as magnesium (Mg). In some embodiments, the doping concentration of the second GaN layer 116 may be about 1×10 18 cm -3 About 1×10 19 cm -3 In some embodiments, the second GaN layer 116 may have a width 116w along the X-axis ranging from about 2 μm to about 3 μm.

[0073] When a voltage is applied to the second GaN layer 116, the polarization effect may cause a two-dimensional electron gas 2DEG to be formed in the first GaN layer 106 directly below the second GaN layer 116, thereby causing the two-dimensional electron gas 2DEG to become continuous along the upper region of the first GaN layer 106. When a voltage exceeding the threshold voltage of the GaN device 100 is applied, the two-dimensional electron gas under the gate may be sufficiently enhanced to conduct current within the first GaN layer 106. In some embodiments, the presence of the AlGaN layer 108 directly below the second GaN layer 116 allows the AlGaN layer 108 to partially or completely control the threshold voltage of the GaN device 100. The threshold voltage, in turn, determines whether the GaN device 100 is turned on in response to the voltage applied to the second GaN layer 116.

[0074] refer to Figure 2The isolation region 110 may cut off the two-dimensional electron gas 2DEG at the AlGaN / GaN heterojunction interface and provide electrical isolation between adjacent GaN HEMT devices and / or adjacent active and passive components (not shown) integrated with or deposited on the substrate 102. The isolation region 110 may include regions of the first GaN layer 106 and the AlGaN layer 108 implanted with oxygen. In some embodiments, the isolation region 110 may have a depth along the Z-axis ranging from about 100 nm to about 1500 nm.

[0075] In some embodiments, the first S / D contact structure 114D and the second S / D contact structure 114S may be ohmic contacts disposed on the AlGaN layer 108. In some embodiments, the first S / D contact structure 114D and the second S / D contact structure 114S may be disposed on opposite sides of the gate contact structure 120. The first S / D contact structure 114D and the second S / D contact structure 114S may be connected to the drain region 108D and the source region 108S of the AlGaN layer 108, respectively. In some embodiments, the first S / D contact structure 114D may be referred to as a "drain contact structure". The second S / D contact structure 114S may be referred to as a "source contact structure". In some embodiments, the first S / D contact structure 114D and the second S / D contact structure 114S may include titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu), nickel (Ni), molybdenum (Mo), platinum (Pt), tantalum (Ta), iridium (Ir), and other suitable conductive materials. The gate contact structure 120 may be an ohmic contact disposed on the second GaN layer 116. In some embodiments, the gate contact structure 120 may include Ti, TiN, Al, Cu, Pt, and other suitable conductive materials.

[0076] In some embodiments, a first distance d1 between the first S / D contact structure 114D and the gate contact structure 120 may be greater than a second distance d2 between the second S / D contact structure 114S and the gate contact structure 120. In some embodiments, the first distance d1 may be in a range of about 15 μm to about 20 μm. The region between the first S / D contact structure 114D and the gate contact structure 120 may be referred to as a "drift region". Manufacturing defects formed in the drift region may not immediately cause device failure, but subsequent device failure in HTRB testing may occur after a certain time (e.g., about 150 hours, about 500 hours). In some embodiments, the second distance d2 may be in a range of about 0.5 μm to about 1 μm. Manufacturing defects formed between the second S / D contact structure 114S and the gate contact structure 120 may cause an electrical short between the S / D and gate contact structures, thereby causing an immediate device failure, which may be easier to detect for various device tests.

[0077] In some embodiments, the passivation layer 122 may be disposed on the AlGaN layer 108 and the second GaN layer 116 to passivate the top surfaces of the AlGaN layer 108 and the second GaN layer 116. In some embodiments, the passivation layer 122 may include an oxide, a nitride, or an oxynitride. In some embodiments, the passivation layer 122 may include aluminum oxide. In some embodiments, the passivation layer 122 may have a thickness ranging from about 150 nm to about 250 nm.

[0078] In some embodiments, the nitride layer 124 may be disposed on the passivation layer 122 and may provide electrical isolation between the gate contact structure 120, the first S / D contact structure 114D, and the second S / D contact structure 114S. In some embodiments, the nitride layer 124 may include silicon nitride or other suitable dielectric materials. In some embodiments, the nitride layer 124 may have a thickness ranging from about 60 nm to about 100 nm.

[0079] In some embodiments, the oxide layer 126 may be disposed on the nitride layer 124 and may provide electrical isolation between the first field plate 130 and the metal via 136. In some embodiments, the oxide layer 126 may include silicon oxide or other suitable dielectric materials. In some embodiments, the oxide layer 126 may have a thickness ranging from about 150 nm to about 250 nm.

[0080] In some embodiments, the ILD layer 128 may be disposed on the oxide layer 126 and may provide electrical isolation between the second field plate 134 and the metal via 136. In some embodiments, the ILD layer 128 may include silicon oxide or other suitable dielectric materials. In some embodiments, the ILD layer 128 may have a thickness ranging from about 1000 nm to about 2000 nm.

[0081] refer to Figure 1 and Figure 2In some embodiments, the first field plate 130 and the one or more artificial field plates 132 may be disposed on the nitride layer 124. In some embodiments, the first field plate 130 and the artificial field plate 132 may be formed in the same process and may include Ti, TiN, or other suitable conductive materials. In some embodiments, the first field plate 130 may have a width 130w ranging from about 2 μm to about 3 μm along the X-axis. In some embodiments, the first field plate 130 may be adjacent to the gate contact structure 120 and disposed between the gate contact structure 120 and the first S / D contact structure 114D. In some embodiments, the distance 130d between the first field plate 130 and the first S / D contact structure 114D may be in the range of about 12 μm to about 18 μm. In some embodiments, the ratio of the distance 130d to the first distance d1 of the drift region may be in the range of about 75% to about 85%. In some embodiments, the first field plate 130 may be electrically connected to the second S / D contact structure 114S to reduce the non-uniform electric field distribution around the gate contact structure 120.

[0082] In some embodiments, the artificial field plate 132 may be uniformly disposed between the first S / D contact structure 114D and the gate contact structure 120 to monitor manufacturing defects formed in the drift region and improve the uniformity of the electric field, thereby improving device performance. In some embodiments, the artificial field plate 132 may be between the second S / D contact structure 114S and the gate contact structure 120. In some embodiments, the artificial field plate 132 may improve the defect detection sensitivity during device testing and may help evaluate the impact of defects in the drift region on the AlGaN layer 108 on device performance. In some embodiments, the artificial field plate 132 may improve the uniformity of the electric field between the gate contact structure 120 and the first S / D contact structure 114D, thereby improving device performance.

[0083] In some embodiments, the artificial field plate 132 may have a thickness ranging from about 0.5 μm 2 to about 10 μm 2 If the pattern size is less than about 0.5 μm 2 If the pattern size is larger than about 10 μm, the defect detection sensitivity may be reduced and the device performance may be reduced. 2 , the artificial field plate 132 can be short-circuited to the adjacent structure.

[0084] In some embodiments, the distance between the artificial field plate 132 and the first S / D contact structure 114D may be in the range of about 1 μm to about 18 μm. If the distance is less than about 1 μm, the artificial field plate 132 may be shorted to the first S / D contact structure 114D. If the distance is greater than about 18 μm, the artificial field plate 132 may be shorted to the gate contact structure 120.

[0085] In some embodiments, the number of artificial field plates 132 may be in the range of about 1 to about 1000. If the number is less than about 1, the artificial field plates 132 may not improve defect detection sensitivity and electric field uniformity. If the number is greater than about 1000, the artificial field plates 132 may be shorted to adjacent structures, and manufacturing costs may increase.

[0086] In some embodiments, the artificial field plate 132 may include p-type GaN in the second GaN layer 116 formed in the same process. In some embodiments, the artificial field plate 132 may include a conductive material in the first S / D contact structure 114D and the second S / D contact structure 114S or the second field plate 134 formed in the same process. In some embodiments, the artificial field plate 132 may include a conductive material such as Al and Cu in the metal wiring 138B formed in the same process.

[0087] refer to Figure 1 and Figure 2In some embodiments, the second field plate 134 may be disposed on the first field plate 130. In some embodiments, the second field plate 134 may include TiN or other conductive materials. In some embodiments, the distance 134d between the second field plate 134 and the first S / D contact structure 114D may be in the range of about 8 μm to about 15 μm. The third field plate 138A may be disposed on the second field plate 134. In some embodiments, the third field plate 138A may include Al, Cu, or other conductive materials. In some embodiments, the distance 138d between the third field plate 138A and the first S / D contact structure 114D may be in the range of about 6 μm to about 10 μm. In some embodiments, the first field plate 130, the second field plate 134, and the third field plate 138A may be connected to the second S / D contact structure 114S via metal vias 136 and may be electrically biased at ground. In some embodiments, the first field plate 130 may be referred to as a "gate field plate (GFP)" because the first field plate 130 may be formed in the same process as the gate contact structure 120. In some embodiments, the second field plate 134 may be referred to as a "TiN field plate (TFP)" because the second field plate 134 may include TiN. In some embodiments, the third field plate 138A may be referred to as a "source field plate (SFP)" because the third field plate 138A may be connected to the second S / D contact structure 114S. In some embodiments, the metal via 136 may include tungsten (W) or other suitable conductive materials. In some embodiments, the metal wiring 138B may be disposed on the ILD layer 128 and formed in the same process as the third field plate 138A. In some embodiments, the metal wiring 138B may include Al, Cu, or other suitable conductive materials. In some embodiments, the metal wiring 138B may be part of an interconnect structure (not shown) of the GaN device 100.

[0088] Figure 3 A schematic diagram of a GaN device 100 in a circuit context according to some embodiments of the present disclosure is shown. The circuit 150 may include the GaN device 100 electrically connected to a driver stage 152 for applying a voltage to a gate terminal (e.g., gate contact structure 120 or second GaN layer 116) of the GaN device 100. In response to the applied voltage reaching a threshold voltage, a source voltage Vss (e.g., ground) at a source terminal (e.g., second S / D contact structure 114S or source region 108S) may be provided as an output voltage V out Appearing at the drain terminal of the GaN device 100 (eg, the first S / D contact structure 114D or the drain region 108D), the load may be connected to the output voltage V out .

[0089] Figure 4 is a flow chart of a method 400 for fabricating a GaN device 100 with an artificial field plate according to some embodiments of the present disclosure. The method 400 may not be limited to the GaN device 100, and may be applied to other devices that would benefit from an artificial field plate. Additional manufacturing operations may be performed between various operations of the method 400, and may be omitted solely for clarity and ease of description. Additional processes may be provided before, during, and / or after the method 400; some embodiments of the present disclosure briefly describe one or more of these additional processes. Furthermore, not all operations may be required to perform the disclosure provided by some embodiments of the present disclosure. Additionally, some of the operations may be performed simultaneously, or may be performed concurrently. Figure 4 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described.

[0090] For ease of explanation, reference will be made to Figures 5 to 18 The example manufacturing process for manufacturing the GaN device 100 shown in FIG. Figure 4 The operations shown in . Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 ,and Fig.17 Cross-sectional views of a GaN device 100 with an artificial field plate are shown at various stages of its fabrication, in accordance with some embodiments. Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.16 ,and Fig.18 A plan view of a GaN device 100 with an artificial field plate is shown at various stages of its fabrication, in accordance with some embodiments. Figures 5 to 18 The components in Figures 1 to 3 The elements in have the same annotations as above.

[0091] refer to Figure 4 , method 400 begins at operation 410 and a process of forming a first GaN layer on a substrate. For example, Figure 5As shown in , a first GaN layer 106 may be formed on a substrate 102. In some embodiments, the substrate 102 may include a crystalline semiconductor layer whose top surface is parallel to the (111) crystal plane. The substrate 102 may be made of a semiconductor material such as Si. In some embodiments, the transition layer 104 may be blanket deposited on the substrate 102 to minimize lattice mismatch and promote subsequent growth of the GaN layer. The first GaN layer 106 may be blanket deposited on the transition layer 104. In some embodiments, the transition layer 104 and the first GaN layer 106 may be blanket deposited by metal oxide chemical vapor deposition (MOCVD) or other suitable deposition methods. In some embodiments, the transition layer 104 and the first GaN layer 106 may be epitaxially grown on the substrate 102. In some embodiments, the transition layer 104 may include a nucleation layer 104A, a gradient buffer layer 104B, and a superlattice layer 104C to gradually increase the gallium concentration, thereby increasing the lattice constant for growing the first GaN layer 106.

[0092] refer to Figure 4 In operation 420, an AlGaN layer is formed on the first GaN layer. For example, Figure 5 As shown in FIG. 1 , an AlGaN layer 108 may be formed on the first GaN layer 106. In some embodiments, the AlGaN layer 108 may be blanket deposited on the first GaN layer 106 by MOCVD or other suitable deposition methods. In some embodiments, the AlGaN layer 108 may be epitaxially grown on the first GaN layer 106. In some embodiments, the AlGaN layer 108 may be AlGaN. 1-x Ga x N, and the value of x may be in the range of about 0.8 to about 0.85, or about 80% to about 85%. The interface between the AlGaN layer 108 and the first GaN layer 106, or the AlGaN / GaN heterojunction, may introduce a two-dimensional electron gas 2DEG in the upper region of the first GaN layer 106 through piezoelectric polarization and spontaneous polarization effects.

[0093] refer to Figure 4 In operation 430, a second GaN layer is formed on the AlGaN layer. For example, Figure 5 and Figure 6As shown in , a second GaN layer 116* may be formed on the AlGaN layer 108. In some embodiments, the second GaN layer 116* may be blanket deposited on the AlGaN layer 108 by chemical vapor deposition (CVD), MOCVD, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma CVD (HDPCVD), atomic layer deposition (ALD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or other suitable deposition methods. In some embodiments, the second GaN layer 116* may be epitaxially grown on the AlGaN layer 108. In some embodiments, the second GaN layer 116* may have a dopant of a different type than the dopant of the first GaN layer 106. For example, the first GaN layer 106 may include n-type dopants such as carbon and Si. The second GaN layer 116* may include a p-type dopant, such as Mg. In some embodiments, the doping concentration of the second GaN layer 116 may be about 1×10 18 cm -3 About 1×10 19 cm -3 within the range.

[0094] In some embodiments, the blanket deposited second GaN layer 116* may be patterned and etched to form the second GaN layer 116, such as Figure 7 and Figure 8 In some embodiments, the second GaN layer 116 may have a width 116w ranging from about 2 μm to about 3 μm along the X-axis. After forming the second GaN layer 116, a passivation layer 122 may be formed, such as Figure 7 and Figure 8 In some embodiments, as Figure 7As shown in , an interface layer 121 may be formed on the AlGaN layer 108 and the second GaN layer 116 to facilitate the formation of a passivation layer 122. In some embodiments, the passivation layer 122 may be blanket deposited on the AlGaN layer 108 and the second GaN layer 116 by CVD, ALD, PECVD, spin coating, or other suitable deposition methods. In some embodiments, the passivation layer 122 may include an oxide, a nitride, or an oxynitride to passivate the top surface of the AlGaN layer 108 and the second GaN layer 116. In some embodiments, the passivation layer 122 may include aluminum oxide. After forming the passivation layer 122, an implantation process 740 may be performed to form the isolation region 110, such as Figure 7 and Figure 8 . In some embodiments, the implantation process 740 may implant oxygen into the AlGaN layer 108 and the first GaN layer 106. In some embodiments, the patterning process may define the isolation region 110 for the implantation process 740, and a mask layer (not shown) may be formed on the passivation layer 122 to protect the region outside the isolation region 110. In some embodiments, the isolation region 110 may have a depth along the Z-axis ranging from about 100 nm to about 1500 nm.

[0095] refer to Figure 4 In operation 440, first and second S / D contact structures are formed in contact with the AlGaN layer. Fig. 9 and Fig.10 As shown in , a first S / D contact structure 114D and a second S / D contact structure 114S in contact with the AlGaN layer 108 may be formed. In some embodiments, the patterning process may use a photoresist mask, a hard mask, or a combination thereof to define the positions of the first S / D contact structure 114D and the second S / D contact structure 114S. The etching process may form openings in the passivation layer 122 and / or the AlGaN layer 108 to expose the AlGaN layer 108. A conductive material may be deposited in the openings to form ohmic contacts between the AlGaN layer 108 and the first S / D contact structure 114D and the second S / D contact structure 114S. In some embodiments, the first S / D contact structure 114D and the second S / D contact structure 114S may have a T-shape, such as Figure 2 and Fig.11. In some embodiments, the first S / D contact structure 114D and the second S / D contact structure 114S may include a metal or a metal alloy formed by a plating process, such as electroplating and electroless plating. In some embodiments, the first S / D contact structure 114D and the second S / D contact structure 114S may include a multi-layer metal stack formed by a multi-step deposition process. In some embodiments, the first S / D contact structure 114D and the second S / D contact structure 114S may include a metal, for example, Ti, TiN, Al, Cu, Ni, Mo, Pt, Ta, Ir, or a combination thereof.

[0096] In some embodiments, a nitride layer 124 may be formed after forming the first S / D contact structure 114D and the second S / D contact structure 114S. Fig.11 and Fig.12 . In some embodiments, the nitride layer 124 may be blanket deposited on the passivation layer 122 and the first S / D contact structure 114D and the second S / D contact structure 114S by CVD, ALD, or other suitable deposition methods. In some embodiments, the nitride layer 124 may include silicon nitride or other suitable dielectric materials. In some embodiments, the nitride layer 124 may have a thickness ranging from about 60 nm to about 100 nm.

[0097] refer to Figure 4 In operation 450, a gate contact structure is formed on the second GaN layer. For example, Fig.13 and Fig.14 As shown in , a gate contact structure 120 may be formed on the second GaN layer 116. In some embodiments, the patterning process may use a photoresist mask, a hard mask, or a combination thereof to define the gate contact structure 120. The etching process may form an opening in the nitride layer 124 and the passivation layer 122 to expose the second GaN layer 116. A conductive material may be deposited in the opening and in contact with the second GaN layer 116 to form the gate contact structure 120.

[0098] refer to Figure 4 In operation 460, one or more artificial field plates are formed between the gate contact structure and the first S / D contact structure. Fig.13 and Fig.14As shown in , the first field plate 130 and the artificial field plate 132 may be formed between the gate contact structure 120 and the first S / D contact structure 114D. In some embodiments, the first field plate 130 and the artificial field plate 132 may be defined in the same patterning process as the gate contact structure 120. After depositing the conductive material and removing the photoresist mask and the hard mask, the gate contact structure 120 in contact with the second GaN layer 116 may be formed. The first field plate 130 and the artificial field plate 132 may be formed on the nitride layer 124 between the gate contact structure 120 and the first S / D contact structure 114D. In some embodiments, the artificial field plate 132 may be formed between the gate contact structure 120 and the second S / D contact structure 114S (not shown). In some embodiments, the gate contact structure 120, the first field plate 130, and the artificial field plate 132 may include Ti, TiN, Al, Cu, Ni, Mo, Pt, Ta, Ir, or other suitable conductive materials.

[0099] In some embodiments, the artificial field plate 132 may be uniformly disposed between the first S / D contact structure 114D and the gate contact structure 120 to monitor manufacturing defects formed in the drift region and improve the electric field uniformity, thereby improving device performance. In some embodiments, the artificial field plate 132 may improve defect detection sensitivity during device testing and may help evaluate the impact of defects in the drift region on the AlGaN layer 108 on device performance. In some embodiments, the artificial field plate 132 may improve the electric field uniformity between the gate contact structure 120 and the first S / D contact structure 114D, thereby improving device performance.

[0100] In some embodiments, the artificial field plate 132 may have a thickness ranging from about 0.5 μm 2 to about 10 μm 2 If the pattern size is less than about 0.5 μm 2 If the pattern size is larger than about 10 μm, the defect detection sensitivity may be reduced and the device performance may be reduced. 2 , the artificial field plate 132 can be short-circuited to the adjacent structure.

[0101] In some embodiments, the distance between the artificial field plate 132 and the first S / D contact structure 114D may be in the range of about 1 μm to about 18 μm. If the distance is less than about 1 μm, the artificial field plate 132 may be shorted to the first S / D contact structure 114D. If the distance is greater than about 18 μm, the artificial field plate 132 may be shorted to the gate contact structure 120.

[0102] In some embodiments, the number of artificial field plates 132 may be in the range of about 1 to about 1000. If the number is less than about 1, the artificial field plates 132 may not improve defect detection sensitivity and electric field uniformity. If the number is greater than about 1000, the artificial field plates 132 may be shorted to adjacent structures, and manufacturing costs may increase.

[0103] In some embodiments, the artificial field plate 132 may be formed during the operation of forming the second GaN layer 116, and the artificial field plate 132 may include p-type GaN. In some embodiments, the artificial field plate 132 may be formed during the operation of forming the first S / D contact structure 114D and the second S / D contact structure 114S, and the artificial field plate 132 includes the same conductive material as the first S / D contact structure 114D and the second S / D contact structure 114. In some embodiments, the artificial field plate 132 may be formed during the operation of forming the second field plate 134, and the artificial field plate 132 includes the same conductive material as the second field plate 134. In some embodiments, the artificial field plate 132 may be formed during the operation of forming the metal wiring 138B, and the artificial field plate 132 includes the same conductive material as the metal wiring 138B.

[0104] After forming the artificial field plate 132, an oxide layer 126 may be formed, such as Fig.15 and Fig.16 In some embodiments, the oxide layer 126 may be blanket deposited on the nitride layer 124, the gate contact structure 120, the first field plate 130, and the artificial field plate 132 by CVD, ALD, or other suitable deposition methods. In some embodiments, the oxide layer 126 may include silicon oxide or other suitable dielectric materials.

[0105] After forming the oxide layer 126, the second field plate 134 may be formed. Fig.15 and Fig.16 In some embodiments, the conductive material may be blanket deposited on the oxide layer 126 by MOCVD or other suitable deposition methods. The patterning process may use a photoresist mask, a hard mask, or a combination thereof to define the second field plate 134. The etching process may remove the deposited conductive material outside the second field plate 134.

[0106] The formation of the second field plate 134 may be followed by blanket deposition of the ILD layer 128, formation of the metal via 136, and formation of the third field plate 138A and the metal wiring 138B, the detailed processes of which are omitted only for clarity and ease of description. In some embodiments, the first field plate 130, the second field plate 134, and the third field plate 138A may be electrically connected to the second S / D contact structure 114S via the metal via 136. In some embodiments, the artificial field plate 132 may be physically and electrically separated from the first S / D contact structure 114D and the second S / D contact structure 114S.

[0107] Various embodiments in the present disclosure provide example methods for forming an artificial field plate 132 in a GaN device 100. The GaN device 100 may include a first GaN layer 106 on a substrate 102, an AlGaN layer 108 on the first GaN layer 106, and a second GaN layer 116 on the AlGaN layer 108. A first S / D contact structure 114D and a second S / D contact structure 114S may contact the AlGaN layer 108. A gate contact structure 120 may contact the second GaN layer 116. One or more artificial field plates 132 may be located between the gate contact structure 120 and the first S / D contact structure 114D, and may be physically and electrically separated from the first S / D contact structure 114D and the second S / D contact structure 114S. In some embodiments, the artificial field plate 132 may improve the defect detection sensitivity of the GaN device 100 during testing, and may help evaluate the impact of defects in the drift region on device performance. In some embodiments, the artificial field plate 132 can improve the electric field uniformity between the gate contact structure 120 and the first S / D contact structure 114D and improve device performance. In some embodiments, the artificial field plate 132 can reduce manufacturing costs and improve defect control of the GaN device 100.

[0108] In some embodiments, a semiconductor device includes a gate structure on a substrate, a first source / drain region and a second source / drain (S / D) region, a gate contact structure electrically connected to the gate structure, a first source / drain contact structure and a second source / drain contact structure electrically connected to the first source / drain region and the second source / drain region, respectively, and one or more artificial field plates disposed between the gate contact structure and the first source / drain contact structure. The one or more artificial field plates are electrically separated from the first source / drain contact structure and the second source / drain contact structure. In some embodiments, the first source / drain region is a drain region, and the first source / drain contact structure is electrically connected to the drain region. In some embodiments, a first distance between the first source / drain contact structure and the gate contact structure is greater than a second distance between the second source / drain contact structure and the gate contact structure. In some embodiments, the distance between the first source / drain contact structure and the one or more artificial field plates is in a range of about 1 μm to about 18 μm. In some embodiments, a dimension of each of the one or more artificial field plates is about 0.5 μm. 2 to about 10 μm 2 In some embodiments, the number of the one or more artificial field plates is in the range of about 1 to about 1000. In some embodiments, the semiconductor device further includes an additional field plate. The additional field plate is disposed between the gate contact structure and the first source / drain contact structure and is electrically connected to the second source / drain contact structure, wherein the one or more artificial field plates are disposed between the additional field plate and the first source / drain contact structure. In some embodiments, the one or more artificial field plates include a conductive material in the gate structure, a conductive material in the gate contact structure, a conductive material in the first source / drain contact and the second source / drain contact structure, or a conductive material in the interconnect structure of the semiconductor device.

[0109] In some embodiments, a semiconductor device includes a first gallium nitride (GaN) layer on a substrate, an aluminum gallium nitride (AlGaN) layer on the first gallium nitride layer, a second gallium nitride layer on the AlGaN layer, a gate contact structure in contact with the second gallium nitride layer, a first source / drain contact structure and a second source / drain contact structure in contact with the AlGaN layer, and one or more artificial field plates disposed on the AlGaN layer and between the gate contact structure and the first source / drain contact structure. The first and second source / drain contact structures are disposed on opposite sides of the gate contact structure. The one or more artificial field plates are separated from the first source / drain contact structure and the second source / drain contact structure. In some embodiments, the first source / drain contact structure is a drain contact structure, and the first gallium nitride layer and the second gallium nitride layer include different types of dopants. In some embodiments, a first distance between the first source / drain contact structure and the gate contact structure is greater than a second distance between the second source / drain contact structure and the gate contact structure. In some embodiments, the distance between the first source / drain contact structure and the one or more artificial field plates is in a range of about 1 μm to about 18 μm. In some embodiments, the size of each of the one or more artificial field plates is about 0.5 μm. 2 to about 10 μm 2 In some embodiments, the number of the one or more artificial field plates is in the range of about 1 to about 1000. In some embodiments, the semiconductor device further comprises an additional field plate disposed between the gate contact structure and the first source / drain contact structure and electrically connected to the first source / drain contact structure, wherein the one or more artificial field plates are disposed between the additional field plate and the first source / drain contact structure. In some embodiments, the one or more artificial field plates comprise gallium nitride, titanium nitride, titanium, or copper.

[0110] In some embodiments, a method of manufacturing a semiconductor device includes forming a first gallium nitride layer on a substrate, forming an aluminum gallium nitride layer on the first gallium nitride layer, forming a second gallium nitride layer on the aluminum gallium nitride layer, forming a first source / drain contact structure and a second source / drain contact structure in contact with the aluminum gallium nitride layer, forming a gate contact structure in contact with the second gallium nitride layer, and forming one or more artificial field plates between the gate contact structure and the first source / drain contact structure. The first source / drain contact structure and the second source / drain contact structure are disposed on opposite sides of the second gallium nitride layer. The one or more artificial field plates are separated from the first source / drain contact structure and the second source / drain contact structure. In some embodiments, forming the first source / drain contact structure and the second source / drain contact structure includes forming a first source / drain contact structure having a first distance from the gate contact structure, and forming a second source / drain contact structure having a second distance from the gate contact structure, wherein the first distance is greater than the second distance. In some embodiments, forming one or more artificial field plates includes forming one or more artificial field plates at a distance in a range from about 1 μm to about 18 μm from the first source / drain contact structure. In some embodiments, forming one or more artificial field plates includes forming a first source / drain contact structure having a thickness in a range from about 0.5 μm to about 10 μm. 2 to about 10 μm 2 One or more artificial field plates of a size.

[0111] According to some embodiments of the present disclosure, a semiconductor device includes a first gallium nitride layer on a substrate, an aluminum gallium nitride layer on the first gallium nitride layer, a second gallium nitride layer on the aluminum gallium nitride layer, a gate contact structure in contact with the second gallium nitride layer, a first source / drain contact structure and a second source / drain contact structure in contact with the aluminum gallium nitride layer, one or more artificial field plates disposed between the gate contact structure and the first source / drain contact structure, a first field plate adjacent to the gate contact structure and disposed between the gate contact structure and the first source / drain contact structure, and a second field plate disposed on the first field plate. The first source / drain contact structure and the second source / drain contact structure are disposed on opposite sides of the gate contact structure. The one or more artificial field plates are separated from the first source / drain contact structure and the second source / drain contact structure. The first field plate and the second field plate are electrically connected to the second source / drain contact structure.

[0112] It should be understood that the detailed description section, rather than the summary section, is intended to be used to interpret the scope of the claims. The summary section may set forth one or more but not all possible embodiments of the disclosure contemplated by the inventor, and is therefore not intended to limit the scope of the claims in any way.

[0113] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: A gate structure, a first source / drain region and a second source / drain region on a substrate; a gate contact structure electrically connected to the gate structure; a first source / drain contact structure and a second source / drain contact structure, electrically connected to the first source / drain region and the second source / drain region, respectively; and One or more artificial field plates are disposed between the gate contact structure and the first source / drain contact structure, wherein the one or more artificial field plates are electrically separated from the first source / drain contact structure and the second source / drain contact structure.

2. The semiconductor device according to claim 1, wherein The first source / drain region is a drain region, and the first source / drain contact structure is electrically connected to the drain region.

3. The semiconductor device according to claim 1, wherein: A first distance between the first source / drain contact structure and the gate contact structure is greater than a second distance between the second source / drain contact structure and the gate contact structure.

4. The semiconductor device according to claim 1, wherein: A distance between the first source / drain contact structure and the one or more artificial field plates is in a range of 1 μm to 18 μm.

5. The semiconductor device according to claim 1, wherein A dimension of each of the one or more artificial field plates is within 0.5 μm 2 Up to 10μm 2 within the range.

6. The semiconductor device according to claim 1, wherein: The number of the one or more artificial field plates is in the range of 1 to 1000.

7. The semiconductor device according to claim 1, wherein Further including: An additional field plate is disposed between the gate contact structure and the first source / drain contact structure and is electrically connected to the second source / drain contact structure, wherein the one or more artificial field plates are disposed between the additional field plate and the first source / drain contact structure.

8. A semiconductor device, characterized in that: Include: a first gallium nitride layer on a substrate; an aluminum gallium nitride layer on the first gallium nitride layer; a second gallium nitride layer on the aluminum gallium nitride layer; a gate contact structure in contact with the second gallium nitride layer; a first source / drain contact structure and a second source / drain contact structure in contact with the aluminum gallium nitride layer, wherein the first source / drain contact structure and the second source / drain contact structure are disposed on opposite sides of the gate contact structure; and One or more artificial field plates are disposed on the aluminum gallium nitride layer and between the gate contact structure and the first source / drain contact structure, wherein the one or more artificial field plates are separated from the first source / drain contact structure and the second source / drain contact structure.

9. The semiconductor device according to claim 8, wherein: A first distance between the first source / drain contact structure and the gate contact structure is greater than a second distance between the second source / drain contact structure and the gate contact structure.

10. A semiconductor device, characterized in that: Include: a first gallium nitride layer on a substrate; an aluminum gallium nitride layer on the first gallium nitride layer; a second gallium nitride layer on the aluminum gallium nitride layer; a gate contact structure in contact with the second gallium nitride layer; a first source / drain contact structure and a second source / drain contact structure in contact with the aluminum gallium nitride layer, wherein the first source / drain contact structure and the second source / drain contact structure are disposed on opposite sides of the gate contact structure; One or more artificial field plates are disposed between the gate contact structure and the first source / drain contact structure, wherein the one or more artificial field plates are separated from the first source / drain contact structure and the second source / drain contact structure; a first field plate adjacent to the gate contact structure and disposed between the gate contact structure and the first source / drain contact structure; and A second field plate is disposed on the first field plate, wherein the first field plate and the second field plate are electrically connected to the second source / drain contact structure.

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