Development circuit

Abstract

An embodiment of the utility model provides a development circuit, which relates to the technical field of chips and comprises a power supply circuit, a data acquisition circuit, a program burning interface circuit, a micro-control unit and a display circuit, the power supply circuit is electrically connected with an external power supply and supplies power, and the program burning interface circuit is electrically connected with program burning equipment. The data acquisition circuit is used for acquiring external parameter information and inputting the external parameter information to the micro-control unit, the micro-control unit executes the program code and sends a generated processing result to the display circuit for display, and a hardware development environment based on the micro-control unit is provided for a user.

Description

Technical Field

[0001] The utility model relates to the technical field of chips, in particular to a development circuit. Background Art

[0002] A microcontroller unit (MCU) is an integrated circuit chip that integrates processor, memory, and input / output functions on a single chip. MCU is widely used in embedded systems to control various electronic devices and machines.

[0003] In order to facilitate developers, students and chip enthusiasts to develop software and hardware based on microcontroller units, it is necessary to build a hardware development environment based on microcontroller units. Utility Model Content

[0004] The utility model provides a development circuit to at least solve the problem in the prior art that a hardware development environment for a micro control unit needs to be built.

[0005] The embodiment of the utility model provides a development circuit, including: a power supply circuit, a data acquisition circuit, a program burning interface circuit, a micro control unit and a display circuit;

[0006] The power supply circuit is electrically connected to the micro control unit, the program burning interface circuit, the data acquisition circuit, and the display circuit respectively; the power supply circuit is used to be electrically connected to an external power supply and supply power;

[0007] The data acquisition circuit is electrically connected to the micro control unit; the data acquisition circuit is used to collect external parameter information and input it into the micro control unit;

[0008] The program burning interface circuit is electrically connected to the micro control unit; the program burning interface circuit is used for an external program burning device to burn the program code for processing the parameter information into the micro control unit;

[0009] The micro control unit is electrically connected to the display circuit; it is used to execute the program code and send the generated processing results to the display circuit for display.

[0010] The embodiment of the utility model provides a development circuit, which is electrically connected to an external power supply through a power supply circuit and supplies power, and a program burning interface circuit is electrically connected to a program burning device so that the program burning device burns the program code into a micro control unit, a data acquisition circuit acquires external parameter information and inputs it into the micro control unit, the micro control unit executes the program code, and sends the generated processing result to a display circuit for display, thereby providing users with a hardware development environment based on the micro control unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the description of the embodiments of the utility model will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 It is a structural schematic diagram of a development circuit provided by an embodiment of the utility model;

[0013] Figure 2 It is a specific structural schematic diagram of the development circuit provided by the embodiment of the utility model;

[0014] Figure 3 It is a structural schematic diagram of a program burning interface circuit provided by an embodiment of the utility model;

[0015] Figure 4 It is a structural schematic diagram of a data acquisition circuit provided by an embodiment of the utility model;

[0016] Figure 5 It is a structural schematic diagram of a display circuit provided by an embodiment of the utility model;

[0017] Figure 6 It is a structural schematic diagram of a power supply circuit provided by an embodiment of the utility model;

[0018] Figure 7 It is a structural schematic diagram of a power supply interface unit provided in an embodiment of the utility model;

[0019] Figure 8 It is a structural schematic diagram of a voltage stabilizing unit provided in an embodiment of the utility model;

[0020] Fig. 9 It is a structural schematic diagram of a power supply detection unit provided in an embodiment of the utility model;

[0021] Fig.10 It is a structural diagram of a simulation debugging interface circuit provided by an embodiment of the utility model;

[0022] Fig.11 It is a structural schematic diagram of a mode conversion circuit provided by an embodiment of the utility model;

[0023] Fig.12 It is a structural diagram of a program debugging interface circuit provided by an embodiment of the utility model;

[0024] Fig.13 It is a structural schematic diagram of a first crystal oscillator subcircuit provided in an embodiment of the utility model;

[0025] Fig.14 It is a structural schematic diagram of a second crystal oscillator subcircuit provided in an embodiment of the utility model;

[0026] Fig.15 It is a structural schematic diagram of an alarm circuit provided by an embodiment of the utility model;

[0027] Fig.16 It is a structural schematic diagram of a storage circuit provided by an embodiment of the utility model;

[0028] Fig.17 It is a structural schematic diagram of a key circuit provided by an embodiment of the utility model;

[0029] Fig.18 It is a structural schematic diagram of a wired communication circuit provided by an embodiment of the utility model;

[0030] Fig.19 It is a schematic diagram of the structure of a wireless communication circuit provided by an embodiment of the utility model;

[0031] Fig. 20 It is a schematic diagram of the structure of the reset circuit provided by the embodiment of the utility model;

[0032] Fig.21 It is a structural schematic diagram of an external power supply control circuit provided by an embodiment of the utility model;

[0033] Fig. 22 It is a structural schematic diagram of a power supply filter circuit provided by an embodiment of the utility model;

[0034] Fig.23 It is a schematic diagram of a micro control unit provided in an embodiment of the utility model.

[0035] Reference numerals:

[0036] 10-micro control unit; 11-alarm circuit; 12-storage circuit; 13-button circuit; 131-button sub-circuit; 14-wired communication circuit; 15-wireless communication circuit; 16-reset circuit; 17-external power supply control circuit; 171-relay; 18-power supply filter circuit; 20-data acquisition circuit; 30-program burning interface circuit; 40-display circuit; 50-power supply circuit; 51-power supply interface unit; 52-voltage stabilizing unit; 53-power supply detection unit; 60-simulation debugging interface circuit; 70-mode conversion circuit; 80-program debugging interface circuit; 90-crystal oscillator circuit. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0038] Reference Figure 1 The embodiment of the utility model provides a development circuit, including: a power supply circuit 50, a data acquisition circuit 20, a program burning interface circuit 30, a micro control unit 10 and a display circuit 40; the power supply circuit 50 is electrically connected to the micro control unit 10, the program burning interface circuit 30, the data acquisition circuit 20, and the display circuit 40 respectively; the power supply circuit 50 is used to be electrically connected to an external power supply and supply power; the data acquisition circuit 20 is electrically connected to the micro control unit 10; the data acquisition circuit 20 is used to collect external parameter information and input it to the micro control unit 10; the program burning interface circuit 30 is electrically connected to the micro control unit 10; the program burning interface circuit 30 is used for an external program burning device to burn the program code for processing the parameter information into the micro control unit 10; the micro control unit 10 is electrically connected to the display circuit 40; and is used to execute the program code and send the generated processing result to the display circuit 40 for display.

[0039] It should be noted that the power supply circuit 50 is specifically used to convert the input power supply signal of the external power supply input into a stable output power supply signal output, and the power supply circuit 50 is also specifically used to directly output the input power supply signal of the external power supply input.

[0040] In some embodiments, the voltage value of the input power supply signal of the external power input power supply circuit 50 can be 5V, and the voltage value of the output power supply signal output by the power supply circuit 50 can be 3.3V; the power supply voltage of the micro control unit 10 is 3.3V, and the output power supply signal is used to power the micro control unit 10; the power supply voltage of the program burning interface circuit 30 is 3.3V, and the output power supply signal is used to power the micro control unit 10; the power supply voltage of the data acquisition circuit 20 is 3.3V, and the output power supply signal is used to power the micro control unit 10; the power supply voltage of the display circuit 40 is 5V, and the input power supply signal is used to power the micro control unit 10.

[0041] External parameter information is information of external parameters. The types of external parameters may include temperature, humidity, pressure, air pressure, current, voltage, etc. The external parameter information may be parameter values ​​of external parameters. The processing results may be in the form of graphics, sound, video, text, etc.

[0042] In some embodiments, the program burning interface circuit 30 may also be used to electrically connect to an external emulator and implement signal interaction between the emulator and the micro control unit 10 , as well as to debug the micro control unit 10 .

[0043] In summary, the embodiment of the utility model provides a development circuit, which is electrically connected to an external power supply through a power supply circuit 50 and supplies power, and the program burning interface circuit 30 is electrically connected to a program burning device, so that the program burning device burns the program code into the micro control unit 10, and the data acquisition circuit 20 collects external parameter information and inputs it into the micro control unit 10, and the micro control unit 10 executes the program code to generate a processing result according to the parameter information, and then displays the processing result through the display circuit 40, so as to provide users with a hardware development environment based on the micro control unit 10. Optionally, refer to Figure 2 In some embodiments, the development circuit includes a microcontroller unit 10, a power supply circuit 50, a mode conversion circuit 70, a program debugging interface circuit 80, a program burning interface circuit 30, a simulation debugging interface circuit 60, an external power supply control circuit 17, a data acquisition circuit 20, an alarm circuit 11, a wired communication circuit 14, a crystal oscillator circuit 90, a wireless communication circuit 15, a display circuit 40, a reset circuit 16, a storage circuit 12, a button circuit 13, and a power supply filter circuit 18.

[0044] The power supply circuit 50, the mode conversion circuit 70, the program debugging interface circuit 80, the program burning interface circuit 30, the simulation debugging interface circuit 60, the external power supply control circuit 17, the data acquisition circuit 20, the alarm circuit 11, the wired communication circuit 14, the crystal oscillator circuit 90, the wireless communication circuit 15, the display circuit 40, the reset circuit 16, the storage circuit 12, the key circuit 13, and the power supply filter circuit 18 are respectively electrically connected to the micro control unit 10; the mode conversion circuit 70, the program debugging interface circuit 80, the program burning interface circuit 30, the simulation debugging interface circuit 60, the external power supply control circuit 17, the data acquisition circuit 20, the alarm circuit 11, the wired communication circuit 14, the wireless communication circuit 15, the display circuit 40, the reset circuit 16, the storage circuit 12, the key circuit 13, and the power supply filter circuit 18 are respectively electrically connected to the power supply circuit 50.

[0045] Optional, see Figure 3In some embodiments, the program burning interface circuit 30 includes a program burning interface P1 and a first resistor R1; a first end P1-1 of the program burning interface P1 is electrically connected to the power supply circuit 50, a second end P1-2 of the program burning interface P1 is electrically connected to a memory chip select end 1037 of the micro control unit 10, a third end P1-3 to a fifth end P1-5 of the program burning interface P1 are electrically connected to the micro control unit 10 respectively, specifically, a third end P1-3 of the program burning interface P1 is electrically connected to a memory data output end 1035 of the micro control unit 10, a fourth end P1-4 of the program burning interface P1 is electrically connected to a memory clock end 1034 of the micro control unit 10, a fifth end P1-5 of the program burning interface P1 is electrically connected to a memory data input end 1036 of the micro control unit 10, and a sixth end P1-6 of the program burning interface P1 is grounded. A first end of the first resistor R1 is electrically connected to a second end P1 - 2 of the program burning interface P1 , and a second end of the first resistor R1 is grounded.

[0046] It should be noted that the program burning interface P1 is used to be electrically connected to the program burning device so that the program burning device can burn the program code to the micro control unit 10. The first end P1-1 of the program burning interface P1 is used to receive the output power supply signal of the power supply circuit 50. The second end P1-2 of the program burning interface P1 is used for the program burning device to send the chip select signal of the memory to the memory of the micro control unit 10. The third end P1-3 of the program burning interface P1 is used for the memory of the micro control unit 10 to send the data feedback signal to the program burning device. The fourth end P1-4 of the program burning interface P1 is used for the program burning device to interact with the memory of the micro control unit 10 for clock signals. The fifth end P1-5 of the program burning interface P1 is used for the program burning device to send the data signal of the program code to the memory of the micro control unit 10; the sixth end P1-6 of the program burning interface P1 is grounded for grounding the program burning device.

[0047] In the embodiment of the utility model, the program burning interface P1 is electrically connected to the program burning device so that the program burning device burns program codes into the micro control unit 10 , and the voltage of the memory chip select terminal 1037 of the micro control unit 10 is clamped by the first resistor R1 .

[0048] Optional, see Figure 4In some embodiments, the data acquisition circuit 20 includes an acquisition chip U1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first capacitor C1; the data terminal U1-1 of the acquisition chip U1 is electrically connected to the data terminal 1024 of the micro control unit 10, the alarm terminal U1-3 of the acquisition chip U1 is electrically connected to the twenty-second input and output terminal 1001 of the micro control unit 10, the clock terminal U1-4 of the acquisition chip U1 is electrically connected to the first protocol clock terminal 1023 of the micro control unit 10, the power supply terminal U1-5 of the acquisition chip U1 is electrically connected to the power supply circuit 50, and the reset terminal U1-6 of the acquisition chip U1 is electrically connected to the system reset terminal 1021 of the micro control unit 10; the second resistor R The first end of the first resistor R2 is electrically connected to the power supply circuit 50, and the second end of the second resistor R2 is electrically connected to the address terminal U1-2 of the acquisition chip U1; the first end of the third resistor R3 is electrically connected to the address terminal U1-2 of the acquisition chip U1, and the second end of the third resistor R3 is grounded; the first end of the fourth resistor R4 is electrically connected to the power supply circuit 50, and the second end of the fourth resistor R4 is electrically connected to the clock terminal U1-4 of the acquisition chip U1; the first end of the fifth resistor R5 is electrically connected to the power supply circuit 50, and the second end of the fifth resistor R5 is electrically connected to the data terminal U1-1 of the acquisition chip U1; the first end of the first capacitor C1 is electrically connected to the power supply terminal U1-5 of the acquisition chip U1, and the second end of the first capacitor C1 is grounded.

[0049] Specifically, the parameter information includes temperature value and humidity value. The acquisition chip U1 is used to collect temperature value and humidity value and input them into the micro control unit 10. When the temperature value exceeds the preset temperature threshold, a temperature alarm signal is input to the micro control unit 10. When the humidity value exceeds the preset humidity threshold, a humidity alarm signal is input to the micro control unit 10.

[0050] The data terminal U1-1 of the acquisition chip U1 is used for data exchange of parameter information of the internal integrated circuit protocol (IIC, Inter-Integrated Circuit) with the data terminal 1024 of the micro control unit 10; the alarm terminal U1-3 of the acquisition chip U1 is used for inputting a temperature alarm signal to the micro control unit 10 when the temperature value exceeds a preset temperature threshold, and for inputting a humidity alarm signal to the micro control unit 10 when the humidity value exceeds a preset humidity threshold; the clock terminal U1-4 of the acquisition chip U1 is used for clock signal exchange of the internal integrated circuit protocol with the first protocol clock terminal 1023 of the micro control unit 10; the power supply terminal U1-5 of the acquisition chip U1 is used for receiving the output power supply signal of the power supply circuit 50; the reset terminal U1-6 of the acquisition chip U1 is used for receiving The reset signal is sent by the system reset terminal 1021 of the micro control unit 10; the address terminal U1-2 of the acquisition chip U1 is used to determine the address of the acquisition chip U1. When the address terminal U1-2 of the acquisition chip U1 is grounded, the address terminal U1-2 of the acquisition chip U1 is at a low level, and the address of the acquisition chip U1 is 0x44. When the address terminal U1-2 of the acquisition chip U1 is electrically connected to the power supply, the address terminal U1-2 of the acquisition chip U1 is at a high level; the redundant terminal U1-7 of the acquisition chip U1, the ground terminal U1-8 of the acquisition chip U1, and the pad terminal U1-9 of the acquisition chip U1 are all grounded.

[0051] In the embodiment of the utility model, the level of the address terminal U1-2 of the acquisition chip U1 can be controlled by cooperating with the second resistor R2 and the third resistor R3, that is, when the third resistor R3 is a zero-ohm resistor, the address terminal U1-2 of the acquisition chip U1 is at a low level, and when the third resistor R3 is an ordinary resistor with a resistance value, the address terminal U1-2 of the acquisition chip U1 is at a high level; the fourth resistor R4 and the fifth resistor R5 are both pull-up resistors; the first capacitor C1 is a filter capacitor; the acquisition chip U1 is used to collect external parameter information and input it into the micro control unit 10.

[0052] Optionally, in some embodiments, the acquisition chip U1 is a temperature and humidity sensor; the parameter information includes temperature information and humidity information.

[0053] It should be noted that the acquisition chip U1 has two IIC addresses for users to select, and the acquisition chip U1 is packaged in a miniaturized dual flat no-lead package (DFN).

[0054] In the embodiment of the utility model, the temperature value and humidity value are collected by the collection chip U1 and input into the micro control unit 10. When the temperature value exceeds the preset temperature threshold, the temperature alarm signal is input into the micro control unit 10. When the humidity value exceeds the preset humidity threshold, the humidity alarm signal is input into the micro control unit 10.

[0055] Optional, see Figure 5 In some embodiments, the display circuit 40 includes a display driver chip U2, a digital tube, a sixth resistor R6, a seventh resistor R7, a second capacitor C2, and a third capacitor C3; the display driver chip U2 is electrically connected to the digital tube, and the display driver chip U2 is used to control the digital tube to display the processing result; the power supply terminal U2-10 of the display driver chip U2 is electrically connected to the power supply circuit 50; the clock terminal U2-2 of the display driver chip U2 is electrically connected to the first protocol clock terminal 1023 of the micro control unit 10, and the data terminal U2-3 of the display driver chip U2 is electrically connected to the micro The data terminal 1024 of the control unit 10 is electrically connected; the first end of the sixth resistor R6 is electrically connected to the power supply circuit 50, and the second end of the sixth resistor R6 is electrically connected to the data terminal U2-3 of the display driver chip U2; the first end of the seventh resistor R7 is electrically connected to the power supply circuit 50, and the second end of the seventh resistor R7 is electrically connected to the clock terminal U2-2 of the display driver chip U2; the first end of the second capacitor C2 and the first end of the third capacitor C3 are electrically connected to the power supply circuit 50, respectively, and the second end of the second capacitor C2 and the second end of the third capacitor C3 are both grounded.

[0056] It should be noted that the power supply terminal U2-10 of the display driver chip U2 is used to receive the input power supply signal of the external power supply provided by the power supply circuit 50, the clock terminal U2-2 of the display driver chip U2 is used to interact with the first protocol clock terminal 1023 of the micro control unit 10 for the clock signal of the internal integrated circuit protocol, and the data terminal U2-3 of the display driver chip U2 interacts with the data terminal 1024 of the micro control unit 10 for the data signal of the internal integrated circuit protocol of the processing result.

[0057] In the embodiment of the utility model, the sixth resistor R6 and the seventh resistor R7 are both pull-up resistors, and the second capacitor C2 and the third capacitor C3 are both filter capacitors; the digital tube is driven by the display driver chip U2, so that the digital tube can display the processing results.

[0058] Optional, see Figure 6In some embodiments, the power supply circuit 50 includes a voltage stabilizing unit 52, a power supply interface unit 51, and a power supply detection unit 53; the power supply interface unit 51 is electrically connected to the voltage stabilizing unit 52 and to the external power supply; the voltage stabilizing unit 52 is electrically connected to the micro control unit 10, the program burning interface circuit 30, the data acquisition circuit 20, and the display circuit 40, respectively, so as to output a stable output power supply signal to the micro control unit 10, the program burning interface circuit 30, the data acquisition circuit 20, and the display circuit 40; the power supply detection unit 53 is electrically connected to the power supply interface unit 51 and the micro control unit 10, respectively, for inputting the power supply status of the external power supply to the micro control unit 10.

[0059] In an embodiment of the utility model, the voltage stabilizing unit 52 is electrically connected to the external power supply through the power supply interface unit 51, and the input power supply signal of the external power supply is converted into a stable output power supply signal and output through the voltage stabilizing unit 52 to power the micro control unit 10, the program burning interface circuit 30, the data acquisition circuit 20, the display circuit 40 and other parts. The power supply status of the external power supply is input to the micro control unit 10 through the power supply detection unit 53, so that the micro control unit 10 can handle the power supply status of the external power supply in time (such as power off protection) when it is abnormal.

[0060] Optionally, in some embodiments, reference Figure 7 The power supply interface unit 51 includes an interface chip P2, an eighth resistor R8, and a first voltage regulator diode D1. Figure 8 , the voltage stabilizing unit 52 includes a first voltage stabilizing chip U3, a fourth capacitor C4, a fifth capacitor group C5, and a sixth capacitor C6; the interface chip P2 is electrically connected to the external power supply, and the second end P2-2 of the interface chip P2 and the fifth end P2-5 of the interface chip P2 are electrically connected to the first end of the eighth resistor R8 respectively; the second end of the eighth resistor R8 is electrically connected to the input end U3-3 of the first voltage stabilizing chip U3 in the voltage stabilizing unit 52 and the first end of the first voltage stabilizing diode D1 respectively; the second end of the first voltage stabilizing diode D1 is grounded; the first stabilizing The output end U3-4 of the voltage stabilizing chip U3 is electrically connected to the micro control unit 10, the program burning interface circuit 30, the data acquisition circuit 20, and the display circuit 40, respectively; the first end of the fourth capacitor C4 and the first end of the fifth capacitor group C5 are electrically connected to the second end of the eighth resistor R8 in the power supply interface unit 51, respectively, and the second end of the fourth capacitor C4 and the second end of the fifth capacitor group C5 are both grounded; the first end of the sixth capacitor C6 is electrically connected to the output end U3-4 of the first voltage stabilizing chip U3, and the second end of the sixth capacitor C6 is grounded.

[0061] Specifically, the type of the interface chip P2 is a Universal Serial Bus (USB) interface, such as a Type-C (a new type of USB interface standard) interface including 6 terminals;

[0062] The interface chip P2 can be electrically connected to an external power supply, the second end P2-2 of the interface chip P2 and the fifth end P2-5 of the interface chip P2 are both used to output the input power supply signal of the external power supply, the first end P2-1 of the interface chip P2 and the sixth end P2-6 of the interface chip P2 are both used to be grounded, the third end P2-3 of the interface chip P2 and the fourth end P2-4 of the interface chip P2 are redundant ports, so the third end P2-3 of the interface chip P2 and the fourth end P2-4 of the interface chip P2 are left vacant. The power supply interface unit 51 also includes a ninth resistor R9, the first end of the ninth resistor R9 is electrically connected to the seventh end P2-7 of the interface chip P2, and the second end of the ninth resistor R9 is grounded; the seventh end P2-7 of the interface chip P2 is a redundant port, so it is grounded through the ninth resistor R9.

[0063] The power supply adopts a resistance voltage division collection method; the ground terminal U3-1 of the first voltage stabilizing chip U3 is grounded, and the redundant output terminal U3-2 of the first voltage stabilizing chip U3 is vacant.

[0064] In the embodiment of the utility model, the eighth resistor R8 is a fuse to protect the voltage stabilizing chip from being damaged by abnormally high voltage; the ninth resistor R9 is used to ground the seventh terminal P2-7 of the interface chip P2; the first voltage stabilizing diode D1 is used to provide the voltage of the input power supply signal of the external power supply provided by the interface chip P2 to the first voltage stabilizing chip U3; the fourth capacitor C4, the capacitors in the fifth capacitor group C5, and the sixth capacitor C6 are all filter capacitors; the first voltage stabilizing chip U3 is used to convert the input power supply signal of the external power supply provided by the interface chip P2 into a stable output power supply signal and output it.

[0065] It should be noted that the output terminal U3-4 of the first voltage stabilizing chip U3 is electrically connected to the first terminal P1-1 of the program burning interface P1 in the program burning interface circuit 30 and the power terminal U1-5 of the acquisition chip U1 in the data acquisition circuit 20, respectively, so as to provide output power supply signals for the program burning interface P1 and the acquisition chip U1; the second terminal P2-2 of the interface chip P2 and the fifth terminal P2-5 of the interface chip P2 are also electrically connected to the first terminal of the sixth resistor R6 and the seventh resistor R7 in the display circuit 40, respectively, so as to provide the sixth resistor R6 and the seventh resistor R7 with an input power supply signal of an external power supply; the second terminal P2-2 of the interface chip P2 and the fifth terminal P2-5 of the interface chip P2 are also electrically connected to the power terminal U2-10 of the display driver chip U2 in the display circuit 40, respectively, so as to provide the display driver chip U2 with an input power supply signal of an external power supply.

[0066] Optional, see Fig. 9 In some embodiments, the power supply detection unit 53 includes a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a seventh capacitor C7; the first end of the tenth resistor R10 is electrically connected to the second end of the eighth resistor R8 in the power supply interface unit 51, and the second end of the tenth resistor R10 is electrically connected to the first end of the eleventh resistor R11 and the first end of the twelfth resistor R12 respectively; the second end of the eleventh resistor R11 is grounded, and the second end of the twelfth resistor R12 is electrically connected to the power-off detection input terminal 1011 of the micro control unit 10; the first end of the seventh capacitor C7 is electrically connected to the second end of the twelfth resistor R12, and the second end of the seventh capacitor C7 is grounded.

[0067] In the embodiment of the utility model, the power-off detection input terminal 1011 of the micro control unit 10 is used to detect whether the external power supply is powered, that is, to detect whether the external power supply provides an input power supply signal. The tenth resistor R10, the eleventh resistor R11, and the twelfth resistor R12 cooperate to provide the power-off detection input terminal 1011 of the micro control unit 10 with a voltage adapted to the power-off detection input terminal 1011 of the micro control unit 10, and the voltage range is 0 volts to 3.3 volts; the seventh capacitor C7 is a filter capacitor.

[0068] Optionally, in some embodiments, the development circuit also includes a simulation debugging interface circuit 60, and the simulation debugging interface circuit 60 is electrically connected to the power supply circuit 50 and the micro control unit 10 respectively; the simulation debugging interface circuit 60 is used to electrically connect to an external emulator and realize signal interaction between the emulator and the micro control unit 10, as well as to debug the micro control unit 10.

[0069] In the embodiment of the utility model, the simulation debugging interface circuit 60 can realize electrical connection with an external simulator and realize signal interaction between the simulator and the micro control unit 10 , as well as debug the micro control unit 10 .

[0070] Optional, see Fig.10In some embodiments, the simulation debugging interface circuit 60 includes a simulation debugging interface P3; a test reset signal terminal P3-1 of the simulation debugging interface P3 is electrically connected to a test reset signal terminal 1030 of the micro control unit 10, a test data output terminal P3-2 of the simulation debugging interface P3 is electrically connected to a test data input terminal 1031 of the micro control unit 10, a test data input terminal P3-3 of the simulation debugging interface P3 is electrically connected to a test data output terminal 1032 of the micro control unit 10, a test mode selection terminal P3-4 of the simulation debugging interface P3 is electrically connected to a test mode selection terminal 1033 of the micro control unit 10, a test clock terminal P3-5 of the simulation debugging interface P3 is electrically connected to a test clock terminal 1029 of the micro control unit 10, and a power supply terminal P3-7 of the simulation debugging interface P3 is electrically connected to the power supply circuit 50.

[0071] It should be noted that the test reset signal terminal P3-1 of the simulation debugging interface P3 is used to implement the simulator to send a test reset signal to the micro control unit 10 through the test reset signal terminal P3-1 of the simulation debugging interface P3, the test data output terminal P3-2 of the simulation debugging interface P3 is used to implement the simulator to send a test data signal to the micro control unit 10 through the test data output terminal P3-2 of the simulation debugging interface P3, and the test data input terminal P3-3 of the simulation debugging interface P3 is used to implement the micro control unit 10 to send a test data signal to the simulator through the test data input terminal P3-3 of the simulation debugging interface P3. The simulator sends a test data feedback signal, the test mode selection terminal P3-4 of the simulation debugging interface P3 is used to enable the simulator to send a test mode selection signal to the microcontroller unit 10 through the test mode selection terminal P3-4 of the simulation debugging interface P3, and the test clock terminal P3-5 of the simulation debugging interface P3 is used to enable the simulator to interact with the test clock terminal 1029 of the microcontroller unit 10 through the test clock terminal P3-5 of the simulation debugging interface P3; the power supply terminal P3-7 of the simulation debugging interface P3 is electrically connected to the output terminal U3-4 of the first voltage stabilizing chip U3 in the voltage stabilizing unit 52.

[0072] In the embodiment of the present invention, the external emulator can interact with the signals of the micro control unit 10 through the emulation debugging interface P3 and debug the micro control unit 10 .

[0073] Optionally, in some embodiments, the simulation debugging interface circuit 60 also includes a test reset unit P4, a thirteenth resistor R13, and a fourteenth resistor R14; the first end P4-1 of the test reset unit P4 is grounded, and the second end P4-2 of the test reset unit P4 is electrically connected to the test mode end 1020 of the microcontroller unit 10, the first end of the thirteenth resistor R13, and the second end of the fourteenth resistor R14 respectively; the second end of the thirteenth resistor R13 is electrically connected to the data reset end P3-6 of the simulation debugging interface P3; the second end of the fourteenth resistor R14 is electrically connected to the power supply end P3-7 of the simulation debugging interface P3; when the first end P4-1 of the test reset unit P4 is connected to the second end P4-2 of the test reset unit P4, the power supply end P3-7 of the simulation debugging interface P3 and the data reset end P3-6 of the simulation debugging interface P3 are both grounded, so that the emulator is reset.

[0074] In an embodiment of the utility model, the data reset terminal P3-6 of the simulation debugging interface P3 is used to realize that when the first terminal P4-1 of the test reset unit P4 is disconnected from the second terminal P4-2 of the test reset unit P4, the emulator is electrically connected to the test mode terminal 1020 of the micro control unit 10 through the data reset terminal P3-6 of the simulation debugging interface P3 and the thirteenth resistor R13 and debugged; when the first terminal P4-1 of the test reset unit P4 is connected to the second terminal P4-2 of the test reset unit P4, the data reset terminal P3-6 of the simulation debugging interface P3 and the debug reset terminal of the simulation debugging interface P3 are both grounded, so that the emulator is reset; the fourteenth resistor R14 is a pull-up resistor.

[0075] Optionally, in some embodiments, the simulation debugging interface circuit 60 includes a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, and a nineteenth resistor R19; the first end of the fifteenth resistor R15 is electrically connected to the power supply circuit 50, and the second end of the sixteenth resistor R16 is electrically connected to the test data input terminal 1031 of the micro control unit 10; the first end of the sixteenth resistor R16 is electrically connected to the power supply circuit 50, and the second end of the seventeenth resistor R17 is electrically connected to the test data output terminal 1031 of the micro control unit 10 1032 is electrically connected; the first end of the seventeenth resistor R17 is electrically connected to the power supply circuit 50, and the second end of the eighteenth resistor R18 is electrically connected to the test mode selection terminal 1033 of the micro control unit 10; the first end of the eighteenth resistor R18 is electrically connected to the power supply circuit 50, and the second end of the eighteenth resistor R18 is electrically connected to the test clock terminal 1029 of the micro control unit 10; the first end of the nineteenth resistor R19 is electrically connected to the test reset signal terminal 1030 of the micro control unit 10, and the second end of the nineteenth resistor R19 is grounded.

[0076] It should be noted that the first ends of the fifteenth resistor R15 to the nineteenth resistor R19 are electrically connected to the output end U3 - 4 of the first voltage stabilizing chip U3 in the voltage stabilizing unit 52 , respectively.

[0077] Specifically, the five resistors from the fifteenth resistor R15 to the nineteenth resistor R19 are all pull-up resistors.

[0078] Optionally, in some embodiments, the development circuit also includes a mode conversion circuit 70, and the mode conversion circuit 70 is electrically connected to the power supply circuit 50 and the micro control unit 10 respectively; the mode conversion circuit 70 is used to control the micro control unit 10 to be disconnected from the simulation debugging interface circuit 60 when the micro control unit 10 is electrically connected to the program burning interface circuit 30; and to control the micro control unit 10 to be disconnected from the program burning interface circuit 30 when the micro control unit 10 is electrically connected to the simulation debugging interface circuit 60.

[0079] In the embodiment of the utility model, the mode conversion circuit 70 can be used to control the micro control unit 10 to select one of the program burning interface circuit 30 and the simulation debugging interface circuit 60 for electrical connection, so as to switch the micro control unit 10 between the program burning mode and the simulation debugging mode.

[0080] Optional, see Fig.11In some embodiments, the mode conversion circuit 70 includes a mode conversion unit P5, a twentieth resistor R20, and a twenty-first resistor R21; the first end P5-1 of the mode conversion unit P5 is electrically connected to the first end of the twenty-first resistor R21 and the startup configuration end 1022 of the micro control unit 10, respectively, and the second end P5-2 of the mode conversion unit P5 is electrically connected to the first end of the twenty-first resistor R20; the second end of the twenty-first resistor R20 is electrically connected to the power supply circuit 50, and the second end of the twenty-first resistor R21 is grounded; when the first end P5-1 and the second end P5-2 of the mode conversion unit P5 are connected, the micro control unit 10 is controlled to be electrically connected to the program burning interface circuit 30; when the first end P5-1 and the second end P5-2 of the mode conversion unit P5 are disconnected, the micro control unit 10 is controlled to be electrically connected to the simulation debugging interface circuit 60.

[0081] It should be noted that the second end of the twentieth resistor R20 is electrically connected to the output end U3 - 4 of the first voltage stabilizing chip U3 in the voltage stabilizing unit 52 .

[0082] In the embodiment of the utility model, when the first end P5-1 and the second end P5-2 are connected through the mode conversion unit P5, the twentieth resistor R20 and the twenty-first resistor R21 are both voltage-dividing resistors, so that the level of the startup configuration end 1022 of the micro control unit 10 is a high level, and the micro control unit 10 is electrically connected to the program burning interface circuit 30; when the first end P5-1 and the second end P5-2 of the mode conversion unit P5 are disconnected, the twentieth resistor R20 is an invalid resistor, and the twenty-first resistor R21 is a pull-down resistor, so that the level of the startup configuration end 1022 of the micro control unit 10 is a low level, and the micro control unit 10 is electrically connected to the simulation debugging interface circuit 60.

[0083] Optionally, in some embodiments, the development circuit also includes a program debugging interface circuit 80, and the program debugging interface circuit 80 is electrically connected to the power supply circuit 50 and the micro control unit 10 respectively; the program debugging interface circuit 80 is used to output debugging information when debugging the micro control unit 10.

[0084] In the embodiment of the utility model, the debugging information is outputted through the program debugging interface circuit 80, so that the staff can be informed of the problems that occur during the debugging process and the intermediate debugging results.

[0085] Optional, see Fig.12In some embodiments, the program debugging interface circuit 80 includes a program debugging unit P6, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, and a twenty-fifth resistor R25; the first end P6-1 of the program debugging unit P6 is electrically connected to the first end of the twenty-second resistor R22 and the first end of the twenty-fourth resistor R24, respectively, and the second end P6-2 of the program debugging unit P6 is electrically connected to the first end of the twenty-third resistor R23 and the first end of the twenty-fifth resistor R25, respectively; the second end of the twenty-second resistor R22 is electrically connected to the power supply circuit 50, and the second end of the twenty-fourth resistor R24 ​​is electrically connected to the first serial port data output terminal 1013 of the micro control unit 10; the second end of the twenty-third resistor R23 is electrically connected to the power supply circuit 50, and the second end of the twenty-fifth resistor R25 is electrically connected to the first serial port data input terminal 1012 of the micro control unit 10.

[0086] It should be noted that the second end of the twenty-third resistor R23 and the second end of the twenty-second resistor R22 are electrically connected to the output end U3 - 4 of the first voltage stabilizing chip U3 , respectively.

[0087] In the embodiment of the utility model, the twenty-second resistor R22 and the twenty-third resistor R23 are both pull-up resistors, and the twenty-fourth resistor R24 ​​and the twenty-fifth resistor R25 are both voltage-dividing resistors.

[0088] Optionally, in some embodiments, the development circuit further includes a crystal oscillator circuit 90 , which is electrically connected to the micro control unit 10 ; the crystal oscillator circuit 90 is used to generate a clock signal of the micro control unit 10 .

[0089] It should be noted that the crystal oscillator circuit 90 can generate multiple clock signals.

[0090] In the embodiment of the present invention, the clock signal of the micro control unit 10 is realized by a crystal oscillator circuit 90 .

[0091] Optionally, in some embodiments, the crystal oscillator circuit 90 includes a first crystal oscillator sub-circuit and a second crystal oscillator sub-circuit; the first crystal oscillator sub-circuit is electrically connected to the power supply circuit 50 and the micro control unit 10, respectively, and the first crystal oscillator sub-circuit is used to generate a clock signal when the micro control unit 10 is working normally; the second crystal oscillator sub-circuit is electrically connected to the power supply circuit 50 and the micro control unit 10, respectively, and the second crystal oscillator sub-circuit is used to generate a clock signal when the micro control unit 10 is in sleep mode.

[0092] In the embodiment of the utility model, the first crystal oscillator sub-circuit is used to generate a clock signal when the micro control unit 10 is working normally, and the second crystal oscillator sub-circuit is used to generate a clock signal when the micro control unit 10 is in sleep mode.

[0093] Optional, see Fig.13 In some embodiments, the first crystal oscillator sub-circuit includes a first crystal oscillator Y1, a twenty-sixth resistor R26, an eighth capacitor C8, and a ninth capacitor C9; a first end of the first crystal oscillator Y1 is electrically connected to a first crystal oscillator input terminal 1016 of the micro control unit 10, and a second end of the first crystal oscillator Y1 is electrically connected to a first crystal oscillator output terminal 1017 of the micro control unit 10; a first end of the twenty-sixth resistor R26 is electrically connected to a first end of the first crystal oscillator Y1, and a second end of the twenty-sixth resistor R26 is electrically connected to a second end of the first crystal oscillator Y1; a first end of the eighth capacitor C8 is electrically connected to a first end of the first crystal oscillator Y1, and a second end of the eighth capacitor C8 is grounded; a first end of the ninth capacitor C9 is electrically connected to a second end of the first crystal oscillator Y1, and a second end of the ninth capacitor C9 is grounded.

[0094] In the embodiment of the utility model, the twenty-sixth resistor R26, the eighth capacitor C8 and the ninth capacitor C9 cooperate to stabilize the crystal frequency of the first crystal oscillator Y1. The first crystal oscillator Y1 is used to generate a clock signal when the micro control unit 10 works normally.

[0095] Optional, see Fig.14 In some embodiments, the second crystal oscillator sub-circuit includes a second crystal oscillator Y2, a twenty-seventh resistor R27, a tenth capacitor C10, and an eleventh capacitor C11; the first end of the second crystal oscillator Y2 is electrically connected to the second crystal oscillator input terminal 1018 of the micro control unit 10, and the second end of the second crystal oscillator Y2 is electrically connected to the second crystal oscillator output terminal 1019 of the micro control unit 10; the first end of the twenty-seventh resistor R27 is electrically connected to the first end of the second crystal oscillator Y2, and the second end of the twenty-seventh resistor R27 is electrically connected to the second end of the second crystal oscillator Y2; the first end of the tenth capacitor C10 is electrically connected to the first end of the second crystal oscillator Y2, and the second end of the tenth capacitor C10 is grounded; the first end of the eleventh capacitor C11 is electrically connected to the second end of the second crystal oscillator Y2, and the second end of the eleventh capacitor C11 is grounded.

[0096] In the embodiment of the utility model, the twenty-seventh resistor R27, the tenth capacitor C10 and the eleventh capacitor C11 cooperate to stabilize the crystal frequency of the second crystal oscillator Y2. The second crystal oscillator Y2 is used to generate a clock signal when the micro control unit 10 works normally.

[0097] Optionally, in some embodiments, the development circuit further includes an alarm circuit 11, and the alarm circuit 11 is electrically connected to the power supply circuit 50 and the micro control unit 10 respectively; the alarm circuit 11 is used to generate alarm information when the parameter information meets preset conditions.

[0098] Specifically, the parameter information may be a parameter value of an external parameter, and the preset condition may be that the parameter value of the external parameter is greater than a parameter threshold. For example, if the external parameter is temperature, the preset condition may be that the temperature value is greater than a preset temperature threshold.

[0099] In the embodiment of the utility model, the alarm circuit 11 generates alarm information when the parameter information meets the preset conditions.

[0100] Optional, see Fig.15 In some embodiments, the alarm circuit 11 includes a first transistor Q1, a twenty-eighth resistor R28, a forty-third resistor R43, and a speaker B1; the collector of the first transistor Q1 is electrically connected to the first end of the forty-three resistor, the base of the first transistor Q1 is electrically connected to the first end of the twenty-eighth resistor R28, and the emitter of the first transistor Q1 is grounded; the second end of the twenty-eighth resistor R28 is electrically connected to the twenty-third input-output terminal 1002 of the micro control unit 10; the positive electrode of the speaker B1 is electrically connected to the power supply circuit 50, and the negative electrode of the speaker B1 is electrically connected to the second end of the forty-three resistor, and the speaker B1 is used to display the alarm information.

[0101] It should be noted that the positive electrode of the speaker B1 is electrically connected to the output terminal U3 - 4 of the first voltage stabilizing chip U3 .

[0102] Specifically, the first transistor Q1 is an NPN transistor, which is composed of three semiconductors, including two N (Negative Electricity) type semiconductors (electronic semiconductors) and one P (Positive Electricity) type semiconductor (hole semiconductor), with the P type semiconductor in the middle and two N type semiconductors on both sides.

[0103] In the embodiment of the utility model, the twenty-eighth resistor R28 and the forty-third resistor R43 are both voltage-dividing resistors. When the twenty-third input-output terminal 1002 of the microcontroller unit 10 is at a high level, the first transistor Q1 is turned on, and the speaker B1 is powered on and broadcasts an alarm sound signal; when the twenty-third input-output terminal 1002 of the microcontroller unit 10 is at a low level, the first transistor Q1 is turned off, and the speaker B1 is powered off. Optionally, in other embodiments, the first transistor Q1 is a PNP transistor, which is composed of three semiconductors, including an N-type semiconductor and two P-type semiconductors, with the N-type semiconductor in the middle and the two P-type semiconductors on both sides. The emitter of the first transistor Q1 is electrically connected to the power supply circuit 50, the collector of the first transistor Q1 is electrically connected to the positive electrode of the speaker B1, the base of the first transistor Q1 is electrically connected to the first end of the twenty-eighth resistor R28; the second end of the twenty-eighth resistor R28 is electrically connected to the twenty-third input-output terminal 1002 of the micro control unit 10; the negative electrode of the speaker B1 is electrically connected to the second end of the forty-three resistor, and the first end of the forty-three resistor is grounded.

[0104] Specifically, the emitter of the first transistor Q1 is electrically connected to the output terminal U3 - 4 of the first voltage stabilizing chip U3 .

[0105] In the embodiment of the utility model, when the twenty-third input-output terminal 1002 of the microcontroller unit 10 is at a low level, the first transistor Q1 is turned on, and the speaker B1 is powered on and broadcasts an alarm sound signal; when the twenty-third input-output terminal 1002 of the microcontroller unit 10 is at a high level, the first transistor Q1 is disconnected, and the speaker B1 is powered off.

[0106] Optionally, in some embodiments, the development circuit further includes a storage circuit 12, and the storage circuit 12 is electrically connected to the power supply circuit 50 and the micro control unit 10 respectively; the storage circuit 12 is used to store the parameter information.

[0107] In the embodiment of the present utility model, the data storage of the micro control unit 10 is realized by the storage circuit 12 .

[0108] Optional, see Fig.16In some embodiments, the storage circuit 12 includes a storage chip U4, a twenty-ninth resistor R29, a thirtieth resistor R30, and a thirty-first resistor R31; a chip select input terminal U4-1 of the storage chip U4 is electrically connected to a chip select output terminal 1028 of the micro control unit 10, a data input terminal U4-2 of the storage chip U4 is electrically connected to a data output terminal 1026 of the micro control unit 10, a write protection input terminal U4-3 of the storage chip U4 is electrically connected to an eighteenth input and output terminal 1005 of the micro control unit 10, a data output terminal U4-5 of the storage chip U4 is electrically connected to a data input terminal 1027 of the micro control unit 10, and a clock terminal U4-6 of the storage chip U4 is electrically connected to a second protocol clock terminal 1025 of the micro control unit 10, The hold input terminal U4-7 of the memory chip U4 is electrically connected to the thirteenth input-output terminal 1004 of the micro control unit 10, and the power supply terminal U4-8 of the memory chip U4 is electrically connected to the power supply circuit 50; the first end of the twenty-ninth resistor R29 is electrically connected to the chip select input terminal U4-1 of the memory chip U4, and the second end of the twenty-ninth resistor R29 is electrically connected to the power supply circuit 50; the first end of the thirtieth resistor R30 is electrically connected to the write protection input terminal U4-3 of the memory chip U4, and the second end of the thirtieth resistor R30 is electrically connected to the power supply circuit 50; the first end of the thirty-first resistor R31 is electrically connected to the hold input terminal U4-7 of the memory chip U4, and the second end of the thirty-first resistor R31 is electrically connected to the power supply circuit 50.

[0109] It should be noted that the power supply terminal U4-8 of the storage chip U4 is electrically connected to the output terminal U3-4 of the first voltage regulator chip U3, and the ground terminal U4-4 of the storage chip U4 is grounded; the second end of the twenty-ninth resistor R29, the second end of the thirtieth resistor R30, and the second end of the thirty-first resistor R31 are all electrically connected to the output terminal U3-4 of the first voltage regulator chip U3.

[0110] The storage circuit 12 also includes a filter capacitor group, which includes multiple capacitors. For example, the filter capacitor group includes a twelfth capacitor C12 and a thirteenth capacitor C13. The first end of the twelfth capacitor C12 and the first end of the thirteenth capacitor C13 are both electrically connected to the output end U3-4 of the first voltage regulator chip U3, and the second end of the twelfth capacitor C12 and the second end of the thirteenth capacitor C13 are both grounded.

[0111] Specifically, the chip select input terminal U4-1 of the memory chip U4 is used to receive the chip select signal of the serial peripheral interface protocol (SPI) sent by the chip select output terminal 1028 of the micro control unit 10, the data input terminal U4-2 of the memory chip U4 is used to receive the data signal of the serial peripheral interface protocol output by the data output terminal 1026 of the micro control unit 10, the write protection input terminal U4-3 of the memory chip U4 is used for the write operation prevention signal of the serial peripheral interface protocol of the eighteenth input and output terminal 1005 of the micro control unit 10, the data output terminal U4-5 of the memory chip U4 is used to send the data feedback signal of the serial peripheral interface protocol to the data input terminal 1027 of the micro control unit 10, the clock terminal U4-6 of the memory chip U4 is used to interact with the clock signal of the serial peripheral interface protocol with the second protocol clock terminal 1025 of the micro control unit 10, and the hold input terminal U4-7 of the memory chip U4 is used to receive the control signal of the serial peripheral interface protocol sent by the thirteenth input and output terminal 1004 of the micro control unit 10 to control the pause and resumption of data transmission.

[0112] In the embodiment of the utility model, the twenty-ninth resistor R29, the thirtieth resistor R30, and the thirty-first resistor R31 are all pull-up resistors; the twelfth capacitor C12 and the thirteenth capacitor C13 are both filter capacitors; and data storage of the micro control unit 10 can be achieved through the storage chip U4.

[0113] Optionally, in some embodiments, the development circuit further includes a key circuit 13, and the key circuit 13 is electrically connected to the power supply circuit 50 and the micro control unit 10 respectively; the key circuit 13 is used to control the working process of the micro control unit 10.

[0114] It should be noted that the key circuit 13 may include multiple keys, through which the working process of the microcontroller unit 10 can be controlled. For example, through the keys, the time, temperature, and humidity in the microcontroller unit 10 can be set, and the broadcast of the speaker B1 and the switch of the relay 171 in the external power supply control circuit 17 electrically connected to the microcontroller unit 10 can be manually controlled.

[0115] In the embodiment of the utility model, the staff can directly control the working process of the micro control unit 10 through the key circuit 13 .

[0116] Optionally, in some embodiments, the button circuit 13 includes a plurality of button sub-circuits 131 connected in parallel, each of the button sub-circuits 131 includes a button, a fourteenth capacitor, and a thirty-second resistor; the first end of the button is electrically connected to the first end of the thirty-second resistor, the second end of the button is respectively electrically connected to the first end of the button and an input / output end of the microcontroller unit 10, the third end of the button is grounded, and when the button is closed, the first end of the button and the second end of the button are respectively connected to the third end of the button; the first end of the fourteenth capacitor is electrically connected to the first end of the thirty-second resistor, the second end of the fourteenth capacitor is grounded; the second end of the thirty-second resistor is electrically connected to the power supply circuit 50.

[0117] Specifically, refer to Fig.17 The key circuit 13 includes four key sub-circuits 131 connected in parallel. The first key sub-circuit 131 includes a key 1311, a fourteenth capacitor C14a, and a thirty-second resistor R32a; the first end of the key 1311 is electrically connected to the first end of the thirty-second resistor R32a, the second end of the key 1311 is electrically connected to the first end of the key 1311 and the control input and output end 1009 of the micro control unit 10, and the third end of the key 1311 is grounded. When the key 1311 is closed, the first end of the key 1311 and the second end of the key 1311 are connected to the third end of the key 1311 respectively; the first end of the fourteenth capacitor C14a is electrically connected to the first end of the thirty-second resistor R32a, and the second end of the fourteenth capacitor C14a is grounded; the second end of the thirty-second resistor R32a is electrically connected to the output end U3-4 of the first voltage regulator chip U3; similarly, the key sub-circuits including keys 1312, 1313, and 1314 are not described in detail.

[0118] The fourth end of the key 1311 in the first key subcircuit 131 is electrically connected to the third end of the key 1311 in the first key subcircuit 131 and the third end of the key 1312 in the second key subcircuit 131, respectively; the fourth end of the key 1312 in the second key subcircuit 131 is electrically connected to the third end of the key 1312 in the second key subcircuit 131 and the third end of the key 1313 in the third key subcircuit 131, respectively; the fourth end of the key 1313 in the third key subcircuit 131 is electrically connected to the third end of the key 1313 in the third key subcircuit 131 and the third end of the key 1314 in the fourth key subcircuit 131, respectively; and the fourth end of the key 1314 in the fourth key subcircuit 131 is grounded.

[0119] In the embodiment of the utility model, the staff can control multiple working processes of the micro control unit 10 respectively through the key circuit 13.

[0120] Optionally, in some embodiments, the development circuit further includes a wired communication circuit 14, and the wired communication circuit 14 is electrically connected to the power supply circuit 50 and the micro control unit 10 respectively; the wired communication circuit 14 is used to realize communication between the micro control unit 10 and external devices.

[0121] It should be noted that the communication between the micro control unit 10 and the external device implemented by the wired communication circuit 14 may be RS422 (a differential signal transmission standard) or RS485 (a differential signal transmission standard).

[0122] In the embodiment of the utility model, wired communication between the micro control unit 10 and external devices can be achieved through the wired communication circuit 14 .

[0123] Optional, see Fig.18In some embodiments, the wired communication circuit 14 includes a transceiver chip U5, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36, a thirty-seventh resistor R37, a thirty-eighth resistor R38, a fifteenth capacitor C15, and a second voltage-stabilizing diode D2; a receiver output terminal U5-1 of the transceiver chip U5 is electrically connected to a first end of the thirty-third resistor R33, a receiver output enable terminal U5-2 of the transceiver chip U5, and a driver output enable terminal U5-3 of the transceiver chip U5 are respectively connected to the micro control unit 10 The thirty-seventh input-output terminal 1010 of the microcontroller 10 is electrically connected, the driver input terminal U5-4 of the transceiver chip U5 is electrically connected to the first end of the thirty-fourth resistor R34, the first differential signal terminal U5-6 of the transceiver chip U5 and the second differential signal terminal U5-7 of the transceiver chip U5 are both used to communicate with the external device, the power supply terminal U5-8 of the transceiver chip U5 is electrically connected to the first end of the thirty-fifth resistor R35; the second end of the thirty-third resistor R33 is electrically connected to the second serial port data input terminal 1014 of the microcontroller 10; the first end of the thirty-fourth resistor R34 is electrically connected to the second serial port data input terminal 1014 of the microcontroller 10; the first end of the thirty-fourth resistor R34 is electrically connected to the first end of the thirty-fifth resistor R35 The first end of the thirty-sixth resistor R36 is electrically connected to the first end of the thirty-fifth resistor R35, and the second end of the thirty-sixth resistor R36 is electrically connected to the first differential signal terminal U5-6 of the transceiver chip U5; the first end of the thirty-seventh resistor R37 is electrically connected to the second differential signal terminal U5-7 of the transceiver chip U5, and the second end of the thirty-seventh resistor R37 is grounded; the first end of the thirty-eighth resistor R38 ... first end of the thirty-fifth resistor R35, and the second end of the thirty-sixth resistor R36 is electrically connected to the first differential signal terminal U5-6 of the transceiver chip U5; the first end of the thirty-seventh resistor R37 is electrically connected to the second differential signal terminal U5-7 of the transceiver chip U5, and the second end of the thirty-seventh resistor R37 is grounded; the first end of the thirty-eighth resistor R38 is electrically connected to the first end of the thirty-fifth resistor R38, and the second end of the thirty-seventh resistor R38 is electrically connected to the first end of the thirty-fifth resistor R38 The first end of the fifteenth capacitor C15 is electrically connected to the power supply terminal U5-8 of the transceiver chip U5, and the second end of the fifteenth capacitor C15 is grounded; the first end of the second voltage regulator diode D2 is electrically connected to the first differential signal terminal U5-6 of the transceiver chip U5, and the second end of the second voltage regulator diode D2 is electrically connected to the second differential signal terminal U5-7 of the transceiver chip U5.

[0124] The receiver output terminal U5-1 of the transceiver chip U5 is used to output a data signal to the micro control unit 10; the receiver output enable terminal U5-2 of the transceiver chip U5 is used to control the enable of the receiver output terminal U5-1 of the transceiver chip U5; the driver output enable terminal U5-3 of the transceiver chip U5 is used to control the enable of the driver output; the driver input terminal U5-4 of the transceiver chip U5 is used to receive the data signal output by the micro control unit 10; the first differential signal terminal U5-6 of the transceiver chip U5 and the second differential signal terminal U5-7 of the transceiver chip U5 are used to communicate with external devices; the power supply terminal U5-8 of the transceiver chip U5 is used to receive the power supply signal, which is achieved by electrically connecting the second end of the thirty-fifth resistor R35 with the second end P2-2 and the fifth end P2-5 of the interface chip P2 in the power supply interface unit; the ground terminal U5-5 of the transceiver chip U5 is grounded.

[0125] In the embodiment of the utility model, the thirty-third resistor R33 and the thirty-fourth resistor R34 are matching resistors, the thirty-fifth resistor R35, the thirty-sixth resistor R36 and the thirty-eighth resistor R38 are all voltage-dividing resistors; the thirty-seventh resistor R37 is a pull-down resistor; the fifteenth capacitor C15 is a filter capacitor; the second voltage-stabilizing diode D2 is used to stabilize the voltage difference between the first differential signal terminal U5-6 of the transceiver chip U5 and the second differential signal terminal U5-7 of the transceiver chip U5; through the transceiver chip U5, wired communication between the microcontroller unit 10 and the external device can be realized.

[0126] Optionally, in some embodiments, the development circuit also includes a wireless communication circuit 15, and the wireless communication circuit 15 is electrically connected to the power supply circuit 50 and the micro control unit 10 respectively; the wireless communication circuit 15 is used to realize communication between the micro control unit 10 and external devices.

[0127] It should be noted that the communication between the micro control unit 10 and the external device implemented by the wireless communication circuit 15 may be Wi-Fi (a wireless network communication technology).

[0128] In the embodiment of the utility model, wireless communication between the micro control unit 10 and external devices can be achieved through the wireless communication circuit 15 .

[0129] Optional, see Fig.19In some embodiments, the wireless communication circuit 15 includes a wireless communication chip U6, a second voltage stabilizing chip U7, a thirty-ninth resistor R39, a fortieth resistor R40, a sixteenth capacitor group C16, a seventeenth capacitor C17, and an eighteenth capacitor C18; the data receiving end U6-4 of the wireless communication chip U6 is electrically connected to the second serial port data output end 1015 of the micro control unit 10, the data sending end U6-5 of the wireless communication chip U6 is electrically connected to the second serial port data input end 1014 of the micro control unit 10, the enable end U6-6 of the wireless communication chip U6 is electrically connected to the first end of the fortieth resistor R40, the reset end U6-7 of the wireless communication chip U6 is electrically connected to the system reset end 1021 of the micro control unit 10, and the power supply end U6-8 of the wireless communication chip U6 is electrically connected to the first The output end U7-2 of the second voltage stabilizing chip U7 is electrically connected; the second end of the fortieth resistor R40 is electrically connected to the output end U7-2 of the second voltage stabilizing chip U7; the input end U7-3 of the second voltage stabilizing chip U7 is electrically connected to the first end of the thirty-ninth resistor R39, and the second end of the thirty-ninth resistor R39 is electrically connected to the power supply circuit 50; the first end of the sixteenth capacitor group C16 is electrically connected to the power supply end U6-8 of the wireless communication chip U6, and the second end of the sixteenth capacitor group C16 is grounded; the first end of the seventeenth capacitor C17 is electrically connected to the output end U7-2 of the second voltage stabilizing chip U7, and the second end of the seventeenth capacitor C17 is grounded; the first end of the eighteenth capacitor C18 is electrically connected to the second end of the thirty-ninth resistor R39, and the second end of the eighteenth capacitor C18 is grounded.

[0130] It should be noted that the second end of the thirty-ninth resistor R39 is electrically connected to the second end P2-2 and the fifth end P2-5 of the interface chip P2 in the power supply interface unit.

[0131] The data receiving terminal U6-4 of the wireless communication chip U6 is used to receive the data signal of the micro control unit 10; the data sending terminal U6-5 of the wireless communication chip U6 is used to send the data signal to the micro control unit 10; the enable terminal U6-6 of the wireless communication chip U6 is used to control the enablement of the wireless communication chip U6; the reset terminal U6-7 of the wireless communication chip U6 is used to control the reset of the wireless communication chip U6; the power supply terminal U6-8 of the wireless communication chip U6 is used to receive the power supply signal; the first redundant terminal U6-2 of the wireless communication chip U6 and the second redundant terminal U6-3 of the wireless communication chip U6 are vacant, and the ground terminal U6-1 of the wireless communication chip U6 is grounded.

[0132] In the embodiment of the utility model, the thirty-ninth resistor R39 is a zero-ohm resistor; the fortieth resistor R40 is a matching resistor; the sixteenth capacitor group C16, the seventeenth capacitor C17, and the eighteenth capacitor C18 are all filter capacitors; through the second voltage regulator chip U7, a stable power supply signal is provided to the wireless communication chip U6; through the wireless communication chip U6, wireless communication between the micro control unit 10 and external devices can be realized.

[0133] Optionally, in some embodiments, the hardware development circuit of the micro control unit 10 further includes a reset circuit 16, and the reset circuit 16 is electrically connected to the power supply circuit 50 and the micro control unit 10 respectively; the reset circuit 16 is used to control the reset of the micro control unit 10.

[0134] In the embodiment of the present invention, the reset circuit 16 is used to reset the micro control unit 10 .

[0135] Optional, see Fig. 20 In some embodiments, the reset circuit 16 includes a reset switch S1, a forty-first resistor R41, and a nineteenth capacitor C19; the first end of the reset switch S1 is electrically connected to the system reset end 1021 of the micro control unit 10, and the second end of the reset switch S1 is grounded; the first end of the forty-first resistor R41 is electrically connected to the power supply circuit 50, and the second end of the forty-first resistor R41 is electrically connected to the first end of the nineteenth capacitor C19; the first end of the nineteenth capacitor C19 is electrically connected to the system reset end 1021 of the micro control unit 10, and the second end of the nineteenth capacitor C19 is grounded.

[0136] In the embodiment of the utility model, the nineteenth capacitor C19 is a filter capacitor; when the reset switch S1 is disconnected, the forty-first resistor R41 is a pull-up resistor, and the system reset terminal 1021 of the micro control unit 10 is a high level; when the reset switch S1 is closed, the system reset terminal 1021 of the micro control unit 10 is a low level, and the micro control unit 10 is reset.

[0137] Optionally, in some embodiments, the hardware development circuit of the micro control unit 10 also includes an external power supply control circuit 17, and the external power supply control circuit 17 is electrically connected to the power supply circuit 50 and the micro control unit 10, respectively; the external power supply control circuit 17 is used for the micro control unit 10 to control the power supply to external devices through the external power supply control circuit 17.

[0138] In the embodiment of the utility model, the power supply to the external device is controlled by the external power supply control circuit 17 .

[0139] Optional, see Fig.21In some embodiments, the external power supply control circuit 17 includes a relay 171, a first diode D3, a second diode D4, a second transistor Q2, and a forty-second resistor R42; the positive electrode of the relay 171 is electrically connected to the power supply circuit 50, the negative electrode of the relay 171 is electrically connected to the collector of the second transistor Q2, the normally open end of the relay 171, the normally closed end of the relay 171, and the common end of the relay 171 are electrically connected to the external device respectively; the positive electrode of the first diode D3 is electrically connected to the negative electrode of the relay 171, and the negative electrode of the first diode D3 is electrically connected to the positive electrode of the relay 171; the base of the second transistor Q2 is electrically connected to the negative electrode of the second diode D4, and the emitter of the second transistor Q2 is grounded; the positive electrode of the second diode D4 is electrically connected to the first end of the forty-second resistor R42; the second end of the forty-second resistor R42 is electrically connected to the twenty-fourth input-output terminal 1003 of the micro control unit 10.

[0140] It should be noted that the second transistor Q2 is an NPN transistor; the positive electrode of the relay 171 is electrically connected to the second terminal P2-2 and the fifth terminal P2-5 of the interface chip P2 in the power supply interface unit.

[0141] In the embodiment of the utility model, the first diode D3 is used to protect the relay 171 from being damaged by the sudden voltage, the second diode D4 is used for rectification, and the forty-second resistor R42 is a matching resistor; the second transistor Q2 is used to control the closing and opening of the relay 171. When the second transistor Q2 is turned on, the relay 171 is energized and turned on, and when the second transistor Q2 is turned off, the relay 171 is de-energized and disconnected; through the relay 171, the power supply to the external device can be controlled.

[0142] Optionally, in some other embodiments, the second transistor Q2 is a PNP transistor, the emitter of the second transistor Q2 is electrically connected to the power supply circuit 50, the base of the second transistor Q2 is electrically connected to the first end of the forty-second resistor R42, and the emitter of the second transistor Q2 is electrically connected to the positive electrode of the relay 171; the negative electrode of the relay 171 is grounded, the normally open end of the relay 171, the normally closed end of the relay 171, and the common end of the relay 171 are electrically connected to external devices respectively; the positive electrode of the first diode D3 is electrically connected to the negative electrode of the relay 171, and the negative electrode of the first diode D3 is electrically connected to the positive electrode of the relay 171; the second end of the forty-second resistor R42 is electrically connected to the twenty-fourth input-output terminal 1003 of the micro control unit 10.

[0143] It should be noted that the emitter of the second transistor Q2 is electrically connected to the second end P2-2 and the fifth end P2-5 of the interface chip P2 in the power supply interface unit.

[0144] In the embodiment of the present invention, when the second transistor Q2 is turned on, the relay 171 is powered on and turned on, and when the second transistor Q2 is turned off, the relay 171 is powered off and turned off.

[0145] Optionally, in some embodiments, the hardware development circuit of the micro control unit 10 also includes a power supply filter circuit 18, and the power supply filter circuit 18 is electrically connected to the power supply circuit 50; the power supply filter circuit 18 includes a plurality of parallel twentieth capacitors, a first end of the twentieth capacitor is electrically connected to the power supply circuit, and a second end of the twentieth capacitor is grounded.

[0146] Specifically, refer to Fig. 22 The power supply filter circuit 18 includes four parallel-connected twentieth capacitors, wherein the first ends of the twentieth capacitor C20a, the twentieth capacitor C20b, the twentieth capacitor C20c, and the twentieth capacitor C20d are electrically connected to the output end U3-4 of the first voltage regulator chip U3, respectively, and the second ends of the twentieth capacitor C20a, the twentieth capacitor C20b, the twentieth capacitor C20c, and the twentieth capacitor C20d are all grounded.

[0147] In the embodiment of the utility model, the output power supply signal output by the first voltage stabilizing chip U3 is filtered by the power supply filter circuit 18 .

[0148] Optional, see Fig.23 In some embodiments, the ports of the microcontroller unit 10 include a memory chip select terminal 1037 of the microcontroller unit 10, a memory data output terminal 1035 of the microcontroller unit 10, a memory clock terminal 1034 of the microcontroller unit 10, a memory data input terminal 1036 of the microcontroller unit 10, a data terminal 1024 of the microcontroller unit 10, a twenty-second input and output terminal 1001 of the microcontroller unit 10, a first protocol clock terminal 1023 of the microcontroller unit 10, a system reset terminal 1021 of the microcontroller unit 10, a power-off detection input terminal 1011 of the microcontroller unit 10, a test reset signal terminal 1030 of the microcontroller unit 10, a test data input terminal 1031 of the microcontroller unit 10, a test data output terminal 1032 of the microcontroller unit 10, a test mode selection terminal 1033 of the microcontroller unit 10, a test clock terminal 1029 of the microcontroller unit 10, a test mode terminal 1020 of the microcontroller unit 10, a startup configuration terminal 1022 of the microcontroller unit 10, and a first serial port data input terminal 1012 of the microcontroller unit 10;

[0149] The ports of the microcontroller unit 10 further include a first crystal oscillator input terminal 1016 of the microcontroller unit 10, a first crystal oscillator output terminal 1017 of the microcontroller unit 10, a second crystal oscillator input terminal 1018 of the microcontroller unit 10, a second crystal oscillator output terminal 1019 of the microcontroller unit 10, a twenty-third input and output terminal 1002 of the microcontroller unit 10, a chip select output terminal 1028 of the microcontroller unit 10, a data output terminal 1026 of the microcontroller unit 10, an eighteenth input and output terminal 1005 of the microcontroller unit 10, a data input terminal 1027 of the microcontroller unit 10, a second protocol clock terminal 1025 of the microcontroller unit 10, and a second crystal oscillator input terminal 1018 of the microcontroller unit 10. The thirteenth input and output terminal 1004 of the control unit 10, the thirty-seventh input and output terminal 1010 of the microcontroller unit 10, the second serial port data input terminal 1014 of the microcontroller unit 10, the second serial port data output terminal 1015 of the microcontroller unit 10, the twenty-fourth input and output terminal 1003 of the microcontroller unit 10, the control input and output terminal 1009 of the microcontroller unit 10, the control input and output terminal 1008 of the microcontroller unit 10, the control input and output terminal 1007 of the microcontroller unit 10, and the control input and output terminal 1006 of the microcontroller unit 10. The port description of the microcontroller unit 10 is as mentioned above and will not be repeated here.

[0150] The development circuit is suitable for medical temperature and humidity acquisition terminals, agricultural irrigation data gateways, aquaculture data acquisition control terminals, and school experimental teaching scenarios, etc. It makes full use of the interface resources of the microcontroller unit, lowers the design threshold for developers, students, and chip enthusiasts, reduces the development time based on the microcontroller unit, and reduces the development difficulty based on the microcontroller unit 10.

[0151] In summary, the embodiment of the utility model provides a development circuit, which is electrically connected to an external power supply through a power supply circuit and supplies power, and a program burning interface circuit is electrically connected to a program burning device so that the program burning device burns the program code into a micro control unit, a data acquisition circuit collects external parameter information and inputs it into the micro control unit, the micro control unit executes the program code, and sends the generated processing results to a display circuit for display, thereby providing users with a hardware development environment based on the micro control unit.

[0152] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A development circuit, characterized in that, include: Power supply circuit, data acquisition circuit, program burning interface circuit, micro control unit and display circuit; The power supply circuit is electrically connected to the micro control unit, the program burning interface circuit, the data acquisition circuit, and the display circuit respectively; the power supply circuit is used to be electrically connected to an external power supply and supply power; The data acquisition circuit is electrically connected to the micro control unit; the data acquisition circuit is used to collect external parameter information and input it into the micro control unit; The program burning interface circuit is electrically connected to the micro control unit; the program burning interface circuit is used for an external program burning device to burn the program code for processing the parameter information into the micro control unit; The micro control unit is electrically connected to the display circuit; and is used to execute the program code and send the generated processing result to the display circuit for display; The program burning interface circuit includes a program burning interface and a first resistor; the first end of the program burning interface is electrically connected to the power supply circuit, and the third end to the fifth end of the program burning interface are electrically connected to the micro control unit respectively; the first end of the first resistor is electrically connected to the second end of the program burning interface, and the second end is grounded.

2. The development circuit according to claim 1, characterized in that: The data acquisition circuit includes an acquisition chip, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a first capacitor; The data terminal of the acquisition chip is electrically connected to the data terminal of the micro control unit, the alarm terminal of the acquisition chip is electrically connected to the twenty-second input and output terminal of the micro control unit, and the clock terminal of the acquisition chip is electrically connected to the first protocol clock terminal of the micro control unit; A first end of the second resistor is electrically connected to the power supply circuit, and a second end of the second resistor is electrically connected to an address end of the acquisition chip; A first end of the third resistor is electrically connected to the address end of the acquisition chip, and a second end is grounded; A first end of the fourth resistor is electrically connected to the power supply circuit, and a second end thereof is electrically connected to a clock end of the acquisition chip; A first end of the fifth resistor is electrically connected to the power supply circuit, and a second end thereof is electrically connected to the data end of the acquisition chip; The first end of the first capacitor is electrically connected to the power supply end of the acquisition chip, and the second end is grounded.

3. The development circuit according to claim 1, characterized in that: The display circuit includes a display driver chip, a digital tube, a sixth resistor, a seventh resistor, a second capacitor, and a third capacitor; The power supply terminal of the display driver chip is electrically connected to the power supply circuit; the clock terminal of the display driver chip is electrically connected to the first protocol clock terminal of the micro control unit, and the data terminal of the display driver chip is electrically connected to the data terminal of the micro control unit; The digital tube is electrically connected to the display driver chip; A first end of the sixth resistor is electrically connected to the power supply circuit, and a second end thereof is electrically connected to a data end of the display driver chip; A first end of the seventh resistor is electrically connected to the power supply circuit, and a second end thereof is electrically connected to a clock end of the display driving chip; The first end of the second capacitor and the first end of the third capacitor are electrically connected to the power supply circuit respectively, and the second end of the second capacitor and the second end of the third capacitor are both grounded.

4. The development circuit according to claim 1, characterized in that: The power supply circuit includes a voltage stabilizing unit, a power supply interface unit, and a power supply detection unit; The power supply interface unit is electrically connected to the voltage stabilizing unit and the external power supply; The voltage stabilizing unit is electrically connected to the micro control unit, the program burning interface circuit, the data acquisition circuit, and the display circuit respectively to output a stable output power supply signal; The power supply detection unit is electrically connected to the power supply interface unit and the micro control unit respectively.

5. The development circuit according to claim 4, characterized in that: The power supply interface unit includes an interface chip, an eighth resistor, and a first voltage stabilizing diode; the voltage stabilizing unit includes a first voltage stabilizing chip, a fourth capacitor, a fifth capacitor group, and a sixth capacitor; The interface chip is electrically connected to the external power supply, and the second end and the fifth end of the interface chip are electrically connected to the first end of the eighth resistor respectively; The first end of the first voltage stabilizing diode is electrically connected to the second end of the eighth resistor, and the second end is grounded; The output end of the first voltage stabilizing chip is electrically connected to the micro control unit, the program burning interface circuit, the data acquisition circuit, and the display circuit respectively; The first end of the fourth capacitor and the first end of the fifth capacitor group are electrically connected to the second end of the eighth resistor respectively, and the second end of the fourth capacitor and the second end of the fifth capacitor group are both grounded; The first end of the sixth capacitor is electrically connected to the output end of the first voltage stabilizing chip, and the second end is grounded.

6. The development circuit according to claim 5, characterized in that: The power supply detection unit includes a tenth resistor, an eleventh resistor, a twelfth resistor, and a seventh capacitor; The first end of the tenth resistor is electrically connected to the second end of the eighth resistor, and the second end of the tenth resistor is electrically connected to the first end of the eleventh resistor and the first end of the twelfth resistor respectively; The second end of the eleventh resistor is grounded, and the second end of the twelfth resistor is electrically connected to the power-off detection input end of the micro control unit; The first end of the seventh capacitor is electrically connected to the second end of the twelfth resistor, and the second end is grounded.

7. The development circuit according to claim 1, characterized in that: The development circuit also includes a simulation debugging interface circuit; the simulation debugging interface circuit is electrically connected to the power supply circuit and the micro control unit respectively; The simulation debugging interface circuit is used to be electrically connected to an external simulator and realize signal interaction between the simulator and the micro control unit, as well as to debug the micro control unit.

8. The development circuit according to claim 7, characterized in that: The simulation debugging interface circuit includes a simulation debugging interface; The test reset signal terminal of the simulation debugging interface is electrically connected to the test reset signal terminal of the micro control unit, the test data output terminal of the simulation debugging interface is electrically connected to the test data input terminal of the micro control unit, the test data input terminal of the simulation debugging interface is electrically connected to the test data output terminal of the micro control unit, the test mode selection terminal of the simulation debugging interface is electrically connected to the test mode selection terminal of the micro control unit, the test clock terminal of the simulation debugging interface is electrically connected to the test clock terminal of the micro control unit, and the power supply terminal of the simulation debugging interface is electrically connected to the power supply circuit.

9. The development circuit according to claim 1, characterized in that: The development circuit also includes a program debugging interface circuit; the program debugging interface circuit is electrically connected to the power supply circuit and the micro control unit respectively; The program debugging interface circuit is used to output debugging information when debugging the micro control unit.

10. The development circuit according to claim 9, characterized in that: The program debugging interface circuit includes a program debugging interface, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, and a twenty-fifth resistor; The first end of the program debugging interface is electrically connected to the first end of the 22nd resistor and the first end of the 24th resistor respectively, and the second end of the program debugging interface is electrically connected to the first end of the 23rd resistor and the first end of the 25th resistor respectively; The second end of the 22nd resistor is electrically connected to the power supply circuit, and the second end of the 24th resistor is electrically connected to the first serial port data output end of the micro control unit; A second end of the twenty-third resistor is electrically connected to the power supply circuit, and a second end of the twenty-fifth resistor is electrically connected to the first serial port data input end of the micro control unit.

11. The development circuit according to claim 1, characterized in that: The development circuit also includes a crystal oscillator circuit; The crystal oscillator circuit is electrically connected to the micro control unit; the crystal oscillator circuit is used to generate a clock signal of the micro control unit.

12. The development circuit according to claim 11, characterized in that: The crystal oscillator circuit comprises a first crystal oscillator sub-circuit and a second crystal oscillator sub-circuit; The first crystal oscillator sub-circuit is electrically connected to the power supply circuit and the micro control unit respectively; the first crystal oscillator sub-circuit is used to generate a clock signal when the micro control unit is working normally; The second crystal oscillator sub-circuit is electrically connected to the power supply circuit and the micro control unit respectively; the second crystal oscillator sub-circuit is used to generate a clock signal when the micro control unit is in sleep mode.

13. The development circuit according to claim 1, characterized in that: The development circuit also includes an alarm circuit; The alarm circuit is electrically connected to the power supply circuit and the micro control unit respectively; the alarm circuit is used to generate alarm information when the parameter information meets the preset conditions.

14. The development circuit according to claim 13, characterized in that: The alarm circuit includes a first transistor, a twenty-eighth resistor, a forty-third resistor, and a speaker; The collector of the first transistor is electrically connected to the first end of the forty-three resistors, the base of the first transistor is electrically connected to the first end of the twenty-eighth resistor, and the emitter of the first transistor is grounded; The second end of the 28th resistor is electrically connected to the 23rd input-output terminal of the micro control unit; The positive electrode of the speaker is electrically connected to the power supply circuit, and the negative electrode of the speaker is electrically connected to the second end of the forty-three resistors.

15. The development circuit according to claim 1, characterized in that: The development circuit also includes a storage circuit; The storage circuit is electrically connected to the power supply circuit and the micro control unit respectively.

16. The development circuit according to claim 1, characterized in that: The development circuit also includes a key circuit; The key circuit is electrically connected to the power supply circuit and the micro control unit respectively.

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