Display device

Abstract

The utility model relates to a display device capable of differentiating resonance distance according to the wavelength of light to be emitted in each pixel. The display device comprises a substrate; an interlayer insulating film disposed on the substrate and having a first trench and a second trench having different depths from each other; a first reflective electrode disposed inside the first trench; a (1-1)-th electrode connected to the first reflective electrode on the interlayer insulating film; a second reflective electrode disposed inside the second trench; a first-second electrode connected to the second reflective electrode on the interlayer insulating film; a second electrode on the (1-1) th electrode and the (1-2) th electrode; a first color filter disposed on the second electrode so as to overlap the (1-1)-th electrode; and a second color filter disposed on the second electrode so as to overlap the first and second electrodes, the interlayer insulating film includes a plurality of insulating films, at least two of the plurality of insulating films are composed of different substances, and at least one of the first trench and the second trench penetrates through the plurality of insulating films composed of different substances of the interlayer insulating film.

Description

Technical Field

[0001] The utility model relates to a display device, in particular to a display device capable of differentiating resonance distances according to the wavelength of light to be emitted in each pixel and a manufacturing method thereof. Background Art

[0002] A head mounted display (HMD) is a display device that is worn on the head by a user in the form of glasses or a helmet and forms a focus at a distance close to the eyes. A head mounted display can realize virtual reality (VR) or augmented reality (AR).

[0003] A head-mounted display is a device that uses multiple lenses to magnify and display an image displayed by a small display device. Therefore, the display device used in the head-mounted display may need to provide an image with high resolution, for example, an image with a resolution of 3000 PPI (Pixels Per Inch) or more. For this reason, as a display device used in a head-mounted display, a small-scale organic light-emitting display device 10 with high resolution, namely OLEDoS (Organic Light Emitting Diode on Silicon) is used. OLEDoS is a device that displays images by configuring an organic light-emitting diode (OLED) on a semiconductor wafer substrate configured with a complementary metal oxide semiconductor (CMOS, Complementary Metal Oxide Semiconductor).

[0004] Patent document: Korean Patent Publication No. 10-2022-0050298 (published on April 25, 2022) Utility Model Content

[0005] The utility model aims to provide a display device and a manufacturing method thereof, which can differentiate the resonance distance according to the wavelength of light to be emitted in each pixel.

[0006] The problems of the present invention are not limited to the problems mentioned above, and those skilled in the art can clearly understand other technical problems not mentioned from the following description.

[0007] In order to achieve the above-mentioned purpose, a display device according to an embodiment of the present invention includes: a substrate SSUB; an interlayer insulating film, which is arranged on the substrate and has a first groove TRC1 and a second groove TRC2 or TRC3 with different depths from each other; a first reflective electrode RE1, which is arranged inside the first groove; a 1-1 electrode AND1, which is connected to the first reflective electrode on the interlayer insulating film; a second reflective electrode RE2, which is arranged inside the second groove; a 1-2 electrode AND2, which is connected to the second reflective electrode on the interlayer insulating film; a second electrode CAT, which is on the 1-1 electrode and the 1-2 electrode; a first color filter CF1, which is arranged on the second electrode so as to overlap with the 1-1 electrode; and a second color filter CF2, which is arranged on the second electrode so as to overlap with the 1-2 electrode, the interlayer insulating film includes a plurality of insulating films IS1 to IS6, at least two of the plurality of insulating films are composed of substances different from each other, and at least one of the first groove and the second groove penetrates the plurality of insulating films composed of substances different from each other of the interlayer insulating film.

[0008] The number of insulating films penetrated by the first trench is different from the number of insulating films penetrated by the second trench.

[0009] The interlayer insulating film includes: a first insulating film; and a second insulating film disposed on the first insulating film adjacent to the first insulating film and composed of a material different from that of the first insulating film.

[0010] The interlayer insulating film includes a plurality of first insulating films and a plurality of second insulating films that are alternately arranged.

[0011] The first reflective electrode is disposed along an inner wall of the first groove, and the second reflective electrode is disposed along an inner wall of the second groove.

[0012] The first reflective electrode and the second reflective electrode each have a U-shaped cross section.

[0013] The semiconductor device further includes: a first intermediate insulating film MS1 disposed between the first reflective electrode and the 1-1 electrode; and a second intermediate insulating film MS2 disposed between the second reflective electrode and the 1-2 electrode.

[0014] The first interlayer insulating film is surrounded by the first reflective electrode and the 1-1 electrode, and the second interlayer insulating film is surrounded by the second reflective electrode and the 1-2 electrode.

[0015] The thickness of the first interlayer insulating film is different from the thickness of the second interlayer insulating film.

[0016] A distance between an inner side surface of a first reflective electrode disposed at an innermost side of the first groove and the second electrode is different from a distance between an inner side surface of a second reflective electrode disposed at an innermost side of the second groove and the second electrode.

[0017] The 1-1 electrode is connected to the transistor on the substrate through a contact hole CT connected to the first trench.

[0018] The 1-1 electrode is connected to the transistor on the substrate via a contact hole CT penetrating the interlayer insulating film.

[0019] The display device further includes an intermediate layer IL between the 1-1 electrode and between the 1-2 electrode and the second electrode.

[0020] The display device further includes a pixel defining layer PDL disposed between the 1-1 electrode, the 1-2 electrode, and the intermediate layer to define a light emitting region.

[0021] In addition, in order to achieve the above-mentioned purpose, a manufacturing method of a display device according to an embodiment of the present invention includes: a step of forming an interlayer insulating film including a plurality of insulating films on a substrate; a step of forming a first groove and a second groove having different depths in the interlayer insulating film; a step of forming a reflective electrode layer on an inner wall of the first groove, an inner wall of the second groove, and the interlayer insulating film; a step of forming an intermediate insulating film on the reflective electrode layer; a step of removing the reflective electrode layer on the interlayer insulating film and the intermediate insulating film on the interlayer insulating film, thereby forming a first intermediate insulating film and a second intermediate insulating film respectively arranged inside the first groove and inside the second groove and separated from each other while forming a first reflective electrode and a second reflective electrode respectively arranged along the inner wall of the first groove and the inner wall of the second groove and separated from each other; a step of forming a 1-1 electrode connected to the first reflective electrode and a 1-2 electrode connected to the first reflective electrode on the interlayer insulating film, at least two of the plurality of insulating films include different substances, and at least one of the first groove and the second groove penetrates through the plurality of insulating films including different substances of the interlayer insulating film.

[0022] The step of removing the reflective electrode layer on the interlayer insulating film and the intermediate insulating film is performed by chemical mechanical polishing.

[0023] Details of other embodiments are included in the detailed description and drawings.

[0024] According to the display device and the manufacturing method thereof of the utility model, the depth of the groove is formed to be different for each pixel, so that the resonance distance can be adjusted differently for each pixel. Thus, while simplifying the process steps, the microcavity (Micro-cavity; or thin film resonance) effect for light can be increased and / or optimized according to the wavelength of light to be emitted in each pixel and the corresponding resonance distance and / or resonance number, etc.

[0025] Furthermore, since trenches having different depths are formed using a plurality of insulating films having different etching ratios, the depth of the trench can be more accurately controlled for each pixel.

[0026] On the other hand, the effects obtained in the present invention are not limited to the effects mentioned above, and a person having ordinary knowledge in the technical field to which the present invention belongs can clearly understand other effects not mentioned from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is an exploded perspective view showing a display device according to an embodiment.

[0028] Figure 2 It is shown Figure 1 A layout diagram of an example of a display panel shown.

[0029] Figure 3 is a block diagram showing a display device according to an embodiment.

[0030] Figure 4 is an equivalent circuit diagram of a first pixel according to an embodiment.

[0031] Figure 5 is a diagram showing a layout of pixels of a display area according to an embodiment.

[0032] Figure 6 It is shown along Figure 5 A cross-sectional view of an example of a display device taken along line AA'.

[0033] Figure 7 is a perspective view showing a head mounted display device according to an embodiment.

[0034] Figure 8 It is shown Figure 7 An exploded perspective view of an example of a head-mounted display device.

[0035] Fig. 9 is a perspective view showing a head mounted display device according to an embodiment.

[0036] Fig.10 is a cross-sectional view of a display device according to an embodiment.

[0037] Fig.11 This is a diagram for explaining the connection relationship between an anode electrode and a transistor in a display device according to an embodiment.

[0038] Fig.12 This is a diagram for explaining the connection relationship between an anode electrode and a transistor in a display device according to an embodiment.

[0039] Figures 13 to 22 is a process cross-sectional view for explaining a method for manufacturing a display device according to an embodiment.

[0040] Fig.23 is a cross-sectional view of a display device according to an embodiment.

[0041] Fig.24 as well as Fig.25 is a process cross-sectional view for explaining a method for manufacturing a display device according to an embodiment.

[0042] (Explanation of Reference Numerals)

[0043] INS9: Ninth interlayer insulation film

[0044] INS10: Tenth interlayer insulation film

[0045] IS1: First insulation film

[0046] IS2: Second insulation film

[0047] IS3: Third insulation film

[0048] IS4: Fourth Insulation Film

[0049] IS5: The Fifth Insulation Film

[0050] IS6: Sixth Insulation Film

[0051] TRC1: First groove

[0052] TRC2: Second groove

[0053] TRC3: Third groove

[0054] PDL: Pixel Definition Layer

[0055] RE1: First reflective electrode

[0056] RE2: Second reflective electrode

[0057] RE3: The third reflective electrode

[0058] MS1: First intermediate insulating film

[0059] MS2: Second intermediate insulating film

[0060] MS3: Third intermediate insulating film

[0061] AND1: First anode electrode

[0062] AND2: Second anode electrode

[0063] AND3: The third anode electrode

[0064] IL: Intermediate Layer

[0065] CAT: Second electrode

[0066] TFE: Encapsulation layer

[0067] ADL: Adhesion layer

[0068] CF1: First Color Filter

[0069] CF2: Second color filter

[0070] CF3: Third Color Filter

[0071] LNS: Lens

[0072] PX1: The First Pixel

[0073] PX2: The Second Pixel

[0074] PX3: The Third Pixel

[0075] EA1: First light-emitting area

[0076] EA2: Second light emitting area

[0077] EA3: The third luminous area DETAILED DESCRIPTION

[0078] If you refer to the attached Figure 1 The advantages and features of the utility model and the methods for achieving them will become clear from the detailed embodiments described below. However, the utility model is not limited to the embodiments disclosed below, and will be implemented in various forms different from each other. The embodiments are only provided to make the disclosure of the utility model complete, in order to fully inform the scope of the utility model to those who have common knowledge in the technical field to which the utility model belongs. The utility model is only defined by the scope of the claimed rights.

[0079] Reference to an element or layer being "on" another element or layer includes all situations where the element is directly on top of the other element or has another layer or other element interposed therebetween. The same reference numerals throughout the specification refer to the same constituent elements. The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings used to illustrate the embodiments are exemplary, and the present invention is not limited to the matters shown in the drawings.

[0080] Although the terms first, second, etc. are used to describe a variety of components, these components are of course not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, of course, the first component mentioned below can also be the second component within the technical concept of the present disclosure.

[0081] Each feature of the various embodiments of the present invention may be combined or combined partially or in whole, and various linkages and drives may be implemented technically. The various embodiments may be implemented independently of each other, or may be implemented together as an associated relationship.

[0082] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0083] Figure 1 is an exploded perspective view showing a display device according to an embodiment. Figure 2 It is shown Figure 1 A layout diagram of an example of a display panel shown. Figure 3 is a block diagram showing a display device according to an embodiment.

[0084] Reference Figure 1 and Figure 2 According to one embodiment, the display device 10 is a device for displaying dynamic images or still images. According to one embodiment, the display device 10 can be applied to portable electronic devices such as mobile phones (Mobile Phone), smart phones (SmartPhone), tablet PCs (Tablet Personal Computer), mobile communication terminals, electronic manuals, electronic books, PMPs (Portable Multimedia Players), navigators, and UMPCs (Ultra Mobile PCs). For example, the display device 10 can be applied as a display unit of a television, a notebook computer, a monitor, an advertising board, or the Internet of Things (IOT). Alternatively, the display device 10 can be applied to a smart watch (Smart Watch), a watch phone (Watch Phone), and a head-mounted display (Head Mounted Display, HMD) for realizing virtual reality and augmented reality.

[0085] A display device 10 according to an embodiment includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , and a driving circuit 450 .

[0086] The display panel 100 may be formed of a quadrilateral and similar plane forms. For example, the display panel 100 may have a quadrilateral and similar plane forms having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be formed into a circle or a right angle in a manner having a predetermined curvature. The plane form of the display panel 100 is not limited to a quadrilateral, and may be formed similarly to other polygons, circles, or ellipses. The plane form of the display device 10 may follow the plane form of the display panel 100, but the embodiments of the present specification are not limited thereto.

[0087] like Figure 2 As shown, the display panel 100 includes a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0088] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of light emission control lines EL, and a plurality of data lines DL.

[0089] Each of the plurality of pixels PX includes a light emitting element that emits light. The plurality of pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of light emitting control lines EL may extend in the first direction DR1 and be arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and be arranged in the first direction DR1.

[0090] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of light emission control lines EL include a plurality of first light emission control lines EL1 and a plurality of second light emission control lines EL2.

[0091] The plurality of unit pixels UPX include a plurality of pixels PX1, PX2, and PX3. The plurality of pixels PX1, PX2, and PX3 may be as follows Figure 4 The plurality of pixel transistors are formed by a semiconductor process and are arranged on a semiconductor substrate ( Figure 6 For example, a plurality of pixel transistors may be formed by complementary metal oxide semiconductors (CMOS, Complementary Metal Oxide Semiconductor).

[0092] Each of the plurality of pixels PX1, PX2, and PX3 can be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines GBL, any one of the plurality of first light-emitting control lines EL1, any one of the plurality of second light-emitting control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 can receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and the light-emitting element emits light according to the data voltage.

[0093] The non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0094] The scanning driving area SDA may be an area where the scanning driving unit 610 and the light emitting driving unit 620 are arranged. Figure 2 In the example, the scanning driving unit 610 is configured on the left side of the display area DAA, and the light emitting driving unit 620 is configured on the right side of the display area DAA, but the embodiments of this specification are not limited thereto. For example, the scanning driving unit 610 and the light emitting driving unit 620 can be configured on both the left and right sides of the display area DAA.

[0095] The scanning driving unit 610 includes a plurality of scanning transistors, and the light emitting driving unit 620 includes a plurality of light emitting transistors. The plurality of scanning transistors and the plurality of light emitting transistors may be formed by a semiconductor process and formed on a semiconductor substrate ( Figure 6 For example, the plurality of scanning transistors and the plurality of light emitting transistors may be formed of a complementary metal oxide semiconductor (CMOS).

[0096] The scan driving unit 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400 and sequentially output it to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS and sequentially output it to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS and sequentially output it to the bias scan line EBL.

[0097] The light-emitting driving section 620 includes a first light-emitting control driving section 621 and a second light-emitting control driving section 622. Each of the first light-emitting control driving section 621 and the second light-emitting control driving section 622 can receive a light-emitting timing control signal ECS from the timing control circuit 400. The first light-emitting control driving section 621 can generate a first light-emitting control signal according to the light-emitting timing control signal ECS and sequentially output it to the first light-emitting control line EL1. The second light-emitting control driving section 622 can generate a second light-emitting control signal according to the light-emitting timing control signal ECS and sequentially output it to the second light-emitting control line EL2.

[0098] The data driving area DDA may be an area where the data driving unit 700 is configured. The data driving unit 700 may include a plurality of data transistors, which are formed by a semiconductor process and formed on a semiconductor substrate ( Figure 6 For example, the plurality of data transistors may be formed of a complementary metal oxide semiconductor (CMOS).

[0099] The data driving unit 700 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 400. The data driving unit 700 may convert the digital video data DATA into an analog data voltage according to the data timing control signal DCS and output the analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 are selected by the write scan signal of the scan driving unit 610, and the data voltage is supplied to the selected pixels PX1, PX2, and PX3.

[0100] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may not be covered by a cover layer ( Figure 6 CVL) and a polarizing plate (not shown) are covered and exposed.

[0101] The heat dissipation layer 200 may overlap the display panel 100 in the thickness direction of the display panel 100, that is, in the third direction DR3. The heat dissipation layer 200 may be disposed on one side of the display panel 100, for example, on the back side. The heat dissipation layer 200 serves to dissipate heat generated in the display panel 100. The heat dissipation layer 200 may include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al) having high thermal conductivity.

[0102] The circuit board 300 may be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 100 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film having a soft material. Figure 1 In the embodiment, the circuit board 300 is illustrated as being unfolded, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the back surface of the display panel 100. The one end of the circuit board 300 may be an opposite end of the other end of the circuit board 300 connected to the plurality of pads PD of the pad area PDA of the display panel 100 using a conductive adhesive member.

[0103] The driving circuit 450 may include a timing control circuit 400 and a power supply circuit 500 .

[0104] The timing control circuit 400 may receive digital video data DATA and a timing signal from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 according to the timing signal. The timing control circuit 400 may output the scan timing control signal SCS to the scan driving section 610 and the light emission timing control signal ECS to the light emission driving section 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driving section 700.

[0105] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply them to the display panel 100. The description of the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be combined with Figure 4 This will be described later.

[0106] The timing control circuit 400 and the power supply circuit 500 may be formed of respective integrated circuits (ICs) and attached to one side of the circuit board 300. The scanning timing control signal SCS, the light emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0107] Figure 4 is an equivalent circuit diagram of a first pixel according to an embodiment.

[0108] Reference Figure 4 , the first pixel PX1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first light-emitting control line EL1, the second light-emitting control line EL2 and the data line DL. In addition, the first pixel PX1 can be connected to the first drive voltage line VSL that applies the first drive voltage VSS equivalent to the low potential voltage, the second drive voltage line VDL that applies the second drive voltage VDD equivalent to the high potential voltage, and the third drive voltage line VIL that applies the third drive voltage VINT equivalent to the initialization voltage. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. At this time, the first drive voltage VSS can be a voltage lower than the third drive voltage VINT. The second drive voltage VDD can be a voltage higher than the third drive voltage VINT.

[0109] The first pixel PX1 includes a plurality of transistors T1 - T6 , a light emitting element (LE), a first capacitor C1 , and a second capacitor C2 .

[0110] The light emitting element ED emits light according to the driving current Ids flowing in the channel of the first transistor T1. The light emission of the light emitting element ED may be proportional to the driving current Ids. The light emitting element ED may be arranged between the fourth transistor T4 and the first driving voltage line VSL. It may be that the first electrode of the light emitting element ED is connected to the drain electrode of the fourth transistor T4, and the second electrode is connected to the first driving voltage line VSL. It may be that the first electrode of the light emitting element ED is an anode electrode, and the second electrode of the light emitting element ED is a cathode electrode. The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer arranged between the first electrode and the second electrode, but the embodiments of the present specification are not limited thereto. For example, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode, but in this case, the light emitting element ED may be a micro light emitting diode.

[0111] The first transistor T1 may be a driving transistor that controls a driving current Ids flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0112] The second transistor T2 may be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Thus, the data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0113] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 connects the first node N1 to the second node N2 by turning on the write control signal of the control scan line GCL. Thus, the gate electrode and the source electrode of the first transistor T1 are connected, so that the first transistor T1 can work as a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0114] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first light emission control signal of the first light emission control line EL1 to connect the second node N2 to the third node N3. Thus, the driving current of the first transistor T1 may be supplied to the light emitting element ED. The fourth transistor T4 includes a gate electrode connected to the first light emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0115] The fifth transistor T5 may be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scanning signal of the bias scanning line EBL and connects the third node N3 to the third driving voltage line VIL. Thus, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element ED. The fifth transistor T5 includes a gate electrode connected to the bias scanning line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0116] The sixth transistor T6 can be configured between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second light emitting control signal of the second light emitting control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Thus, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second light emitting control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0117] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0118] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0119] The first node N1 is a connection point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a connection point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a connection point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element ED.

[0120] Each of the first to sixth transistors T1 to T6 may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the embodiments of the present specification are not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, each of a portion of the transistors in the first to sixth transistors T1 to T6 may be a P-type MOSFET, and each of the remaining transistors may be an N-type MOSFET.

[0121] exist Figure 4 In the example, the first pixel PX1 is illustrated as including six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to the following. Figure 4 For example, the number of transistors and the number of capacitors of the first pixel PX1 are not limited to Figure 4 As shown.

[0122] In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be combined with Figure 4 The equivalent circuit diagram of the first pixel PX1 described above is substantially the same, and therefore, description of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 will be omitted in this specification.

[0123] Figure 5 is a diagram showing a layout of pixels of a display area according to an embodiment.

[0124] Reference Figure 5 Each of the plurality of pixels PX includes a first light emitting area EA1 of a first pixel PX1, a second light emitting area EA2 of a second pixel PX2, and a third light emitting area EA3 of a third pixel PX3.

[0125] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a rectangular, square, or rhombus-like quadrilateral plane form. For example, the first light emitting area EA1 may have a rectangular plane form having short sides in the first direction DR1 and long sides in the second direction DR2. In addition, each of the second light emitting area EA2 and the third light emitting area EA3 may have a rectangular plane form having long sides in the first direction DR1 and short sides in the second direction DR2.

[0126] The length of the first direction DR1 of the first light emitting area EA1 may be smaller than that of the second light emitting area EA2 and smaller than that of the third light emitting area EA3. The length of the first direction DR1 of the second light emitting area EA2 and the length of the first direction DR1 of the third light emitting area EA3 may be substantially the same.

[0127] The length of the first light emitting area EA1 in the second direction DR2 may be greater than the sum of the second light emitting area EA2 and the third light emitting area EA3. The length of the second light emitting area EA2 in the second direction DR2 may be less than the length of the third light emitting area EA3 in the second direction DR2.

[0128] exist Figure 5 In the example, each of the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3 has a quadrilateral plane form, but the embodiments of the present specification are not limited thereto. For example, each of the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3 may have a plane form other than a quadrilateral, a circle or an ellipse.

[0129] In each of the plurality of pixels PX, the first light emitting region EA1 and the second light emitting region EA2 may be adjacent in the first direction DR1. In addition, the first light emitting region EA1 and the third light emitting region EA3 may be adjacent in the first direction DR1. In addition, the second light emitting region EA2 and the third light emitting region EA3 may be adjacent in the second direction DR2. The area of ​​the first light emitting region EA1, the area of ​​the second light emitting region EA2, and the area of ​​the third light emitting region EA3 may be different.

[0130] The first light emitting area EA1 may emit light of a first color, the second light emitting area EA2 may emit light of a second color, and the third sub-pixel BP may emit light of a third color. Here, the light of the first color may be light of a cyan wavelength band, the light of the second color may be light of a green wavelength band, and the light of the third color may be light of a red wavelength band. For example, the cyan wavelength band may refer to a wavelength band in which the main peak wavelength of the light is approximately 370nm to 460nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is approximately 480nm to 560nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is approximately 600nm to 750nm.

[0131] exist Figure 5 In the example, each of the plurality of pixels PX includes three light emitting areas EA1, EA2, and EA3, but the embodiments of the present specification are not limited thereto. That is, each of the plurality of pixels PX may also include four light emitting areas.

[0132] In addition, the arrangement of the light emitting regions of the plurality of pixels PX is not limited to Figure 5 For example, the light emitting regions of the plurality of pixels PX may be configured as a stripe structure in which the light emitting regions are arranged in the first direction DR1, or a diamond structure in which the light emitting regions are arranged. A hexagonal structure or a hexagonal structure in which light-emitting areas are arranged in a hexagonal planar form.

[0133] Figure 6 It is shown along Figure 5 A cross-sectional view of an example of a display device is taken along line AA'.

[0134] Reference Figure 6 The display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EMTL, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate.

[0135] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors TRS, a plurality of semiconductor insulating films covering the plurality of pixel transistors TRS, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors TRS. The plurality of pixel transistors TRS may be combined Figure 4 The first to sixth transistors T1 to T6 are described.

[0136] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first-type dopant. A plurality of well areas WA may be configured on the semiconductor substrate SSUB. The plurality of well areas WA may be regions doped with a second-type dopant. The second-type dopant may be different from the aforementioned first-type dopant. For example, in the case where the first-type dopant is a p-type dopant, the second-type dopant may be an n-type dopant. Alternatively, in the case where the first-type dopant is an n-type dopant, the second-type dopant may be a p-type dopant.

[0137] Each of the plurality of well regions WA includes a source area SA corresponding to a source electrode of the pixel transistor TRS, a drain area DA corresponding to a drain electrode, and a channel area CH disposed between the source area SA and the drain area DA.

[0138] Each of the source region SA and the drain region DA may be a region doped with a first type dopant. The gate electrode GE of the pixel transistor TRS may overlap with the well region WA in the third direction DR3. The channel region CH may overlap with the gate electrode GE in the third direction DR3. The source region SA may be configured on one side of the gate electrode GE, and the drain region DA may be configured on the other side of the gate electrode GE.

[0139] Each of the plurality of well regions WA further includes a first low-concentration dopant region LDD1 disposed between the channel region CH and the source region SA and a second low-concentration dopant region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration dopant region LDD1 may be a region having a lower dopant concentration than the source region SA. The second low-concentration dopant region LDD2 may be a region having a lower dopant concentration than the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration dopant region LDD1 and the second low-concentration dopant region LDD2. Therefore, the length of the channel region CH of each of the pixel transistors TRS may be increased, and thus punch-through and hot carrier phenomena may be prevented by a short channel.

[0140] The first semiconductor insulating film SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0141] The second semiconductor insulating film SINS2 may be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0142] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors TRS through a hole penetrating the first semiconductor insulating film SINS1 and the second interlayer insulating film INS2. The plurality of contact terminals CTE may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0143] A third semiconductor insulating film SINS3 may be disposed on the side of each of the plurality of contact terminals CTE. The top of each of the plurality of contact terminals CTE may not be covered by the third semiconductor insulating film SINS3 but may be exposed. The third semiconductor insulating film SINS3 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0144] A glass substrate or a polymer resin substrate such as polyimide can replace the semiconductor substrate SSUB. In this case, thin film transistors can be arranged on the glass substrate or the polymer resin substrate. The glass substrate is a rigid substrate that does not bend, and the polymer resin substrate is a flexible substrate that can be bent or curled.

[0145] The light emitting element back plate EBP includes first to eighth metal layers ML1-ML8, reflective metal layers RL1-RL4, a plurality of vias VA1-VA10 and a step layer STPL. In addition, the light emitting element back plate EBP includes a plurality of interlayer insulating films INS1-INS10 disposed between the first to sixth metal layers ML1-ML6.

[0146] The first to eighth metal layers ML1-ML8 are connected to a plurality of contact terminals CTE exposed in the semiconductor backplane SBP to realize Figure 4 The circuit of the first pixel PX1 shown in FIG. 1 is used. That is, only the first to sixth transistors T1 to T6 are formed on the semiconductor backplane SBP, and the connection between the first to sixth transistors T1 to T6 and the first capacitor C1 and the second capacitor C2 is formed by the first to eighth metal layers ML1 to ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4 and the source region corresponding to the source electrode of the fifth transistor T5 and the first electrode of the light emitting element ED is also formed by the first to eighth metal layers ML1 to ML8.

[0147] The first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first interlayer insulating film INS1 and be connected to the contact terminal CTE exposed in the semiconductor backplane SBP. Each of the first metal layers ML1 may be disposed on the first interlayer insulating film INS1 and connected to the first vias VA1.

[0148] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 may penetrate the second interlayer insulating film INS2 and be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and be connected to the second vias VA2.

[0149] The third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 may penetrate the third interlayer insulating film INS3 and be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and connected to the third vias VA3.

[0150] The fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 may penetrate the fourth interlayer insulating film INS4 and be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and connected to the fourth vias VA4.

[0151] The fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 may penetrate the fifth interlayer insulating film INS5 and be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and connected to the fifth vias VA5.

[0152] The sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 may penetrate the sixth interlayer insulating film INS6 and be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and be connected to the sixth vias VA6.

[0153] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 may penetrate the seventh interlayer insulating film INS7 and be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and connected to the seventh vias VA7.

[0154] The eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may penetrate the eighth interlayer insulating film INS8 and be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and be connected to the eighth vias VA8.

[0155] The first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be composed of substantially the same material. The first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. The first to eighth vias VA1 to VA8 may be composed of substantially the same material. The first to eighth interlayer insulating films INS1 to ILD8 may be composed of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0156] Each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same. For example, the thickness of the first metal layer ML1 is approximately Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 is approximately The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 is approximately

[0157] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same. For example, each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be approximately Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be approximately

[0158] The ninth interlayer insulating film INS9 may be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be made of silicon oxide (SiOx ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0159] Each of the ninth vias VA9 may pass through the ninth interlayer insulating film INS9 and be connected to the exposed eighth metal layer ML8. The ninth via VA9 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the ninth via VA9 may be approximately

[0160] Each of the first reflective metal layers RL1 may be disposed on the ninth interlayer insulating film INS9 and connected to the ninth via VA9. The first reflective metal layer RL1 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0161] Each of the second reflective metal layers RL2 may be disposed on the first reflective metal layer RL1. The second reflective metal layer RL2 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the second reflective metal layer RL2 may be titanium nitride TiN.

[0162] In the first pixel PX1, a step layer STPL may be configured on the second reflective metal layer RL2. The step layer STPL may not be configured in each of the second pixel PX2 and the third pixel PX3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first light emitting layer EML1 to the fourth reflective metal layer RL4 so as to facilitate reflection of the light of the first color emitted from the first light emitting layer EML1 of the first pixel PX1. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of the present specification are not limited thereto. The thickness of the step layer STPL can be approximately

[0163] In the first pixel PX1, the third reflective metal layer RL3 may be disposed on the second reflective metal layer RL2 and the step layer STPL. In the second pixel PX2 and the third pixel PX3, the third reflective metal layer RL3 may be disposed on the second reflective metal layer RL2. The third reflective metal layer RL3 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0164] At least one of the first reflective metal layer RL1, the second reflective metal layer RL2, and the third reflective metal layer RL3 may be omitted.

[0165] Each of the fourth reflective metal layers RL4 can be configured on the third reflective metal layer RL3. The fourth reflective metal layer RL4 can be a layer that reflects light from the first to third light-emitting layers EML1, EML2, and EML3. The fourth reflective metal layer RL4 may include a metal with high reflectivity to facilitate reflection of light. The fourth reflective metal layer RL4 may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an alloy of silver (Ag), palladium (Pd), and copper (Cu), namely an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the embodiments of the present specification are not limited thereto. The thickness of each of the fourth reflective metal layers RL4 may be approximately

[0166] The tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9 and the fourth reflective metal layer RL4. The tenth interlayer insulating film INS10 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0167] Each of the tenth vias VA10 may penetrate the tenth interlayer insulating film INS10 and be connected to the exposed ninth metal layer ML9. The tenth via VA10 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. Due to the step layer STPL, the thickness of the tenth via VA10 in the first pixel PX1 may be less than the thickness of the tenth via VA10 in each of the second pixel PX2 and the third pixel PX3. For example, the thickness of the tenth via VA10 in the first pixel PX1 may be approximately The thickness of the tenth via VA10 in each of the second pixel PX2 and the third pixel PX3 is approximately

[0168]

[0169] The light emitting device layer EMTL may be disposed on the light emitting device backplane EBP. The light emitting device layer EMTL may include a light emitting device ED including a first electrode AND, an intermediate layer IL, and a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0170] The first electrode AND of each of the light emitting elements ED may be disposed on the tenth interlayer insulating film INS10 and connected to the tenth via VA1. The first electrode AND of each of the light emitting elements ED may be connected to the drain region DA or the source region SA of the pixel transistor TRS through the tenth via VA10, the first to fourth reflective metal layers RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements ED may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the light emitting elements ED may be titanium nitride TiN.

[0171] The pixel defining film PDL may be disposed on a portion of the first electrode AND of each light emitting element ED. The pixel defining film PDL may cover the edge of the first electrode AND of each light emitting element ED. The pixel defining film PDL may play a role in dividing the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0172] The first light emitting region EA1 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second light emitting region EA2 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third light emitting region EA3 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0173] The pixel defining film PDL may include first to third pixel defining films PDL1, PDL2, and PDL3. The first pixel defining film PDL1 may be disposed on the edge of each first electrode AND of the light emitting element ED, the second pixel defining film PDL2 may be disposed on the first pixel defining film PDL1, and the third pixel defining film PDL3 may be disposed on the second pixel defining film PDL2. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of the present specification are not limited thereto. The thickness of the first pixel defining film PDL1, the thickness of the second pixel defining film PDL2, and the thickness of the third pixel defining film PDL3 may be approximately

[0174] Each of the plurality of trenches TRC may penetrate the first pixel defining film PDL1 , the second pixel defining film PDL2 , and the third pixel defining film PDL3 . In each of the plurality of trenches TRC, a portion of the tenth interlayer insulating film INS10 may have a recessed form.

[0175] At least one trench TRC may be disposed between adjacent pixels PX1, PX2, and PX3. Figure 6 In the example shown in FIG. 1 , two trenches TRC are arranged between adjacent pixels PX1 , PX2 , and PX3 , but the embodiments of the present specification are not limited thereto.

[0176] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0177] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, IL3 that emit light different from each other. For example, the intermediate layer IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked in sequence.

[0178] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0179] A first charge generation layer for supplying charges to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. A second charge generation layer for supplying charges to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be disposed between the second intermediate layer IL2 and the third intermediate layer IL3.

[0180] The first intermediate layer IL1 can be configured on the first electrode AND and the pixel defining film PDL, and is configured on the bottom surface of the groove TRC in each of the grooves TRC. Due to the groove TRC, the first intermediate layer IL1 can be disconnected between the pixels PX1, PX2, and PX3 adjacent to each other. The second intermediate layer IL2 can be configured on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 can be disconnected between the pixels PX1, PX2, and PX3 adjacent to each other. The third intermediate layer IL3 can be configured on the second intermediate layer IL2. Due to the groove TRC, the third intermediate layer IL3 can be disconnected between the pixels PX1, PX2, and PX3 adjacent to each other. That is, each of the plurality of grooves TRC can be a structure for disconnecting the first to third intermediate layers IL1, IL2, and IL3 of the light emitting element layer EMTL between the pixels PX1, PX2, and PX3 adjacent to each other.

[0181] In order to stably disconnect the first to third intermediate layers IL1, IL2, IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2, PX3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining film PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3.

[0182] In order to disconnect the first to third intermediate layers IL1, IL2, IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2, PX3, another structure may be provided instead of the trench TRC. For example, a reverse tapered partition wall may be provided on the pixel defining layer PDL instead of the trench TRC.

[0183] The number of intermediate layers IL1, IL2, IL3 that emit light different from each other is not limited to Figure 6 As shown. For example, the intermediate layer IL may include two intermediate layers. In this case, it may be that either of the two intermediate layers is substantially the same as the first intermediate layer IL1, and the other includes a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to either intermediate layer and supplying charges to the other intermediate layer may be configured between the two intermediate layers.

[0184] In addition, Figure 6 The example is that the first to third intermediate layers IL1, IL2, and IL3 are all configured in the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, but the embodiments of this specification are not limited to this. For example, the first intermediate layer IL1 can be configured in the first light-emitting area EA1, and not configured in the second light-emitting area EA2 and the third light-emitting area EA3. In addition, the second intermediate layer IL2 can be configured in the second light-emitting area EA2, and not configured in the first light-emitting area EA1 and the third light-emitting area EA3. In addition, the third intermediate layer IL3 can be configured in the third light-emitting area EA3, and not configured in the first light-emitting area EA1 and the second light-emitting area EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0185] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of grooves TRC. The second electrode CAT may be formed of a transparent conductive material TCO (Transparent Conductive Material) such as ITO, IZO, or a semi-transmissive metal material (Semi-transmissive Conductive Material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag) that can transmit light. In the case where the second electrode CAT is formed of a semi-transmissive metal material, the light extraction efficiency in each of the first to third pixels PX1, PX2, and PX3 may be improved through a micro cavity.

[0186] The encapsulation layer TFE may be disposed on the light emitting element layer EMTL. The encapsulation layer TFE may include at least one inorganic film TFE1, TFE3 to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer TFE may include at least one organic film to protect the light emitting element layer EMTL from impurities such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0187] The first encapsulating inorganic film TFE1 may be disposed on the second electrode CAT, the encapsulating organic film TFE2 may be disposed on the first encapsulating inorganic film TFE1, and the second encapsulating inorganic film TFE3 may be disposed on the encapsulating organic film TFE2. The first encapsulating inorganic film TFE1 and the second encapsulating inorganic film TFE3 may be formed by alternately stacking silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x) and aluminum oxide layer (AlO x ) is formed by a multilayer film of one or more inorganic films. The encapsulating organic film TFE2 may be a monomer. Alternatively, the encapsulating organic film TFE2 may be an organic film of acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0188] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0189] The optical layer OPL includes a plurality of color filters CF1, CF2, CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, CF3 may include first to third color filters CF1, CF2, CF3. The first to third color filters CF1, CF2, CF3 may be disposed on the adhesive layer ADL.

[0190] The first color filter CF1 may overlap with the first light emitting area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of the first color, that is, light of the cyan wavelength band. The cyan wavelength band may be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 may transmit light of the first color in the light emitted from the first light emitting area EA1.

[0191] The second color filter CF2 may overlap with the second light emitting area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of the second color, i.e., light of the green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 may transmit light of the second color in the light emitted from the second light emitting area EA2.

[0192] The third color filter CF3 may overlap with the third light emitting area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color, i.e., light of a red wavelength band. The cyan wavelength band may be approximately 600 nm to 750 nm. Therefore, the third color filter CF3 may transmit light of a third color in the light emitted from the third light emitting area EA3.

[0193] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light toward the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0194] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL has a predetermined refractive index in order to allow light to travel in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film of acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0195] The covering layer CVL can be arranged on the filling layer FIL. The covering layer CVL can be a glass substrate or a polymer resin such as a resin. When the covering layer CVL is a glass substrate, it can be attached to the filling layer FIL. In this case, the filling layer FIL can play a role in bonding the covering layer CVL. When the covering layer CVL is a glass substrate, it can play a role of a packaging substrate. When the covering layer CVL is a polymer resin such as a resin, it can be directly coated on the filling layer FIL.

[0196] The polarizing plate may be disposed on one side of the cover layer CVL. The polarizing plate may be a structure for preventing visibility reduction due to external light reflection. The polarizing plate may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter-wave plate), but the embodiments of the present specification are not limited thereto. However, in the case where visibility due to external light reflection is sufficiently improved by the first to third color filters CF1, CF2, CF3, the polarizing plate may also be omitted.

[0197] Figure 7 is a perspective view showing a head mounted display device according to an embodiment. Figure 8 It is shown Figure 7 An exploded perspective view of an example of a head-mounted display device.

[0198] Reference Figure 7 and Figure 8According to one embodiment, a head-mounted display device 1000 includes a first display device 10_1, a second display device 10_2, a display device storage portion 1100, a storage cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical component 1510, a second optical component 1520, a control circuit board 1600 and a connector 1610.

[0199] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 6 The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 are omitted.

[0200] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0201] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600, and disposed between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 supports and fixes the first display device 10_1, the second display device 10_2 and the control circuit board 1600.

[0202] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device receiving portion 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through the connector 1610. The control circuit board 1600 converts an image source input from the outside into digital video data DATA, and transmits the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector 1610.

[0203] The control circuit board 1600 may transmit the digital video data DATA of the left-eye image most suitable for the user's left eye to the first display device 10_1, and transmit the digital video data DATA of the right-eye image most suitable for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0204] The display device storage portion 1100 serves to store the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical component 1510, the second optical component 1520, the control circuit board 1600, and the connector 1610. The storage cover 1200 is configured to cover an open side of the display device storage portion 1100. The storage cover 1200 may include a first eyepiece 1210 configured for the user's left eye and a second eyepiece 1220 configured for the user's right eye. Figure 7 and Figure 8 In the example, the first eyepiece 1210 and the second eyepiece 1220 are configured separately, but the embodiments of the present specification are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be integrated into one.

[0205] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user may view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and may view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0206] The headband 1300 serves to fix the display device storage unit 1100 on the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the storage cover 1200 can be kept in a state where they are respectively arranged on the left eye and the right eye of the user. When the display device storage unit 1100 is implemented to be lightweight and small, the head mounted display device 1000 may include a headband 1300 instead of the headband 1300. Fig. 9 That kind of glasses frame.

[0207] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external storage slot for storing an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a WIFI module, or a Bluetooth module.

[0208] Fig. 9 is a perspective view showing a head mounted display device according to an embodiment.

[0209] Reference Fig. 9According to an embodiment, the head mounted display device 1000_1 may be a display device in which the display device storage portion 1200_1 is implemented as a lightweight and compact glasses form. According to an embodiment, the head mounted display device 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, glasses frame legs 1040, 1050, an optical component 1060, an optical path conversion component 1070, and a display device storage portion 1200_1.

[0210] The display device storage portion 1200_1 may include a display device 10_3, an optical component 1060, and an optical path conversion component 1070. The image displayed on the display device 10_3 may be magnified by the optical component 1060, and the optical path is converted by the optical path conversion component 1070 to be provided to the right eye of the user through the right eye lens 1020. Thus, the user may view an augmented reality image that is a combination of a virtual image displayed on the display device 10_3 through the right eye and a real image viewed through the right eye lens 1020.

[0211] exist Fig. 9 The example in the figure shows that the display device storage part 1200_1 is configured at the right end of the support frame 1030, but the embodiments of this specification are not limited to this. For example, the display device storage part 1200_1 can be configured at the left end of the support frame 1030, in which case the image of the display device 10_3 can be provided to the left eye of the user. Alternatively, the display device storage part 1200_1 can be configured entirely at the left end and the right end of the support frame 1030, in which case the user can view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0212] Fig.10 is a cross-sectional view of a display device according to an embodiment.

[0213] Reference Fig.10 The ninth interlayer insulating film INS9 may be disposed on the semiconductor substrate SSUB (hereinafter, substrate SSUB). Figure 6 The same as the ninth interlayer insulating film INS9.

[0214] A tenth interlayer insulating film INS10 may be configured on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 may include a plurality of insulating films having different etching ratios from each other. For example, the tenth interlayer insulating film INS10 may be sequentially stacked along the third direction DR3 on the ninth interlayer insulating film INS9, and include a first insulating film IS1, a second insulating film IS2, a third insulating film IS3, a fourth insulating film IS4, a fifth insulating film IS5, and a sixth insulating film IS6 having different etching ratios from each other. In other words, the tenth interlayer insulating film INS10 may include a first insulating film IS1, a second insulating film IS2, a third insulating film IS3, a fourth insulating film IS4, a fifth insulating film IS5, and a sixth insulating film IS6 sequentially stacked along the third direction DR3 on the ninth interlayer insulating film INS9, and at least two of the insulating films IS1 to IS6 may include different substances from each other. For example, two insulating films adjacent to each other in the third direction DR3 may include different substances from each other.

[0215] The insulating films adjacent to each other among the plurality of insulating films included in the tenth interlayer insulating film INS10 may have different etching ratios from each other. For example, the first insulating film IS1 and the second insulating film IS2 may be insulating films having different etching ratios from each other. In one embodiment, the first insulating film IS1 may be a SiN x The second insulating film IS2 may be an insulating film including SiO x As a specific example, SiN x and SiO x It can have an etching ratio of 1:5. In this case, for the same etching solution, SiO x SiN x Etches 5 times more.

[0216] The insulating films that are spaced apart from each other among the plurality of insulating films included in the tenth interlayer insulating film INS10 may have the same etching ratio as each other. For example, the first insulating film IS1, the third insulating film IS3, and the fifth insulating film IS5 may be insulating films having the same etching ratio. In one embodiment, the first insulating film IS1, the third insulating film IS3, and the fifth insulating film IS5 may be insulating films each including SiN x In addition, in one embodiment, the second insulating film IS2, the fourth insulating film IS4 and the sixth insulating film IS6 may be made of SiO xFor example, the first insulating film IS1, the third insulating film IS3, and the fifth insulating film IS5 may be insulating films having the same material, and the second insulating film IS2, the fourth insulating film IS4, and the sixth insulating film IS6 may be insulating films having the same material. In one embodiment, the interlayer insulating film may have a stacked structure in which insulating films having different etching ratios are alternately arranged along the third direction DR3.

[0217] On the other hand, adjacent insulating films may have different thicknesses from each other. For example, the second insulating film IS2 may have a greater thickness than the first insulating film IS1. At this time, the first insulating film IS1, the third insulating film IS3, and the fifth insulating film IS5 may have the same thickness as each other, and the second insulating film IS2, the fourth insulating film IS4, and the sixth insulating film IS6 may have the same thickness as each other. Here, the thickness may mean the size in the third direction DR3. For example, the SiN x Each insulating film (eg, IS1, IS3, IS5) may have to The thickness of SiO x Each insulating film (eg, IS2, IS4, IS6) may have to Thickness.

[0218] The tenth interlayer insulating film INS10 may have a plurality of grooves having different depths from each other. Here, the depth means the size in the third direction DR3. For example, the tenth interlayer insulating film INS10 may have a first groove TRC1 configured corresponding to the first pixel PX1 (or the first light emitting area EA1 of the first pixel PX1, or the first color filter CF1 of the first pixel PX1), a second groove TRC2 configured corresponding to the second pixel PX2 (or the second light emitting area EA2 of the second pixel PX2, or the second color filter CF2 of the second pixel PX2), and a third groove TRC3 configured corresponding to the third pixel PX3 (or the third light emitting area EA3 of the third pixel PX3, or the third color filter CF3 of the third pixel PX3), as shown in FIG. Fig.10 As shown, the aforementioned first to third grooves TRC1-TRC3 may have different depths from each other. For example, the second groove TRC2 overlapping with the second color filter CF2 may have a greater depth than the third groove TRC3 overlapping with the third color filter CF3, and the first groove TRC1 overlapping with the first color filter CF1 may have a greater depth than the second groove TRC2 overlapping with the second color filter CF2. In other words, the depth of the second groove TRC2 may be greater than the depth of the third groove TRC3, and less than the depth of the first groove TRC1.

[0219] As mentioned above, in order to make the depth of each groove TRC1-TRC3 different, for example, the number of insulating films penetrated by the first groove TRC1, the second groove TRC2 and the third groove TRC3 may be different. For example, in one embodiment, the first groove TRC1 can penetrate the sixth insulating film IS6, the fifth insulating film IS5, the fourth insulating film IS4, the third insulating film IS3 and the second insulating film IS2. On the other hand, although not shown, a portion of the first insulating film IS1 is removed through the first groove TRC1. The second groove TRC2 can penetrate the sixth insulating film IS6, the fifth insulating film IS5 and the fourth insulating film IS4. On the other hand, although not shown, a portion of the third insulating film IS3 can be removed through the second groove TRC2. The third groove TRC3 can penetrate the sixth insulating film IS6. On the other hand, although not shown, a portion of the fifth insulating film IS5 can be removed through the third groove TRC3.

[0220] In one embodiment, the first color filter CF1 may be a red filter, the second color filter CF2 may be a green filter, and the third color filter CF3 may be a cyan filter. In addition, in one embodiment, the first color filter CF1 may be a cyan filter, the second color filter CF2 may be a green filter, and the third color filter CF3 may be a red filter. In addition, in one embodiment, the first color filter CF1 may be a red filter, the second color filter CF2 may be a cyan filter, and the third color filter CF3 may be a green filter. In addition, in one embodiment, the first color filter CF1 may be a green filter, the second color filter CF2 may be a cyan filter, and the third color filter CF3 may be a red filter.

[0221] The aforementioned red filter can transmit red light and block light of other colors (e.g., cyan light and green light), the aforementioned green filter can transmit green light and block light of other colors (e.g., red light and cyan light), and the aforementioned cyan filter can transmit cyan light and block light of other colors (e.g., red light and green light).

[0222] A 1-1 electrode AND1 (hereinafter, a first anode electrode AND1 ), a 1-2 electrode AND2 (hereinafter, a second anode electrode AND2 ), and a 1-3 electrode AND3 (hereinafter, a third anode electrode AND3 ) may be disposed on the tenth interlayer insulating film INS10 .

[0223] The first reflective electrode RE1, the second reflective electrode RE2 and the third reflective electrode RE3 may be respectively disposed in the first trench TRC1, the second trench TRC2 and the third trench TRC3 of the tenth interlayer insulating film INS10. For example, the first reflective electrode RE1 may be disposed along the inner wall of the first trench TRC1, the second reflective electrode RE2 may be disposed along the inner wall of the second trench TRC2 and the third reflective electrode RE3 may be disposed along the inner wall of the third trench TRC3. In one embodiment, the first reflective electrode RE1, the second reflective electrode RE2 and the third reflective electrode RE3 may respectively have a U-shaped cross section. In one embodiment, each reflective electrode RE1-RE3 may include the aforementioned Figure 6 The first to fourth reflective metal layers RL1-RL4 are shown. For example, the first reflective electrode RE1 includes the first to fourth reflective metal layers RL1-RL4, the second reflective electrode RE2 includes the first to fourth reflective metal layers RL1-RL4, and the third reflective electrode RE3 includes the first to fourth reflective metal layers RL1-RL4.

[0224] The first intermediate insulating film MS1, the second intermediate insulating film MS2 and the third intermediate insulating film MS3 may be respectively disposed inside the first trench TRC1, the second trench TRC2 and the third trench TRC3. For example, the first intermediate insulating film MS1 may be disposed inside the first trench TRC1 in a manner surrounded by the first reflective electrode RE1 and the first anode electrode AND1, the second intermediate insulating film MS2 may be disposed inside the second trench TRC2 in a manner surrounded by the second reflective electrode RE2 and the second anode electrode AND2, and the third intermediate insulating film MS3 may be disposed inside the third trench TRC3 in a manner surrounded by the third reflective electrode RE3 and the third anode electrode AND3.

[0225] The first intermediate insulating film MS1, the second intermediate insulating film MS2, and the third intermediate insulating film MS3 may have different thicknesses from each other. For example, the second intermediate insulating film MS2 may have a greater thickness than the third intermediate insulating film MS3, and the first intermediate insulating film MS1 may have a greater thickness than the second intermediate insulating film MS2. Here, the thickness may mean the size in the third direction DR3.

[0226] As described above, the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3 may be arranged on the tenth interlayer insulating film INS10. For example, the first anode electrode AND1 may be arranged on the tenth interlayer insulating film INS10 in a manner overlapping the first reflective electrode RE1 and the first intermediate insulating film MS1, the second anode electrode AND2 may be arranged on the tenth interlayer insulating film INS10 in a manner overlapping the second reflective electrode RE2 and the second intermediate insulating film MS2, and the third anode electrode AND3 may be arranged on the tenth interlayer insulating film INS10 in a manner overlapping the third reflective electrode RE3 and the third intermediate insulating film MS3.

[0227] On the sixth insulating film IS6 of the tenth interlayer insulating film INS10, the first anode electrode AND1 may overlap with the first reflective electrode RE1 and the first intermediate insulating film MS1, on the sixth insulating film IS6 of the tenth interlayer insulating film INS10, the second anode electrode AND2 may overlap with the second reflective electrode RE2 and the second intermediate insulating film MS2, and on the sixth insulating film IS6 of the tenth interlayer insulating film INS10, the third anode electrode AND3 may overlap with the third reflective electrode RE3 and the third intermediate insulating film MS3. The first anode electrode AND1 may be electrically connected to the first reflective electrode RE1, the second anode electrode AND2 may be electrically connected to the second reflective electrode RE2, and the third anode electrode AND3 may be electrically connected to the third reflective electrode RE3. Here, each of the first to third anode electrodes AND1-AND3 may overlap with the aforementioned Figure 6 The first electrodes AND shown are identical.

[0228] A pixel defining film PDL defining the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be disposed on the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3. The pixel defining film PDL may be disposed, for example, between the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3 and the intermediate layer IL to define the light emitting areas EA1-EA3. In one embodiment, the pixel defining film PDL may include, for example, Figure 6 The first pixel defining film PDL1, the second pixel defining film PDL2 and the third pixel defining film PDL3 are formed.

[0229] An intermediate layer IL may be disposed on the pixel definition layer PDL. The intermediate layer IL may include the aforementioned Figure 6 The first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 are formed.

[0230] The second electrode CAT may be disposed on the intermediate layer IL. Fig.10The second electrode CAT can be connected with the aforementioned Figure 6 The second electrode CAT is the same.

[0231] An encapsulation layer TFE may be disposed on the second electrode CAT. Fig.10 The encapsulation layer TFE can be Figure 6 The encapsulation layer is the same as TFE.

[0232] An adhesive layer ADL may be disposed on the encapsulation layer TFE. Fig.10 The adhesive layer ADL can be combined with the aforementioned Figure 6 The adhesive layer ADL is the same.

[0233] A color filter layer including a first color filter CF1 , a second color filter CF2 , and a third color filter CF3 may be disposed on the adhesive layer ADL. Fig.10 The first color filter CF1, the second color filter CF2 and the third color filter CF3 can be respectively connected to the aforementioned Figure 6 The first color filter CF1, the second color filter CF2 and the third color filter CF3 are the same.

[0234] A plurality of lenses LNS may be disposed on the color filter layer (eg, the first color filter CF1 , the second color filter CF2 , and the third color filter CF3 ). Fig.10 The multiple lenses LNS can be used with the aforementioned Figure 6 The multiple lenses LNS are identical.

[0235] According to the different depths of the first groove TRC1, the second groove TRC2 and the third groove TRC3 respectively overlapping with the first color filter CF1, the second color filter CF2 and the third color filter CF3, the distances between the first reflective electrode RE1, the second reflective electrode RE2 and the third reflective electrode RE3 and the second electrode CAT arranged in each groove TRC1-TRC3 may be different. For example, when the distance between the inner side surface of the first reflective electrode RE1 and the second electrode CAT is defined as the first resonance distance rd1, the distance between the inner side surface of the second reflective electrode RE2 and the second electrode CAT is defined as the second resonance distance rd2, and the distance between the inner side surface of the third reflective electrode RE3 and the second electrode CAT is defined as the third resonance distance rd3, the aforementioned first resonance distance rd1, the second resonance distance rd2 and the third resonance distance rd3 may be defined by the following relational expression 1. Here, the first resonance distance rd1, the second resonance distance rd2 and the third resonance distance rd3 may mean the sizes in the third direction DR3, respectively.

[0236] <Relation 1>

[0237] rd1>rd2>rd3

[0238] On the other hand, the inner side surface of the reflective electrode mentioned above may refer to a portion of the reflective electrode that is disposed at the innermost side of the trench and in contact with the intermediate insulating film. For example, the inner side surface of the first reflective electrode RE1 may be a portion that is disposed at the innermost side of the first trench TRC1 and in contact with the first intermediate insulating film MS1. In other words, the inner side surface of the first reflective electrode RE1 may be a portion that is disposed at the innermost side of the first trench TRC1 and in contact with the first intermediate insulating film MS1. Fig.10 A first reflective electrode portion in contact with a side axis of an arrow defining a first resonance distance rd1.

[0239] In one embodiment, the depth of the groove of each pixel PX1-PX3 is different, so the resonance distance rd1, rd2, rd3 between the reflective electrode and the second electrode CAT is adjusted differently according to each pixel PX1-PX3). As a result, the microcavity (Micro-cavity; or thin film resonance) effect for light can be increased and / or optimized according to the wavelength of the light to be emitted in each pixel PX1-PX3 and the corresponding resonance distance and / or resonance number. For example, the first color light, the second color light and the third color light can be appropriately amplified in the first light-emitting area EA1, the second light-emitting area EA2 and the third light-emitting area EA3, respectively. As an embodiment, the first color light emitted by the first light-emitting area EA1 can be red light corresponding to the first color filter CF1, the second color light emitted by the second light-emitting area EA2 can be green light corresponding to the second color filter CF2, and the third color light emitted by the third light-emitting area EA3 can be cyan light corresponding to the third color filter CF3. In other words, the resonance distance rd2 of the second light emitting area EA2 emitting green light may be greater than the resonance distance rd3 of the third light emitting area EA3 emitting cyan light and may be smaller than the resonance distance rd1 of the first light emitting area EA1 emitting red light.

[0240] Fig.11 This is a diagram for explaining the connection relationship between an anode electrode and a transistor in a display device according to an embodiment.

[0241] like Fig.11 As shown, the first anode electrode AND1 may be connected to the transistor (eg, Figure 6 The contact hole CT may be connected to the drain region of the first trench TRC1. In addition, the contact hole CT penetrates the tenth interlayer insulating film INS10 and the ninth interlayer insulating film INS9 to expose the eighth metal layer ML8. The first anode electrode AND1 may be connected to the eighth metal layer ML8 through the first reflective electrode RE1 in the first trench TRC1 and the first reflective electrode RE1 in the contact hole CT. Figure 6As shown, the eighth metal layer ML8 may be connected to the drain area DA of the transistor TRS through the underlying metal layer.

[0242] The aforementioned non-light emitting area may mean, for example, an area other than the light emitting areas EA1 , EA2 , and EA3 in the display area.

[0243] On the other hand, the second anode electrode AND2 and the third anode electrode AND3 may be connected in the same manner as shown in FIG. Fig.11 The first anode electrode AND1 as shown is connected to the corresponding transistor in the same manner.

[0244] Fig.12 This is a diagram for explaining the connection relationship between an anode electrode and a transistor in a display device according to an embodiment.

[0245] like Fig.12 As shown, the contact hole CT may be arranged adjacent to the first trench TRC1 in the non-light emitting region. The contact hole CT may penetrate the tenth interlayer insulating film INS10 and the ninth interlayer insulating film INS9 to expose the eighth metal layer ML8. The first anode electrode AND1 may be arranged along the inner wall of the contact hole CT. The first anode electrode AND1 may be connected to the eighth metal layer ML8 through the contact hole CT. Figure 6 As shown, the eighth metal layer ML8 may be connected to the drain region DA of the corresponding transistor through the underlying metal layer.

[0246] The aforementioned non-light emitting area may mean, for example, an area other than the light emitting areas EA1 - EA3 in the display area.

[0247] On the other hand, the second anode electrode AND2 and the third anode electrode AND3 may be connected in the same manner as shown in FIG. Fig.12 The first anode electrode AND1 as shown is connected to the corresponding transistor in the same manner.

[0248] Figures 13 to 22 is a process cross-sectional view for explaining a method for manufacturing a display device according to an embodiment.

[0249] First, if Fig.13 As shown, a ninth interlayer insulating film INS9 may be disposed on the substrate SSUB.

[0250] Then, if Fig.14As shown, a tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9. For example, a first insulating film IS1 may be disposed on the ninth interlayer insulating film INS9, and then a second insulating film IS2 may be disposed on the first insulating film IS1, and then a third insulating film IS3 may be disposed on the second insulating film IS2, and then a fourth insulating film IS4 may be disposed on the third insulating film IS3, and then a fifth insulating film IS5 may be disposed on the fourth insulating film IS4, and then a sixth insulating film IS6 may be disposed on the fifth insulating film IS5.

[0251] Afterwards, if Fig.15 As shown, the first trench TRC1, the second trench TRC2, and the third trench TRC3 may have different depths. At this time, at least one of the first trench TRC1, the second trench TRC2, and the third trench TRC3 may penetrate a plurality of insulating films having different etching ratios.

[0252] In one embodiment, the first trench TRC1 may penetrate the sixth insulating film IS6, the fifth insulating film IS5, the fourth insulating film IS4, the third insulating film IS3 and the second insulating film IS2. The first trench TRC1 may be formed by etching the sixth insulating film IS6, the fifth insulating film IS5, the fourth insulating film IS4, the third insulating film IS3 and the second insulating film IS2 in sequence through a first mask. Here, the etching process may be, for example, a dry etching process. The etching ratios between adjacent insulating films are different, so when etching any insulating film, the insulating film below any insulating film may act as an etching stop film during the etching process. For example, in the formation process of the first trench TRC1, during the etching process for the sixth insulating film IS6, the fifth insulating film IS5 below it may act as an etching stop film during the etching process. On the other hand, a portion of the first insulating film IS1 may be removed during the formation of the first trench TRC1.

[0253] The second trench TRC2 may penetrate the sixth insulating film IS6, the fifth insulating film IS5, and the fourth insulating film IS4. The second trench TRC2 may be formed by sequentially etching the sixth insulating film IS6, the fifth insulating film IS5, and the fourth insulating film IS4 using a second mask. Here, the etching process may be, for example, a dry etching process. The etching ratios between adjacent insulating films are different, so when etching any one of the insulating films, the insulating film below any one of the insulating films may act as an etching stop film during the etching process. On the other hand, a portion of the third insulating film IS3 may be removed during the formation of the second trench TRC2.

[0254] The third trench TRC3 may penetrate the sixth insulating film IS6. The third trench TRC3 may be formed by etching the sixth insulating film IS6 through a third mask. Here, the etching process may be, for example, a dry etching process. The etching ratios between adjacent insulating films are different, so when etching any insulating film, the insulating film below any insulating film may act as an etching stop film during the etching process. On the other hand, a portion of the fifth insulating film IS5 may be removed during the formation of the third trench TRC3.

[0255] According to the method for manufacturing a display device according to an embodiment, the trenches TRC1 - TRC3 having different depths are formed by using a plurality of insulating films having different etching ratios. Therefore, the depths of the trenches TRC1 - TRC3 can be more accurately controlled for each pixel PX1 - PX3 .

[0256] On the other hand, during or after the process of forming the first trench TRC1, the second trench TRC2, and the third trench TRC3, a Fig.11 as well as Fig.12 The contact hole CT.

[0257] Then, if Fig.16 As shown, a reflective electrode layer REL may be disposed on the tenth interlayer insulating film INS10 having the first trench TRC1, the second trench TRC2, and the third trench TRC3. At this time, the reflective electrode layer REL may also be formed on the tenth interlayer insulating film INS10, and may also be formed on the inner wall of the first trench TRC1, the inner wall of the second trench TRC2, and the inner wall of the third trench TRC3. In other words, at least a portion of the reflective electrode layer REL may be formed along the inner wall of the first trench TRC1, the inner wall of the second trench TRC2, and the inner wall of the third trench TRC3.

[0258] Afterwards, if Fig.17 As shown, an intermediate insulating film MSL may be disposed on the reflective electrode layer REL. In this case, the intermediate insulating film MSL may also be disposed in the first trench TRC1, the second trench TRC2, and the third trench TRC3.

[0259] Then, the intermediate insulating film MSL and the reflective electrode layer REL are polished (or removed or planarized) by chemical mechanical polishing (CMP), so that Fig.18As shown, the first reflective electrode RE1, the second reflective electrode RE2 and the third reflective electrode RE3 separated from each other can be formed, and the first intermediate insulating film MS1, the second intermediate insulating film MS2 and the third intermediate insulating film MS3 separated from each other can be formed. In other words, by chemical mechanical polishing, the portion on the tenth interlayer insulating film INS10 in the intermediate insulating film MSL and the reflective electrode layer REL can be selectively removed. In other words, with the upper surface of the sixth insulating film IS6 of the tenth interlayer insulating film INS10 as a reference, the intermediate insulating film MSL and the reflective electrode layer REL can be planarized.

[0260] Afterwards, if Fig.19 As shown, the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3 may be arranged on the tenth interlayer insulating film INS10 (for example, the sixth insulating film IS6 of the tenth interlayer insulating film INS10). For example, the first anode electrode AND1 may be formed on the tenth interlayer insulating film INS10 in a manner of contacting the first reflective electrode RE1 and the first intermediate insulating film MS1, the second anode electrode AND2 may be formed on the tenth interlayer insulating film INS10 in a manner of contacting the second reflective electrode RE2 and the second intermediate insulating film MS2, and the third anode electrode AND3 may be formed on the tenth interlayer insulating film INS10 in a manner of contacting the third reflective electrode RE3 and the third intermediate insulating film MS3.

[0261] Then, if Fig. 20 As shown, a pixel defining film PDL may be formed to cover the edges of the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3. The pixel defining film PDL may define a first emission area EA1 of the first pixel PX1, a second emission area EA2 of the second pixel PX2, and a third emission area EA3 of the third pixel PX3.

[0262] Then, if Fig.21 As shown, an intermediate layer IL may be disposed on the pixel defining layer PDL.

[0263] Afterwards, if Fig. 22 As shown, a second electrode CAT may be disposed on the intermediate layer IL.

[0264] Then, if Fig.10 As shown, an encapsulation layer TFE, an adhesive layer ADL, a first color filter CF1, a second color filter CF2, a third color filter CF3, and a lens LNS may be formed on the second electrode CAT.

[0265] Fig.23 is a cross-sectional view of a display device according to an embodiment.

[0266] Fig.23 The display device is different from the aforementioned display device in that the number of the tenth interlayer insulating film INS10 is different. Fig.10 There are differences in the display devices, and the differences are highlighted as follows.

[0267] like Fig.23 As shown, the tenth interlayer insulating film INS10 may include a first insulating film IS1 , a second insulating film IS2 , and a third insulating film IS3 sequentially arranged along the third direction DR3 on the ninth interlayer insulating film INS9 .

[0268] Adjacent insulating films among the first to third insulating films IS3 of the tenth interlayer insulating film INS10 may have different etching ratios from each other. For example, the first insulating film IS1 and the second insulating film IS2 may have different etching ratios from each other. On the other hand, the first insulating film IS1 and the third insulating film IS3 may have the same etching ratio. For example, the first insulating film IS1 and the third insulating film IS3 may each include SiN x , and the second insulating film IS2 may include SiO x .

[0269] The first insulating film IS1 , the second insulating film IS2 , and the third insulating film IS3 may have the same thickness. Here, the thickness may mean a size in the third direction DR3 .

[0270] The tenth interlayer insulating film INS10 may have a plurality of grooves having different depths from each other. Here, the depth may mean a size in the third direction DR3. For example, the tenth interlayer insulating film INS10 may have a first groove TRC1 configured corresponding to the first pixel PX1 (or the first light emitting area EA1 of the first pixel PX1, or the first color filter CF1 of the first pixel PX1), a second groove TRC2 configured corresponding to the second pixel PX2 (or the second light emitting area EA2 of the second pixel PX2, or the second color filter CF2 of the second pixel), and a third groove TRC3 configured corresponding to the third pixel PX3 (or the third light emitting area EA3 of the third pixel PX3, or the third color filter CF3 of the third pixel PX3), as shown in FIG. Fig.23As shown, the aforementioned first to third grooves TRC1-TRC3 may have different depths from each other. For example, the second groove TRC2 overlapping with the second color filter CF2 may have a greater depth than the third groove TRC3 overlapping with the third color filter CF3, and the first groove TRC1 overlapping with the first color filter CF1 may have a greater depth than the second groove TRC2 overlapping with the second color filter CF2. In other words, the depth of the second groove TRC2 may be greater than the depth of the third groove TRC3 and less than the depth of the first groove TRC1. In one embodiment, the first groove TRC1 may penetrate the third insulating film IS3, the second insulating film IS2 and the first insulating film IS1. On the other hand, although not shown, a portion of the ninth interlayer insulating film INS9 may be removed through the first groove TRC1. The second groove TRC2 may penetrate the third insulating film IS3 and the second insulating film IS2. On the other hand, although not shown, a portion of the first insulating film IS1 may be removed through the second groove TRC2. The third groove TRC3 may penetrate the third insulating film IS3. On the other hand, although not shown, a portion of the second insulating film IS2 may be removed through the third trench TRC3 .

[0271] In one embodiment, the first color filter CF1 may be a red filter, the second color filter CF2 may be a green filter, and the third color filter CF3 may be a cyan filter. In addition, in one embodiment, the first color filter CF1 may be a cyan filter, the second color filter CF2 may be a green filter, and the third color filter CF3 may be a red filter. In addition, in one embodiment, the first color filter CF1 may be a red filter, the second color filter CF2 may be a cyan filter, and the third color filter CF3 may be a green filter. In addition, in one embodiment, the first color filter CF1 may be a green filter, the second color filter CF2 may be a cyan filter, and the third color filter CF3 may be a red filter.

[0272] According to the different depths of the first groove TRC1, the second groove TRC2, and the third groove TRC3 respectively overlapping with the first color filter CF1, the second color filter CF2, and the third color filter CF3, the distances between the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 and the second electrode CAT arranged in each groove may be different. For example, when the distance between the inner side surface of the first reflective electrode RE1 and the second electrode CAT is defined as the first resonance distance rd1, the distance between the inner side surface of the second reflective electrode RE2 and the second electrode CAT is defined as the second resonance distance rd2, and the distance between the inner side surface of the third reflective electrode RE3 and the second electrode CAT is defined as the third resonance distance rd3, the aforementioned first resonance distance rd1, the second resonance distance rd2, and the third resonance distance rd3 may be defined by the aforementioned relational expression 1. Here, the first resonance distance rd1, the second resonance distance rd2, and the third resonance distance rd3 may mean the sizes in the third direction DR3, respectively.

[0273] Fig.24 as well as Fig.25 is a process cross-sectional view for explaining a method for manufacturing a display device according to an embodiment.

[0274] Fig.24 as well as Fig.25 It can be for the aforementioned Fig.23 Process cross-sectional view of a display device.

[0275] First, if Fig.24 As shown, a tenth interlayer insulating film INS10 may be configured on the ninth interlayer insulating film INS9. For example, a first insulating film IS1 may be configured on the ninth interlayer insulating film INS9, and then a second insulating film IS2 may be configured on the first insulating film IS1, and then a third insulating film IS3 may be configured on the second insulating film IS2. Then, a first trench TRC1, a second trench TRC2, and a third trench TRC3 may be formed that penetrate at least a portion of the insulating film of the tenth interlayer insulating film INS10. The first trench TRC1, the second trench TRC2, and the third trench TRC3 may have different depths from each other.

[0276] After that, the reflective electrode layer REL may be formed on the tenth interlayer insulating film INS10. At this time, the reflective electrode layer REL may be further formed along the inner wall of the first trench TRC1, the inner wall of the second trench TRC2, and the inner wall of the third trench TRC3.

[0277] For the description of the next process, refer to the above, for example, Figures 17 to 22 And related instructions.

[0278] A person with common knowledge in the technical field to which the utility model belongs will understand that it can be implemented in other specific forms without changing the technical concept or essential features of the utility model. Therefore, the embodiments described above should be understood as exemplary in all aspects and not restrictive. The scope of the utility model is shown by the attached claims, and all changes or deformations derived from the meaning, scope and equivalent concepts of the claims should be interpreted as included in the scope of the utility model.

[0279] On the other hand, in this specification and the drawings, preferred embodiments of the present invention are disclosed. Even if specific terms are used, they are only used to facilitate the description of the technical content of the present invention and to help understand the general meaning of the present invention, and do not limit the scope of the present invention. It should be clear to a person with common knowledge in the technical field to which the present invention belongs. In addition to the embodiments disclosed herein, the technical concept based on the present invention can also be implemented.

Claims

1. A display device, characterized in that: include: substrate; an interlayer insulating film disposed on the substrate and having a first trench and a second trench having different depths from each other; A first reflective electrode, disposed inside the first groove; a 1-1 electrode connected to the first reflective electrode on the interlayer insulating film; A second reflective electrode is disposed inside the second groove; a 1-2 electrode connected to the second reflective electrode on the interlayer insulating film; A second electrode, on the 1-1 electrode and the 1-2 electrode; a first color filter, arranged on the second electrode so as to overlap with the 1-1 electrode; as well as a second color filter arranged on the second electrode so as to overlap with the first-second electrode; The interlayer insulating film includes a plurality of insulating films, At least two of the plurality of insulating films are composed of materials different from each other, At least one of the first trench and the second trench passes through a plurality of insulating films composed of different materials of the interlayer insulating film.

2. The display device according to claim 1, characterized in that The number of insulating films penetrated by the first trench is different from the number of insulating films penetrated by the second trench.

3. The display device according to claim 1, characterized in that The interlayer insulating film includes: a first insulating film; and The second insulating film is disposed on the first insulating film adjacent to the first insulating film and is composed of a material different from that of the first insulating film.

4. The display device according to claim 3, characterized in that: The interlayer insulating film includes a plurality of first insulating films and a plurality of second insulating films that are alternately arranged.

5. The display device according to claim 1, characterized in that The first reflective electrode is arranged along the inner wall of the first groove, The second reflective electrode is disposed along an inner wall of the second groove.

6. The display device according to claim 5, characterized in that: The first reflective electrode and the second reflective electrode each have a U-shaped cross section.

7. The display device according to claim 1, characterized in that The display device further includes: a first intermediate insulating film disposed between the first reflective electrode and the 1-1 electrode; and The second intermediate insulating film is arranged between the second reflective electrode and the 1-2 electrode.

8. The display device according to claim 7, characterized in that: The first intermediate insulating film is surrounded by the first reflective electrode and the 1-1 electrode. The second interlayer insulating film is surrounded by the second reflective electrode and the 1-2 electrode.

9. The display device according to claim 7, characterized in that: The thickness of the first interlayer insulating film is different from the thickness of the second interlayer insulating film.

10. The display device according to claim 1, characterized in that A distance between an inner side surface of a first reflective electrode disposed at an innermost side of the first groove and the second electrode is different from a distance between an inner side surface of a second reflective electrode disposed at an innermost side of the second groove and the second electrode.

11. The display device according to claim 1, characterized in that: The 1-1 electrode is connected to the transistor on the substrate through a contact hole connected to the first trench.

12. The display device according to claim 1, characterized in that: The 1-1 electrode is connected to the transistor on the substrate via a contact hole penetrating the interlayer insulating film.

13. The display device according to claim 12, characterized in that: The display device further includes: an intermediate layer between the 1-1 electrode and between the 1-2 electrode and the second electrode.

14. The display device according to claim 13, characterized in that: The display device further includes a pixel defining film disposed between the 1-1 electrode, the 1-2 electrode and the intermediate layer to define a light emitting area.

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