Package structure

Abstract

The utility model provides a packaging piece structure. The package structure may utilize a bridging die to electrically connect one die to another die and to at least one additional die adjacent to the bridging die. The aspect ratio of the gap between the bridging die and the at least one additional die is controlled by thinning the bridging die to be thinner than the at least one additional die. The package structure may utilize a bonding structure to abut the dielectric material of the attached die to the metal bonding structure of the base die.

Description

Technical Field

[0001] The utility model relates to a packaging structure. Background Art

[0002] Integrated circuit packages are becoming more and more complex, with more device dies being packaged in the same package to achieve more functionality. For example, a System on Integrated Chip (SoIC) has been developed to include multiple device dies, such as multiple processors and multiple memory cubes, in the same package. A SoIC may include multiple device dies that are formed using different technologies and may have different functionality from other device dies bonded to the same device die, thereby forming a system. This can save manufacturing costs and optimize device performance. Utility Model Content

[0003] The utility model provides a package structure, comprising: a first tube core, the first tube core comprising a first bonding pad and a dummy bonding structure arranged at a first surface of the first tube core, the first bonding pad and the dummy bonding structure being laterally surrounded by a first dielectric bonding layer; and a second tube core, the second tube core comprising a second bonding pad arranged at a second surface of the second tube core, the second bonding pad being laterally surrounded by a second dielectric bonding layer, the second bonding pad being directly bonded to the first bonding pad, an inner portion of the second dielectric bonding layer being bonded to the first dielectric bonding layer, and an edge portion of the second dielectric bonding layer being adjacent to the dummy bonding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0005] Figure 1 A perspective view of a package structure at an intermediate step is shown in accordance with some embodiments.

[0006] Figure 2 A top view of a package assembly is shown having a plurality of device dies defined therein.

[0007] Figure 3 to Figure 4 A cross-sectional view illustrating an intermediate stage in the formation of a package assembly according to some embodiments of the present disclosure.

[0008] Figures 5 and 6 A cross-sectional view illustrating an intermediate stage in the formation of a package assembly according to some embodiments of the present disclosure.

[0009] Figures 7 and 8 A cross-sectional view illustrating an intermediate stage in the formation of a bridge assembly according to some embodiments of the present disclosure.

[0010] Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F , Figure 12G , Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig.13F , Figure 13G , Fig.14A , Fig. 14B , Fig.15 , Fig.16 , Fig.17 , Fig.18 as well as Fig.19 Intermediate stages in the formation of a package structure having die positioning structures using a bridge die and various architectures are shown in accordance with some embodiments.

[0011] Fig. 20A , Fig. 20B , Fig. 20C , Fig.20D , Fig.20E , Fig.20F , Fig.21A , Fig. 21B , Fig. 21C , Fig.21D , Fig.21E , Fig.21F , Fig. 22 , Fig.23 , Fig.24 as well as Fig.25 Intermediate stages in the formation of a package structure using die positioning structures of various architectures are shown in accordance with some embodiments.

[0012] [Description of Figure Numbers]

[0013] 10: Carrying substrate;

[0014] 12: Release layer;

[0015] 14, 22: Encapsulation;

[0016] 16: Insulation layer;

[0017] 18: bonding layer;

[0018] 20, 154: joint structure;

[0019] 20b, 154b: active bonding pads;

[0020] 20bp, 154bp, 254, 354, 404: junction pad;

[0021] 20c, 154c: corner positioning structure;

[0022] 20d, 154d: dummy bonding pads;

[0023] 20e, 154e: edge positioning structure;

[0024] 20ls, 154ls: positioning structure;

[0025] 20r, 154r: annular positioning structure;

[0026] 23, 138, 238, 332, 338: dielectric layer;

[0027] 24: chip bonding layer;

[0028] 25, 136, 146, 236, 246, 336: through holes;

[0029] 25m: Metallized pattern;

[0030] 26, 100, 200, 300: chips;

[0031] 27: Re-route the line structure;

[0032] 28: passivation layer;

[0033] 30: Metal column;

[0034] 32: Metal top cover layer;

[0035] 34: conductive connector;

[0036] 50: SoIC package device;

[0037] 105: tube core, first tube core;

[0038] 205: tube core, second tube core;

[0039] 105a: first die, die, device die;

[0040] 105b: second die, die, device die;

[0041] 106: cutting line;

[0042] 116: optional perforation, silicon via;

[0043] 120, 220: semiconductor substrate;

[0044] 122, 222: integrated circuit devices;

[0045] 124, 224: interlayer dielectric;

[0046] 128, 228: contact plug;

[0047] 130, 230, 330: internal connection structure;

[0048] 132: dielectric layer, intermetallic dielectric layer;

[0049] 132A: corresponding dielectric layer;

[0050] 134, 234, 334: metal wire;

[0051] 134A: metal wire, top metal wire;

[0052] 138A, 138B, 138C, 238A, 238B, 238C: dielectric sublayer;

[0053] 144, 244: Metallic features;

[0054] 152, 252, 352: dielectric bonding layer;

[0055] 156, 157, 256, 257, 356: bonding pad through holes;

[0056] 160: Monomerization process;

[0057] 202a, 202b, 202c: die bonding area;

[0058] 205a, 205b: device die;

[0059] 216: Silicon vias;

[0060] 305: bridge die;

[0061] 305a, 305b: silicon bridge die, bridge die;

[0062] 320, 320': substrate;

[0063] 395, 397: Package devices;

[0064] 400: packaging substrate;

[0065] 402: substrate core;

[0066] D1, D2, D3, D4, D5: distance;

[0067] G1: gap;

[0068] T1, T2, T3: thickness. DETAILED DESCRIPTION

[0069] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0070] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0071] Devices that are packaged in three dimensions can utilize chip stacking or chip-on-wafer stacking to achieve greater functionality in a smaller overall footprint. Bonding multiple chips to other multiple chips or other multiple chips can utilize a direct bonding method, in which multiple bonding pads in a first device are pressed to multiple bonding pads of a second device, and the dielectric layer of the first device is pressed to the dielectric layer of the second device. Through pressure and annealing processes, the dielectric layers are melted or bonded together to form a molten bond across the interface, and the bonding pads are bonded together through inter-diffusion of materials. One of the challenges faced when bonding devices is warping. The devices may experience different warping characteristics, and direct bonding techniques may fail due to the pressure of warping, resulting in delamination or voids. An embodiment provides a direct bonding technique to increase the bonding interface strength, in which the dielectric material along the edge of the top die is adjacent to the dummy bonding pad of the lower die or chip. The connection of the dummy bonding pad (which is metallization) to the dielectric material is achieved through a variety of mechanisms, which will be discussed in further detail below. These metal-to-dielectric bonds may be located at the edges and / or corners of the top die, which are the portions of the top die most susceptible to delamination or other warpage-induced failures.

[0072] A bridge die can be used to electrically couple multiple metal features from one device to another. For example, the bridge die can provide an electrical path from a first external connector of the bridge die to a second external connector of the bridge die. The first external connector can then be connected, for example, to a first device, and the second external connector can be connected, for example, to a second device, thereby forming an electrically conductive bridge between the first device and the second device. One problem with such interconnects within a bridge die is that in a device with multiple top device dies, the thickness of the die and the gap between the dies can result in multiple openings between each other having a height-to-width ratio that makes it difficult to reliably deposit an encapsulation between the bridge die and the top device die. For example, when the spacing is between about 50 μm and 100 μm and the thickness of the bridge die and the thickness of the top device die are between 200 μm and 500 μm, the combination of an aspect ratio of between 4:1 and 10:1 and a relatively deep opening of between 200 μm and 500 μm may result in insufficient deposition of the encapsulant. Embodiments use a bridge die that is much thinner than the top device die, which effectively reduces the aspect ratio to between 1:5 and 1:3 (measured based on the smaller height of the bridge die).

[0073] The embodiments discussed herein are discussed in the context of three-dimensional packages (e.g., system on integrated circuit (SoIC) packages) and methods of forming the same, but it will be appreciated that the disclosed techniques and devices may be used in other packaging contexts. Intermediate stages of forming a SoIC package will be described according to some embodiments. Certain variations in some embodiments will also be discussed. In the various views and illustrative embodiments, similar reference component numbers are used to represent similar components. It will be appreciated that while the concepts of the disclosed embodiments are explained using the formation of a SoIC package as an example, the disclosed embodiments may also be readily applied to other bonding methods and structures (e.g., where metal pads and vias are bonded to one another).

[0074] Figure 1 A perspective view of a SoIC package device 50 in an intermediate step according to some embodiments is shown. Some details are omitted for clarity. Although some examples of types of dies 105 and 205 are listed below, dies 105 and 205 can be any dies. Die 105 can be a logic die, such as a central processing unit (CPU) die, a micro control unit (MCU) die, an input-output (IO) die, a baseband (BB) die, an application processor (AP) die, or the like. Die 105 can also be a memory die, such as a dynamic random access memory (DRAM) die or a static random access memory (SRAM) die. Die 105 can be part of a chip (see Figure 2 In some embodiments, the plurality of dies 205 may be attached to a chip that is later singulated (see, e.g. Fig. 20A as well as FIG. 20B to FIG. 25 ). Die 205 is electrically bonded to die 105. Die 205 may be a logic die, which may be a CPU die, an MCU die, an IO die, a baseband die, or an AP die. Die 205 may also be a memory die. Multiple dies 205 may be bonded to die 105, each die 205 having different and / or similar functions.

[0075] The bridge die 305 is bonded to the first die 105a (also referred to as a die, a device die) and the second die 105b (also referred to as a die, a device die), and bridges the connection between the first die 105a and the second die 105b. It should be understood that in some embodiments, multiple bridge dies 305 can be used with multiple dies 105 in various combinations.

[0076] Figure 2 A chip 100 is shown in which a plurality of dies 105 are defined or formed (or, more generally, a package assembly in which a plurality of dies 105 are defined or formed, for example, a chip is provided as an example as shown). The dies 105 may all be of the same design and function, or may be of different designs and functions. The dashed lines represent dicing lines 106, where the dies 105 will be separated from each other in a subsequent singulation process.

[0077] Figures 3 to 6 A cross-sectional view illustrating an intermediate stage in the formation of a package assembly according to some embodiments of the present disclosure. Figure 3 A partial cross-sectional view of chip 100 is shown. According to some embodiments of the present disclosure, chip 100 is a device chip including a plurality of integrated circuit devices 122, which include, for example, active devices such as transistors and / or diodes, and may be passive devices such as capacitors, inductors, resistors, or the like. In other embodiments of the present disclosure, chip 100 includes passive devices (no active devices). Chip 100 may include a plurality of package device areas, which will be separated from chip 100 in a singulation process to form a plurality of dies 105. These package device areas are referred to as dies 105. As shown, chip 100 includes a portion of die 105a and a portion of die 105b. Die 105 may be an integrated circuit die, a passive die, an interposer, etc. It should be understood that these views are illustrative only and not restrictive.

[0078] According to some embodiments of the present disclosure, a chip 100 includes a semiconductor substrate 120 and a plurality of features formed at a top surface of the semiconductor substrate 120. The semiconductor substrate 120 may be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, and / or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. The semiconductor substrate 120 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. A plurality of shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 120 to isolate a plurality of active regions in the semiconductor substrate 120. A plurality of optional through vias 116 (also referred to as through silicon vias) may be formed to extend into the semiconductor substrate 120, and the optional through vias 116 may be used to electrically couple features on opposite sides of the chip 100 to each other.

[0079] According to some embodiments of the present disclosure, the chip 100 includes a plurality of integrated circuit devices 122 formed on a top surface of a semiconductor substrate 120. Exemplary integrated circuit devices 122 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like. Details of the integrated circuit devices 122 are not shown here. According to other embodiments, the chip 100 is used to form an interposer, wherein the semiconductor substrate 120 may be a semiconductor substrate or a dielectric substrate instead of a semiconductor substrate.

[0080] An inter-layer dielectric (ILD) 124 is formed on the semiconductor substrate 120 and fills the space between the gate stacks (not shown) of the plurality of transistors in the integrated circuit device 122. According to some embodiments, the inter-layer dielectric 124 is formed of phospho silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho silicate glass (BPSG), fluorosilicate glass (FSG), silicon oxide formed by tetraethyl orthosilicate (TEOS), or the like. The interlayer dielectric 124 can be formed by spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) or the like.

[0081] A plurality of contact plugs 128 are formed in the interlayer dielectric 124 for electrically connecting the integrated circuit device 122 with a plurality of overlying metal lines 134 and a plurality of vias 136. According to some embodiments of the present disclosure, the contact plugs 128 are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of the contact plugs 128 may include forming a plurality of contact openings in the interlayer dielectric 124, filling the contact openings with a conductive material, and performing a planarization process (e.g., a chemical mechanical polishing (CMP) process) to level the top surfaces of the contact plugs 128 with the top surface of the interlayer dielectric 124.

[0082] An interconnect structure 130 resides on the interlayer dielectric 124 and the contact plug 128. The interconnect structure 130 includes a plurality of dielectric layers 132 and a plurality of metal lines 134 and a plurality of vias 136 formed in the dielectric layers 132. The dielectric layer 132 may be alternatively referred to as an inter-metal dielectric (IMD) layer 132 hereinafter. According to some embodiments of the present disclosure, at least a lower dielectric layer in the dielectric layer 132 is formed of a low-k dielectric material having a dielectric constant (k-value) lower than about 3.0 or about 2.5. The dielectric layer 132 may be formed of black diamond (registered trademark of Applied Materials), a low dielectric constant dielectric material containing carbon, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. According to alternative embodiments of the present disclosure, some or all of the dielectric layers 132 are formed of non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or the like. According to some embodiments of the present disclosure, the formation of the dielectric layer 132 includes depositing a dielectric material containing a porogen, and then performing a curing process to remove the porogen, so that the remaining dielectric layer 132 becomes porous. A plurality of etch stop layers (not shown) that may be formed of silicon carbide, silicon nitride, or the like may be formed between the intermetallic dielectric layers 132, and are not shown for simplicity.

[0083] Metal lines 134 and vias 136 are formed in the dielectric layer 132. Metal lines 134 at the same level are sometimes collectively referred to as metal layers below. According to some embodiments of the present disclosure, the interconnect structure 130 includes multiple metal layers interconnected through vias 136. Metal lines 134 and vias 136 may be formed of copper or copper alloys, or may be formed of other metals. The formation process may include a single damascene process and a dual damascene process. In the single damascene process, a trench is first formed in one of the dielectric layers 132, and then the trench is filled with a conductive material. Then, a planarization process (e.g., a CMP process) is performed to remove excess conductive material above the top surface of the intermetallic dielectric layer, leaving metal lines in the trench. In the dual damascene process, trenches and via openings are simultaneously formed in the intermetallic dielectric layer, and the via openings are connected to the underlying trenches. Then, a conductive material is filled into the trench and the via opening to form a metal line and a via, respectively. The conductive material may include a diffusion barrier and a copper-containing metal material on the diffusion barrier. The diffusion barrier may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0084] The metal lines 134 include a plurality of metal lines 134A, which may be referred to as top metal lines. The top metal lines 134A are also collectively referred to as top metal layers. The corresponding dielectric layer 132A may be formed of a non-low-k dielectric material such as undoped silicate glass (USG), silicon oxide, silicon nitride, or the like. The corresponding dielectric layer 132A may also be formed of a low-k dielectric material, which may be selected from a material similar to the underlying intermetallic dielectric layer 132.

[0085] According to some embodiments of the present disclosure, a plurality of dielectric layers 138 and a plurality of dielectric bonding layers 152 are formed over the top metal line 134A. For example, the dielectric layer 138 and the dielectric bonding layer 152 may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, or the like, and in some embodiments, the dielectric layer 138 may be formed of a plurality of dielectric sublayers 138A, 138B, and 138C. First, the dielectric sublayer 138A is formed. Next, a plurality of via openings corresponding to a plurality of vias 146 may be formed in the dielectric sublayer 138A using a photolithography process, the photolithography process using, for example, a photoresist and / or a hard mask formed and patterned on the dielectric sublayer 138A to help form the plurality of via openings corresponding to the vias 146. Anisotropic etching may be used to form these trenches through the photoresist and / or the hard mask.

[0086] A plurality of vias 146 and a plurality of metal features 144 may be formed on dielectric sublayer 138A. Vias 146 and metal features 144 may be formed by a process similar to the formation of vias 136 and metal lines 134 described above, but other suitable processes may also be used. Metal features 144 and vias 146 may be formed of copper or a copper alloy, or may be formed of other metals. In one embodiment, metal features 144 and / or vias 146 may be formed of aluminum or an aluminum-copper alloy. In some embodiments, metal features 144 may be used for die testing.

[0087] In some embodiments, the metal feature 144 can be directly detected to perform a chip probe (CP) test of the chip 100. Optionally, a plurality of solder areas (e.g., solder balls or solder bumps) can be provided on the metal feature 144, and the solder areas can be used to perform a CP test on the chip 100. The CP test can be performed on the chip 100 to determine whether each die 105 in the chip 100 is a known good die (KGD). Therefore, only the die 105 (i.e., KGD) will undergo subsequent processing steps for packaging, while the die that fails the CP test will not be packaged. After testing, the solder area (if any) may be removed in subsequent processing steps.

[0088] Then, dielectric sublayer 138B may be deposited on metal features 144 to a desired thickness. In some embodiments, dielectric sublayer 138B may then be planarized to flush the top surface, while in other embodiments, the planarization step may be omitted. In some embodiments, dielectric sublayer 138C is then deposited. Other embodiments may not use dielectric sublayer 138C, which may be omitted.

[0089] Next, a plurality of bonding pad vias 156 and a plurality of bonding pad vias 157 may be formed. The bonding pad vias 156 extend through the entire dielectric layer 138 to the interconnect structure 130, and the bonding pad vias 157 extend to the metal feature 144 and are electrically coupled thereto. The plurality of openings for the bonding pad vias 156 and the bonding pad vias 157 may be formed using a photoresist (not shown) and / or a hard mask (not shown) formed and patterned on the dielectric layer 138 to help form the plurality of openings for the bonding pad vias 156 and the bonding pad vias 157. According to some embodiments of the present disclosure, anisotropic etching is performed to form the openings. The etching may stop on the metal feature 144 (for the bonding pad vias 157) or on the metal line 134 of the interconnect structure 130 (for the bonding pad vias 156).

[0090] Next, the plurality of openings for the bonding pad vias 156 and the bonding pad vias 157 may be filled with a conductive material. A conductive diffusion barrier (not shown, also referred to as a diffusion barrier) may be formed first. According to some embodiments of the present disclosure, the conductive diffusion barrier may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive diffusion barrier is formed, for example, by atomic layer deposition (ALD), physical vapor deposition (PVD), or the like. The conductive diffusion barrier may include a layer in the openings for the bonding pad vias 156 and the bonding pad vias 157 and a layer extending on the top surface of the dielectric layer 138.

[0091] Next, a metal material is deposited to form bonding pad vias 156 and 157 by electrochemical plating (ECP) or other suitable deposition processes, for example. The metal material is deposited on the conductive diffusion barrier and fills the remaining openings for bonding pad vias 156 and 157. The metal material may also extend on the top surface of dielectric layer 138. The metal material may include copper or a copper alloy. Bonding pad vias 156 and 157 may be formed simultaneously.

[0092] A planarization process such as a chemical mechanical polishing (CMP) process may then be performed to remove excess portions of the metal material and the conductive diffusion barrier until the dielectric layer 138 is exposed. The remaining portions of the conductive diffusion barrier and the conductive metal material include bond pad vias 156 and 157.

[0093] Next, a dielectric bonding layer 152 may be formed over the dielectric layer 138, and a plurality of openings for a plurality of bond pads 154bp may be formed in the dielectric bonding layer 152. The bond pads 154bp may include a plurality of dummy bond pads 154d (which may be pads that are not electrically coupled to any other conductive component in the device) or a plurality of active bond pads 154b (which may be electrically coupled to any underlying conductive features, such as bond pad vias 156 and bond pad vias 157). The plurality of openings may be formed using a photoresist (not shown) and / or a hard mask (not shown), which is formed and patterned on the dielectric bonding layer 152 to help form the plurality of openings for the bond pads 154bp. According to some embodiments of the present disclosure, anisotropic etching or wet etching is performed to form openings for the bond pads 154bp. The etching may stop on dielectric sublayer 138C, which may be used as an etch stop in some embodiments. In other embodiments, dielectric bonding layer 152 may have an etching selectivity to dielectric layer 138, so that after dielectric bonding layer 152 is etched through, dielectric layer 138 is still not etched through. In some embodiments, etching may be time-based. The opening for bonding pad 154bp may expose the upper surface of bonding pad via 156 and bonding pad via 157.

[0094] Next, the diffusion barrier and the metal material can be deposited in the opening to form the bonding pad 154bp. The bonding pad 154bp can be formed using a process and material similar to that used to form the bonding pad via 156 and the bonding pad via 157 described above. Then, a planarization process such as a chemical mechanical polishing (CMP) process can be performed to remove the excess portion of the metal material and the diffusion barrier until the dielectric bonding layer 152 is exposed. The remaining portion of the diffusion barrier and the metal material includes the bonding pad 154bp, which is then used to bond to another device. It should be understood that the metal line can also be formed simultaneously with the bonding pad 154bp.

[0095] In some embodiments, the bonding pad via 156 and the bonding pad via 157 can be formed at the same time as the bonding pad 154bp. In such an embodiment, after the dielectric bonding layer 152 is formed, a plurality of openings are formed in the dielectric bonding layer 152, as described above. Then, other plurality of openings for the bonding pad via 156 and the bonding pad via 157 are formed in the dielectric layer 138, as described above. Next, a conductive diffusion barrier and a metal material can be formed for the bonding pad vias 156 and 157 and the bonding pad 154bp in the same process, as described above. Then, a planarization process such as a CMP process can be used to remove the excess portion in the metal material and the conductive diffusion barrier until the dielectric bonding layer 152 is exposed. The remaining portion in the conductive diffusion barrier and the metal material includes the bonding pad 154bp, which is then used to bond to another device. The metal wire extending in the same layer as the bonding pad 154bp can also be formed simultaneously with the bonding pad 154bp. It should be understood that the additional bonding pad vias 156 and 157 shown can be formed.

[0096] The position and number of bonding pads 154bp can be adjusted according to the device to be bonded thereto in subsequent processes. In some embodiments, one or more of bonding pads 154bp are not electrically connected to any device in die 105. Such bonding pads 154bp can be considered as dummy bonding pads 154d. In some embodiments, dummy bonding pads 154d can continue to cross the surface of die 105, while in other embodiments, bonding pads 154bp including dummy bonding pads 154d can only be located at the position where other devices are to be attached.

[0097] Figure 4 The die 105 is shown after being singulated from the chip 100. A singulation process 160 (see FIG. 1 ) is used to singulate the device die from the chip 100. Figure 3 ) may be any suitable process, such as using a die saw, laser cutting, or the like to cut through the chip 100 and the structures formed thereon.

[0098] Figure 5 The formation of a chip 200 including a plurality of dies 205 (e.g., device die 205a and device die 205b) is shown. According to some embodiments of the present disclosure, the die 205 is a logic die, which may be a CPU die, an MCU die, an IO die, a baseband die, or an AP die. The die 205 may also be a memory die. The chip 200 includes a semiconductor substrate 220, which may be a silicon substrate.

[0099] The die 205 may include an integrated circuit device 222, an interlayer dielectric 224 on the integrated circuit device 222, and a plurality of contact plugs 228 for electrical connection to the integrated circuit device 222. The die 205 may further include a plurality of interconnect structures 230 for connecting to a plurality of active devices and a plurality of passive devices in the die 205. The interconnect structures 230 include a plurality of metal lines 234 and a plurality of vias 236.

[0100] A plurality of through silicon vias (TSVs) 216, sometimes referred to as through semiconductor vias or through-holes, may optionally be formed to penetrate into the semiconductor substrate 220 (and ultimately penetrate through the semiconductor substrate 220 by being exposed from the opposite side). If used, the TSVs 216 may be used to connect a plurality of devices and a plurality of metal lines formed on the front side (top side as shown) of the semiconductor substrate 220 to the back side of the semiconductor substrate 220. The TSVs 216 may be formed using processes and materials similar to those used to form the bond pad vias 156 as described above and will not be repeated, including, for example, a time-based etching process such that the TSVs 216 may have a bottom portion disposed between the top and bottom surfaces of the semiconductor substrate 220.

[0101] The die 205 may include a plurality of dielectric layers 238 and a plurality of dielectric bonding layers 252. A plurality of vias 246 and a plurality of metal features 244 may be formed and disposed in the dielectric layer 238 (which may include multiple dielectric sublayers 238A, 238B, and 238C). A plurality of bond pad vias 256 and a plurality of bond pad vias 257 are also formed and disposed in the dielectric layer 238, and a plurality of bond pads 254 are also formed and disposed in the dielectric bonding layer 252.

[0102] The processes and materials used to form the various features of die 205 may be similar to the processes and materials used to form the various similar features of die 105 and are therefore not repeated here. Similar features between die 105 and die 205 share the same last two digits in their reference component numbers.

[0103] exist Figure 6 In the embodiment, the chip 200 is divided into a plurality of separate device dies 205, for example, including a device die 205a and a device die 205b. Figure 5 ) can be compared with the above Figure 4 The monomerization processes discussed are the same or similar.

[0104] Figure 7The formation of a chip 300 according to some embodiments is shown, wherein the chip 300 includes a plurality of bridge dies 305 (e.g., silicon bridge die (also referred to as bridge die) 305a and silicon bridge die (also referred to as bridge die) 305b). The substrate 320 may include any candidate substrate discussed above with respect to the semiconductor substrate 120. An interconnect structure 330 is provided to electrically connect various bonding pads 354 to other bonding pads 354 of the various bonding pads 354 and / or to a plurality of optional through silicon vias.

[0105] The interconnect structure 330 includes a plurality of dielectric layers 332 and a plurality of metal lines 334 and a plurality of vias 336 formed in the dielectric layers 332. The interconnect structure 330 may be formed using the same processes and materials as described above with respect to the interconnect structure 130 (and the same processes and materials as described above with respect to the dielectric layers 132 for the dielectric layers 332, the same processes and materials as described above with respect to the metal lines 134 for the metal lines 334, and the same processes and materials as described above with respect to the vias 136 for the vias 336).

[0106] The bridge die 305 may include a plurality of dielectric layers 338 and a dielectric bonding layer 352. A plurality of bond pad vias 356 are formed and disposed in the dielectric layers 338, and a plurality of bond pads 354 are formed and disposed in the dielectric bonding layer 352. The processes and materials used to form the various features of the bridge die 305 may be similar to the processes and materials used to form the various similar features of the die 105, and therefore are not repeated here. Similar features between the die 105 and the bridge die 305 share the same last two codes in their reference component numbers.

[0107] After forming the bonding pads 354, the substrate 320 of the bridge die 305 may be thinned to become a substrate 320', such that the total thickness of the chip 300 is between about 15 μm and 30 μm. In some embodiments, the substrate 320 may be completely removed by a thinning process. The thinning process may include an etching process, a grinding process, a CMP process, or a combination thereof.

[0108] exist Figure 8 In the embodiment, the chip 300 is divided into a plurality of separate bridge dies 305, for example, including a bridge die 305a and a bridge die 305b. Figure 7 ) can be compared with the above Figure 4 The monomerization processes discussed are the same or similar.

[0109] Fig.9A , 9B arrive Fig.19 An intermediate step of forming a SoIC package using a bridge die (e.g., bridge die 305) is shown. Some of the multiple drawings include one or more top-down views. For example, Fig.9Ais a cross-sectional view, and Fig. 9B It should be understood that these views are only examples and variations thereof are within the scope of the present disclosure. For example, the top view and cross-sectional view provided in each figure may be only partial views and may incorporate other devices or structures.

[0110] exist Fig.9A and Fig. 9B In the present invention, a carrier substrate 10 is provided, and a release layer 12 is formed on the carrier substrate 10. The carrier substrate 10 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 10 may be a chip, so that a plurality of packages may be formed on the carrier substrate 10 at the same time.

[0111] The release layer 12 may be formed of a polymer-based material that can be removed with the carrier substrate 10 from an overlying structure to be formed in a subsequent step. In some embodiments, the release layer 12 is an epoxy-based thermal-release material that loses adhesion when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 12 may be a UV glue that loses adhesion when exposed to UV light. The release layer 12 may be dispensed and cured in a liquid manner, may be a laminated film laminated to the carrier substrate 10, or may be the like. The top surface of the release layer 12 may be horizontal and may have a high degree of flatness.

[0112] Two or more of the plurality of dies 105 may be placed on the carrier substrate 10 and attached to the release layer 12. Each die 105 (e.g., dies 105a and 105b, which may be collectively referred to as dies 105) may be placed on the release layer 12 by a pick and place process to place each die 105 on the carrier substrate 10. In some embodiments, as Fig.9A and 9B As shown in , the dies 105a and 105b can be placed face down (back side up). In other embodiments, the dies 105a and 105b can be placed face up. It should be understood that each die 105 can have the same or different functions and can be the same size or different sizes from each other.

[0113] exist Fig. 10A and Fig. 10BIn the embodiment of the present invention, a filler material (e.g., an insulating material or encapsulant 14) may be deposited over the dies 105a and 105b and laterally surround the dies 105a and 105b. The encapsulant 14 may include a dielectric material such as a resin, epoxy, polymer, oxide, nitride, the like, or a combination thereof. The encapsulant 14 may be deposited by any suitable process, such as flow CVD, spin coating, PVD, the like, or a combination thereof.

[0114] exist Fig.11A and Fig. 11B In the embodiment of the present invention, a planarization process may be used to make the upper surface of the encapsulant 14 flush with the upper surfaces of the dies 105a and 105b. The planarization process may include grinding and / or chemical mechanical polishing (CMP) processes. The planarization process may continue until the through silicon vias 116 penetrate through the semiconductor substrate 120 of each die 105 (see FIG. Figure 4 ) was exposed.

[0115] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F and Figure 12G The formation of a bonding layer 18 and the formation of a plurality of bonding structures 20 in the bonding layer 18 are shown. Fig. 12A is a cross-sectional view, and Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F and 12G Shown according to various embodiments Fig. 12A, wherein the various embodiments illustrate a plurality of different architectures of the bonding structure 20. The bonding layer 18 may be formed on the upper surface of the encapsulation 14 and the through silicon via 116. The bonding structure 20 is formed in the bonding layer 18. The bonding structure 20 may include a plurality of active bond pads 20b that are physically coupled to the through silicon via 116, a plurality of dummy bond pads 20d that are not connected to any metal feature of the die 105, a plurality of edge landing structures 20e that are disposed around the die bonding area and are a special type of dummy bond pads, a plurality of ring landing structures 20r that are disposed as ring-shaped metal lines that surround the die bonding area and overlap thereon, and a plurality of corner landing structures 20c that are disposed at the corners of the die bonding area and are L-shaped metal lines. The various bonding structures 20 will be discussed in more detail below. For simplicity, the dummy bonding pad 20d and the active bonding pad 20b may be simply referred to as bonding pads 20bp.

[0116] The bonding layer 18 may be formed of any suitable insulating layer, such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, the like, or a combination thereof, and may be deposited using any suitable technique, such as CVD, PVD, spin coating, etc. In order to form the bonding structure 20, a plurality of openings may be formed in the bonding layer 18 according to the position and shape of the bonding structure 20. The plurality of openings may be formed using a photoresist (not shown) and / or a hard mask (not shown), which is formed and patterned over the bonding layer 18 to help form the plurality of openings of the bonding structure 20. In some embodiments, anisotropic etching or wet etching is performed to form the plurality of openings of the bonding structure 20. The etching may stop on the substrate 120 of the encapsulation body 14 and the dies 105a, 105b. The plurality of openings for the bonding structure 20 may expose the upper surface of the through silicon vias 116.

[0117] Next, a diffusion barrier and a metal material may be deposited in the plurality of openings to form a bonding structure 20. The diffusion barrier and the metal material may be deposited using the materials and techniques discussed above for forming the bonding pad vias 156 and 157. A planarization process such as a chemical mechanical polishing (CMP) process may then be performed to remove excess portions of the metal material and the diffusion barrier until the bonding layer 18 is exposed. The remaining portions of the diffusion barrier and the metal material comprise a bonding structure 20, which is then used to bond to another device.

[0118] like Fig. 12AAs shown, in some embodiments, one or more dummy bond pads 20d may be disposed on a portion of encapsulation 14 between die 105a and 105b. Dummy bond pads 20d may be included for pattern loading considerations and may also help provide better direct bonding, thereby reducing the likelihood of failure.

[0119] Reference Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F and Figure 12G , the die attaching region 202a (as shown in dotted lines) is located at the upper surface of the die 105a (as shown in dotted lines). Similarly, the die attaching region 202b (as shown in dotted lines) is located at the upper surface of the die 105b (as shown in dotted lines). In addition, the die attaching region 202c is located at the upper surfaces of both the die 105a and the die 105b, and overlaps the encapsulation 14 located between the die 105a and 105b. The bonding structure 20 that completely falls within the die attaching regions 202a, 202b, and 202c can be a bonding pad 20bp, which includes an active bonding pad 20b and / or a dummy bonding pad 20d. The bonding structure 20 disposed at the edge of the die attaching regions 202a, 202b, and 202c is a dummy structure, which can be an edge positioning structure 20e, an annular positioning structure 20r, or a corner positioning structure 20c. These can be collectively referred to as positioning structures 20ls. Each of the positioning structures 201s is disposed at an edge and / or corner of the die attach regions 202a, 202b, and 202c and is partially located within the die attach regions 202a, 202b, and 202c and partially located outside the die attach regions 202a, 202b, and 202c.

[0120] In subsequent processes, multiple device dies and / or multiple bridge dies are attached to the die attach regions 202a, 202b, 202c and bonded to the bonding pads 20bp. According to some embodiments, the edges of the device dies and / or bridge dies are placed on the positioning structures 20ls (including edge positioning structures 20e, ring positioning structures 20r and / or corner positioning structures 20c), and the dielectric material located at the edges of the device dies and / or bridge dies is adjacent to the positioning structures 20ls, as described below.

[0121] exist Fig. 12BIn the embodiment, the edge positioning structure 20e is continuously and completely around the die bonding areas 202a, 202b and 202c. The edge positioning structure 20e adopts the same size and spacing as the bonding pads 20bp. The edge positioning structure 20e is set at each of the four corners of each of the die bonding areas 202a, 202b and 202c. In some embodiments, the bonding structures 20 are dispersed in a regular pattern, and each bonding structure 20 has the same size and the same spacing. In such an embodiment, the regular pattern can help achieve a pattern loading effect. Fig. 12B For example, a dummy bonding pad 20 d (indicated by a dotted line) is disposed between the die attach region 202 a and the die attach region 202 c to continue the regular pattern of the bonding structure 20 .

[0122] exist Fig. 12C In the embodiment shown in FIG. 1 , the edge positioning structures 20e are only disposed at the corners of the die attach regions 202a, 202b and 202c.

[0123] exist Fig.12D In the embodiment, the edge positioning structures 20e are disposed at the corners of the die attach regions 202a, 202b, and 202c. In addition, one of the edge positioning structures 20e is disposed over the periphery of the die attach regions 202a, 202b, and 202c in each direction from the edge positioning structure 20e located at the corner toward the edge positioning structure 20e located at the adjacent corner. When the spacing between the bonding structures 20 in the die attach regions 202a, 202b, and / or 202c is a regular spacing, the additional edge positioning structures 20e may be spaced apart from the edge positioning structures 20e located at the corner by one pitch in each of two directions toward the edge positioning structures 20e located at other corners.

[0124] exist Fig.12E In the embodiment of the present invention, the positioning structure 201s is an annular positioning structure 20r, replacing the edge positioning structure 20e. The annular positioning structure 20r spans the periphery of the die attach regions 202a, 202b, and 202c. In some embodiments, the annular positioning structure 20r can be a broken ring or a segmented ring, for example, as shown relative to the corresponding die attach region 202a, the annular positioning structure 20r appears as an incoherent line segment in a top-down view.

[0125] exist Fig.12F, the positioning structure 201s is a corner positioning structure 20c. The corner positioning structure 20c is a special type of the ring positioning structure 20r, in which portions of the ring are removed between multiple corner portions. For example, at a corner of the die attach area 202a, the first leg of the L-shaped corner positioning structure 20c extends along a first edge of the die attach area 202a, and the second leg of the L-shaped corner positioning structure 20c extends along a second edge of the die attach area 202a, and the first edge intersects the second edge.

[0126] Figure 12G An embodiment is shown that does not utilize a positioning structure of the bonding structure 20. In such an embodiment, each of the bonding structures 20 is either an active bonding pad 20b or a dummy bonding pad 20d.

[0127] It should be understood that FIG. 12B to FIG. 12G Each arrangement of the bonding structures 20 discussed may be combined with one another without limitation. For example, the die attach regions 202a and 202b may utilize edge locating structures 20e and the die attach region 202c may utilize annular locating structures 20r. In another example, the die attach region 202c may utilize corner locating structures 20c and the die attach regions 202a and 202b may omit locating structures. In short, any one of the locating structures 201s may or may not be used with any one of the die attach regions 202a, 202b, and / or 202c without limitation.

[0128] exist Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig.13F and Figure 13G In FIG. 1 , device dies 205 a and 205 b (which may be referred to as die 205 ) and bridge die 305 are bonded to die 105 . Fig.13A is a cross-sectional view, and Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig.13F and Figure 13G According to the above Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F and Figure 12G The embodiment discussed Fig.13A Top view of the structure.

[0129] Each component (i.e., die 205 and bridge die 305) can be positioned over bonding structure 20 using a pick and place process. In some embodiments, each die 205 and each bridge die 305 can be placed and bonded one at a time, while in other embodiments, all dies 205 and bridge die 305 can be placed together and then bonded simultaneously. In some embodiments, such as when bridge die 305 has a smaller thickness than die 205, bridge die 305 can be placed and bonded first before the remaining dies 205 are placed and bonded.

[0130] The bonding mechanism for bonding the bridge die 305 to the device dies 105a, 105b may utilize a direct bonding process, wherein the metal of the bonding pad 20bp is directly bonded to the metal of the bonding pad 354 and the metal of the bonding pad 254, without using solder material at the interface of the bonding pad 354 and the bonding pad 254. In addition, the bonding mechanism for bonding the bridge die 305 to the device dies 105a, 105b may further include melting the dielectric bonding layer 252 to the bonding layer 18. And further, as discussed in more detail below, the bonding mechanism for bonding the bridge die 305 to the device dies 105a and 105b may further include bonding edge portions and / or corner portions of the dielectric bonding layer 252 to the positioning structure 201s.

[0131] Each die 205 bonded to die 105 may have been tested and determined to be KGD before being bonded to die 105. Although each of dies 105a and 105b is shown as being bonded to one die 205, it should be understood that other device dies similar to die 205 may be bonded to die 105. The other device dies may be the same as die 205 or different from die 205. For example, die 205 and the other device dies may be different types of dies selected from the types listed above. In addition, die 205 may be a digital circuit die, and the other device dies may be analog circuit dies. Die 105 and die 205 (and other device dies, if any) combine functions as a system. Splitting the functions and circuits of the system to different dies such as die 105 and die 205 can optimize the formation of these dies and achieve a reduction in manufacturing costs. Likewise, each bridge die 305 bonded to the die 105 to provide a bridge connection between the die 105 may be tested and determined to be a KGD prior to being bonded to the die 105 .

[0132] The die 205 and the bridge die 305 can be bonded to the die 105a and 105b by electrical contact of direct metal-to-metal bonding, melting of dielectric materials, and bonding between metal and dielectric materials. For example, the bonding pads 254 and the bonding pads 354 are bonded to the bonding structure 20 by direct metal-to-metal bonding. According to some embodiments of the present disclosure, the direct metal-to-metal bonding is a direct copper-to-copper bonding. The size of the bonding pads 254 and 354 can be greater than, equal to, or less than the size of the corresponding bonding pads 20bp. In addition, the dielectric bonding layers 252 and 352 are bonded to the bonding layer 18 by dielectric-to-dielectric bonding, which can be, for example, a molten bond (with generated Si-O-Si bonds). In addition, the edge areas and / or corner areas of the dielectric bonding layers 252 and 352 are bonded or molten to the positioning structure 20ls.

[0133] To achieve direct bonding, die 205 and bridge die 305 are positioned relative to die 105 so that the bonding pads 254 and 354 of each of die 205 and bridge die 305 are aligned with the bonding pads 20bp on die 105. The upper die (die 205 and bridge die 305) are pressed together with the lower die (dies 105a and 105b). Annealing is then performed to allow the metal in the bonding pads 20bp to diffuse with the metal of the corresponding overlying bonding pads 254 and 354. In some embodiments, the metal in the bonding structure 20 diffuses with the metal of the corresponding bonding pads 254 and 354 to align the metal lattices between the corresponding bonding pads, thereby achieving bonding of the bonding pads to each other. Even if they are bonded together, an interface between the corresponding bonding pads can still be observed, or in other words, the bonding pads 254 and the bonding pads 20bp will remain discrete and will not be completely merged together, like being melted together.

[0134] In the same process, annealing causes the dielectric bonding layer 252 and the dielectric bonding layer 352 to be fused to the corresponding bonding layer 18. In particular, the dielectric material in each layer can cross-bond with the opposite layer. For example, if the dielectric bonding layer 252 and the bonding layer 18 are both silicon oxide (SiO2), the oxygen atoms of the molecules in one bonding layer can bond with the silicon atoms and oxygen atoms of the molecules in the other bonding layer to form cross-bonds, such as Si-O-Si bonds. Similar effects can occur with other dielectric materials (such as silicon nitride, silicon oxynitride, etc.).

[0135] In the same annealing process, the annealing causes the portions of the dielectric bonding layer 252 that contact the positioning structures 201s (e.g., edge positioning structures 20e, ring positioning structures 20r, and / or corner positioning structures 20c) and the portions of the dielectric bonding layer 352 that contact the positioning structures 201s (e.g., edge positioning structures 20e, ring positioning structures 20r, and / or corner positioning structures 20c) to abut (or bond) with the metal of the positioning structures 201s. In some embodiments, the dielectric-to-metal bonding can be through metal diffusion into the dielectric bonding layer 252. For example, the metal of the positioning structures 201s can diffuse into the dielectric bonding layer 252 or 352. Then, due to the annealing, a crystallized lattice of the material including the metal and the dielectric bonding layer 252 or 352 can be formed. At the same time, the dielectric bonding layer 252 and the dielectric bonding layer 352 can act as a diffusion barrier so that diffusion does not continue into the dielectric bonding layer 252 or 352 to negatively affect the insulating properties of the dielectric bonding layer 252 or 352. In some embodiments, the dielectric-to-metal bonding can occur by forming a chemical bond between the metal of the positioning structure 201s and the dielectric bonding layer 252 or 352. For example, the annealing temperature can cause some bonds in the dielectric bonding layer 252 or 352 to break and bond to the metal of the positioning structure 201s through chemical recombination. For example, a nitride or oxide of the metal material in the positioning structure 201s can be formed. For example, when the positioning structure 201s is made of copper and the dielectric bonding layer 252 or 352 is made of silicon oxide, silicon nitride, silicon oxynitride, or the like, CuO or CuN can be formed at the interface between the dielectric bonding layer 252 or 352 and the positioning structure 201s. In some embodiments, diffusion and chemical bonding may occur simultaneously. The resulting bond between the positioning structure 201s and the dielectric bonding layer 252 or 352 is stronger for the edges and / or corners of the die 205 and the bridge die 305 than for typical fused edges and / or corners.

[0136] The annealing temperature may be higher than about 350° C., and according to some embodiments may be in a range between about 350° C. to about 550° C. The annealing time may be in a range between about 1.5 hours to about 3.0 hours, and according to some embodiments may be in a range between about 1.0 hours to about 2.5 hours.

[0137] Fig.13AFurther shown is a distance D1 of gap G1 between bridge die 305 and device die 205b. A similar gap and distance is located on the opposite side of bridge die 305 from device die 205b (between bridge die 305 and device die 205a), and the following discussion also applies to this gap. As described above, the thickness T1 of bridge die 305 is much less than the thickness T2 of device die 205b. Bridge die 305 having a thickness T1 that is less than thickness T2 allows the aspect ratio of gap G1 to be controlled by thickness T1, rather than by thickness T2. For example, for a particular distance D1 in gap G1, if thickness T1 is as large as thickness T2, gap G1 may not be reliably filled due to the extreme aspect ratio. However, using a thinner thickness T1 can reduce the aspect ratio because the aspect ratio of gap G1 becomes determined by thickness T1. Furthermore, by utilizing a reduced thickness T1, distance D1 can also be reduced to allow for better chip density on die 105. In some embodiments, thickness T1 may be in a range between about 15 μm and 50 μm, and thickness T2 may be in a range between about 5 times thickness T1 to 20 times thickness T1, for example, between about 100 μm and about 500 μm. In some embodiments, thickness T2 may be in a range between about 5 times thickness T1 to 15 times thickness T1. The distance D1 of gap G1 between bridge die 305 and device die 205b may be between about 50 μm and 100 μm. Thus, the aspect ratio is actually reduced to between about 1:5 and 1:3 (bridge die 305 is measured to have a smaller height) compared to an aspect ratio of between about 2:1 and 10:1 (which would be the case if bridge die 305 had a similar thickness to device die 205b). The distance D2 between dies 105 may be in a range between about 50 μm and 100 μm.

[0138] Embodiments may use the positioning structure 201s with the die 205 and the bridge die 305 having similar thicknesses to each other, may use the positioning structure 201s with the die 205 and the bridge die 305 having different thicknesses to each other (eg, Fig.13A ), or the positioning structure 201s may be omitted and the die 205 and the bridge die 305 may be utilized with different thicknesses. The following provides an example of using the positioning structure 201s with multiple dies having similar thicknesses to each other.

[0139] For the embodiment using the positioning structure 201s, Fig.13A A call out circle is shown in FIG. 3 to show an enlarged section of the interface at the edge of the die 205 and the bridge die 305. Fig.13AIt can be seen that the distance D3 corresponds to the width of the positioning structure 201s, the distance D4 corresponds to the width of the portion of the positioning structure 201s that has an interface with the dielectric bonding layer 252 or 352, and the distance D5 corresponds to the width of the portion of the positioning structure 201s that has no contact with the dielectric bonding layer 252 or 352, or in other words, the distance D5 corresponds to the portion of the positioning structure 201s that protrudes laterally from the edge of the tube core 205 or the bridge tube core 305). In some embodiments, the distance D3 can be in the range between about 1 μm and 5 μm. The distance D4 and the distance D5 can each be about 10% to 90% of the distance D3, their sum is 100% of the distance D3, and the distance D4 is about 0.5 μm at the minimum. The distance D4 having a minimum distance of 0.5 μm provides a sufficient positioning area for effective bonding of the corners and / or edges of the tube core 205 or the bridge tube core 305 to the positioning structure 201s.

[0140] Reference Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig.13F and Figure 13G , shows a top view of the connected die 205 and bridge die 305 according to various configurations of the bonding pads 20bp and / or the positioning structures 20ls. Fig. 13B In FIG. 1 , the edge positioning structure 20 e is continuous and completely surrounds the periphery of the die 205 and the bridge die 305 . Fig. 13C In the embodiment, the edge positioning structure 20e is disposed in the corner area of ​​the tube core 205 and the bridge tube core 305. Fig.13D , the edge positioning structures 20e are disposed in the corner regions of the die 205 and the bridge die 305. In addition, at least one of the edge positioning structures 20e is disposed along the edge between the corner regions of the die 205 and the bridge die 305. In some embodiments, the inner edge positioning structures 20e may be spaced apart from the edge positioning structures 20e at the corners by the same spacing as the spacing of the bonding structures 20 (e.g., the active bonding pads 20b and the dummy bonding pads 20d) at the inner portions of the die 205 and the bridge die 305. Fig. 13B , Fig. 13C and Fig.13D In each of the embodiments consistent with , at the corner regions of the die 205 and the bridge die 305, the area of ​​the covered edge positioning structure 20e has a quarter circular or pie wedged shape (when the edge positioning structure 20e is circular in a top view). Fig. 13B and Fig.13DIn each consistent embodiment, the area of ​​the edge locating structure 20e engaged at the corner region can be approximately half the area of ​​the edge locating structure 20e engaged at the edge region between the corner regions.

[0141] exist Fig.13E In FIG. 1 , the annular positioning structure 20r spans the periphery of the tube die 205 and the bridge tube die 305 , wherein the covered portion is bonded to the tube die 205 and the bridge tube die 305 , and the laterally protruding portion does not contact the tube die 205 and the bridge tube die 305 . Fig.13F In the embodiment, the positioning structure is a corner positioning structure 20c arranged in the corner area of ​​the tube core 205 and the bridge tube core 305, and the first leg of the L-shaped corner positioning structure 20c extends along the first edge of the tube core 205 and the bridge tube core 305, and the second leg of the L-shaped corner positioning structure 20c extends along the second edge of the tube core 205 and the bridge tube core 305, and the first edge intersects the second edge.

[0142] Figure 13G An embodiment of a positioning structure that does not utilize bonding structures 20 is shown. In such an embodiment, each of the bonding structures 20 is either an active bonding pad 20b or a dummy bonding pad 20d. As described above, in the embodiment described, the thickness of the bridge die 305 is much smaller than the die 205, and Figures 13B-13F In the consistent embodiment shown in , different thicknesses of the bridge die 305 are optional.

[0143] It should be understood that FIG. 13B to FIG. 13G Each arrangement of the die and positioning structure 201s discussed in the above can be combined with each other without restriction. For example, the die 205 can be made of a FIG. 13B to FIG. 13G Similarly, the bridge die 305 may utilize a combination of positioning structures 201s taken from FIG. 13B to FIG. 13G In short, any one of the positioning structures 201s may or may not be used with any one of the tube die 205 and the bridge tube die 305 without limitation.

[0144] exist Fig.14A and Fig. 14B In the embodiment, a fill material such as an insulating material or an encapsulant 22 may be deposited over the die 205 and the bridge die 305 and laterally surround the die 205 and the bridge die 305. Fig.14A As shown, the gap G1 between the bridge die 305 and the die 205 is reduced by reducing the thickness of the bridge die 305 (see Fig.13A), the encapsulant 22 can reliably fill the gap G1 to the bottom of the gap G1. Because the encapsulant 22 can reliably fill the gap G1, it can have an interface with the positioning structure 201s, where the positioning structure 201s intersects the sides of the tube core 205 and the bridge tube core 305. The encapsulant 22 can include a dielectric material, such as a resin, epoxy, polymer, oxide, nitride, the like, or a combination thereof, which can be deposited by any suitable process, such as flowable CVD, spin coating, PVD, the like, or a combination thereof.

[0145] like Fig.14A and 14B As shown, a planarization process can then be used to flush the upper surface of the encapsulant 22 with the upper surface of the die 205. It is worth noting that when the thickness is different, the bridge die 305 remains buried, such as Fig.14A As shown. The planarization process may include grinding and / or chemical mechanical polishing (CMP) processes. The planarization process may continue until the through silicon via 216 (if used) is exposed through the substrate 220 of the tube core 205. This may reduce the thickness of the tube core 205 from thickness T2 to thickness T3. Thickness T3 may be greater than 100 μm, for example, in the range of about 100 μm to 500 μm. In some embodiments, thickness T3 may be in the range of about 3 times thickness T1 to 10 times thickness T1.

[0146] In some embodiments, Fig.14A and Fig. 14B The structure of is only a single package location among multiple package locations. For example, the carrier substrate 10 can be a chip that extends beyond the sidewalls or encapsulation 14 shown in the figure, and additional package areas can be formed adjacent to the package areas shown in the figure. Such package areas can be separated from each other in subsequent processes. In such an embodiment, the encapsulation 14, the bonding layer 18, and the encapsulation 22 can also extend to the lateral extent of the carrier substrate 10. In other embodiments, Fig.14A and Fig. 14B The structures shown in FIG. 1 are different structures and can be formed separately on individual carrier substrates 10 .

[0147] exist Fig.15 In the embodiment, an optional wafer bonding layer 24 may be deposited on Fig.14A structure, and the optional chip 26 can be bonded to Fig.14Astructure. In some embodiments, the chip 26 may be a support wafer and may be made of any suitable material, such as silicon, sapphire, or the like. The chip bonding layer 24 may be deposited using a spin coating technique to achieve high flatness, and the chip 26 may be pressed against the chip bonding layer 24 to obtain adhesion. The chip bonding layer 24 may include any suitable material deposited by CVD, PECVD, high density plasma (HDP) CVD (HDP-CVD) or similar processes, such as silicon oxynitride, silicon carbonitride, undoped silicon glass, silicon oxide formed by TEOS, the like, or a combination thereof. In some embodiments, the chip bonding layer 24 may include gold, indium, tin, copper, the like, or a combination thereof, deposited by sputtering, PVD, plating (electroplating or electroless plating), or the like. In yet another embodiment, the chip bonding layer 24 may include a polymer or glue and may be deposited by spin coating, lamination, or the like.

[0148] exist Fig.16 In the process, carrier substrate debonding is performed to remove (or peel off) the carrier substrate 10 from the front side of the die 105 and the encapsulation body 14. According to some embodiments, the debonding includes projecting light (e.g., laser light or UV light) to the release layer 12, so that the release layer 12 decomposes under the heat of the light, and the carrier substrate 10 can be removed. Then, the above structure can be turned over and placed on top of a tape (not shown).

[0149] exist Fig.17 In the embodiment, a passivation layer 28 is formed on the front side of the device dies 105a and 105b and on the encapsulation body 14. The passivation layer 28 can be a single layer or a composite layer and can be formed of a non-porous material. In some embodiments, the passivation layer 28 includes a composite layer having a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) on the silicon oxide layer. The passivation layer 28 can also be formed of other non-porous dielectric materials, such as USG, silicon oxynitride, and the like. The passivation layer 28 can also be formed of polyimide, polybenzoxazole (PBO), and the like. The passivation layer 28 can be deposited by any suitable technique, such as PVD, CVD, spin coating, the like, or a combination thereof. Then, the passivation layer 28 can be patterned so that a plurality of openings in the passivation layer 28 expose the bonding structure 154 and the device dies 105a and 105b.

[0150] exist Fig.18In the embodiment of the present invention, a plurality of conductive connectors 34 are formed in the openings or in the passivation layer 28. In some embodiments, the conductive connectors 34 may include an optional under bump metallurgy (UBM) extending through the passivation layer 28 to physically and electrically couple to the bonding structure 154. The under bump metallurgy may be formed of the same material as the bonding structure 154. The conductive connectors 34 may include ball grid array (BGA) connectors formed by bumps, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electrolesspalladium-immersion gold (ENEPIG) technology, or the like. The conductive connectors 34 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. The conductive connectors 34 may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The conductive connector 34 may not contain solder and have substantially vertical sidewalls. In some embodiments, the conductive connector 34 includes a metal pillar 30 and a metal cap layer 32 formed on top of the metal pillar 30. The metal cap layer 32 may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

[0151] The singulation process 160 described above may be used to separate the plurality of packages into a plurality of package devices 395, each package device 395 including a die 105, a die 205, a bridge die 305, and a conductive connector 34. If used, the chip 26 may be removed or left in place. The chip 26 may be removed by grinding, etching, planarization, or a combination thereof. In some embodiments, the chip bonding layer 24 may be light sensitive, and the stripping process may include using UV light to strip the chip 26.

[0152] exist Fig.19In the embodiment of the present invention, the package device 395 is attached to the package substrate 400 through the conductive connector 34. The package substrate 400 can be a printed circuit board (PCB). The package substrate 400 can include a substrate core 402 and a plurality of bond pads 404 on the substrate core 402. An optional redistribution structure (not shown) can also be used on the substrate core 402. The substrate core 402 can be made of a semiconductor material such as silicon germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like can also be used. In addition, the substrate core 402 can be a SOI substrate. In general, the SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI or a combination thereof. The substrate core 402 can be an organic substrate. In an alternative embodiment, the substrate core 402 is based on an insulating core, such as a fiberglass reinforced resin core. An example core material is a glass fiber resin, such as FR4. An alternative to the core material includes bismaleimide-triazine (BT) resin, or other PCB materials or films. A build up film such as ABF or other laminated layers can be used for the substrate core 402.

[0153] The substrate core 402 may include active devices and passive devices (not shown). A wide variety of devices (such as transistors, capacitors, resistors, combinations of these and the like) may be used to generate and design the structure and functional requirements of the device stack. The devices may be formed using any suitable method.

[0154] In some embodiments, the conductive connectors 34 are reflowed to electrically couple and physically attach the package device 395 to the bonding pads 404. In some embodiments, a solder resist (not shown) is formed over the substrate core 402, and the conductive connectors 34 may be disposed within a plurality of openings in the solder resist to electrically and mechanically couple to the bonding pads 404. The solder resist may be used to protect areas of the substrate core 402 and / or the bonding pads 404 from external damage.

[0155] Figures 20A-20F arrive Fig.25 105 is shown as an intermediate stage of forming a package using a positioning structure according to other embodiments. These figures do not use a bridge die 305, but do show two variations of the above-described embodiments, both of which can be incorporated into the above-described embodiments using a bridge die 305. The first variation is that the die 105 is used facing up. In the above-described embodiments, the die 105 is used facing down. In addition, because a bridge die is not used, the die 105 is not shown as having been segmented before use. In other words, the chip 100 includes each of the die 105 (e.g., die 105a and die 105b) before singulation. It should therefore be understood that the above embodiments can utilize a die 105 facing up. The details of how to use a die 105 facing up can be obtained from the following description. The second variation is that the die 205 has approximately the same thickness. In the above-described embodiments, the bridge die 305 can be changed to have the same thickness as the die 205. Therefore, it should be understood from the following discussion how to use the dies with the positioning structures 201s (as described above) when the dies have the same thickness.

[0156] In the following description, similar reference component numbers are used to refer to similar components. Therefore, the discussion of these components is omitted, and the details of similar components can be referred to above. It should also be noted that, since the tube core 105 is facing up, the bonding pad 154bp (including multiple active bonding pads 154b and multiple dummy bonding pads 154d) is used to replace the bonding pad 20bp (including multiple active bonding pads 20b and multiple dummy bonding pads 20d). Similarly, the positioning structure 154ls (dummy structure, including multiple edge positioning structures 154e, multiple annular positioning structures 154r and multiple corner positioning structures 154c) is used to replace the positioning structure 20ls (including multiple edge positioning structures 20e, multiple annular positioning structures 20r and multiple corner positioning structures 20c).

[0157] Fig. 20A It is shown that a plurality of dies 105 (eg, die 105a and die 105b) are formed in a plurality of corresponding regions of chip 100. This structure is similar to Figure 3However, the die 105 is not cut and separated from the chip 100, but is temporarily kept as it is. However, in some embodiments, the die 105 can be divided and attached to the carrier (as described above). Figure 4 ), but the die 105 may be attached face-up and packaged sideways.

[0158] Fig. 20A is a cross-sectional view, and Fig. 20B , Fig. 20C , Fig.20D , Fig.20E and Fig.20F It shows the various embodiments Fig. 12A FIG. 1 is a top view of a structure of FIG. 1 , wherein the various embodiments illustrate a plurality of different architectures of a bonding structure 154 (including a positioning structure 154ls and a bonding pad 154bp). The bonding structure 154 may include a bonding pad through hole 156 or 157 (see FIG. 1 ) that is physically coupled to the bonding pad. Figure 3 ), a plurality of active bonding pads 154b having a plurality of metal features 154b connected to the die 105, a plurality of dummy bonding pads 154d not connected to any metal feature of the die 105, a plurality of edge positioning structures 154e disposed around the die attach area and serving as a special type of dummy bonding pads, a plurality of ring-shaped positioning structures 154r disposed in a ring-shaped metal line surrounding the die attach area and overlapping thereon, and a plurality of corner positioning structures 154c disposed at the corners surrounding the die attach area and in the form of an L-shaped metal line. The bonding pads 154bp may include active bonding pads 154b and / or dummy bonding pads 154d.

[0159] Reference Fig. 20B , Fig. 20C , Fig.20D , Fig.20E and Fig.20F, the die attach region 202a (as shown by the dotted line) is located at the upper surface of the die 105a. Similarly, the die attach region 202b (as shown by the dotted line) is located at the upper surface of the die 105b. The bonding structure 154 that falls completely within the die attach regions 202a and 202b can be an active bonding pad 154b and / or a dummy bonding pad 154d. For simplicity, the active bonding pad 154b and / or the dummy bonding pad 154d can be referred to as a bonding pad 154bp. The bonding structure 154 disposed at the edge of the die attach regions 202a and 202b can be an edge positioning structure 154e, an annular positioning structure 154r, or a corner positioning structure 154c. The edge positioning structure 154e, the annular positioning structure 154r, and / or the corner positioning structure 154c can be referred to as a positioning structure 154ls. Each of these locating structures 154ls is disposed at the edges and / or corners of the die attach regions 202a and 202b and is partially inside the die attach regions 202a and 202b and partially outside the die attach regions 202a and 202b.

[0160] In subsequent processing, multiple device dies are attached to die attach regions 202a and 202b and bonded to active bond pads 154b and dummy bond pads 154d. According to some embodiments, the edges of the device dies are placed on positioning structures 154ls (including edge positioning structures 154e, ring positioning structures 154r, and / or corner positioning structures 154c), and the dielectric material at the edges of the device dies is adjacent to the positioning structures 154ls, as described below.

[0161] exist Fig. 20B In the embodiment, the edge positioning structure 154e is similar to Fig. 12B The edge positioning structure 154e is formed to be continuous and completely surround the periphery of the die attach regions 202a and 202b. The edge positioning structure 154e has the same size and spacing as the bonding pads 154bp.

[0162] exist Fig. 20C In the embodiment, the edge positioning structures 154e are only provided at the corners of the die attach regions 202a and 202b, as shown in FIG. Fig. 12C The edge positioning structure 20e is the same.

[0163] exist Fig.20D In the embodiment, the edge positioning structure 154e is similar to Fig.12D The edge positioning structure 20e is disposed at the corner of the die attaching regions 202a and 202b. In addition, at least one edge positioning structure 154e is disposed around the die attaching regions 202a and 202b in each direction from the edge positioning structure 154e located at the corner.

[0164] exist Fig.20EIn the embodiment, the positioning structure 154ls replaces the edge positioning structure 154e with the ring positioning structure 154r, as shown in FIG. Fig.12E The annular positioning structure 20r is the same as the annular positioning structure 20r. The annular positioning structure 20r spans the periphery of the die bonding areas 202a and 202b. In some embodiments, the annular positioning structure 20r can be a broken ring or a segmented ring, for example, relative to Fig.12E The corresponding die attach area 202a is shown as a discontinuous line segment in the top view.

[0165] exist Fig.20F In the embodiment, the positioning structure is a corner positioning structure 154c, which is similar to the corner positioning structure 20c, as shown above. Fig.12F shown.

[0166] exist Fig.21A , Fig. 21B , Fig. 21C , Fig.21D , Fig.21E and Fig.21F In the embodiment, multiple dies 205 (e.g., device dies 205a and 205b) can be coupled to die attach regions (e.g., die attach regions 202a and 202b) of dies 105 (e.g., die 105a and die 105b). The dies can be coupled to the die attach regions 202a and 202b of the die 105 (e.g., die 105a and die 105b) by a method similar to that described above for each of the above embodiments. Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E and Fig.13F However, for Fig.21A , Fig. 21B , Fig. 21C , Fig.21D , Fig.21E and Fig.21F In the embodiment consistent with that shown in , die 205 and die 105 are face-to-face, rather than face-to-back. In particular, die 205 can be bonded to die 105 via a direct bonding process without solder material, such that bonding pad 254 is directly bonded to bonding pad 154bp, dielectric bonding layer 252 is fused or bonded to dielectric bonding layer 152, and portions of dielectric bonding layer 252 are adjacent to positioning structure 154ls (similar to the adjacent to positioning structure 20ls described above, so it will not be repeated).

[0167] Reference Fig. 21B , Fig. 21C , Fig.21D , Fig.21E and Fig.21F , shows a top view of the connected die 205 according to various configurations of the bonding pads 154bp and / or the positioning structures 154ls. Fig. 21B In FIG. 1 , the edge positioning structure 154 e is continuous and completely surrounds the periphery of the tube core 205. In FIG. Fig. 21C In FIG. 1 , the edge positioning structure 154 e is disposed in a corner region of the tube core 205 . Fig.21D In some embodiments, the edge positioning structures 154e are disposed in the corner regions of the die 205. In addition, at least one of the edge positioning structures 154e is disposed along the edge between the corner regions of the die 205. In some embodiments, the inner edge positioning structures 154e can be spaced apart from the edge positioning structures 154e at the corners by the same spacing as the spacing of the bonding pads 154bp at the inner portion of the die 205. Fig. 21B , Fig. 21C and Fig.21D In each of the embodiments consistent with , at the corner region of the die 205, the area of ​​the covered edge positioning structure 154e has a quarter circle or a pie wedge shape (when the edge positioning structure 154e is circular in top view). Fig. 21B and Fig.21D In each consistent embodiment, the area of ​​the edge locating structure 154e engaged at the corner region can be approximately half the area of ​​the edge locating structure 154e engaged at the edge region between the corner regions.

[0168] exist Fig.21E In FIG. 1 , the annular positioning structure 154 r spans the periphery of the tube die 205 , wherein the covered portion is bonded to the tube die 205 , and the laterally protruding portion does not contact the tube die 205 . Fig.21F In the embodiment, the positioning structure is a corner positioning structure 154c arranged in a corner area of ​​the tube core 205, wherein a first leg of the L-shaped corner positioning structure 154c extends along a first edge of the tube core 205, a second leg of the L-shaped corner positioning structure 154c extends along a second edge of the tube core 205, and the first edge intersects with the second edge.

[0169] exist Fig. 22 In the embodiment of the present invention, a fill material (eg, an insulating material or an encapsulant 22) may be deposited over the die 205 and laterally surround the die 205. Fig. 22 As shown, a planarization process may then be used to flush the upper surface of the encapsulant 22 with the upper surface of the die 205, wherein the planarization process is similar to the above planarization process. Fig.14A and Fig. 14B The plurality of silicon through vias 216 (see Figure 5 ) can be exposed through the planarization process.

[0170] exist Fig.23In the embodiment of the present invention, a redistribution structure 27 is formed on the package 22 and on the die 205. The redistribution structure 27 can electrically couple the signal from the silicon through-via 216 and / or other signals to the conductive connector formed subsequently. The redistribution structure 27 can be formed by a single damascene process or a dual damascene process, using alternating multiple dielectric layers 23 to form multiple metallization patterns 25m and multiple vias 25v coupled to the metallization patterns 25 through the dielectric layers 23. As an example of forming the redistribution structure 27, a first layer of dielectric layer 23 can be formed on the package 22 and on the die 205. Then, a plurality of openings can be formed in the dielectric layer 23 using an acceptable photolithography process to expose the silicon through-via 216 or other conductive features. The through hole 25v and the metallization pattern 25m can be formed in the same process, for example, by depositing a blanket seed layer over the dielectric layer 23 and over the silicon through-holes 216 and other conductive features within the plurality of openings, and the deposition includes, for example, PVD, CVD, sputtering, the like, etc. Then, a photoresist can be formed on the seed layer by spin coating and patterned, leaving a plurality of openings where the metallization pattern 25m will be deposited and up to the seed layer. Next, the conductive material of the metallization pattern 25m is deposited on the exposed seed layer, for example, by electroplating or an electrochemical process. Then, the photoresist can be removed, and the seed layer now exposed can be removed, for example, by an etching process. Then, another layer of the dielectric layer 23 can be deposited, and the metallization pattern 25m and the through hole 25 located on and passing through the other layer of the dielectric layer 23 can be formed. The process can be repeated to form any desired number of layers in the redistribution wiring structure 27.

[0171] Next, a passivation layer 28 and a plurality of conductive connections 34 may be formed on the above structure, with the conductive connections 34 being in a plurality of openings of the passivation layer 28. The passivation layer 28 and the conductive connections 34 may be formed according to the above materials and processes.

[0172] exist Fig.24 In the embodiment of the present invention, the singulation process 160 can be used to separate the die 105 and the die 205 from each other. The singulation process 160 can, for example, be used to cut the scribe lines between the package regions or between the die regions. In some embodiments, each of the singulated packages can include multiple dies 105 and / or multiple dies 205.

[0173] exist Fig.25, the package device 397 includes a second die 205 mounted to the first die 105 using a plurality of locating structures 154ls, the locating structures 154ls providing greater adhesion at the edges and / or corners of the second die 205 than a typical dielectric to dielectric fusion bond. The package device 397 can then be mounted to a package substrate 400, similar to the above description of Fig.19 Description of the package device 395.

[0174] Embodiments, at least in some embodiments, achieve advantages by providing locating structures at the edges of the die attach area of ​​the first die. The edges and / or corners of the second die can then be attached to the locating structures by a direct bonding process, which abuts the dielectric material of the second die to the conductive material of the locating structures. In some embodiments, a bridge die can be used that has a thickness less than the thickness of the additionally attached device die, so that the aspect ratio of the gap between the bridge die and the additionally attached device die can be controlled based on the thickness of the bridge die (to have a greater width than height). Embodiments including a bridge die with a reduced thickness can also be used in conjunction with locating structures to achieve better attachment of the bridge die and / or device die to the die attach area of ​​the first die.

[0175] One embodiment is a method, the method comprising aligning a bonding pad of a second die with a first bonding pad metal of a first die, the first die comprising a first bonding pad metal and a second bonding pad metal, and the second bonding pad metal is adjacent to the first bonding pad metal. The method further comprises bonding a second dielectric bonding layer of the second die to the first dielectric bonding layer of the first die. The method further comprises bonding the bonding pad of the second die to the first bonding pad metal of the first die, the bonding pad of the second die being directly interfacing with the first bonding pad metal. The method further comprises bonding the second dielectric bonding layer of the second die adjacent to the second bonding pad metal of the first die.

[0176] In an embodiment, bonding the second dielectric bonding layer, bonding the bonding pad of the second tube core, and adjoining the second dielectric bonding layer occur in the same bonding process. In an embodiment, the bonding process may include: placing the second tube core on the first tube core; pressing the bonding pad of the second tube core on the first bonding pad metal, pressing the second dielectric bonding layer on the first dielectric bonding layer, and pressing the second dielectric bonding layer on the second bonding pad metal; annealing the combination of the second tube core and the first tube core, so that the metal material of the bonding pad and the first bonding pad metal diffuse with each other, forming a dielectric to dielectric bond between the second dielectric bonding layer and the first dielectric bonding layer, and forming multiple chemical bonds between the second dielectric bonding layer and the first bonding pad metal. In an embodiment, the first bonding pad metal is arranged into a first group of bonding pads, and the second bonding pad metal is arranged into a second group of bonding pads. In an embodiment, a plurality of first bonding pads in the first group of bonding pads are spaced apart from each other by a first spacing, and a plurality of second bonding pads in the second group of bonding pads are spaced apart from each other by a first spacing. In an embodiment, the second bonding pad metal protrudes laterally from the edge of the second tube core. In an embodiment, the bonding pad is a first bonding pad, the second die is a bridge die, and the method may include: attaching the first die to a carrier; attaching the third die to the carrier; depositing a first encapsulation on the carrier, the first encapsulation laterally surrounding the first die and the third die; forming a first bonding layer over the first encapsulation and over the first die and the third die; forming a first bonding pad metal of the first die in the first bonding layer on the first die; forming a third bonding pad metal of the third die in the first bonding layer on the third die; bonding the second bonding pad of the second die to the third bonding pad metal of the third die; and adjoining the second dielectric bonding layer of the second die to the fourth bonding pad metal of the third die. In an embodiment, the method may include: bonding a first bonding pad of a fourth die to a first bonding pad metal of a first die; bonding a first bonding pad of a fifth die to a third bonding pad metal of a third die, the fourth die being laterally spaced a first distance from the second die, the second die having a first thickness, the fourth die and the fifth die having a second thickness, the second thickness being between 5 times and 15 times the first thickness; depositing a second encapsulant on the first encapsulant, the first die, the second die, the third die, the fourth die, and the fifth die, the second encapsulant contacting an upper portion of the first die between the second die and the fourth die. In an embodiment, a ratio of the first thickness to the first distance is 1:1 to 1:3.

[0177] Another embodiment is a method, the method comprising bonding a bridge die to a first die and a second die, the bridge die electrically coupling the first die to the second die, the bridge die having a first thickness. The method further comprises bonding a third die to the first die, bonding a fourth die to the second die, the bridge die being located between the third die and the fourth die, the third die having a second thickness, and the fourth die having a third thickness, wherein each of the second thickness and the third thickness is between 5 times and 15 times the first thickness. The method further comprises depositing an encapsulant over the bridge die, the first die, and the second die, the encapsulant laterally surrounding the third die, the fourth die, and the bridge die. The method further comprises grinding an upper surface of the encapsulant and an upper portion of the third die and the fourth die until each of the second thickness and the third thickness is between 3 times and 10 times the first thickness.

[0178] In an embodiment, the method may include forming a dummy support pad at the upper surface of the first tube core and the second tube core, wherein the bonding of the bridge tube core may include abutting the dielectric bonding layer of the bridge tube core with the dummy support pad. In an embodiment, the dummy support pad extends laterally beyond the edge of the bridge tube core, so that the first part of the dummy support pad has an interface with the bridge tube core, and the second part of the dummy support pad is exposed from the bridge tube core. In an embodiment, the dummy support pad is arranged at the corner of the bridge tube core, the second part of the dummy support pad is exposed from the bridge tube core along the first side of the bridge tube core, and the third part of the dummy support pad is exposed from the bridge tube core along the second side of the bridge tube core. In an embodiment, the dummy support pad has a linear structure in a plan view, and the first line portion of the dummy support pad meets the second line portion of the dummy support pad and intersects at the corner of the bridge tube core. In an embodiment, the first distance is the shortest distance between the bridge tube core and the third tube core, wherein the ratio of the first distance to the first thickness falls between 3:1 and 1:1. In an embodiment, the first thickness is between 15 μm and 25 μm.

[0179] Another embodiment is a package structure, the package structure comprising a first tube core and a second tube core. The first tube core may be provided with a first bonding pad and a dummy bonding structure at its first surface, the first bonding pad and the dummy bonding structure are laterally surrounded by a first dielectric bonding layer. The second tube core may be provided with a second bonding pad at its second surface, the second bonding pad is laterally surrounded by a second dielectric bonding layer, the second bonding pad is directly bonded to the first bonding pad, the inner portion of the second dielectric bonding layer is bonded to the first dielectric bonding layer, and the edge portion of the second dielectric bonding layer is adjacent to the dummy bonding structure.

[0180] In an embodiment, the dummy bonding structure corresponds to a corner region of the second die, and the corner region of the second die contacts the dummy bonding structure. In an embodiment, the dummy bonding structure may include a first line segment extending along a first edge of the second die and a second line segment extending along a second edge of the second die, and the first line segment and the second line segment meet at the corner region of the second die. In an embodiment, the second thickness is between 3 times and 10 times the first thickness; the encapsulant laterally surrounds the second die, the fourth die, and the bridge die, and the encapsulant completely fills the space between the bridge die and the second die, and the space has a width falling between 1 times and 3 times the first thickness.

[0181] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A package structure, characterized in that: include: A first tube core, the first tube core comprising a first bonding pad and a dummy bonding structure disposed at a first surface of the first tube core, the first bonding pad and the dummy bonding structure being laterally surrounded by a first dielectric bonding layer; as well as A second tube core, the second tube core includes a second bonding pad arranged at the second surface of the second tube core, the second bonding pad is laterally surrounded by a second dielectric bonding layer, the second bonding pad is directly bonded to the first bonding pad, the inner portion of the second dielectric bonding layer is bonded to the first dielectric bonding layer, and the edge portion of the second dielectric bonding layer is adjacent to the dummy bonding structure.

2. The package structure according to claim 1, characterized in that: The dummy bonding structure corresponds to a corner region of the second die, and the corner region of the second die contacts the dummy bonding structure.

3. The package structure according to claim 2, characterized in that: The dummy bonding structure includes a first line segment extending along a first edge of the second tube die and a second line segment extending along a second edge of the second tube die, and the first line segment and the second line segment meet at the corner area of ​​the second tube die.

4. The package structure according to claim 1, characterized in that: Also includes: a third tube core, disposed adjacent to the first tube core and spaced apart from the first tube core by a first distance; a fourth tube die, attached to the third tube die; A bridge die, attached to the first die and the third die, the bridge die spans the first distance, the bridge die has a first thickness, and the second die has a second thickness, wherein the second thickness is 3 to 10 times the first thickness; as well as An encapsulant laterally surrounds the second die, the fourth die and the bridge die, wherein the encapsulant completely fills a space between the bridge die and the second die, wherein the space has a width ranging from 1 to 3 times the first thickness.

5. The package structure according to claim 4, characterized in that: Also includes: Another encapsulation body laterally surrounds the first tube die and the third tube die.

6. The package structure according to claim 4, characterized in that: The thickness of the bridge die is between 15 μm and 25 μm.

7. The package structure according to claim 1, characterized in that: There is dielectric-to-dielectric bonding between the second dielectric bonding layer and the first dielectric bonding layer, and there are multiple chemical bonds between the second dielectric bonding layer and the first bonding pad metal.

8. The package structure according to claim 1, characterized in that: The first bonding pads include a first group of bonding pads, and the second bonding pads include a second group of bonding pads.

9. The package structure according to claim 8, characterized in that: The first group of bonding pads are spaced apart from each other by a first distance, and the second group of bonding pads are spaced apart from each other by the first distance.

10. The package structure according to claim 1, characterized in that: Also includes: a first encapsulation body, laterally surrounding the first tube core; as well as The second encapsulant laterally surrounds the second die.

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