Display panel and display device

Abstract

The utility model provides a display panel and a display device. The display panel comprises a connecting electrode, the connecting electrode is located between a first insulating layer and a second insulating layer, the connecting electrode is connected with a pixel circuit through a first via hole penetrating through the first insulating layer, and a first electrode of a light-emitting element is connected with the connecting electrode through a second via hole penetrating through the second insulating layer, the range of the ratio of the maximum size of the second via hole in the second direction to the maximum size of the pixel opening in the second direction is larger than or equal to 0.05 and smaller than or equal to 0.48, so that the flatness of the sub-pixels is facilitated, the display effect is improved, and a high-resolution product is obtained.

Description

Technical Field

[0001] At least one embodiment of the utility model relates to a display panel and a display device. Background Art

[0002] With the rapid development of science and technology, display media has become an important part of people's lives. Organic light-emitting diode (OLED) display media has excellent color and image quality due to its self-luminous property. Utility Model Content

[0003] At least one embodiment of the present utility model provides a display panel and a display device, which are beneficial to the flatness of sub-pixels, to improve the display effect, and to obtain a high-resolution product.

[0004] At least one embodiment of the utility model provides a display panel, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixels comprising pixel openings, the pixel openings being configured to define a light-emitting area of ​​the sub-pixels, a first defining portion being arranged between two adjacent pixel openings in a first direction, a second defining portion being arranged between two adjacent pixel openings in a second direction, the first direction intersecting with the second direction, a thickness of the first defining portion being unequal to a thickness of the second defining portion, the sub-pixels comprising a pixel circuit and a light-emitting element connected to the pixel circuit, the light-emitting element having a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode, the first electrode of the light-emitting element being closer to the base substrate than the light-emitting functional layer, the display panel further comprising an insulator The insulating material layer is located on the side of the pixel circuit away from the base substrate, the insulating material layer includes a first insulating layer and a second insulating layer, the first insulating layer includes an organic material, the second insulating layer includes an organic material, the first insulating layer is closer to the base substrate than the second insulating layer, the display panel also includes a connecting electrode, the connecting electrode is located between the first insulating layer and the second insulating layer, the connecting electrode is connected to the pixel circuit through a first via hole penetrating the first insulating layer, the first electrode of the light-emitting element is connected to the connecting electrode through a second via hole penetrating the second insulating layer, and the ratio of the maximum dimension of the second via hole along the second direction to the maximum dimension of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.48.

[0005] For example, a ratio of a maximum dimension of the second via hole along the second direction to a maximum dimension of the pixel opening along the second direction is in a range of greater than or equal to 0.12 and less than or equal to 0.24.

[0006] For example, a ratio of a maximum dimension of the second via hole along the first direction to a maximum dimension of the pixel opening along the first direction is in a range of greater than or equal to 0.05 and less than or equal to 0.24.

[0007] For example, a ratio of a maximum dimension of the second via hole along the first direction to a maximum dimension of the pixel opening along the first direction is in a range of greater than or equal to 0.08 and less than or equal to 0.18.

[0008] For example, the thickness of the first defining portion is smaller than the thickness of the second defining portion.

[0009] For example, the thickness of the first insulating layer is less than or equal to the thickness of the second insulating layer.

[0010] For example, the thickness of the first insulating layer is less than or equal to 2 micrometers, and the thickness of the second insulating layer is less than or equal to 2 micrometers.

[0011] For example, a size of the first via hole is less than or equal to 10 micrometers, and a size of the second via hole is less than or equal to 10 micrometers.

[0012] For example, a size of the first via hole is less than or equal to 5 micrometers, and a size of the second via hole is less than or equal to 5 micrometers.

[0013] For example, a size of the first via hole is greater than or equal to 2 micrometers, and a size of the second via hole is greater than or equal to 2 micrometers.

[0014] For example, the second via holes are multiple, the first electrode of the light emitting element is connected to the connection electrode through the multiple second via holes penetrating the second insulating layer, and the multiple second via holes are located at the edge of the pixel opening.

[0015] For example, a size of each of the plurality of second via holes is less than or equal to 10 micrometers.

[0016] For example, the orthographic projection of the connecting electrode on the base substrate overlaps with the orthographic projection of the pixel opening of the sub-pixel on the base substrate.

[0017] For example, the orthographic projection of the connecting electrode on the base substrate covers the orthographic projection of the pixel opening of the sub-pixel on the base substrate.

[0018] For example, the connection electrode contacts the first insulating layer, the connection electrode has a plurality of openings exposing a portion of the first insulating layer, and a pixel opening of one sub-pixel overlaps with one or more openings of the connection electrode.

[0019] For example, the pixel circuit includes a storage capacitor having a first plate and a second plate, the first plate and the second plate are insulated from each other, and the size of each opening of the connecting electrode is smaller than the size of the first plate and smaller than the size of the second plate.

[0020] For example, the display panel further includes at least two barrier dams and at least one isolation groove located between adjacent barrier dams, wherein the isolation groove is configured to accommodate redundant ink.

[0021] For example, the at least two barrier dams include a first barrier dam and a second barrier dam, the first barrier dam is closer to the display area of ​​the display panel than the second barrier dam, and a height of the first barrier dam is smaller than a height of the second barrier dam.

[0022] For example, the display panel also includes a pixel defining layer, which includes a defining portion and an isolation portion, the defining portion is configured to define a pixel opening of the sub-pixel, at least one of the at least two blocking dams includes the isolation portion, and the thickness of the isolation portion is greater than the thickness of the defining portion.

[0023] For example, at least one partition structure is provided in the isolation trench, and the partition structure is configured to partition the light-emitting functional layer.

[0024] For example, the display panel further includes a conductive connection portion, the conductive connection portion and the connection electrode are located in the same layer, and the conductive connection portion and the connection electrode are insulated from each other.

[0025] For example, the conductive connection portion has a plurality of hollow structures, and the connection electrode is located in one of the plurality of hollow structures.

[0026] For example, in the hollow structure and the connecting electrode located therein, the ratio of the area of ​​the connecting electrode to the area of ​​the hollow structure is less than or equal to 10%.

[0027] For example, in the hollow structure and the connecting electrode located therein, the area ratio of the connecting electrode to the hollow structure is greater than or equal to 70%.

[0028] For example, the conductive connection portion has a plurality of first conductive lines and a plurality of second conductive lines.

[0029] For example, each of the plurality of first conductive lines and each of the plurality of second conductive lines are insulated from each other, and the plurality of first conductive lines and the plurality of second conductive lines are alternately arranged in the first direction or the second direction.

[0030] For example, the connection electrode is disposed between adjacent first conductive lines and second conductive lines, and the first conductive lines, the connection electrode, and the second conductive lines are arranged in sequence.

[0031] For example, the display panel further includes a dummy block, the dummy block is floating, and the dummy block and the conductive connection portion are located in the same layer.

[0032] For example, the area of ​​the dummy block is larger than the area of ​​the connecting electrode.

[0033] For example, the dummy block is arranged in the hollow structure.

[0034] For example, the display panel further includes a dummy block, the dummy block is floating, and the dummy block and the conductive connection portion are located in the same layer.

[0035] For example, the area of ​​the dummy block is larger than the area of ​​the connecting electrode.

[0036] For example, the dummy block is disposed between adjacent first conductive lines and second conductive lines.

[0037] For example, the display panel further includes a power line connected to the conductive connection portion, and the power line is configured to provide a constant power supply voltage to the pixel circuit.

[0038] For example, the power line includes a first power line, which is connected to the pixel circuit and configured to provide a constant first voltage signal to the pixel circuit.

[0039] For example, the first power line includes a first power signal line and a first power connection line, the first power signal line and the first power connection line are connected and cross-arranged, and the conductive connection portion is connected to the first power connection line.

[0040] For example, the power line includes a second power line, which is connected to the second electrode of the light emitting element and is configured to provide a constant second voltage signal.

[0041] For example, the display panel also includes a first power line and a second power line, the first power line is connected to the pixel circuit and is configured to provide a constant first voltage signal to the pixel circuit, the second power line is connected to the second electrode of the light-emitting element and is configured to provide a constant second voltage signal, the first conductive line is connected to the first power line, and the second conductive line is connected to the second power line.

[0042] For example, the display panel also includes a conductive bus, which is located on the same layer as the connecting electrode, and the conductive bus and the conductive connecting part are an integral structure. The conductive bus extends along the second direction, and the size of the conductive bus in the second direction is larger than the size of the conductive connecting part in the second direction. The orthographic projection of the conductive bus on the base substrate overlaps with the orthographic projection of the pixel opening of the first row of sub-pixels on the base substrate.

[0043] For example, the display panel further includes a plurality of signal generating circuits, wherein each of the plurality of signal generating circuits is disposed between two adjacent columns of pixel circuits.

[0044] For example, the multiple sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, the area of ​​the pixel opening of the third sub-pixel is larger than the area of ​​the pixel opening of the second sub-pixel, and larger than the area of ​​the pixel opening of the first sub-pixel, and the number of signal generating circuits overlapping with the pixel opening of the third sub-pixel is larger than the number of signal generating circuits overlapping with the pixel opening of the first sub-pixel, and larger than the number of signal generating circuits overlapping with the pixel opening of the second sub-pixel.

[0045] For example, the signal generating circuit includes a gate signal generating circuit and a light emitting signal generating circuit, and the signal generating circuit and the light emitting signal generating circuit are formed between two different columns of pixel circuits.

[0046] For example, the pixel circuit of the first sub-pixel, the pixel circuit of the second sub-pixel, and the pixel circuit of the third sub-pixel have different widths.

[0047] For example, the width of the pixel circuit of the first sub-pixel is greater than the width of the pixel circuit of the third sub-pixel, and the width of the pixel circuit of the third sub-pixel is greater than the width of the pixel circuit of the second sub-pixel.

[0048] For example, the display panel also includes an initialization line and a first power line, the initialization line is configured to provide a constant initialization voltage to the pixel circuit, the first power line is configured to provide a constant first voltage signal to the pixel circuit, the initialization line overlaps with the pixel opening of the third sub-pixel, the first power line overlaps with the pixel opening of the first sub-pixel, and the width of the initialization line is smaller than the width of the first power line.

[0049] For example, the orthographic projection of the pixel opening of the sub-pixel on the base substrate overlaps with the orthographic projection of at least one pixel circuit on the base substrate, and overlaps with the orthographic projection of at least one signal generating circuit on the base substrate.

[0050] For example, the display panel further includes a data line, a first gate line, a second gate line, a third gate line, a fourth gate line, a first power line, a first initialization voltage line, and a second initialization voltage line, wherein the pixel circuit includes a driving transistor, a light emitting control transistor, a data writing transistor, a first reset transistor, a second reset transistor and a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate of the storage capacitor is connected to the gate of the driving transistor, the second electrode plate of the storage capacitor is connected to the first electrode of the driving transistor, the first electrode of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second electrode of the data writing transistor, the gate of the data writing transistor is connected to the first gate line, the first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate of the driving transistor, the gate of the first reset transistor is connected to the second gate line, the gate of the second reset transistor is connected to the third gate line, the first electrode of the second reset transistor is connected to the second initialization line The first gate line is connected to the first power line, the second gate line is connected to the second power line, the second gate line is connected to the first power line, the second gate line is connected to the first power line, the first ...

[0051] For example, the display panel also includes a data line, the pixel circuit includes a driving transistor and a data writing transistor, the data line is connected to a first electrode of the data writing transistor, the second electrode of the data writing transistor is connected to a gate of the driving transistor, the data lines are arranged in a plurality of data lines, the plurality of data lines include a first data line, a second data line, and a third data line, the first data line overlaps with a pixel opening of the first sub-pixel, the second data line overlaps with a pixel opening of the second sub-pixel, the third data line overlaps with a pixel opening of the third sub-pixel, the first data line, the second data line, and the third data line are arranged in sequence, and a ratio of a first spacing between the first data line and the second data line to a second spacing between the second data line and the third data line is in a range of 0.8-1.2.

[0052] For example, the multiple sub-pixels include a middle sub-pixel close to the center of the display panel and an edge sub-pixel close to the edge of the display panel, and the refresh frequency of the middle sub-pixel and the refresh frequency of the edge sub-pixel are configured to be adjustable in a preset working mode.

[0053] For example, the refresh frequency of the middle sub-pixel is greater than the refresh frequency of the edge sub-pixel.

[0054] For example, the display panel also includes a data line, the pixel circuit includes a driving transistor and a data writing transistor, the data line is connected to a first electrode of the data writing transistor, the second electrode of the data writing transistor is connected to a gate of the driving transistor, the data line is arranged in a plurality of lines, the display panel includes a display area and a peripheral area located on at least one side of the display area, the display panel also includes a plurality of fan-out lines, the data line is connected to one of the plurality of fan-out lines, the plurality of fan-out lines gradually converge in a direction from a connection position close to the data line and the fan-out line to a connection position away from the data line and the fan-out line, the plurality of fan-out lines extend from the display area to the peripheral area, the plurality of fan-out lines and the plurality of data lines are located at different layers, and the plurality of data lines are closer to the substrate than the plurality of fan-out lines.

[0055] An embodiment of the utility model further provides a display panel, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixels comprising a pixel opening, a pixel circuit and a light-emitting element connected to the pixel circuit, the light-emitting element having a first electrode, the display panel further comprising an insulating material layer, the insulating material layer being located on a side of the pixel circuit away from the base substrate, the insulating material layer comprising a first insulating layer and a second insulating layer, the first insulating layer comprising an organic material, the second insulating layer comprising an organic material, the first insulating layer being closer to the base substrate than the second insulating layer, the display panel further comprising a connecting electrode, the connecting electrode being located between the first insulating layer and the second insulating layer, the connecting electrode being connected to the pixel circuit through a first via hole penetrating the first insulating layer, the first electrode of the light-emitting element being connected to the pixel circuit through a first via hole penetrating the second insulating layer The second via hole is connected to the connecting electrode, the pixel circuit includes a driving transistor and a storage capacitor, the storage capacitor includes a first plate and a second plate, the first plate of the storage capacitor is connected to the gate of the driving transistor, the second plate of the storage capacitor is connected to the first electrode of the driving transistor, the orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, the second plate is arranged in the same layer as the channel of the driving transistor, and the second plate is closer to the substrate than the first plate, wherein the ratio of the maximum dimension of the second via hole along the second direction to the maximum dimension of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.48.

[0056] For example, an orthographic projection of the second electrode plate on the base substrate overlaps with an orthographic projection of the pixel opening on the base substrate.

[0057] For example, the pixel opening is configured to define the light-emitting area of ​​the sub-pixel, a first defining portion is set between two adjacent pixel openings in a first direction, and a second defining portion is set between two adjacent pixel openings in a second direction, the first direction intersects with the second direction, the thickness of the first defining portion is not equal to the thickness of the second defining portion, the light-emitting element also has a second electrode and a light-emitting functional layer located between the first electrode and the second electrode, and the first electrode of the light-emitting element is closer to the base substrate than at least part of the second electrode of the light-emitting element.

[0058] An embodiment of the utility model further provides a display panel, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixels comprising a pixel opening, a pixel circuit and a light-emitting element connected to the pixel circuit, the light-emitting element having a first electrode, the display panel further comprising an insulating material layer, the insulating material layer being located on a side of the pixel circuit away from the base substrate, the insulating material layer comprising a first insulating layer and a second insulating layer, the first insulating layer comprising an organic material, the second insulating layer comprising an organic material, the first insulating layer being closer to the base substrate than the second insulating layer, the display panel further comprising a connecting electrode, the connecting electrode being located between the first insulating layer and the second insulating layer, the connecting electrode being connected to the pixel circuit through a first via hole penetrating the first insulating layer, and the first via hole of the light-emitting element An electrode is connected to the connecting electrode through a second via hole penetrating the second insulating layer, and the display panel also includes a blocking dam and an encapsulation layer, wherein the encapsulation layer is configured to encapsulate the light-emitting element, the encapsulation layer includes a stack of an inorganic encapsulation film and an organic encapsulation film, and an encapsulation glue is provided on the outer side of the encapsulation layer, the second insulating layer includes a planarization layer, the planarization layer includes a first flat portion and a second flat portion, a groove is provided between the first flat portion and the second flat portion, the blocking dam is located at the periphery of the display area of ​​the display panel, and the orthographic projection of the blocking dam on the base substrate covers the orthographic projection of the groove on the base substrate; wherein the ratio of the maximum dimension of the second via hole along the second direction to the maximum dimension of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.48.

[0059] An embodiment of the utility model also provides a display panel, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixels comprising a pixel opening, a pixel circuit and a light-emitting element connected to the pixel circuit, the light-emitting element having a first electrode, the display panel further comprising an insulating material layer, the insulating material layer being located on a side of the pixel circuit away from the base substrate, the insulating material layer comprising a first insulating layer and a second insulating layer, the first insulating layer comprising an organic material, the second insulating layer comprising an organic material, the first insulating layer being closer to the base substrate than the second insulating layer, the display panel further comprising a connecting electrode, the connecting electrode being located between the first insulating layer and the second insulating layer, the connecting electrode being connected to the pixel circuit via a first via hole penetrating the first insulating layer, the first electrode of the light-emitting element being connected to the connecting electrode via a second via hole penetrating the second insulating layer, the display panel further comprising a data line, a first gate line, a second gate line, and a first initial Initialization line, wherein the pixel circuit also includes a data write transistor and a first reset transistor, the first electrode of the data write transistor is connected to the data line, the gate of the drive transistor is connected to the second electrode of the data write transistor, the gate of the data write transistor is connected to the first gate line, the first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate of the drive transistor, the gate of the first reset transistor is connected to the second gate line, the display panel is provided with a dummy sub-pixel near its edge, the dummy sub-pixel has a dummy drive transistor and a first dummy reset transistor, the first dummy reset transistor is connected to the gate of the dummy drive transistor, and the first dummy reset transistor is disconnected from the first initialization line; wherein the ratio of the maximum size of the second via along the second direction to the maximum size of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.48.

[0060] An embodiment of the utility model further provides a display panel, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixels comprising a pixel opening, a pixel circuit and a light-emitting element connected to the pixel circuit, the light-emitting element having a first electrode, the display panel further comprising an insulating material layer, the insulating material layer being located on a side of the pixel circuit away from the base substrate, the insulating material layer comprising a first insulating layer and a second insulating layer, the first insulating layer comprising an organic material, the second insulating layer comprising an organic material, the first insulating layer being closer to the base substrate than the second insulating layer, the display panel further comprising a connecting electrode, the connecting electrode being located between the first insulating layer and the second insulating layer, the connecting electrode being connected to the pixel circuit via a first via hole penetrating the first insulating layer, the first electrode of the light-emitting element being connected to the connecting electrode via a second via hole penetrating the second insulating layer, the light-emitting functional layer covering the side wall of the first defining portion and the side wall of the second defining portion, wherein the ratio of the maximum dimension of the second via hole along the second direction to the maximum dimension of the pixel opening along the second direction is in a range of greater than or equal to 0.05 and less than or equal to 0.48.

[0061] The embodiment of the utility model further provides that the thickness of the first defining portion is smaller than the thickness of the second defining portion, and the light emitting functional layer further includes a portion covering the top wall of the first defining portion. The embodiment of the utility model further provides a display device, comprising any of the above display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present utility model, rather than limiting the present utility model.

[0063] Figure 1 A schematic diagram of a via hole in a display panel for connecting a pixel circuit and a light-emitting element.

[0064] Figure 2 A schematic diagram of a via hole in a display panel for connecting a pixel circuit and a light-emitting element provided in an embodiment of the utility model.

[0065] Figure 3 A plan view of a partial structure of a display panel provided in an embodiment of the utility model.

[0066] Figure 4 A plan view of a pixel defining layer in a display panel provided in an embodiment of the utility model.

[0067] Figure 5A schematic diagram of a display panel provided in accordance with an embodiment of the present invention.

[0068] Figure 6 A plan view of a pixel defining layer in another display panel provided in an embodiment of the present utility model.

[0069] Figure 7 A plan view of a partial structure of a display panel provided in an embodiment of the utility model.

[0070] Figure 8 A circuit diagram of a display panel provided by an embodiment of the utility model.

[0071] Fig. 9 A circuit diagram of a display panel provided in accordance with another embodiment of the present invention.

[0072] Fig.10 A layout diagram of a display panel provided in one embodiment of the utility model.

[0073] FIG. 11A to FIG. 11D for Fig.10 A single layer diagram of the display panel is shown.

[0074] Fig.12 A display panel provided in an embodiment of the utility model

[0075] Fig.13 for Fig.12 A plan view of the conductive pattern layer LYm, the via hole VH1, the via hole VH2, the first electrode layer LY3, and the pixel opening in the display panel is shown.

[0076] Fig.14 A schematic diagram of a partial structure of a display panel provided in an embodiment of the utility model.

[0077] Fig.15 for Fig.14 A plan view of connecting electrodes in a display panel is shown.

[0078] Fig.16A A schematic diagram of a partial structure of a display panel provided in an embodiment of the utility model.

[0079] Fig. 16B for Fig.16A A plan view of connecting electrodes in a display panel is shown.

[0080] Fig.17A A schematic diagram of a partial structure of a display panel provided in an embodiment of the utility model.

[0081] Fig. 17B for Fig.17A A plan view of connecting electrodes in a display panel is shown.

[0082] Fig.18 A partial schematic diagram of a conductive pattern layer LYm of a display panel provided by an embodiment of the utility model.

[0083] Fig.19 A partial schematic diagram of a conductive pattern layer LYm in a display panel provided by an embodiment of the utility model.

[0084] Fig. 20 A plan view of a partial structure of a display panel provided in an embodiment of the utility model.

[0085] Fig.21 A plan view of a partial structure of a display panel provided in another embodiment of the utility model.

[0086] Fig. 22 A partial schematic diagram of a conductive pattern layer LYm in a display panel provided by an embodiment of the utility model.

[0087] Fig.23 A partial schematic diagram of another conductive pattern layer LYm in a display panel provided by an embodiment of the present invention.

[0088] Fig.24 A partial schematic diagram of another conductive pattern layer LYm in a display panel provided by an embodiment of the present invention.

[0089] Fig.25 A plan view of a partial structure of a display panel provided in an embodiment of the utility model.

[0090] Fig.26 A plan view of a partial structure of a display panel provided in an embodiment of the utility model.

[0091] Fig. 27 A plan view of a partial structure of a display panel provided in an embodiment of the utility model.

[0092] Fig.28 A plan view of a portion of the structure in another display panel provided in an embodiment of the present utility model.

[0093] Fig.29 A plan view of a portion of the structure in another display panel provided in an embodiment of the present utility model.

[0094] Fig.30 A plan view of a partial structure of a display panel provided in an embodiment of the utility model.

[0095] Fig.31A plan view of a partial structure of another display panel provided in an embodiment of the utility model.

[0096] Fig.32A A plan view of a partial structure of another display panel provided in an embodiment of the utility model.

[0097] Fig.32B A plan view of a partial structure of another display panel provided in an embodiment of the utility model.

[0098] Fig.33 A layout diagram of another display panel provided in an embodiment of the present utility model.

[0099] Figures 34 to 41 The following are cross-sectional views of partial structures of several display panels provided for some embodiments of the present utility model.

[0100] Fig.42 A plan view of a display panel provided in an embodiment of the utility model.

[0101] Fig.43 A schematic diagram of a display panel provided in an embodiment of the utility model.

[0102] Fig.44 A schematic diagram of a display panel provided in an embodiment of the utility model.

[0103] Figures 45 to 49 Schematic diagrams of several display panels provided in embodiments of the present utility model.

[0104] Fig.50 A schematic diagram of a display panel provided in accordance with an embodiment of the present invention.

[0105] Fig.51 A schematic diagram of a display panel provided in accordance with an embodiment of the present invention.

[0106] Fig.52 It is a schematic diagram of a display panel provided by an embodiment of the utility model.

[0107] Fig.53 The utility model is a circuit diagram of a dummy sub-pixel in a display panel provided by an embodiment of the present invention.

[0108] Fig.54 A layout diagram of a dummy pixel circuit in a display panel provided by an embodiment of the utility model.

[0109] Fig.55 A schematic diagram of a display panel provided in accordance with an embodiment of the present invention.

[0110] Fig.56A schematic diagram of a display panel provided in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0111] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution of the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings of the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the described embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0112] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0113] In a conventional OLED display device, the organic light-emitting layer needs to be completed by an evaporation process, which has stringent process conditions and is difficult to achieve on a large area.

[0114] Using inkjet printing to make OLED light-emitting material layers is the best way to achieve low-cost OLED display panel production and enable OLED display devices to compete in the mid-to-high-end market. Inkjet printing is an efficient process. Compared with evaporation, inkjet printing wastes less material and is very fast.

[0115] When inkjet printing is used to form the light-emitting functional layer of an organic light-emitting diode, a solvent is mainly used to dissolve the organic material to form a solution (ink), and then the solution (ink) is directly sprayed on the surface of the substrate to form a light-emitting functional layer of sub-pixels such as red (R), green (G), and blue (B). Inkjet printing OLED technology has obvious advantages over evaporation technology in terms of manufacturing process, yield, and cost. For example, the light-emitting functional layer includes multiple film layers, such as a light-emitting layer (light-emitting material layer), and the light-emitting functional layer can also have other film layers, such as a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc. At least one of the film layers of the organic light-emitting functional layer can be selected as needed. At least one film layer in the light-emitting functional layer can be produced using an inkjet printing process.

[0116] Due to the large molecular weight of polymers, they are mainly processed into films by solution processing, such as spin coating or printing, and inkjet printing technology is the best method for preparing polymer solutions. In recent years, people have made a lot of efforts to improve the pixel resolution, film uniformity and life extension of display panels, and the research on inkjet printing to form optoelectronic materials has become increasingly active. For example, the hole transport layer, hole injection layer, light-emitting layer and other film layers of the display panel can all be prepared using inkjet printing technology, laying the foundation for the use of full printing to make display panels.

[0117] When the film layer in the light-emitting functional layer is made by inkjet printing process, the flatness requirement of the light-emitting functional layer is relatively high. The flatter the light-emitting functional layer in each sub-pixel is, the more it can reduce or avoid color deviation, and the better the display effect of the display panel. In order to obtain a flat light-emitting functional layer, it can be achieved by adjusting the structure of the display panel.

[0118] Figure 1 Schematic diagram of a via hole in a display panel for connecting a pixel circuit and a light-emitting element. Figure 1 As shown, the sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a is electrically connected to the light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b. For example, the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. The light-emitting element 100b includes a light-emitting area.

[0119] like Figure 1 As shown, the light emitting element 100b includes a first electrode E1, a second electrode E2, and a light emitting functional layer FL located between the first electrode E1 and the second electrode E2. The light emitting element 100b is connected to the pixel circuit 100a through a via hole VH. Figure 1 As shown, the first electrode E1 of the light emitting element 100b is connected to the pixel circuit 100a through a via hole VH. Figure 1As shown, the first electrode E1 of the light emitting element 100b is connected to the pixel circuit 100a through a via hole VH penetrating the insulating layer ISL.

[0120] like Figure 1 As shown, the insulating layer ISL includes a planarization layer PLN and a passivation layer PVX. The material of the passivation layer PVX includes an inorganic insulating material, and the material of the planarization layer PLN includes an organic insulating material. For example, the thickness of the planarization layer PLN is 3-7 microns, and generally the thickness of the planarization layer PLN is about 4 microns. Figure 1 Other structures are also shown, for which reference may be made to the following Figure 2 Description.

[0121] The thickness of the planarization layer PLN of the display panel manufactured by inkjet printing is relatively large, and the size of the via hole VH is also relatively large. Figure 1 As shown, the size of the via hole VH is about 15-20 μm. The large size of the via hole VH is not conducive to the flatness of the sub-pixel and is not conducive to obtaining a high-resolution product.

[0122] The embodiments of the utility model provide a display panel and a display device including the display panel, which reduce the size of a via hole used to connect a pixel circuit and a light-emitting element, so as to facilitate the flatness of a sub-pixel and obtain a high-resolution product.

[0123] Figure 2 A schematic diagram of a via hole in a display panel for connecting a pixel circuit and a light-emitting element provided in an embodiment of the utility model. Figure 3 A plan view of a partial structure of a display panel provided in an embodiment of the utility model. Figure 3 The structure below the connection electrode 80 is omitted. Figure 4 A plan view of a pixel defining layer in a display panel provided in an embodiment of the utility model. Figure 5 A schematic diagram of a display panel provided in accordance with an embodiment of the present invention.

[0124] like Figures 2 to 5 As shown, an embodiment of the utility model provides a display panel, including: a base substrate BS and a plurality of sub-pixels 100 arranged on the base substrate BS, the sub-pixel 100 includes a pixel opening P0, the pixel opening P0 is configured to define the light-emitting area of ​​the sub-pixel 100, a first defining portion 301 is arranged between two adjacent pixel openings P0 in a first direction Y, a second defining portion 302 is arranged between two adjacent pixel openings P0 in a second direction X, the first direction Y intersects with the second direction X, and the thickness of the first defining portion 301 is not equal to the thickness of the second defining portion 302. Figure 2 As shown, the thickness of the first defining portion 301 is Ha, the thickness of the second defining portion 302 is Hb, and Ha≠Hb.

[0125] like Figure 2 As shown, the sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b connected to the pixel circuit 100a, the light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, and the first electrode E1 of the light-emitting element 100b is closer to the substrate BS than the light-emitting functional layer FL.

[0126] like Figure 2 As shown, the display panel also includes an insulating material layer 60, which is located on the side of the pixel circuit 100a away from the substrate BS. The insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602. The first insulating layer 601 includes an organic material, and the second insulating layer 602 includes an organic material. The first insulating layer 601 is closer to the substrate BS than the second insulating layer 602.

[0127] like Figure 2 As shown, the display panel also includes a connecting electrode 80, which is located between the first insulating layer 601 and the second insulating layer 602. The connecting electrode 80 is connected to the pixel circuit 100a through a first via hole VH1 that penetrates the first insulating layer 601, and the first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through a second via hole VH2 that penetrates the second insulating layer 602.

[0128] The display panel provided by the embodiment of the utility model can reduce the size of the second via hole VH2 by setting a first insulating layer 601 and a second insulating layer 602, and setting a connecting electrode 80 between the first insulating layer 601 and the second insulating layer 602, so as to facilitate the flatness of the sub-pixel, improve the display effect, and obtain a high-resolution product.

[0129] like Figure 3 and Figure 4 As shown, the ratio of the maximum dimension X22 of the second via hole VH2 along the second direction X to the maximum dimension DPX of the pixel opening P0 along the second direction X is in the range of greater than or equal to 0.05 and less than or equal to 0.48.

[0130] For example, the ratio of the maximum dimension X22 of the second via hole VH2 along the second direction X to the maximum dimension DPX of the pixel opening P0 along the second direction X ranges from greater than or equal to 0.12 to less than or equal to 0.24.

[0131] For example, the ratio of the maximum dimension Y22 of the second via hole VH2 along the first direction Y to the maximum dimension DPY of the pixel opening P0 along the first direction Y ranges from greater than or equal to 0.05 to less than or equal to 0.24.

[0132] For example, the ratio of the maximum dimension of the second via hole VH2 along the first direction Y to the maximum dimension of the pixel opening P0 along the first direction Y ranges from greater than or equal to 0.08 to less than or equal to 0.18.

[0133] For example, in some embodiments, the display panel includes a blue sub-pixel, a red sub-pixel, and a green sub-pixel. For the blue sub-pixel, the red sub-pixel, and the green sub-pixel, the maximum dimension X22 of the second via hole VH2 along the second direction X is 7.7 μm; for the blue sub-pixel, the maximum dimension DPX of the pixel opening P0 along the second direction X is 57 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 57 μm; for the red sub-pixel, the maximum dimension DPX of the pixel opening P0 along the second direction X is 45 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 45 μm; for the green sub-pixel, the maximum dimension DPX of the pixel opening P0 along the second direction X is 32 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 32 μm.

[0134] In some embodiments, Figure 3 and Figure 4 As shown, the maximum dimension X22 of the second via hole VH2 along the second direction X is 7.7 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 57 μm.

[0135] In some embodiments, Figure 3 and Figure 4 As shown, the maximum dimension Y22 of the second via hole VH2 along the first direction Y is 7.7 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 57 μm.

[0136] In some embodiments, Figure 3 and Figure 4 As shown, for the blue sub-pixel, the maximum dimension X22 of the second via hole VH2 along the second direction X is 7.7 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 57 μm. X22 / DPX=7.7 / 57=0.135.

[0137] In some embodiments, Figure 3 and Figure 4 As shown, for the red sub-pixel, the maximum dimension X22 of the second via hole VH2 along the second direction X is 7.7 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 45 μm. X22 / DPX=7.7 / 45=0.171.

[0138] In some embodiments, Figure 3 and Figure 4As shown, for the green sub-pixel, the maximum dimension X22 of the second via hole VH2 along the second direction X is 7.7 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 32 μm. X22 / DPX=7.7 / 32=0.241.

[0139] For example, Figure 3 and Figure 4 As shown, for the blue sub-pixel, the maximum dimension Y22 of the second via hole VH2 along the first direction Y is 7.7 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 57 μm. Y22 / DPY=7.7 / 57=0.135. Figure 3 and Figure 4 As shown, for the red sub-pixel, the maximum dimension Y22 of the second via hole VH2 along the first direction Y is 7.7 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 45 μm. Y22 / DPY=7.7 / 45=0.171.

[0140] For example, Figure 3 and Figure 4 As shown, for the green sub-pixel, the maximum dimension Y22 of the second via hole VH2 along the first direction Y is 7.7 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 32 μm. Y22 / DPY=7.7 / 32=0.241.

[0141] For example, in some embodiments, the display panel includes a blue sub-pixel, a red sub-pixel, and a green sub-pixel. For the blue sub-pixel, the red sub-pixel, and the green sub-pixel, the maximum dimension X22 of the second via hole VH2 along the second direction X is 18.6 μm; for the blue sub-pixel, the maximum dimension DPX of the pixel opening P0 along the second direction X is 65 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 145 μm; for the red sub-pixel, the maximum dimension DPX of the pixel opening P0 along the second direction X is 32 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 145 μm; for the green sub-pixel, the maximum dimension DPX of the pixel opening P0 along the second direction X is 32 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 145 μm.

[0142] In other embodiments, Figure 3 and Figure 4 As shown, for the blue sub-pixel, the maximum dimension X22 of the second via hole VH2 along the second direction X is 18.6 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 65 μm. X22 / DPX=18.6 / 65=0.286.

[0143] In other embodiments, Figure 3and Figure 4 As shown, for the red sub-pixel, the maximum dimension X22 of the second via hole VH2 along the second direction X is 18.6 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 32 μm. X22 / DPX=18.6 / 32=0.581.

[0144] In other embodiments, Figure 3 and Figure 4 As shown, for the green sub-pixel, the maximum dimension X22 of the second via hole VH2 along the second direction X is 18.6 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 32 μm. X22 / DPX=18.6 / 32=0.581.

[0145] For example, Figure 3 and Figure 4 As shown, for the blue sub-pixel, the maximum dimension Y22 of the second via hole VH2 along the first direction Y is 18.6 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 145 μm. Y22 / DPY=18.6 / 145=0.128.

[0146] For example, Figure 3 and Figure 4 As shown, for the red sub-pixel, the maximum dimension Y22 of the second via hole VH2 along the first direction Y is 18.6 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 145 μm. Y22 / DPY=18.6 / 145=0.128.

[0147] For example, Figure 3 and Figure 4 As shown, for the green sub-pixel, the maximum dimension Y22 of the second via hole VH2 along the first direction Y is 18.6 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 145 μm. Y22 / DPY=18.6 / 145=0.128.

[0148] The above description is based on an example in which the display panel includes a blue sub-pixel, a red sub-pixel, and a green sub-pixel, but the present invention is not limited thereto, and the blue sub-pixel, the red sub-pixel, and the green sub-pixel may also be replaced with sub-pixels of other suitable colors. That is, the embodiments of the present invention do not limit the luminous colors of the sub-pixels.

[0149] It should be noted that the structure of the pixel arrangement is not limited to Figure 4 As shown, the embodiment of the present invention does not limit the structure of the pixel arrangement of the display panel.

[0150] Figure 4In the example, the maximum dimension of the pixel opening P0 along the first direction Y is taken as the maximum length, and the maximum dimension DPX of the pixel opening P0 along the second direction X is taken as the maximum width. For example, in the case of other forms of pixel arrangement, the maximum dimension of the pixel opening P0 along the first direction Y or the maximum dimension DPX of the pixel opening P0 along the second direction X may also be the diagonal of the pixel opening P0. Of course, the embodiments of the present utility model include but are not limited to this.

[0151] In an embodiment of the present utility model, the second via hole VH2 may not overlap with the pixel opening P0, or may overlap with the pixel opening P0. Whether the second via hole VH2 overlaps with the pixel opening P0 mainly considers the flatness and pixel density of the pixel opening P0. Generally speaking, the flatness of the pixel opening P0 is given priority. For example, the second via hole VH2 may not overlap with the pixel opening P0, and the second via hole VH2 may overlap with the pixel opening P0 when the flatness of the pixel opening P0 is not affected.

[0152] For example, Figures 2 to 5 As shown, the display panel further includes a pixel defining layer PDL, the pixel defining layer PDL includes a defining portion 300 , the pixel opening P0 is defined by the defining portion 300 , and the defining portion 300 includes a first defining portion 301 and a second defining portion 302 .

[0153] For example, Figure 2 As shown, the thickness of the first defining portion 301 is less than the thickness of the second defining portion 302. Figure 2 As shown, the thickness of the first defining portion 301 is Ha, the thickness of the second defining portion 302 is Hb, and Ha is smaller than Hb.

[0154] In the embodiment of the present invention, the thickness of a component may refer to the dimension of the component in the third direction Z.

[0155] For example, the thickness of the first defining portion 301 is the maximum dimension of the first defining portion 301 in the third direction Z. For example, the thickness of the second defining portion 302 is the maximum dimension of the second defining portion 302 in the third direction Z.

[0156] In some drawings of the embodiments of the present utility model, the plan view shows the first direction Y and the second direction X, and the cross-sectional view shows the third direction Z. The first direction Y intersects with the second direction X, for example, the first direction Y is perpendicular to the second direction X, and the third direction Z is perpendicular to the second direction X and perpendicular to the first direction Y. Both the first direction Y and the second direction X are directions parallel to the main surface of the substrate. The third direction Z may be a direction perpendicular to the main surface of the substrate. The main surface of the substrate is a surface for manufacturing various components. Figure 2 The upper surface of the middle base substrate BS is the main surface of the base substrate.

[0157] The display panel provided by the embodiment of the present invention uses the first defining portion 301 and the second defining portion 302 with different thicknesses, which is conducive to using the inkjet printing process to manufacture at least one film layer in the light-emitting functional layer.

[0158] For example, Figure 2 As shown, the thickness of the first insulating layer 601 is less than or equal to the thickness of the second insulating layer 602 .

[0159] In the display panel provided by the embodiment of the present invention, the second insulating layer 602 can have the same thickness as the first insulating layer 601 or can be thicker than the first insulating layer 601, so as to make the first electrode of the light-emitting element flat and improve the display effect.

[0160] For example, Figure 2 As shown, the thickness of the first insulating layer 601 is less than or equal to 2 microns, and the thickness of the second insulating layer 602 is less than or equal to 2 microns.

[0161] Figure 2 Take the example that the first insulating layer 601 includes a passivation layer PVX and a planarization layer PLN1. Figure 2 Take the example that the second insulating layer 602 includes the planarization layer PLN2. In other embodiments, the second insulating layer 602 may also include a passivation layer, which may be located between the connecting electrode 80 and the planarization layer PLN2. The passivation layer can protect the conductive layer below it, and the planarization layer plays a planarization role. Of course, in other embodiments, the first insulating layer 601 may include a passivation layer, the planarization layer PLN1, and another passivation layer, and the second insulating layer 602 includes the planarization layer PLN2, that is, Figure 2 Compared to the illustrated embodiment, a passivation layer is further provided between the connection electrode 80 and the planarization layer PLN1.

[0162] The display panel provided by the embodiment of the utility model has a first insulating layer 601, a connecting electrode 80 and a second insulating layer 602 arranged between the pixel circuit and the light-emitting element. Therefore, compared with setting a single planarization layer, the thickness of the first insulating layer 601 and the thickness of the second insulating layer 602 can be set relatively small, so as to facilitate the formation of a second via hole VH2 with a smaller size.

[0163] Figure 2 Also shown are a base substrate BS, a barrier layer BR, a buffer layer BF, a gate insulating layer GI, and an interlayer insulating layer ILD.

[0164] Figure 2 The encapsulation layer EPS is also shown. The encapsulation layer EPS includes an inorganic encapsulation film EPS1, an organic encapsulation film EPS2, and an inorganic encapsulation film EPS3. Figure 2As shown, the organic encapsulation film EPS2 is located between the inorganic encapsulation film EPS1 and the inorganic encapsulation film EPS3. It should be noted that the stacking order of the organic encapsulation film and the inorganic encapsulation film is not limited to that shown in the figure, and the structure of the encapsulation layer EPS is not limited to that shown in the figure.

[0165] For example, Figure 4 As shown, the size of the first via hole VH1 is less than or equal to 10 micrometers, and the size of the second via hole VH2 is less than or equal to 10 micrometers.

[0166] For example, Figure 4 As shown, the size of the first via hole VH1 is less than or equal to 5 micrometers, and the size of the second via hole VH2 is less than or equal to 5 micrometers.

[0167] For example, Figure 4 As shown, the size of the first via hole VH1 is greater than or equal to 2 micrometers, and the size of the second via hole VH2 is greater than or equal to 2 micrometers.

[0168] In some embodiments, a size of the first via hole VH1 is greater than or equal to 2 micrometers and less than or equal to 10 micrometers; a size of the second via hole VH2 is greater than or equal to 2 micrometers and less than or equal to 10 micrometers.

[0169] In some embodiments, a size of the first via hole VH1 is greater than or equal to 2 micrometers and less than or equal to 5 micrometers; a size of the second via hole VH2 is greater than or equal to 2 micrometers and less than or equal to 5 micrometers.

[0170] For example, in an embodiment of the present invention, the size of the second via hole VH2 may be smaller than or equal to the size of the first via hole VH1 .

[0171] The size of the first via hole VH1 may refer to a maximum size of the first via hole VH1 . The size of the second via hole VH2 may refer to a maximum size of the second via hole VH2 .

[0172] For example, Figure 4 and Figure 5 As shown, the pixel defining layer PDL includes a plurality of first defining portions 301 and a plurality of second defining portions 302, the plurality of second defining portions 302 are arranged along the second direction X, the second defining portions 302 extend along the first direction Y, the plurality of first defining portions 301 are arranged into a plurality of groups 0301, each group of first defining portions 0301 is located between two adjacent second defining portions 302, the first defining portions 301 extend along the second direction X, and the first defining portions 301 in each group are arranged along the first direction Y. Figure 4 Three groups of first delimiting portions 0301 are shown.

[0173] like Figure 4As shown, a groove G0 is formed between two adjacent second defining portions 302 , and each groove G0 extends along the first direction Y. During inkjet printing, ink flows in the groove. Figure 4 Three columns of grooves G0 are shown. Taking the first direction Y as the column direction and the second direction X as the row direction as an example, the display panel includes multiple columns of grooves. One column of grooves defines multiple pixel openings P0.

[0174] like Figure 5 As shown, the base substrate BS includes a display area R01 and a peripheral area R02 located at at least one side of the display area R01. Figure 5 As shown, the orthographic projection of the portion DT01 of the data line DT located in the display area R01 on the base substrate BS is located within the orthographic projection of the second defining portion 302 on the base substrate BS. The orthographic projection of the data line DT on the base substrate BS overlaps with the orthographic projection of the second defining portion 302 of the pixel defining layer PDL on the base substrate BS, so that the second defining portion 302 has a protrusion, which is conducive to the flow of ink into the pixel opening P0 in the pixel defining layer during inkjet printing. Figure 5 As shown, the orthographic projection of the display area R01 on the base substrate BS overlaps with the orthographic projection of the pixel defining layer PDL on the base substrate BS. The orthographic projection of the pixel opening P0 of the pixel defining layer PDL on the base substrate BS falls within the orthographic projection of the display area R01 on the base substrate BS.

[0175] Figure 5 Only two data lines DT are shown. For example, one second defining portion 302 may correspond to one data line, but is not limited thereto.

[0176] For example, Figure 5 As shown, a first defining portion 301 is disposed between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is disposed between two adjacent pixel openings P0 in a second direction X, and the first direction Y intersects with the second direction X.

[0177] like Figure 4 and Figure 5 As shown, the pixel opening P0 of the sub-pixel 100 includes a pixel opening P01 of the first sub-pixel 101, a pixel opening P02 of the second sub-pixel 102, and a pixel opening P03 of the third sub-pixel 103. Figure 4 and Figure 5 As shown, the shape and size of the pixel openings P0 of each sub-pixel are the same. Of course, in other embodiments, the shape and size of the pixel openings P0 of different sub-pixels can be determined according to needs.

[0178] Figure 6 A plan view of a pixel defining layer in another display panel provided by an embodiment of the present utility model. Figure 4 The difference is, Figure 6 In the illustrated embodiment, the sizes of the pixel opening P01 of the first sub-pixel 101, the pixel opening P02 of the second sub-pixel 102, and the pixel opening P03 of the third sub-pixel 103 are different. For example, the area of ​​the pixel opening P01 of the first sub-pixel 101 is smaller than the area of ​​the pixel opening P02 of the second sub-pixel 102, and the area of ​​the pixel opening P02 of the second sub-pixel 102 is smaller than the area of ​​the pixel opening P03 of the third sub-pixel 103.

[0179] like Figure 4 and Figure 6 As shown, the areas of the pixel openings P01 of the plurality of first sub-pixels 101 are the same, the areas of the pixel openings P02 of the plurality of second sub-pixels 102 are the same, and the areas of the pixel openings P03 of the plurality of third sub-pixels 103 are the same. That is, the areas of the pixel openings P0 of the sub-pixels emitting light of the same color are the same, and the areas of the pixel openings P0 of the sub-pixels emitting light of different colors may be the same or different.

[0180] The embodiment of the present invention is described by taking the first sub-pixel 101 as a red sub-pixel, the second sub-pixel 102 as a green sub-pixel, and the third sub-pixel 103 as a blue sub-pixel as an example. Of course, the embodiment of the present invention does not limit the light-emitting conditions of each sub-pixel, and other colors of light can be emitted as needed.

[0181] Figure 7 A plan view of a partial structure of a display panel provided in an embodiment of the utility model. Figure 7 The structure below the connection electrode 80 is omitted.

[0182] For example, refer to Figure 2 and Figure 7 The second via holes VH2 are provided in plurality, and the first electrode E1 of the light emitting element 100b is connected to the connection electrode 80 through the plurality of second via holes VH2 penetrating the second insulating layer 602, and the plurality of second via holes VH2 are located at the edge of the pixel opening P0. Figure 7 As shown in FIG. 6 , the same first electrode E1 is connected to the same connection electrode 80 through a plurality of second via holes VH2 penetrating the second insulating layer 602. Figure 3 Compared with the embodiment shown in Figure 7 In the display panel provided by the illustrated embodiment, the same first electrode E1 is connected to the same connection electrode 80 through a plurality of second via holes VH2 , and the plurality of via holes are disposed at the edge of the pixel opening P0 .

[0183] Therefore, in the display panel provided in some embodiments of the present invention, multiple second via holes VH2 are set for the same first electrode E1 to improve the stability of the connection, and the multiple second via holes VH2 are dispersedly arranged at the edge of the pixel opening P0 to reduce the influence of the second via holes VH2 on the flatness of the sub-pixel, improve the display quality, and facilitate obtaining high-resolution products.

[0184] like Figure 7 As shown, four second via holes VH2 are provided for the same first electrode E1, and the four second via holes VH2 are respectively provided at the four corners of the pixel opening P0.

[0185] exist Figure 7 In the embodiment, the second via hole VH2 slightly overlaps with the pixel opening P0. Of course, the second via hole VH2 may not overlap with the pixel opening P0, or may have a larger overlapping area with the pixel opening P0. According to the wiring design around the second via hole VH2, the overlapping of the second via hole VH2 and the pixel opening P0 can be independently designed to balance the flatness.

[0186] In the embodiment of the present invention, when multiple second via holes VH2 are provided for the same first electrode E1, the size of the second via hole VH2 can be the same as that of one second via hole VH2. The size of the second via hole VH2 is mainly limited by the thickness of the second insulating layer and the process of forming the via hole.

[0187] For example, Figure 7 As shown, a size of each of the plurality of second via holes VH2 is less than or equal to 10 micrometers.

[0188] For example, Figure 3 and Figure 7 As shown, the orthographic projection of the connection electrode 80 on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 of the sub-pixel 100 on the base substrate BS. Therefore, the connection electrode 80 can play the role of leveling the light-emitting element of the sub-pixel.

[0189] For example, Figure 3 and Figure 7 As shown, the orthographic projection of the connecting electrode 80 on the base substrate BS covers the orthographic projection of the pixel opening P0 of the sub-pixel 100 on the base substrate BS. Therefore, the connecting electrode 80 can better play the role of leveling the light-emitting element of the sub-pixel.

[0190] Figure 8 A circuit diagram of a display panel provided by an embodiment of the utility model. Fig. 9 A circuit diagram of a display panel provided in accordance with another embodiment of the present invention. Fig.10 A layout diagram of a display panel provided in one embodiment of the utility model. FIG. 11A to FIG. 11D for Fig.10 A single layer diagram of the display panel is shown. Fig.11A for Fig.10 FIG. 4 is a plan view of an active layer LY0 in a display panel shown. Fig. 11B for Fig.10 FIG. 1 is a plan view of the first conductive pattern layer LY1 in the display panel shown.

[0191] Fig. 11C for Fig.10 FIG. 1 is a plan view of an interlayer insulating layer ILD in a display panel. Fig.11D for Fig.10 FIG. 4 is a plan view of the second conductive pattern layer LY2 in the display panel shown. Fig. 11C The interlayer insulating layer ILD is shown with a via hole therein. Figure 1 for Fig.10 A cross-sectional view of the display panel along line A3 - A4 is shown.

[0192] like Figure 8 and Fig. 9 As shown, each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a is electrically connected to the light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b. For example, the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. The light-emitting element 100b includes a light-emitting area.

[0193] Figure 8 Includes a pixel circuit and a light-emitting element in one sub-pixel. Fig. 9 Three sub-pixels are shown. Fig. 9 The three sub-pixels in are located in a row.

[0194] For example, Figure 8 and Fig. 9 As shown, in the sub-pixel 100, the pixel circuit 100a includes a data writing transistor T1, a reset transistor T2, a driving transistor T3, and a storage capacitor Cst, and the light emitting element 100b is connected to the driving transistor T3. The reset transistor T2 is configured to reset the gate T3g of the driving transistor T3. Figure 8 and Fig. 9 As shown, the storage capacitor Cst includes a first terminal C1 and a second terminal C2.

[0195] For example, Figure 8 and Fig. 9As shown, the display panel includes a gate line G1, a gate line G2, a data line DT, a first power line PL1, a second power line PL2, an initialization line INT1, etc. The gate line G2 can also be called a reset control signal line. For example, the first power line PL1 is configured to provide a constant first voltage signal VDD to the sub-pixel 100, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the sub-pixel 100, for example, the first voltage signal VDD is greater than the second voltage signal VSS. The gate line G1 is configured to provide a scan signal SCAN to the sub-pixel 100, the gate line G2 is configured to provide a reset control signal RESET1 to the sub-pixel 100, and the data line DT is configured to provide a data signal (data voltage) DATA to the sub-pixel 100. The initialization line INT1 is configured to provide an initialization voltage Vinit1 to the sub-pixel 100.

[0196] like Figure 8 and Fig. 9 As shown, the driving transistor T3 is electrically connected to the light emitting element 100b, and outputs a driving current to drive the light emitting element 100b to emit light under the control of the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals.

[0197] For example, the light emitting element 100 b includes an organic light emitting diode (OLED), and the light emitting element 100 b emits red light, green light, blue light, or white light when driven by its corresponding pixel circuit 100 a.

[0198] like Figure 8 and Fig. 9 As shown, the display panel further includes a gate line G5 and a light emission control transistor T5. The gate line G5 is configured to provide a light emission control signal EM to the light emission control transistor T5. The second electrode T3b of the driving transistor T3 is connected to the first power line PL1 through the light emission control transistor T5.

[0199] For example, Figure 8 and Fig. 9 As shown, the first electrode T5a of the light emitting control transistor T5 is connected to the first power line PL1, the second electrode T5b of the light emitting control transistor T5 is connected to the second electrode T3b of the driving transistor T3, and the gate T5g of the light emitting control transistor T5 is connected to the gate line G5.

[0200] For example, Figure 8 and Fig. 9As shown, the first electrode E1 of the light emitting element 100b is connected to the first electrode T3a of the driving transistor T3, the second electrode E2 of the light emitting element 100b is connected to the second power line PL2, the second electrode T3b of the driving transistor T3 is connected to the first power line PL1 through the light emitting control transistor T5, the gate T3g of the driving transistor T3 is connected to the second electrode T1b of the data writing transistor T1, the first electrode T1a of the data writing transistor T1 is connected to the data line DT, and the gate T1g of the data writing transistor T1 is connected to the gate line G1. It should be noted that the pixel circuit may not be provided with the light emitting control transistor T5, in which case the second electrode T3b of the driving transistor T3 is directly connected to the first power line PL1.

[0201] For example, Figure 8 and Fig. 9 As shown, the gate T3g of the driving transistor T3 is connected to the first terminal C1 of the storage capacitor Cst, and the second terminal C2 of the storage capacitor Cst is connected to the first electrode T3a of the driving transistor T3. The first terminal C1 of the storage capacitor Cst is also connected to the second electrode T1b of the data writing transistor T1.

[0202] For example, Figure 8 and Fig. 9 As shown, the first electrode T2a of the reset transistor T2 is connected to the initialization line INT1, the second electrode T2b of the reset transistor T2 is connected to the gate T3g of the driving transistor T3, and the gate T2g of the reset transistor T2 is connected to the gate line G2. The first end C1 of the storage capacitor Cst is also connected to the second electrode T2b of the reset transistor T2.

[0203] For example, Figure 8 and Fig. 9 As shown, the display panel further includes a reset transistor T4, and the reset transistor T4 is configured to reset the first electrode E1 of the light emitting element 100b.

[0204] For example, Figure 8 and Fig. 9 As shown, the display panel further includes a gate line G4, which may also be referred to as a reset control signal line. The gate line G4 is configured to provide a reset control signal RESET2 to the reset transistor T4.

[0205] For example, Figure 8 and Fig. 9 As shown, the display panel further includes an initialization line INT2 , and the initialization line INT2 is configured to provide an initialization voltage Vinit2 to the reset transistor T4 .

[0206] For example, Figure 8 and Fig. 9As shown, the first electrode T4a of the reset transistor T4 is connected to the initialization line INT2, the second electrode T4b of the reset transistor T4 is connected to the first electrode E1 of the light emitting element 100b, and the gate T4g of the reset transistor T4 is connected to the gate line G4.

[0207] For example, Figure 8 and Fig. 9 As shown, the second electrode T4b of the reset transistor T4 is connected to the first electrode E1 of the light emitting element 100b through the driving transistor T3, the first electrode T3a of the driving transistor T3 is connected to the first electrode E1 of the light emitting element 100b, and the second electrode T3b of the driving transistor T3 is connected to the second electrode T4b of the reset transistor T4.

[0208] For example, the initialization voltage Vinit1 and the initialization voltage Vinit2 are constant voltage signals, whose magnitudes may be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, the initialization voltage Vinit1 and the initialization voltage Vinit2 may both be less than or equal to the second voltage signal VSS.

[0209] For example, in some embodiments of the present invention, the initialization line INT1 and the initialization line INT2 are connected and are configured to provide the same initialization voltage, that is, the initialization voltage Vinit1 and the initialization voltage Vinit2 are equal, but not limited thereto. In other embodiments, the initialization line INT1 and the initialization line INT2 are insulated from each other to provide different initialization voltages.

[0210] For example, Figure 8 and Fig. 9 As shown, the gate T3g of the driving transistor T3, the first end C1 of the storage capacitor Cst, the second electrode T1b of the data writing transistor T1, and the second electrode T2b of the reset transistor T2 are connected to each other and connected to the node N1, and are at the same potential.

[0211] For example, Figure 8 and Fig. 9 As shown, the second end C2 of the storage capacitor Cst, the first electrode E1 of the light emitting element 100b, and the first electrode T3a of the driving transistor T3 are connected to each other and to the node N2, and are at the same potential.

[0212] For example, Figure 8 and Fig. 9 As shown, the second electrode T5b of the light emitting control transistor T5, the second electrode T4b of the reset transistor T4, and the second electrode T3b of the driving transistor T3 are connected to each other, and are all connected to the node N3, and are at the same potential.

[0213] For example, Fig. 9As shown, the plurality of sub-pixels 100 include a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. For example, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are sequentially arranged along the second direction X. Of course, the sub-pixels within a pixel may also be arranged in other ways.

[0214] For example, Fig. 9 As shown, the driving transistor T3 is a dual-gate transistor, including a sub-transistor T31 and a sub-transistor T32. Fig. 9 As shown, the sub-transistor T31 and the sub-transistor T32 are connected in series. Fig. 9 Taking the driving transistor T3 as a dual-gate transistor as an example, in other embodiments, in addition to the driving transistor T3, other transistors can also be set as dual-gate transistors. That is, each transistor in the pixel circuit can be set as a single-gate transistor or a dual-gate transistor as needed.

[0215] For example, Figure 8 and Fig. 9 As shown, the display panel includes a reset signal transmission line INI, and the second electrode T4b of the reset transistor T4 is connected to the second electrode T3b (node ​​N3) of the driving transistor through the reset signal transmission line INI. One reset transistor T4 can be connected to the node N3 of a row of sub-pixels through the reset signal transmission line INI.

[0216] Figure 2 , Figure 8 and Fig.10 The first terminal C1 and the second terminal C2 of the storage capacitor Cst are shown. The first terminal C1 includes a first electrode Ca (such as Fig.10 , Fig. 11B As shown), the second end C2 includes a second electrode plate Cb (as shown Fig.10 , Fig.11A As shown) and the third plate Cc (as Fig.10 , Fig.11D shown).

[0217] For example, Figure 2 As shown, the first conductive pattern layer LY1 is closer to the base substrate BS than the second conductive pattern layer LY2.

[0218] For example, Figure 4 and Figure 5 As shown, a display panel provided according to an embodiment of the present invention includes: a base substrate BS and a sub-pixel 100 arranged on the base substrate BS. The sub-pixel 100 can be arranged in plurality.

[0219] For example, Figure 2 and Fig.10As shown, the display panel further includes a pixel defining layer PDL, and the sub-pixel 100 includes a pixel opening P0, the pixel opening P0 is configured to expose at least a portion of the first electrode E1, and the pixel opening P0 is configured to define a light emitting area of ​​the sub-pixel 100. For example, Figure 2 As shown, the slope angle of the portion of the pixel defining layer PDL defining the pixel opening P0 is 40-65 degrees, but is not limited thereto.

[0220] For example, Figure 2 and Fig.10 As shown, the sub-pixel 100 includes: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a includes a storage capacitor Cst, the second plate Cb is closer to the substrate BS than the first plate Ca, and the first plate Ca is closer to the substrate BS than the third plate Cc; the light-emitting element 100b includes a first electrode E1, a second electrode E2 and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, and the pixel circuit 100a is configured to drive the light-emitting element 100b.

[0221] Figure 2 Taking the case where each film layer of the light-emitting functional layer FL is formed by inkjet printing as an example, that is, each film layer of the light-emitting functional layer FL is disposed in the pixel opening P0. However, in other implementations, part of the film layers in the light-emitting functional layer FL may be formed by inkjet printing, and another part of the film layers in the light-emitting functional layer FL may be formed by evaporation, and the film layers formed by evaporation may be common layers.

[0222] For example, Fig.10 As shown, the first power line PL1 includes a first power signal line PL11 extending along the second direction X and a first power connection line PL12 extending along the first direction Y, and the first power signal line PL11 and the first power connection line PL12 are connected.

[0223] For example, Fig.10 , Fig. 11B and Fig.11D As shown, the data line DT extends along the first direction Y, and the data line DT is formed in segments. The data line DT includes a first part DTa, a second part DTb and a third part DTc. The first part DTa and the third part DTc are connected through the second part DTb. The first part DTa and the third part DTc are located in the second conductive pattern layer LY2, and the second part DTb is located in the first conductive pattern layer LY1.

[0224] In an embodiment of the present invention, elements located in the second conductive pattern layer LY2 can be connected to elements located in the first conductive pattern layer LY1 and elements located in the active layer LY0 through vias, and elements located in the first conductive pattern layer LY1 and elements located in the active layer LY0 can be connected through elements located in the second conductive pattern layer LY2.

[0225] For example, the insulating layer penetrated by the via hole may be determined according to the condition of the insulating layer between two conductive pattern layers connected by the via hole.

[0226] like Fig.10 , Fig. 11B ,as well as Fig.11D As shown, according to some embodiments of the present invention, the display panel provided uses an active layer LY0, a first conductive pattern layer LY1, and a second conductive pattern layer LY2 to form a pixel circuit 100a, so as to simplify the manufacturing process and reduce the thickness of the display panel. The initialization line INT1 and / or the first power line PL1 can be referred to as a conductive structure 40, and the conductive structure 40 includes a signal transmission line 411 and a signal connection line 412. The conductive structure 40 is configured to provide a voltage signal to the sub-pixel 100, and the signal transmission line 411 extends along the second direction X, and the signal connection line 412 extends along the first direction Y, and the signal connection line 412 is electrically connected to the signal transmission line 411.

[0227] like Fig.10 As shown, the conductive structure 40 includes a conductive structure 400 and a conductive structure 401. Fig.10 As shown, the first power line PL1 may be referred to as a conductive structure 400 , and the initialization line INT1 may be referred to as a conductive structure 401 .

[0228] For example, Fig.10 As shown, the conductive structure 40 adopts a mesh structure, which includes a portion extending along the first direction Y (ie, the signal connection line 412 ) and a portion extending along the second direction X (ie, the signal transmission line 411 ).

[0229] For example, Fig.10 , Fig. 11B ,as well as Fig.11D As shown, two conductive pattern layers are used to form the first power line PL1 of the pixel circuit 100a. Fig.10 , Fig. 11B ,as well as Fig.11D As shown, the portion of the first power line PL1 extending along the first direction Y is formed in sections. Fig.10 and Fig.11D As shown, the portions of the first power line PL1 extending along the second direction X are all located in the second conductive pattern layer LY2 .

[0230] For example, Fig.10 , Fig. 11B ,as well as Fig.11D As shown, the signal connection line 412 includes a first portion 412a, a second portion 412b and a third portion 412c, the first portion 412a and the third portion 412c are connected through the second portion 412b, the first portion 412a and the third portion 412c are located in the first conductive pattern layer LY1, and the second portion 412b is located in the second conductive pattern layer LY2. The signal connection line 412 includes a first power connection line PL12.

[0231] For example, Fig.10 As shown, the first portion PLa and the second portion PLb of the first power connection line PL12 are connected through a via Va, and the second portion PLb and the third portion PLc of the first power connection line PL12 are connected through a via Vb.

[0232] For example, Fig.10 As shown, the first power signal line PL11 and the first power connection line PL12 are connected through a via V0.

[0233] For example, Fig.10 As shown, the first portion DTa and the second portion DTb of the data line DT are connected through a via hole Vc, and the second portion DTb and the third portion DTc of the data line DT are connected through a via hole Vd.

[0234] Fig.11A An active layer LY0 is shown. Fig.11A A channel T1 c of the data writing transistor T1 , a channel T2 c of the reset transistor T2 , a channel T3 c of the driving transistor T3 , and a channel T5 c of the light emission controlling transistor T5 are shown. Fig.11A A second plate Cb is also shown. Fig.11A As shown, the second electrode plate Cb is directly connected to the first electrode T3a of the driving transistor T3, and the two are an integrated structure. Fig.11A As shown, the second electrode T5b of the light emitting control transistor T5 is directly connected to the second electrode T3b of the driving transistor T3, and the two are an integrated structure. Fig.11A In the figure of the active layer LY0 shown, the channel T1c, the channel T2c, the channel T3c and the channel T5c are semiconductors, and the area other than the channel T1c, the channel T2c, the channel T3c and the channel T5c is a conductor. The conductor can be obtained by doping the semiconductor. For example, the material of the channel of each transistor in the active layer LY0 is polysilicon, and the conductor other than the channel is doped polysilicon. Of course, the active layer LY0 is not limited to polysilicon.

[0235] like Fig.11AAs shown, the second electrode plate Cb, the first electrode T3a of the driving transistor T3, the channel T3c of the driving transistor T3, the second electrode T3b of the driving transistor T3, the second electrode T5b of the light emitting control transistor T5, the channel T5c of the light emitting control transistor T5, and the first electrode T5a of the light emitting control transistor T5 are the same figure.

[0236] like Fig.11A As shown, the second electrode T1b of the data writing transistor T1 and the second electrode T2b of the reset transistor T2 are directly connected, and the two are an integrated structure.

[0237] like Fig.11A As shown, the second electrode T1b of the data writing transistor T1, the second electrode T2b of the reset transistor T2, the channel T1c of the data writing transistor T1, and the channel T2c of the reset transistor T2 are the same pattern.

[0238] like Fig.11A As shown, the data writing transistor T1, the reset transistor T2, and the light emission control transistor T5 are all dual-gate transistors. In the same dual-gate transistor, the portion between the two channels is a conductor.

[0239] Fig. 11B The first conductive pattern layer LY1 is shown. Fig. 11B As shown, the first conductive pattern layer LY1 includes a first end C1 (first electrode Ca), a connecting electrode CEa, a connecting electrode CEc, a connecting electrode CEd, a connecting electrode CEe, a first part DTa of the data line DT, a third part DTc of the data line DT, a first part PLa of the first power connection line PL12, and a third part PLc of the first power connection line PL12.

[0240] Fig. 11C An interlayer insulating layer ILD is shown, with vias in the interlayer insulating layer ILD being shown. Fig. 11C Vias V1 to V9, V11 - V13, vias Va to Vd, and via V0 are shown.

[0241] Fig.11D The second conductive pattern layer LY2 is shown. Fig.11D As shown, the second conductive pattern layer LY2 includes a third electrode Cc of the second end C2, a connecting electrode CEf, a gate line G1, a gate line G2, a gate line G5, a reset signal transmission line INI, an initialization voltage line INT11, and a second part PLb of the first power connection line PL12 of the first power signal line PL11.

[0242] Fig.10 A first electrode layer LY3 of the light emitting element is shown. The first electrode layer LY3 comprises a first electrode E1. Fig.10One first electrode E1 is shown. For example, each sub-pixel has one first electrode E1. The first electrode layer LY3 includes a plurality of first electrodes E1.

[0243] Fig.10 The pixel definition layer PDL is shown, and the pixel opening P0 in the pixel definition layer PDL is shown. The pixel opening P0 corresponds to the effective light-emitting area of ​​the sub-pixel. When the display panel adopts an inkjet printing process to manufacture at least one film layer in the light-emitting function layer FL, the film layer manufactured by inkjet printing is located in the pixel opening P0 of the pixel definition layer PDL.

[0244] refer to Figures 10 to 11D , the first power signal line PL11 and the first power connection line PL12 are connected through a via V0.

[0245] refer to Figures 10 to 11D The connecting electrode CEa is connected to the gate line G5 through the via hole V9, and the connecting electrode CEa serves as the gate of the light emitting control transistor T5.

[0246] refer to Figures 10 to 11D The first electrode T5a of the light emission control transistor T5 is connected to the first power line PL1 (first power signal line PL11) through the via V11, and the second electrode T5b of the light emission control transistor T5 is connected to the reset signal transmission line INI through the via V1.

[0247] refer to Figures 10 to 11D The connection electrode CEc is connected to the gate line G1 through the via hole V12, and the connection electrode CEc serves as the gate of the data writing transistor T1.

[0248] refer to Figures 10 to 11D , the data line DT is connected to the first electrode T1a of the data writing transistor T1 through the via V4.

[0249] refer to Figures 10 to 11D The connecting electrode CEd is connected to the gate line G2 through the via hole V6, and the connecting electrode CEd serves as the gate of the reset transistor T2.

[0250] refer to Figures 10 to 11D One end of the connection electrode CEe is connected to the initialization line INT1 (initialization voltage line INT11) through a via V7, and the other end of the connection electrode CEe is connected to the first electrode T2a of the reset transistor T2 through a via V8.

[0251] refer to Figures 10 to 11D One end of the connecting electrode CEf is connected to the first end C1 (the first electrode Ca, the gate of the driving transistor T3) through a via V3, and the other end of the connecting electrode CEf is connected to the first electrode T1b of the data writing transistor T1 (that is, the second electrode T2b of the reset transistor T2) through a via V5.

[0252] refer to Figures 10 to 11D The third electrode plate Cc of the second end C2 is connected to the second electrode plate Cb of the second end C2 (ie, the first electrode T3a of the driving transistor T3) through the via V2.

[0253] refer to Figures 10 to 11D The reset signal transmission line INI is connected to the second electrode T3b of the driving transistor T3 through the via hole V1. Since the second electrode T3b of the driving transistor T3 is an integral structure with the second electrode T5b of the light emitting control transistor T5, the reset signal transmission line INI is connected to the second electrode T5b of the light emitting control transistor T5 through the via hole V1.

[0254] refer to Figures 10 to 11D The second electrode T5b of the light emitting control transistor T5 and the second electrode T3b of the driving transistor T3 are both connected to the reset signal transmission line INI through the via hole V1.

[0255] The display panel provided by the embodiment of the utility model optimizes the balance between luminous uniformity and power consumption by designing the pattern of the active layer LY0 and matching the channel of the driving transistor and the pattern design of the capacitor plate located in the active layer, thereby improving the luminous uniformity of the display panel and reducing power consumption.

[0256] For example, refer to Fig.10 , Fig.11A and Fig.11D The second electrode plate Cb and the channel of the driving transistor T3 are an integrated structure and can be formed by the same film through the same patterning process. The channel of the driving transistor T3 is a semiconductor material, and the second electrode plate Cb is a conductor obtained by doping the semiconductor material.

[0257] Fig.12 A display panel provided in an embodiment of the utility model comprises: Fig.10 A connection electrode 80 is provided on the base of the display panel shown. Figure 2 for Fig.12 A cross-sectional view of the display panel along line A1 - A2 is shown. Fig.13 for Fig.12 A plan view of the conductive pattern layer LYm, the via hole VH1, the via hole VH2, the first electrode layer LY3, and the pixel opening in the display panel is shown. Fig.12 The layout of the pixel circuit in the display panel shown is similar to Fig.10 The layout of the pixel circuits in the display panel shown is the same, and the corresponding structure can be referred to Fig.10 The description will not be repeated here.

[0258] like Figure 2 and Fig.12As shown, the first electrode E1 of the light emitting element 100b is connected to the connection electrode 80 through the second via hole VH2 penetrating the second insulating layer 602, and the connection electrode 80 is connected to the pixel circuit 100a through the first via hole VH1 penetrating the first insulating layer 601. Figure 2 As shown, the connection electrode 80 is located between the first insulating layer 601 and the second insulating layer 602 .

[0259] like Fig.12 and Fig.13 As shown, the connecting electrode 80 is plate-shaped. The connecting electrode 80 overlaps with the pixel opening P0. The connecting electrode 80 can play a role in leveling the sub-pixel. The orthographic projection of the connecting electrode 80 on the base substrate can cover the orthographic projection of the pixel opening P0 on the base substrate to better play a role in leveling.

[0260] Of course, the connection electrode 80 is not limited to Fig.12 and Fig.13 In other embodiments, the connecting electrode 80 may be in other forms. Several situations are listed below.

[0261] Fig.14 A schematic diagram of a partial structure of a display panel provided in an embodiment of the utility model. Fig.15 for Fig.14 FIG. 1 is a plan view of the connecting electrodes in the display panel shown in FIG. Fig.14 and Fig.15 As shown, the connecting electrode 80 includes an electrode body 806 and a plurality of openings 808. Fig.14 and Fig.15 As shown, the plurality of openings 808 are arranged in an array in the first direction Y and the second direction X.

[0262] For example, refer to Figure 2 , Fig.14 and Fig.15 The connection electrode 80 contacts the first insulating layer 601 , and has a plurality of openings 808 exposing a portion of the first insulating layer 601 . The pixel opening P0 of one sub-pixel 100 overlaps with one or more openings of the connection electrode 80 .

[0263] In the display panel provided by the embodiment of the present invention, the connection electrode 80 is laid over a large area at the corresponding pixel opening P0 to play the role of leveling the sub-pixel, and the connection electrode 80 has a plurality of openings 808 to facilitate the degassing of the organic material of the first insulating layer 601 thereunder. For example, the connection electrode 80 has a plurality of openings 808 to facilitate the degassing of the planarization layer PLN1.

[0264] Fig.16A A schematic diagram of a partial structure of a display panel provided in an embodiment of the utility model. Fig. 16B for Fig.16A FIG. 1 is a plan view of the connecting electrodes in the display panel shown in FIG. Fig.14 and Fig.15 Compared to the display panel shown, Fig.16A and Fig. 16B The opening 808 in the display panel shown is in the shape of a long strip. Fig.16A and Fig. 16B As shown, a plurality of openings 808 are arranged in sequence in the second direction X, and each opening 808 extends along the first direction Y.

[0265] Fig.17A A schematic diagram of a partial structure of a display panel provided in an embodiment of the utility model. Fig. 17B for Fig.17A FIG. 1 is a plan view of the connecting electrodes in the display panel shown in FIG. Fig.14 and Fig.15 Compared to the display panel shown, Fig.17A and Fig. 17B The opening 808 in the display panel is shown to be circular.

[0266] It should be noted that the arrangement of the plurality of openings 808 in the connection electrode 80 is not limited to the above description and can be arranged as required.

[0267] For example, Fig.14 , Fig.16A , Fig.17A As shown, the pixel circuit 100a includes a storage capacitor Cst, the storage capacitor Cst has a first plate Ca and a second plate Cb, the first plate Ca and the second plate Cb are insulated from each other, and the size of each opening of the connecting electrode 80 is smaller than the size of the first plate Ca and smaller than the size of the second plate Cb. Fig.14 A first plate Ca and a second plate Cb are shown. Fig.16A and Fig.17A The first electrode plate Ca and the second electrode plate Cb can refer to Fig.14 shown.

[0268] Fig.14 A third plate Cc is also shown. Fig.10 The third electrode plate Cc is connected to the second electrode plate Cb. The size of each opening of the connecting electrode 80 is smaller than the size of the third electrode plate Cc, and smaller than the size of the third electrode plate Cc.

[0269] Fig.18 FIG. 1 is a partial schematic diagram of a conductive pattern layer LYm of a display panel provided by an embodiment of the present utility model. Fig.18 As shown, in the area where a sub-pixel 100 is located, there is a connecting electrode 80 . Fig.18A total of nine connection electrodes 80 are shown at the locations of six sub-pixels 100 in three rows and three columns. Of course, the arrangement of the connection electrodes 80 is not limited to this. The connection electrodes 80 may also have a relatively small area, and other conductive components may be arranged at the remaining positions where the connection electrodes 80 are not arranged. For example, these conductive components may also be connected to conductive components located in other conductive pattern layers. The following is an example of arranging other conductive components at the remaining positions where the connection electrodes 80 are not arranged as components connected to the first power line PL1 and / or the second power line PL2. That is, the layout design of the conductive pattern layer LYm may be performed.

[0270] Fig.19 A partial schematic diagram of a conductive pattern layer LYm in a display panel provided by an embodiment of the utility model. Fig. 20 A plan view of a partial structure of a display panel provided in an embodiment of the utility model. Fig.21 A plan view of a partial structure of a display panel provided in another embodiment of the utility model. Fig. 22 A partial schematic diagram of a conductive pattern layer LYm in a display panel provided by an embodiment of the utility model. Fig.23 A partial schematic diagram of another conductive pattern layer LYm in a display panel provided by an embodiment of the present invention. Fig.24 A partial schematic diagram of another conductive pattern layer LYm in a display panel provided by an embodiment of the present invention. Fig.25 A plan view of a partial structure of a display panel provided in an embodiment of the utility model. Fig.26 A plan view of a partial structure of a display panel provided in an embodiment of the utility model. Fig. 27 A plan view of a partial structure of a display panel provided in an embodiment of the utility model. Fig.28 A plan view of a portion of the structure in another display panel provided in an embodiment of the present utility model. Fig.29 A plan view of a portion of the structure in another display panel provided in an embodiment of the present utility model.

[0271] For example, Figures 19 to 29 As shown, the display panel further includes a conductive connection portion CC, the conductive connection portion CC and the connection electrode 80 are located in the same layer, that is, both are located in the conductive pattern layer LYm, and the conductive connection portion CC and the connection electrode 80 are insulated from each other. The conductive connection portion CC and the connection electrode 80 can be used to connect components that transmit different voltages, respectively. The conductive connection portion CC can be used to connect to a component that transmits a fixed voltage to reduce resistance. The conductive connection portion CC can also play a role in flattening the sub-pixel.

[0272] For example, Figures 19 to 24As shown, the conductive connection portion CC has a plurality of hollow structures K0 , and the connecting electrode 80 is located in one of the plurality of hollow structures K0 .

[0273] For example, Fig. 22 As shown, in the hollow structure K0 and the connecting electrode 80 therein, the area ratio of the connecting electrode 80 to the hollow structure K0 is less than or equal to 10%. The connecting electrode 80 occupies a relatively small proportion in the hollow structure K0.

[0274] For example, Figures 19 to 21 As shown, in the hollow structure K0 and the connecting electrode 80 therein, the area ratio of the connecting electrode 80 to the hollow structure K0 is greater than or equal to 70%. The connecting electrode 80 occupies a relatively large proportion in the hollow structure K0.

[0275] For example, Figure 25 to Figure 29 As shown, the conductive connection portion CC has a plurality of first conductive lines CC1 and a plurality of second conductive lines CC2.

[0276] For example, Figure 25 to Figure 29 As shown, each of the plurality of first conductive lines CC1 and each of the plurality of second conductive lines CC2 are insulated from each other, and the plurality of first conductive lines CC1 and the plurality of second conductive lines CC2 are alternately arranged in the first direction Y or the second direction X. Fig.26 and Fig. 27 As shown, a plurality of first conductive lines CC1 and a plurality of second conductive lines CC2 are alternately arranged in the second direction X. Fig.28 and Fig.29 As shown, a plurality of first conductive lines CC1 and a plurality of second conductive lines CC2 are alternately arranged in the first direction Y. As shown in FIG.

[0277] For example, Fig.25 As shown, the first conductive line CC1 and the second conductive line CC2 are arranged along the second direction X, and the connecting electrode 80 is located in the hollow structure K0 of the first conductive line CC1.

[0278] For example, Figure 26 to Figure 29 As shown, the connection electrode 80 is disposed between adjacent first conductive lines CC1 and second conductive lines CC2 , and the first conductive lines CC1 , the connection electrode 80 , and the second conductive lines CC2 are arranged in sequence.

[0279] like Fig.26 and Fig. 27 As shown, the first conductive line CC1, the connecting electrode 80, and the second conductive line CC2 are arranged in sequence in the second direction X. Fig.28 and Fig.29 As shown, the first conductive line CC1, the connecting electrode 80, and the second conductive line CC2 are arranged in sequence in the first direction Y.

[0280] For example, Figure 23 to Figure 29 As shown, the display panel further includes a dummy block DM, the dummy block DM is floating, and the dummy block DM and the conductive connection part CC are located in the same layer. The dummy block DM can play a role in flattening the sub-pixel.

[0281] For example, Fig.23 and Fig.24 As shown, the area of ​​the dummy block DM is larger than the area of ​​the connection electrode 80 .

[0282] For example, Fig.23 and Fig.24 As shown, the dummy block DM is arranged in the hollow structure K0. Fig.23 and Fig.24 As shown, the dummy block DM and the connecting electrode 80 are arranged in the same hollow structure K0. Fig.24 A hollow structure K01 and a hollow structure K02 are shown. The dummy block DM is located in the hollow structure K02, and the connecting electrode 80 is located in the hollow structure K01.

[0283] For example, Fig.26 and Fig.28 As shown, the display panel further includes a dummy block DM, the dummy block DM is floating, and the dummy block DM and the conductive connection part CC are located in the same layer.

[0284] For example, Fig.26 and Fig.28 As shown, the area of ​​the dummy block DM is larger than the area of ​​the connection electrode 80 .

[0285] For example, Fig.26 and Fig.28 As shown, the dummy block DM is disposed between adjacent first conductive lines CC1 and second conductive lines CC2.

[0286] Fig. 27 The first conductive line CC1 shown may be Fig.26 The dummy block DM in the embodiment is extended to the first conductive line CC1 and merged with the first conductive line CC1.

[0287] Fig.29 The first conductive line CC1 shown may be Fig.26 The dummy block DM in the embodiment is widened to the first conductive line CC1 and merged with the first conductive line CC1. Fig.29 The second conductive line CC2 shown may be Fig.26 The dummy block DM in the embodiment is widened to the second conductive line CC2 and merged with the second conductive line CC2.

[0288] For example, Fig. 20 , Fig.21 , Figure 26 to Figure 29As shown, the display panel further includes a power line, which is connected to the conductive connection portion CC, and the power line is configured to provide a constant power voltage to the pixel circuit 100 a.

[0289] For example, Fig. 20 , Figure 26 to Figure 29 As shown, the power lines include a first power line PL1 , which is connected to the pixel circuit 100 a and configured to provide a constant first voltage signal to the pixel circuit 100 a .

[0290] For example, refer to Figure 5 , Fig. 20 , Figure 26 to Figure 29 The first power line PL1 includes a first power signal line PL11 and a first power connection line PL12. The first power signal line PL11 and the first power connection line PL12 are connected and cross-arranged, and the conductive connection part CC is connected to the first power connection line PL12. The first power line PL1 (first power connection line PL12) is connected to the first conductive line CC1 through a via H1.

[0291] For example, Figure 8 , Fig.21 , Figure 26 to Figure 29 As shown, the power line includes a second power line PL2, which is connected to the second electrode E2 of the light emitting element 100b and is configured to provide a constant second voltage signal.

[0292] For example, Figure 25 to Figure 29 As shown, the display panel further includes a first power line PL1 and a second power line PL2, the first power line PL1 is connected to the pixel circuit 100a and is configured to provide a constant first voltage signal to the pixel circuit 100a, the second power line PL2 is connected to the second electrode E2 of the light emitting element 100b and is configured to provide a constant second voltage signal, the first conductive line CC1 is connected to the first power line PL1, and the second conductive line CC2 is connected to the second power line PL2. The second conductive line CC2 is connected to the second power line PL2 through a via H2.

[0293] Fig. 20 , Fig.21 , Figure 25 to Figure 29 Also shown are the first electrode E1 and the second via hole VH2.

[0294] Fig.30 A plan view of a partial structure of a display panel provided in an embodiment of the utility model. Fig.31 A plan view of a partial structure of another display panel provided in an embodiment of the utility model. Fig.32A A plan view of a partial structure of another display panel provided in an embodiment of the utility model. Fig.32BA plan view of a partial structure of another display panel provided in an embodiment of the utility model.

[0295] For example, Figures 30 to 32B As shown, the display panel also includes a conductive bus LN, the conductive bus LN and the connecting electrode 80 are located in the same layer, the conductive bus LN and the conductive connecting part CC are an integrated structure, the conductive bus LN extends along the second direction X, and the size of the conductive bus LN in the second direction X is greater than the size of the conductive connecting part CC in the second direction X. Figures 30 to 32B The conductive bus LN shown can be connected to the first power line PL1 or the second power line PL2. Figures 30 to 32B The conductive connection portion CC shown may be a first conductive line CC1 connected to the first power line PL1, or Figures 30 to 32B The conductive connection portion CC shown may be a second conductive line CC2.

[0296] For example, Figures 30 to 32B As shown, the display panel includes a first row of sub-pixels R1 and a second row of sub-pixels R2, and the conductive bus LN overlaps with the pixel opening P0 of the first row of sub-pixels R1. That is, the orthographic projection of the conductive bus LN on the substrate overlaps with the orthographic projection of the pixel opening P0 of the first row of sub-pixels R1 on the substrate. In this way, the conductive bus LN can be set in the display area to reduce the size of the frame and achieve a narrow frame. The smaller frame size meets future trends and customer needs.

[0297] Fig.32B A connection electrode 801 of a first row of sub-pixels R1 and a connection electrode 802 of a second row of sub-pixels R2 are shown.

[0298] like Fig.32B As shown, the size of the connecting electrode 801 in the first direction Y is smaller than the size of the connecting electrode 802 in the first direction Y.

[0299] like Fig.32B As shown, the area of ​​the connecting electrode 801 is smaller than the area of ​​the connecting electrode 802 .

[0300] Fig.32A and Fig.32B The conductive connection part CC in the display panel shown can be Fig.31 The dummy block DM in the display panel shown is widened to the right and merged with the conductive connection portion CC.

[0301] For example, Fig.12 , Fig.14 , Fig.16A , Fig.17A , Fig. 20 , Fig.21 , Figures 25 to 32BAs shown, in order to obtain a higher pixel density (Pixels Per Inch, PPI), the orthographic projection of the connecting electrode 80 on the substrate overlaps with the orthographic projection of the pixel opening P0 on the substrate.

[0302] Fig.33 Another display panel layout diagram provided by an embodiment of the present utility model. Fig.12 Compared with the layout shown in FIG. 1 , the first power connection line PL12 is not formed in a segmented manner, but is formed by the same film layer, namely, the first conductive pattern layer LY1. In other embodiments, the layout may also be changed so that the first power connection line PL12 is formed by the same film layer, namely, the second conductive pattern layer LY2. Thus, the layout of the display panel provided by the embodiment of the utility model can be adjusted as needed.

[0303] Figures 34 to 41 The following are cross-sectional views of partial structures of several display panels provided for some embodiments of the present utility model. Fig.42 A plan view of a display panel provided in an embodiment of the utility model.

[0304] For example, Figures 34 to 41 As shown, the display panel further includes at least two barrier dams DMM and at least one isolation groove G located between adjacent barrier dams DMM, and the isolation groove G is configured to accommodate redundant ink.

[0305] For example, Figures 34 to 41 As shown, the at least two barrier dams DMM include a first barrier dam DM1 and a second barrier dam DM2 , the first barrier dam DM1 is closer to the display region R01 of the display panel than the second barrier dam DM2 , and the height of the first barrier dam DM1 is less than that of the second barrier dam DM2 .

[0306] Fig.35 A height TK2 of the first barrier dam DM1 and a height TK3 of the second barrier dam DM2 are shown, and the height TK2 is smaller than the height TK3 .

[0307] For example, Figures 34 to 41 As shown, the display panel further includes a pixel defining layer PDL, the pixel defining layer PDL includes a defining portion 3012 and an isolating portion 312, the defining portion 3012 is configured to define the pixel opening P0 of the sub-pixel 100, and at least one of the at least two blocking dams DMM includes the isolating portion 312. Fig.35 As shown, the thickness of the isolation portion 312 is greater than the thickness of the defining portion 3012. For example, the defining portion 3012 includes the first defining portion 301 and the second defining portion 302 described above. Fig.35 A maximum height TK1 of the delimiting portion 3012 of the PDL is also shown.

[0308] For example, Figures 34 to 41 As shown, at least one partition structure ST is provided in the isolation trench G, and the partition structure ST is configured to partition the light-emitting functional layer FL to prevent water and oxygen from invading the light-emitting functional layer FL in the display area. One or more partition structures ST may be provided in the same isolation trench G.

[0309] Fig.37 There are shown two isolation trenches G. The two isolation trenches G may have different depths.

[0310] like Fig.37 As shown, the depth of the isolation trench G1 is smaller than the depth of the isolation trench G2.

[0311] like Fig.37 As shown, the isolation trench G1 is closer to the display area than the isolation trench G2.

[0312] Fig.39 A barrier dam DM0, a barrier dam DM1, a barrier dam DM2, and a barrier dam DM3 are shown.

[0313] exist Figures 34 to 41 In the figure, the left side is the display area and the right side is the peripheral area.

[0314] Figures 34 to 41 A cutting line CL is also shown. The portion on the right side of the cutting line CL will be removed after cutting. That is, the cutting design of the peripheral area of ​​the display panel can be performed when at least one film layer of the light-emitting functional layer is manufactured by the inkjet printing process.

[0315] Figures 34 to 41 The planarization layer PLN1 and the planarization layer PLN2 in the display panel are shown. Figure 34 to Figure 39 The partition structure ST is made of the planarization layer PLN1 to form a T-shaped or half-T-shaped partition structure. Fig.40 The partition structure ST is made of a film layer located above the planarization layer PLN1 to form a T-shaped partition structure. Fig.41 The partition structure ST is made of a film layer located above the planarization layer PLN1 to form an I-shaped partition structure. Fig.40 The partition structure ST shown may be made of metal and / or insulating material. Fig.41 The partition structure ST shown can be made of metal material.

[0316] It should be noted that the embodiments of the present invention do not limit the shape or film composition of the partition structure, nor are they limited to the forms shown in the figures, as long as they can play the role of partitioning the light-emitting functional layer FL.

[0317] like Fig.42As shown, the display panel includes a display area R01 and a peripheral area R02 surrounding the display area R01. The display area R01 is a region where images can be displayed, and the peripheral area R02 is a frame region.

[0318] Fig.42 The isolation trench G and the barrier dam DMM are shown. Fig.42 As shown, the isolation trench G includes an isolation trench G01 and an isolation trench G02. The number of isolation trenches G and the number of barrier dams DMM are not limited to those shown in the figure, and can be determined according to needs.

[0319] Fig.43 A schematic diagram of a display panel provided in an embodiment of the utility model. Fig.44 A schematic diagram of a display panel provided in an embodiment of the utility model. Figures 45 to 49 Schematic diagrams of several display panels provided in embodiments of the present utility model.

[0320] For example, Figure 43 to Figure 49 As shown, the display panel further includes a plurality of signal generating circuits GDC, each of which is arranged between two adjacent columns of pixel circuits PDC. Such an arrangement can facilitate the realization of a narrow frame.

[0321] For example, Figures 44 to 49 As shown, the plurality of sub-pixels 100 include a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. The area of ​​the pixel opening P0 of the third sub-pixel 103 is greater than the area of ​​the pixel opening P0 of the second sub-pixel 102, and greater than the area of ​​the pixel opening P0 of the first sub-pixel 101. The number of signal generating circuits GDC overlapping with the pixel opening P0 of the third sub-pixel 103 is greater than the number of signal generating circuits GDC overlapping with the pixel opening P0 of the first sub-pixel 101, and greater than the number of signal generating circuits GDC overlapping with the pixel opening P0 of the second sub-pixel 102. Such a configuration is conducive to the layout of the signal generating circuit GDC and to the realization of a narrow frame.

[0322] In the utility model Figures 44 to 49 In the illustrated embodiment, for clarity of illustration, the pixel opening P0 is placed below its corresponding pixel circuit PDC and / or signal generating circuit GDC. That is, in an actual display panel, the pixel opening P0 of the sub-pixel 100 overlaps with its corresponding pixel circuit PDC and / or signal generating circuit GDC.

[0323] For example, Fig.43 As shown, the signal generating circuit GDC includes a gate signal generating circuit GC and a light emitting signal generating circuit EC, and the signal generating circuit GDC and the light emitting signal generating circuit GDC are formed between two different columns of pixel circuits PDC. Fig.43As shown, the pixel circuit PDC is located in the first setting area DA, and the signal generating circuit GDC is located in the second setting area SA. Fig.43 As shown, the signal generating circuit GDC includes a signal generating circuit Dg1, a signal generating circuit Dg2, a signal generating circuit De1, and a signal generating circuit De2.

[0324] like Fig.43 As shown, the signal generating circuit Dg1 is located between two adjacent columns of pixel circuits PDC, the signal generating circuit Dg2 is located between two adjacent columns of pixel circuits PDC, the signal generating circuit De1 is located between two adjacent columns of pixel circuits PDC, and the signal generating circuit De2 is located between two adjacent columns of pixel circuits PDC.

[0325] like Fig.43 As shown, a plurality of signal generating circuits Dg1 and a plurality of pixel circuits PDC are alternately arranged in the second direction X.

[0326] Fig.43 The gate line GL and the light emission control signal line EL are also shown. The gate line GL may be the gate line G1 or the gate line G2, and the light emission control signal line EL may be the gate line G5.

[0327] For example, Figure 46 to Figure 48 As shown, the pixel circuit PDC of the first sub-pixel 101, the pixel circuit PDC of the second sub-pixel 102, and the pixel circuit PDC of the third sub-pixel 103 have different widths. The width of the pixel circuit PDC is the size of the pixel circuit PDC in the second direction X. The different widths of the pixel circuit PDC can reserve space for setting the signal generation circuit GDC.

[0328] For example, Figure 46 to Figure 48 As shown, the width of the pixel circuit PDC of the first sub-pixel 101 is greater than the width of the pixel circuit PDC of the third sub-pixel 103 , and the width of the pixel circuit PDC of the third sub-pixel 103 is greater than the width of the pixel circuit PDC of the second sub-pixel 102 .

[0329] For example, Figure 8 , Fig. 9 and Fig.47 As shown, the display panel also includes an initialization line INT1 and a first power line PL1. The initialization line INT1 is configured to provide a constant initialization voltage Vinit1 to the pixel circuit PDC. The first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit PDC. The initialization line INT1 overlaps with the pixel opening P0 of the third sub-pixel 103. The first power line PL1 overlaps with the pixel opening P0 of the first sub-pixel 101. The width of the initialization line INT1 is smaller than the width of the first power line PL1.

[0330] For example, Fig.47 As shown, the orthographic projection of the pixel opening P0 of the sub-pixel 100 on the substrate BS overlaps with the orthographic projection of at least one pixel circuit PDC on the substrate BS, and overlaps with the orthographic projection of at least one signal generating circuit GDC on the substrate BS.

[0331] For example, Figure 8 and Fig.47 As shown, the display panel also includes a data line DT, a gate line G1, a gate line G2, a gate line G4, a gate line G5, a first power line PL1, a first initialization voltage line INT1, and a second initialization voltage line INT2. The pixel circuit PDC includes a driving transistor T3, a light emitting control transistor T5, a data writing transistor T1, a reset transistor T2, a reset transistor T4 and a storage capacitor Cst. The storage capacitor Cst includes a first electrode Ca and a second electrode Cb. The first electrode Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3, the second electrode Cb of the storage capacitor Cst is connected to the first electrode of the driving transistor T3, the first electrode of the data writing transistor T1 is connected to the data line DT, the gate of the driving transistor T3 is connected to the second electrode of the data writing transistor T1, the gate of the data writing transistor T1 is connected to the gate line G1, the first electrode of the reset transistor T2 is connected to the first initialization line INT1, the second electrode of the reset transistor T2 is connected to the gate of the driving transistor T3, and the reset The gate of transistor T2 is connected to the gate line G2, the gate of reset transistor T4 is connected to the gate line G4, the first electrode of reset transistor T4 is connected to the second initialization line INT1, the second electrode of reset transistor T4 is connected to light-emitting element 100b through driving transistor T3, the gate of light-emitting control transistor T5 is connected to the gate line G5, the first electrode of light-emitting control transistor T5 is connected to the first power line PL1, the second electrode of light-emitting control transistor T5 is connected to the second electrode of driving transistor T3, and multiple signal generating circuits GDC include a first gate signal generating circuit G11, a second gate signal generating circuit G22, a light-emitting control signal generating circuit EN, and an initialization voltage generating circuit Vv. The first gate signal generating circuit G11 is connected to the gate line G1, the second gate signal generating circuit G22 is connected to the gate line G2 and / or the gate line G4, the light-emitting control signal generating circuit EN is connected to the gate line G5, and the initialization voltage generating circuit Vv is connected to the first initialization line INT1 and / or the second initialization line INT2.

[0332] For example, the gate line G1 may be a first gate line, the gate line G2 may be a second gate line, the gate line G4 may be a third gate line, and the gate line G5 may be a fourth gate line.

[0333] For example, the reset transistor T2 may be a first reset transistor, and the reset transistor T4 may be a second reset transistor.

[0334] like Figure 8 and Fig.47 As shown, the width of the first gate signal generating circuit G11 is greater than the width of the light emitting control signal generating circuit EN, the width of the light emitting control signal generating circuit EN is greater than the width of the second gate signal generating circuit G22, and the width of the second gate signal generating circuit G22 is greater than the width of the initialization voltage generating circuit Vv.

[0335] In the embodiment of the present invention, the pixel circuit PDC may be the pixel circuit 100 a described above, but is not limited thereto.

[0336] For example, Fig.49 As shown, the display panel also includes a data line DT, the pixel circuit PDC includes a driving transistor T3 and a data writing transistor T1, the data line DT is connected to the first electrode of the data writing transistor T1, the second electrode of the data writing transistor T1 is connected to the gate of the driving transistor T3, the data line DT is set to multiple, the multiple data lines DT include a first data line DT1, a second data line DT2, and a third data line DT3, the first data line DT1 overlaps with the pixel opening P0 of the first sub-pixel 101, the second data line DT2 overlaps with the pixel opening P0 of the second sub-pixel 102, and the third data line DT3 overlaps with the pixel opening P0 of the third sub-pixel 103, the first data line DT1, the second data line DT2, and the third data line DT3 are arranged in sequence, and the ratio of the first spacing SP1 between the first data line DT1 and the second data line DT2 to the second spacing SP2 between the second data line DT2 and the third data line DT3 is in the range of 0.8-1.2. With such an arrangement, the data line of each sub-pixel overlaps with the corresponding pixel circuit, thereby avoiding affecting other sub-pixels and making the display panel have a higher wiring uniformity.

[0337] Fig.50 A schematic diagram of a display panel provided by an embodiment of the present utility model. Fig.50 As shown, the display panel further includes a driving circuit CCT, and the driving circuit CCT is located at one side of the display panel. The driving circuit CCT may be a driving integrated circuit (IC).

[0338] For example, Fig.50 As shown, the plurality of sub-pixels 100 include a middle sub-pixel 152 near the center of the display panel and an edge sub-pixel 151 near the edge of the display panel, and the refresh frequency of the middle sub-pixel 152 and the refresh frequency of the edge sub-pixel 151 are configured to be adjustable in a preset working mode.

[0339] For example, the refresh frequency of the middle sub-pixel 152 is greater than the refresh frequency of the edge sub-pixel 151 .

[0340] For example, the display panel also includes a data line DT, the pixel circuit PDC includes a driving transistor T3 and a data writing transistor T1, the data line DT is connected to the first electrode of the data writing transistor T1, the second electrode of the data writing transistor T1 is connected to the gate of the driving transistor T3, the data line DT is set to be multiple, the display panel includes a display area R01 and a peripheral area located on at least one side of the display area R01, the display panel also includes multiple fan-out lines, the data line DT is connected to one of the multiple fan-out lines, the multiple fan-out lines gradually converge in a direction from a connection position close to the data line DT and the fan-out line to a connection position away from the data line DT and the fan-out line, the multiple fan-out lines extend from the display area R01 to the peripheral area, the multiple fan-out lines and the multiple data lines DT are located at different layers, and the multiple data lines DT are closer to the substrate BS than the multiple fan-out lines.

[0341] Fig.51 A schematic diagram of a display panel provided by an embodiment of the present utility model. Fig.51 As shown, the display panel further includes a plurality of fan-out lines 86, the substrate BS includes a display area R01 and a peripheral area R02 located at least on one side of the display area R01, the data line DT is connected to one of the plurality of fan-out lines 86, the plurality of fan-out lines 86 gradually gather from a connection position close to the data line DT and the fan-out line 86 to a connection position away from the data line DT and the fan-out line, the plurality of fan-out lines extend from the display area R01 to the peripheral area R02, and the plurality of fan-out lines 86 and the data line DT are located at different layers, as shown in FIG. Figure 2 , Fig.10 and Fig.51 As shown, the data line DT is composed of a portion located in the first conductive pattern layer LY1 and / or a portion located in the second conductive pattern layer LY2, and a plurality of fan-out lines 86 are located in the conductive pattern layer LYm, and the data line DT is closer to the substrate BS than the plurality of fan-out lines 86. Figure 2 , Fig.10 and Fig.51 , the second portion 412 b of the data line DT is closer to the base substrate BS than the plurality of fan-out lines 86 . The first portion 412 a and the third portion 412 c of the data line DT are closer to the base substrate BS than the plurality of fan-out lines 86 .

[0342] For example, Fig.51 As shown, the length of the portion of the fan-out line 86 located in the display area R01 is greater than the length of the portion of the fan-out line 86 located in the peripheral area R02. The display area is the area where the screen is displayed. The peripheral area R02 is the non-display area.

[0343] Fig.51The chip 98 and the chip 99 are also shown. The chip 98 and the chip 99 may be Chip On Flex (or Chip On Film, COF). The data line DT is connected to the chip through the fan-out line 86 .

[0344] like Fig.51 As shown, a data line DT is connected to a fan-out line 86 through a via Vm, and the via Vm penetrates the insulating layer between the data line DT and the fan-out line 86. For example, the via Vm penetrates the insulating layer 601.

[0345] like Figures 2 to 8 , Fig. 9 , Figure 12 to Figure 13As shown, an embodiment of the utility model further provides a display panel, comprising: a base substrate BS and a plurality of sub-pixels 100 arranged on the base substrate BS, the sub-pixel 100 comprising a pixel opening P0, the pixel opening P0 being configured to define a light-emitting area of ​​the sub-pixel 100, a first defining portion 301 being arranged between two adjacent pixel openings P0 in a first direction Y, a second defining portion 302 being arranged between two adjacent pixel openings P0 in a second direction X, the first direction Y intersecting with the second direction X, the thickness of the first defining portion 301 being unequal to the thickness of the second defining portion 302, and the sub-pixel 100 The display panel includes a pixel circuit 100a and a light-emitting element 100b connected to the pixel circuit 100a, wherein the light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, wherein the first electrode E1 of the light-emitting element 100b is closer to the base substrate BS than at least part of the second electrode E2 of the light-emitting element 100b, and the display panel further includes an insulating material layer 60, wherein the insulating material layer 60 is located on a side of the pixel circuit 100a away from the base substrate BS, and the insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602 The first insulating layer 601 includes an organic material, the second insulating layer 602 includes an organic material, the first insulating layer 601 is closer to the base substrate BS than the second insulating layer 602, the display panel further includes a connecting electrode 80, the connecting electrode 80 is located between the first insulating layer 601 and the second insulating layer 602, the connecting electrode 80 is connected to the pixel circuit 100a through a first via hole VH1 penetrating the first insulating layer 601, the first electrode E1 of the light emitting element 100b is connected to the connecting electrode 80 through a second via hole VH2 penetrating the second insulating layer 602, and the pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst includes a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3, the second plate Cb of the storage capacitor Cst is connected to the first electrode of the driving transistor T3, the orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, the orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, and the second plate Cb is arranged on the same layer as the channel T3c of the driving transistor T3 (such as Fig.11A and Fig.12 As shown), the second electrode plate Cb is closer to the substrate BS than the first electrode plate Ca, the orthographic projection of the second electrode plate Cb on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, and the ratio of the maximum dimension of the second via hole VH2 along the second direction X to the maximum dimension of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0346] The embodiments of the utility model provide a display panel and a display device including the display panel, which reduces the size of a via hole used to connect a pixel circuit and a light-emitting element, so as to facilitate the flatness of a sub-pixel and facilitate obtaining a high-resolution product, and the orthographic projection of a storage capacitor Cst on a substrate BS overlaps with the orthographic projection of a pixel opening P0 on the substrate BS, the orthographic projection of a channel of a driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, and the orthographic projection of a second electrode plate Cb on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, thereby playing a role in flattening the sub-pixel.

[0347] The embodiment of the utility model further provides a display panel, such as Figures 2 to 8 , Fig. 9 , Figure 12 to Figure 13As shown, it includes: a base substrate BS and a plurality of sub-pixels 100 arranged on the base substrate BS, and the sub-pixel 100 includes a pixel opening P0. For example, the pixel opening P0 is configured to define the light-emitting area of ​​the sub-pixel 100, a first defining portion 301 is arranged between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is arranged between two adjacent pixel openings P0 in a second direction X, the first direction Y intersects with the second direction X, and the thickness of the first defining portion 301 is not equal to the thickness of the second defining portion 302. The sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b connected to the pixel circuit 100a, the light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, the first electrode E1 of the light-emitting element 100b is closer to the substrate BS than at least part of the second electrode E2 of the light-emitting element 100b, the display panel also includes an insulating material layer 60, the insulating material layer 60 is located on a side of the pixel circuit 100a away from the substrate BS, the insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602, the first insulating layer 601 includes an organic material, the second insulating layer 602 includes an organic material, the first insulating layer 601 is closer to the substrate BS than the second insulating layer 602, the display panel It also includes a connecting electrode 80, which is located between the first insulating layer 601 and the second insulating layer 602. The connecting electrode 80 is connected to the pixel circuit 100a through a first via hole VH1 that penetrates the first insulating layer 601. The first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through a second via hole VH2 that penetrates the second insulating layer 602. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst. The storage capacitor Cst includes a first plate Ca and a second plate Cb. The first plate Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3. The second plate Cb of the storage capacitor Cst is connected to the first electrode of the driving transistor T3. The orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. For example, the orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. The second plate Cb is arranged in the same layer as the channel of the driving transistor T3, and the second plate Cb is closer to the substrate BS than the first plate Ca (e.g. Figure 2 , Fig.11A and Fig. 11B The ratio of the maximum dimension of the second via hole VH2 along the second direction X to the maximum dimension of the pixel opening P0 along the second direction X is in a range of greater than or equal to 0.05 and less than or equal to 0.48.

[0348] The embodiments of the utility model provide a display panel and a display device including the display panel, which reduces the size of the via hole used to connect the pixel circuit and the light-emitting element, so as to facilitate the flatness of the sub-pixel and facilitate the acquisition of a high-resolution product, and the orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, and the orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, which plays a role in flattening the sub-pixel.

[0349] Fig.52 is a schematic diagram of a display panel provided by an embodiment of the present utility model. Fig.52 As shown, the display panel further includes a barrier dam 701 , and a packaging glue 702 is provided on the outer side of the packaging layer EPS, and the packaging glue 702 plays a bonding role. Fig.52 The encapsulation layer EPS is shown with its boundary. Figure 2 and Fig.52 As shown, the second insulating layer 602 includes a planarization layer PLN2, and the planarization layer PLN2 includes a first planar portion PLN11 and a second planar portion PLN22, and a groove GR is provided between the first planar portion PLN11 and the second planar portion PLN22. The blocking dam 701 is located at the periphery of the display area R01 of the display panel, and the orthographic projection of the blocking dam 701 on the base substrate BS covers the orthographic projection of the groove GR on the base substrate BS, so as to reduce or prevent water and oxygen from entering the display area R01 along the planarization layer PLN2, and avoid affecting the light-emitting elements in the display area R01. Of course, in other embodiments, the orthographic projection of the blocking dam 701 on the base substrate BS may not cover the orthographic projection of the groove GR on the base substrate BS.

[0350] For example, the minimum distance from the edge of the display area R01 to the edge of the peripheral area R02 is in the range of 1-5 mm, that is, the size of the frame is in the range of 1-5 mm.

[0351] For example, in order to obtain a better water and oxygen blocking effect, the groove GR is a through hole penetrating the planarization layer PLN2. Fig.52 As shown, the portion of the planarization layer PLN2 located inside the groove GR is a first flat portion PLN11, and the portion of the planarization layer PLN2 located outside the groove GR is a second flat portion PLN22. Fig.52 The first flat portion PLN11 is shown with a boundary of the first flat portion PLN11, and the second flat portion PLN22 is shown with a boundary of the second flat portion PLN22. Fig.52 The example of setting one groove GR is used for explanation, but the number of grooves GR is not limited to one and can be set as needed. The number of grooves GR depends on the degree of narrow frame. The narrower the frame, the fewer the number of grooves GR. Of course, in other embodiments, the groove GR may not be set.

[0352] The embodiment of the utility model further provides a display panel, such as Figures 2 to 8 , Fig. 9 , Figure 12 to Figure 13 , Fig.52 As shown, it includes: a base substrate BS and a plurality of sub-pixels 100 arranged on the base substrate BS, and the sub-pixel 100 includes a pixel opening P0. For example, the pixel opening P0 is configured to define the light-emitting area of ​​the sub-pixel 100, a first defining portion 301 is arranged between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is arranged between two adjacent pixel openings P0 in a second direction X, the first direction Y intersects with the second direction X, and the thickness of the first defining portion 301 is not equal to the thickness of the second defining portion 302. The sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b connected to the pixel circuit 100a, the light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, the first electrode E1 of the light-emitting element 100b is closer to the substrate BS than at least part of the second electrode E2 of the light-emitting element 100b, the display panel also includes an insulating material layer 60, the insulating material layer 60 is located on the side of the pixel circuit 100a away from the substrate BS, the insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602, the first insulating layer 601 includes an organic material, the second insulating layer 602 includes an organic material, the first insulating layer 601 is closer to the substrate BS than the second insulating layer 602, the display panel also includes a connecting electrode 80, the connecting electrode 80 is located between the first insulating layer 601 and the second insulating layer 602, and the connecting electrode 80 is connected to the pixel circuit 100 through a first via hole VH1 penetrating the first insulating layer 601. a is connected to the display panel, the first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through the second via hole VH2 penetrating the second insulating layer 602, the display panel also includes a blocking dam DMM and an encapsulation layer EPS, the encapsulation layer EPS is configured to encapsulate the light-emitting element 100b, the encapsulation layer EPS includes a stack of an inorganic encapsulation film and an organic encapsulation film, an outer side of the encapsulation layer EPS is provided with an encapsulation glue 702, the second insulating layer 602 includes a planarization layer PLN2, the planarization layer PLN2 includes a first flat portion PLN11 and a second flat portion PLN22, a groove GR is provided between the first flat portion PLN11 and the second flat portion PLN22, the blocking dam DMM is located at the periphery of the display area R01 of the display panel, and the orthographic projection of the blocking dam DMM on the substrate BS covers the orthographic projection of the groove GR on the substrate BS; the ratio of the maximum dimension of the second via hole VH2 along the second direction X to the maximum dimension of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0353] Embodiments of the utility model provide a display panel and a display device including the display panel, which reduce the size of vias used to connect pixel circuits and light-emitting elements, so as to facilitate the flatness of sub-pixels and obtain high-resolution products, and the orthographic projection of the blocking dam DMM on the base substrate BS covers the orthographic projection of the groove GR on the base substrate BS, so as to reduce or avoid water and oxygen from entering the display area R01 along the planarization layer PLN2, thereby avoiding affecting the light-emitting elements in the display area R01.

[0354] Fig.53 The utility model is a circuit diagram of a dummy sub-pixel in a display panel provided by an embodiment of the present invention. Fig.54 A layout diagram of a dummy pixel circuit in a display panel provided by an embodiment of the utility model.

[0355] like Fig.53 As shown, the dummy sub-pixel 100d has a dummy driving transistor dT3 and a dummy reset transistor dT2. The gates of the dummy reset transistor dT2 and the dummy driving transistor dT3 are connected. The dummy reset transistor dT2 is disconnected from the initialization line INT1 to reduce power consumption. The dummy sub-pixel 100d is provided to improve etching uniformity rather than to realize the light-emitting function. Fig.53 As shown, the dummy sub-pixel 100d includes a dummy pixel circuit 100da and a dummy light-emitting element 100db. Fig.53 As shown, the composition of the dummy pixel circuit 100da can refer to the composition of the pixel circuit 100a, and the composition of the dummy light emitting element 100db can refer to the composition of the light emitting element 100b. However, the dummy pixel circuit 100da may have a broken line. Fig.53 The dummy pixel circuit 100da shown is described by taking the first electrode E1 of the dummy light emitting element 100db not being connected to the node N2 (the first electrode T3a of the dummy driving transistor dT3), and the dummy reset transistor dT2 not being connected to the initialization line INT1 as an example. In other embodiments, other disconnection methods may be used to make the dummy sub-pixel 100d non-luminous. Fig.53 The bold cross in represents disconnection. For example, in order to disconnect the dummy reset transistor dT2 of the dummy sub-pixel 100d from the initialization line INT1, no via hole may be provided.

[0356] For example, Fig.53 and Fig.54 As shown, the dummy sub-pixel 100d further includes a dummy light emitting control transistor dT5, a first electrode of the dummy light emitting control transistor dT5 is disconnected from the first power line PL1, and a second electrode of the dummy light emitting control transistor dT5 is connected to or disconnected from the second electrode of the dummy driving transistor T3.

[0357] like Fig.54 As shown, in the dashed box F1 (corresponding to Fig.12 No via is provided in the via V7 in the circuit, so that the dummy reset transistor dT2 is disconnected from the initialization line INT1. Fig.54 As shown, in the dashed box F2 (corresponding to Fig.12 In the via hole VH1 in the embodiment, no via hole is provided, so that the dummy pixel circuit 100da is disconnected from the dummy light emitting element 100db. Fig.54 As shown, in the dashed box F3 (corresponding to Fig.12 In the via hole V11 in the embodiment, no via hole is provided, so that the first electrode of the dummy light emitting control transistor dT5 is disconnected from the first power line PL1. Fig.54 As shown, in the dashed box F4 (corresponding to Fig.12 In the via hole V1 in the circuit, no via hole is set, so the second electrode of the virtual light-emitting control transistor dT5 is disconnected from the second electrode of the virtual driving transistor T3. Of course, in order to connect the second electrode of the virtual light-emitting control transistor dT5 with the second electrode of the virtual driving transistor T3, a via hole needs to be set at the corresponding position, and the same is true at other positions.

[0358] The embodiment of the utility model further provides a display panel, such as Figures 2 to 8 , Fig. 9 , Figure 12 to Figure 13 , Fig.53 and Fig.54As shown, it includes: a base substrate BS and a plurality of sub-pixels 100 arranged on the base substrate BS, and the sub-pixel 100 includes a pixel opening P0. For example, the pixel opening P0 is configured to define the light-emitting area of ​​the sub-pixel 100, a first defining portion 301 is arranged between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is arranged between two adjacent pixel openings P0 in a second direction X, the first direction Y intersects with the second direction X, and the thickness of the first defining portion 301 is not equal to the thickness of the second defining portion 302. The sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b connected to the pixel circuit 100a, the light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, the first electrode E1 of the light-emitting element 100b is closer to the base substrate BS than at least part of the second electrode E2 of the light-emitting element 100b, and the display panel further includes an insulating material layer 60, the insulating material layer 60 is located on a side of the pixel circuit 100a away from the base substrate BS, and the insulating material layer 60 includes The display panel further includes a first insulating layer 601 and a second insulating layer 602, wherein the first insulating layer 601 includes an organic material, the second insulating layer 602 includes an organic material, the first insulating layer 601 is closer to the base substrate BS than the second insulating layer 602, the display panel further includes a connecting electrode 80, the connecting electrode 80 is located between the first insulating layer 601 and the second insulating layer 602, the connecting electrode 80 is connected to the pixel circuit 100a through a first via hole VH1 penetrating the first insulating layer 601, and the first electrode E1 of the light emitting element 100b is connected to the pixel circuit 100a through a second via hole VH2 penetrating the second insulating layer 602. VH2 is connected to the connection electrode 80, the display panel further includes a data line DT, a gate line G1, a gate line G2, and an initialization line INT1, the pixel circuit 100a further includes a data writing transistor T1 and a reset transistor T2, the first electrode of the data writing transistor T1 is connected to the data line DT, the gate of the driving transistor T3 is connected to the second electrode of the data writing transistor T1, the gate of the data writing transistor T1 is connected to the gate line G1, the first electrode of the reset transistor T2 is connected to the initialization line INT1, the second electrode of the reset transistor T2 is connected to the gate of the driving transistor T3 The gate of the reset transistor T2 is connected to the gate line G2, and a dummy sub-pixel 100 is provided near the edge of the display panel. The dummy sub-pixel 100 has a dummy driving transistor T3 and a dummy reset transistor dT2. The dummy reset transistor dT2 is connected to the gate of the dummy driving transistor T3, and the dummy reset transistor dT2 is disconnected from the initialization line INT1; the ratio of the maximum dimension of the second via hole VH2 along the second direction X to the maximum dimension of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0359] An embodiment of the utility model provides a display panel and a display device including the display panel, which reduces the size of the via hole used to connect the pixel circuit and the light-emitting element to facilitate the flatness of the sub-pixel and to obtain a high-resolution product, and the dummy reset transistor dT2 is disconnected from the initialization line INT1 to reduce power consumption.

[0360] The embodiment of the utility model further provides a display panel, such as Figures 2 to 8 , Fig. 9 , Figure 12 to Figure 13 As shown, it includes: a base substrate BS and a plurality of sub-pixels 100 arranged on the base substrate BS, and the sub-pixel 100 includes a pixel opening P0. For example, the pixel opening P0 is configured to define the light-emitting area of ​​the sub-pixel 100, a first defining portion 301 is arranged between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is arranged between two adjacent pixel openings P0 in a second direction X, the first direction Y intersects with the second direction X, and the thickness of the first defining portion 301 is not equal to the thickness of the second defining portion 302. The sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b connected to the pixel circuit 100a, the light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, the first electrode E1 of the light-emitting element 100b is closer to the substrate BS than at least a portion of the second electrode E2 of the light-emitting element 100b, the display panel also includes an insulating material layer 60, the insulating material layer 60 is located on a side of the pixel circuit 100a away from the substrate BS, the insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602, the first insulating layer 601 includes an organic material, the second insulating layer 602 includes an organic material, the first insulating layer 601 is closer to the second insulating layer 602 than the first insulating layer 601. The second insulating layer 602 is closer to the base substrate BS. The display panel also includes a connecting electrode 80, which is located between the first insulating layer 601 and the second insulating layer 602. The connecting electrode 80 is connected to the pixel circuit 100a through a first via hole VH1 that penetrates the first insulating layer 601. The first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through a second via hole VH2 that penetrates the second insulating layer 602. The light-emitting function layer FL covers the side wall SW of the first defining portion 301 and covers the side wall SW of the second defining portion 302. The ratio of the maximum dimension of the second via hole VH2 along the second direction X to the maximum dimension of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0361] An embodiment of the utility model provides a display panel and a display device including the display panel, which reduces the size of the via hole used to connect the pixel circuit and the light-emitting element, so as to facilitate the flatness of the sub-pixel and to obtain a high-resolution product. The light-emitting function layer FL is manufactured by inkjet printing technology, and the light-emitting function layer FL covers the side wall of the first defining portion 301 and the side wall of the second defining portion 302.

[0362] Fig.55 A schematic diagram of a display panel provided in accordance with an embodiment of the present invention.

[0363] like Figure 2 and Fig.55 As shown, the thickness of the first delimiting portion 301 is less than the thickness of the second delimiting portion 302, and the light-emitting functional layer FL also includes a portion covering the top wall TW of the first delimiting portion 301. In this case, each film layer of the light-emitting functional layer FL can be made by inkjet printing. Since the thickness of the first delimiting portion 301 is less than the thickness of the second delimiting portion 302, the light-emitting functional layer FL covers the top wall TW of the first delimiting portion 301. The light-emitting functional layer FL covers the side wall of the first delimiting portion 301, covers the side wall of the second delimiting portion 302, and covers the top wall TW of the first delimiting portion 301. For example, the light-emitting functional layer FL does not cover the top wall of the second delimiting portion 302.

[0364] Figure 2 and Fig.55 For example, each film layer of the light-emitting functional layer FL is formed by inkjet printing, that is, each film layer of the light-emitting functional layer FL is arranged in the pixel opening P0. However, in other implementations, some film layers in the light-emitting functional layer FL may be formed by inkjet printing, and some film layers in the light-emitting functional layer FL may be formed by evaporation. The film layers formed by evaporation may be common layers. An embodiment of this case can refer to Fig.56 . Fig.56 A schematic diagram of a display panel provided in accordance with an embodiment of the present invention.

[0365] For example, Figure 2 , Figures 3 to 7 As shown, the display panel further includes a pixel defining layer PDL, the pixel defining layer PDL includes a defining portion 300, the pixel opening P0 is defined by the defining portion 300, the light emitting element 100b includes a first electrode E1 and a light emitting function layer FL, the pixel defining layer PDL is configured to expose at least a portion of the first electrode E1, and at least a portion of the film layer in the light emitting function layer FL covers the side wall SW of the defining portion 300 (such as Figure 2 shown). Figure 2 The light emitting functional layer FL is located in the pixel opening P0 as an example for description. In other embodiments, the light emitting functional layer FL may cover the top wall TW of the first defining portion 301, such as Fig.55 shown.

[0366] For example, Figure 2 As shown, the light emitting element 100b further includes a second electrode E2, the light emitting function layer FL is located between the first electrode E1 and the second electrode E2, and the second electrode E2 is in contact with the top wall of the defining portion 300. Fig.56 As shown, when the light emitting functional layer FL includes a common layer, the second electrode E2 contacts the common layer in the light emitting functional layer FL. For example, the second electrode E2 contacts the common layer in the light emitting functional layer FL close to the second electrode E2. Fig.56 The common layer in the embodiment is the electron injection layer EIL, but is not limited thereto and can be determined as required. Figure 2 and Fig.56 As shown, the orthographic projection of the second electrode E2 on the base substrate BS overlaps with the orthographic projection of the top wall of the defining portion 300 on the base substrate BS.

[0367] Fig.55 and Fig.56 An emission layer EML, a hole injection layer HIL, and a hole transport layer HTL are shown.

[0368] Fig.55 and Fig.56 A light extraction layer CPL is also shown to improve light extraction efficiency.

[0369] Fig.10 and Fig.54 A central axis C0 is also shown. The pixel opening P0 has a central axis C0 extending along the first direction Y. The pixel opening P0 may be axisymmetric with respect to the central axis C0.

[0370] An embodiment of the present invention further provides a display device, comprising any one of the above-mentioned display panels.

[0371] For example, the display device may be a large-sized display device, and at least one film layer in the light-emitting functional layer is manufactured using an inkjet printing process.

[0372] For example, the display device may be an organic light emitting diode display device. The display device may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., which includes an organic light emitting diode display device.

[0373] For example, the inorganic encapsulation film EPS1 and the inorganic encapsulation film EPS3 are made of inorganic insulating materials, and the organic encapsulation film EPS2 is made of organic insulating materials.

[0374] For example, the passivation layer may be made of an inorganic insulating material, and the planarization layer may be made of an organic insulating material.

[0375] In the embodiment of the present invention, the inorganic insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. For example, the organic insulating material includes resin, but is not limited thereto.

[0376] In an embodiment of the present invention, the pixel circuit is not limited to the one shown in the given circuit diagram, and other suitable pixel circuits may be used. The layout diagram of the display panel is also not limited to the one shown in the given layout diagram, and may be adjusted based on the given layout diagram, or other layout methods may be used.

[0377] There are a few points to note:

[0378] (1) In the drawings of the embodiments of the present invention, some drawings only show part of the structure of the display panel for the sake of clarity, but do not show the whole structure.

[0379] (2) In the drawings of the embodiments of the present utility model, only the structures related to the embodiments of the present utility model are involved, and other structures can refer to the general design.

[0380] (3) For the sake of clarity, the thickness of layers or regions is exaggerated in the drawings used to describe the embodiments of the present invention. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0381] (4) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other.

[0382] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: A base substrate and a plurality of sub-pixels arranged on the base substrate, The sub-pixel includes a pixel opening, the pixel opening is configured to define a light emitting area of ​​the sub-pixel, a first defining portion is provided between two adjacent pixel openings in a first direction, a second defining portion is provided between two adjacent pixel openings in a second direction, the first direction intersects with the second direction, and a thickness of the first defining portion is not equal to a thickness of the second defining portion, The sub-pixel includes a pixel circuit and a light-emitting element connected to the pixel circuit, wherein the light-emitting element has a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode, and the first electrode of the light-emitting element is closer to the base substrate than the light-emitting functional layer. The display panel further includes an insulating material layer, the insulating material layer is located on a side of the pixel circuit away from the base substrate, the insulating material layer includes a first insulating layer and a second insulating layer, the first insulating layer includes an organic material, the second insulating layer includes an organic material, and the first insulating layer is closer to the base substrate than the second insulating layer. The display panel further includes a connecting electrode, wherein the connecting electrode is located between the first insulating layer and the second insulating layer. The connecting electrode is connected to the pixel circuit through a first via hole penetrating the first insulating layer, and the first electrode of the light-emitting element is connected to the connecting electrode through a second via hole penetrating the second insulating layer. The ratio of the maximum dimension of the second via hole along the second direction to the maximum dimension of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.

48.

2. The display panel according to claim 1, characterized in that: A ratio of a maximum dimension of the second via hole along the second direction to a maximum dimension of the pixel opening along the second direction is in a range of greater than or equal to 0.12 and less than or equal to 0.

24.

3. The display panel according to claim 1, characterized in that: A ratio of a maximum dimension of the second via hole along the first direction to a maximum dimension of the pixel opening along the first direction is in a range of greater than or equal to 0.05 and less than or equal to 0.

24.

4. The display panel according to claim 1, characterized in that: A ratio of a maximum dimension of the second via hole along the first direction to a maximum dimension of the pixel opening along the first direction is in a range of greater than or equal to 0.08 and less than or equal to 0.

18.

5. The display panel according to claim 1, characterized in that: The thickness of the first defining portion is smaller than the thickness of the second defining portion.

6. The display panel according to claim 1, characterized in that: The thickness of the first insulating layer is less than or equal to the thickness of the second insulating layer.

7. The display panel according to claim 1, characterized in that: The thickness of the first insulating layer is less than or equal to 2 micrometers, and the thickness of the second insulating layer is less than or equal to 2 micrometers.

8. The display panel according to claim 1, characterized in that: The size of the first via hole is less than or equal to 10 micrometers, and the size of the second via hole is less than or equal to 10 micrometers.

9. The display panel according to claim 1, characterized in that: The size of the first via hole is less than or equal to 5 micrometers, and the size of the second via hole is less than or equal to 5 micrometers.

10. The display panel according to claim 1, characterized in that: The size of the first via hole is greater than or equal to 2 micrometers, and the size of the second via hole is greater than or equal to 2 micrometers.

11. The display panel according to claim 1, characterized in that: The second via holes are arranged in plurality, and the first electrode of the light emitting element is connected to the connection electrode through the plurality of second via holes penetrating the second insulating layer, and the plurality of second via holes are located at the edge of the pixel opening.

12. The display panel according to claim 11, characterized in that: A size of each of the plurality of second via holes is less than or equal to 10 micrometers.

13. The display panel according to claim 1, characterized in that: The orthographic projection of the connecting electrode on the base substrate overlaps with the orthographic projection of the pixel opening of the sub-pixel on the base substrate.

14. The display panel according to claim 13, characterized in that: The orthographic projection of the connecting electrode on the base substrate covers the orthographic projection of the pixel opening of the sub-pixel on the base substrate.

15. The display panel according to claim 1, characterized in that: The connection electrode contacts the first insulating layer, and has a plurality of openings exposing a portion of the first insulating layer. A pixel opening of one sub-pixel overlaps with one or more openings of the connection electrode.

16. The display panel according to claim 15, characterized in that: The pixel circuit includes a storage capacitor having a first plate and a second plate, the first plate and the second plate are insulated from each other, and a size of each opening of the connecting electrode is smaller than a size of the first plate and smaller than a size of the second plate.

17. The display panel according to any one of claims 1 to 16, characterized in that: Also included are at least two barrier dams and at least one isolation groove between adjacent barrier dams, wherein the isolation groove is configured to accommodate redundant ink.

18. The display panel according to claim 17, characterized in that: The at least two barrier dams include a first barrier dam and a second barrier dam, the first barrier dam is closer to the display area of ​​the display panel than the second barrier dam, and a height of the first barrier dam is smaller than a height of the second barrier dam.

19. The display panel according to claim 17, characterized in that: It also includes a pixel defining layer, which includes a defining portion and an isolation portion, the defining portion is configured to define a pixel opening of the sub-pixel, at least one of the at least two blocking dams includes the isolation portion, and the thickness of the isolation portion is greater than the thickness of the defining portion.

20. The display panel according to claim 17, characterized in that: At least one partition structure is disposed in the isolation trench, and the partition structure is configured to partition the light-emitting functional layer.

21. The display panel according to any one of claims 1 to 9, characterized in that: It also includes a conductive connecting portion, wherein the conductive connecting portion and the connecting electrode are located in the same layer, and the conductive connecting portion and the connecting electrode are insulated from each other.

22. The display panel according to claim 21, characterized in that: The conductive connection portion has a plurality of hollow structures, and the connection electrode is located in one of the plurality of hollow structures.

23. The display panel according to claim 22, characterized in that: In the hollow structure and the connecting electrode located therein, a ratio of an area of ​​the connecting electrode to an area of ​​the hollow structure is less than or equal to 10%.

24. The display panel according to claim 22, characterized in that: In the hollow structure and the connecting electrode located therein, an area ratio of the connecting electrode to the hollow structure is greater than or equal to 70%.

25. The display panel according to claim 21, characterized in that: The conductive connection portion has a plurality of first conductive lines and a plurality of second conductive lines.

26. The display panel according to claim 25, characterized in that: Each of the plurality of first conductive lines and each of the plurality of second conductive lines are insulated from each other, and the plurality of first conductive lines and the plurality of second conductive lines are alternately arranged in the first direction or the second direction.

27. The display panel according to claim 26, characterized in that: The connecting electrode is disposed between adjacent first conductive lines and second conductive lines, and the first conductive lines, the connecting electrode, and the second conductive lines are arranged in sequence.

28. The display panel according to claim 23, characterized in that: A dummy block is also included, wherein the dummy block is floating and is located at the same layer as the conductive connection portion.

29. The display panel according to claim 28, characterized in that: An area of ​​the dummy block is larger than an area of ​​the connecting electrode.

30. The display panel according to claim 28, characterized in that The dummy block is arranged in the hollow structure.

31. The display panel according to claim 26, characterized in that: A dummy block is also included, wherein the dummy block is floating and is located at the same layer as the conductive connection portion.

32. The display panel according to claim 31, characterized in that: An area of ​​the dummy block is larger than an area of ​​the connecting electrode.

33. The display panel according to claim 31, characterized in that: The dummy block is disposed between adjacent first conductive lines and second conductive lines.

34. The display panel according to claim 21, characterized in that: A power line is also included, wherein the power line is connected to the conductive connection portion, and the power line is configured to provide a constant power supply voltage to the pixel circuit.

35. The display panel according to claim 34, characterized in that: The power lines include a first power line connected to the pixel circuit and configured to provide a constant first voltage signal to the pixel circuit.

36. The display panel according to claim 35, characterized in that: The first power line includes a first power signal line and a first power connection line, the first power signal line and the first power connection line are connected and cross-arranged, and the conductive connection portion is connected to the first power connection line.

37. The display panel according to claim 34, characterized in that: The power line includes a second power line connected to the second electrode of the light emitting element and configured to provide a constant second voltage signal.

38. The display panel according to any one of claims 26-27, 31-33, characterized in that: It also includes a first power line and a second power line, the first power line is connected to the pixel circuit and is configured to provide a constant first voltage signal to the pixel circuit, the second power line is connected to the second electrode of the light-emitting element and is configured to provide a constant second voltage signal, the first conductive line is connected to the first power line, and the second conductive line is connected to the second power line.

39. The display panel according to claim 21, characterized in that: It also includes a conductive bus, which is located in the same layer as the connecting electrode, and the conductive bus and the conductive connecting part are an integral structure. The conductive bus extends along the second direction, and the size of the conductive bus in the second direction is larger than the size of the conductive connecting part in the second direction. The orthographic projection of the conductive bus on the base substrate overlaps with the orthographic projection of the pixel opening of the first row of sub-pixels on the base substrate.

40. The display panel according to any one of claims 1 to 16, characterized in that: It also includes a plurality of signal generating circuits, each of which is arranged between two adjacent columns of pixel circuits.

41. The display panel according to claim 40, characterized in that: The multiple sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, the area of ​​the pixel opening of the third sub-pixel is larger than the area of ​​the pixel opening of the second sub-pixel, and larger than the area of ​​the pixel opening of the first sub-pixel, and the number of signal generating circuits overlapping with the pixel opening of the third sub-pixel is larger than the number of signal generating circuits overlapping with the pixel opening of the first sub-pixel, and larger than the number of signal generating circuits overlapping with the pixel opening of the second sub-pixel.

42. The display panel according to claim 40, characterized in that: The signal generating circuit includes a gate signal generating circuit and a light emitting signal generating circuit, and the signal generating circuit and the light emitting signal generating circuit are formed between two different columns of pixel circuits.

43. The display panel according to claim 41, characterized in that The pixel circuit of the first sub-pixel, the pixel circuit of the second sub-pixel, and the pixel circuit of the third sub-pixel have different widths.

44. The display panel according to claim 43, characterized in that: The width of the pixel circuit of the first sub-pixel is greater than the width of the pixel circuit of the third sub-pixel, and the width of the pixel circuit of the third sub-pixel is greater than the width of the pixel circuit of the second sub-pixel.

45. The display panel according to claim 43, characterized in that: It also includes an initialization line and a first power line, the initialization line is configured to provide a constant initialization voltage to the pixel circuit, the first power line is configured to provide a constant first voltage signal to the pixel circuit, the initialization line overlaps with the pixel opening of the third sub-pixel, the first power line overlaps with the pixel opening of the first sub-pixel, and the width of the initialization line is smaller than the width of the first power line.

46. ​​The display panel according to claim 40, characterized in that: The orthographic projection of the pixel opening of the sub-pixel on the base substrate overlaps with the orthographic projection of at least one pixel circuit on the base substrate, and overlaps with the orthographic projection of at least one signal generating circuit on the base substrate.

47. The display panel according to claim 40, characterized in that: The device further comprises a data line, a first gate line, a second gate line, a third gate line, a fourth gate line, a first power line, a first initialization line, and a second initialization line. The pixel circuit comprises a driving transistor, a light emitting control transistor, a data writing transistor, a first reset transistor, a second reset transistor, and a storage capacitor. The storage capacitor includes a first plate and a second plate, the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first electrode of the driving transistor. The first electrode of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second electrode of the data writing transistor, and the gate of the data writing transistor is connected to the first gate line. The first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The gate of the second reset transistor is connected to the third gate line, the first electrode of the second reset transistor is connected to the second initialization line, and the second electrode of the second reset transistor is connected to the light emitting element through the driving transistor. The gate of the light emitting control transistor is connected to the fourth gate line, the first electrode of the light emitting control transistor is connected to the first power line, and the second electrode of the light emitting control transistor is connected to the second electrode of the driving transistor. The plurality of signal generating circuits include a first gate signal generating circuit, a second gate signal generating circuit, a light emission control signal generating circuit, and an initialization voltage generating circuit, The first gate signal generating circuit is connected to the first gate line, the second gate signal generating circuit is connected to at least one of the second gate line and the third gate line, the light emitting control signal generating circuit is connected to the fourth gate line, and the initialization voltage generating circuit is connected to at least one of the first initialization line and the second initialization line. The width of the first gate signal generating circuit is greater than that of the light emitting control signal generating circuit, the width of the light emitting control signal generating circuit is greater than that of the second gate signal generating circuit, and the width of the second gate signal generating circuit is greater than that of the initialization voltage generating circuit.

48. The display panel according to any one of claims 41, 43-45, characterized in that: The pixel circuit further includes a data line, wherein the pixel circuit includes a driving transistor and a data writing transistor, the data line is connected to a first electrode of the data writing transistor, a second electrode of the data writing transistor is connected to a gate electrode of the driving transistor, and a plurality of data lines are provided. The plurality of data lines include a first data line, a second data line, and a third data line, the first data line overlaps with a pixel opening of the first sub-pixel, the second data line overlaps with a pixel opening of the second sub-pixel, and the third data line overlaps with a pixel opening of the third sub-pixel, The first data line, the second data line, and the third data line are arranged in sequence. A ratio of a first spacing between the first data line and the second data line to a second spacing between the second data line and the third data line is in a range of 0.8-1.

2.

49. The display panel according to any one of claims 1 to 16, characterized in that: The plurality of sub-pixels include a middle sub-pixel near the center of the display panel and an edge sub-pixel near the edge of the display panel, and a refresh frequency of the middle sub-pixel and a refresh frequency of the edge sub-pixel are configured to be adjustable in a preset working mode.

50. The display panel according to claim 49, characterized in that: The refresh frequency of the middle sub-pixel is greater than the refresh frequency of the edge sub-pixel.

51. The display panel according to any one of claims 1 to 16, characterized in that: The display panel further comprises a display area and a peripheral area located at at least one side of the display area. The display panel further comprises a plurality of fan-out lines. The data line is connected to one of the plurality of fan-out lines. The plurality of fan-out lines gradually converge in a direction from a connection position close to the data line and the fan-out line to a connection position away from the data line and the fan-out line. The plurality of fan-out lines extend from the display area to the peripheral area. The plurality of fan-out lines and the plurality of data lines are located at different layers. The plurality of data lines are closer to the substrate than the plurality of fan-out lines.

52. A display panel, characterized in that: include: A base substrate and a plurality of sub-pixels arranged on the base substrate, The sub-pixel includes a pixel opening, a pixel circuit and a light-emitting element connected to the pixel circuit, wherein the light-emitting element has a first electrode. The display panel further includes an insulating material layer, the insulating material layer is located on a side of the pixel circuit away from the base substrate, the insulating material layer includes a first insulating layer and a second insulating layer, the first insulating layer includes an organic material, the second insulating layer includes an organic material, and the first insulating layer is closer to the base substrate than the second insulating layer. The display panel further includes a connecting electrode, wherein the connecting electrode is located between the first insulating layer and the second insulating layer. The connecting electrode is connected to the pixel circuit through a first via hole penetrating the first insulating layer, and the first electrode of the light-emitting element is connected to the connecting electrode through a second via hole penetrating the second insulating layer. The pixel circuit includes a driving transistor and a storage capacitor, the storage capacitor includes a first plate and a second plate, the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first electrode of the driving transistor. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed in the same layer as the channel of the driving transistor, and the second electrode plate is closer to the base substrate than the first electrode plate. The ratio of the maximum dimension of the second via hole along the second direction to the maximum dimension of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.

48.

53. The display panel according to claim 52, characterized in that: The orthographic projection of the second electrode plate on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate.

54. The display panel according to claim 52 or 53, characterized in that: The pixel opening is configured to define a light emitting area of ​​the sub-pixel, a first defining portion is provided between two adjacent pixel openings in a first direction, a second defining portion is provided between two adjacent pixel openings in a second direction, the first direction intersects with the second direction, and a thickness of the first defining portion is not equal to a thickness of the second defining portion, The light emitting element further comprises a second electrode and a light emitting functional layer located between the first electrode and the second electrode. The first electrode of the light emitting element is closer to the base substrate than at least a part of the second electrode of the light emitting element.

55. A display panel, characterized in that: include: A base substrate and a plurality of sub-pixels arranged on the base substrate, The sub-pixel includes a pixel opening, a pixel circuit and a light-emitting element connected to the pixel circuit, wherein the light-emitting element has a first electrode. The display panel further includes an insulating material layer, the insulating material layer is located on a side of the pixel circuit away from the base substrate, the insulating material layer includes a first insulating layer and a second insulating layer, the first insulating layer includes an organic material, the second insulating layer includes an organic material, and the first insulating layer is closer to the base substrate than the second insulating layer. The display panel further includes a connecting electrode, wherein the connecting electrode is located between the first insulating layer and the second insulating layer. The connecting electrode is connected to the pixel circuit through a first via hole penetrating the first insulating layer, and the first electrode of the light-emitting element is connected to the connecting electrode through a second via hole penetrating the second insulating layer. The display panel further includes a barrier dam and an encapsulation layer, wherein the encapsulation layer is configured to encapsulate the light emitting element, and the encapsulation layer includes a stack of an inorganic encapsulation film and an organic encapsulation film. The outer side of the packaging layer is provided with packaging glue, The second insulating layer includes a planarization layer, the planarization layer includes a first planar portion and a second planar portion, a groove is provided between the first planar portion and the second planar portion, The blocking dam is located at the periphery of the display area of ​​the display panel, and the orthographic projection of the blocking dam on the base substrate covers the orthographic projection of the groove on the base substrate; The ratio of the maximum dimension of the second via hole along the second direction to the maximum dimension of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.

48.

56. A display panel, characterized in that: include: A base substrate and a plurality of sub-pixels arranged on the base substrate, The sub-pixel includes a pixel opening, a pixel circuit and a light-emitting element connected to the pixel circuit, wherein the light-emitting element has a first electrode, and the pixel circuit includes a driving transistor. The display panel further includes an insulating material layer, the insulating material layer is located on a side of the pixel circuit away from the base substrate, the insulating material layer includes a first insulating layer and a second insulating layer, the first insulating layer includes an organic material, the second insulating layer includes an organic material, and the first insulating layer is closer to the base substrate than the second insulating layer. The display panel further includes a connecting electrode, wherein the connecting electrode is located between the first insulating layer and the second insulating layer. The connecting electrode is connected to the pixel circuit through a first via hole penetrating the first insulating layer, and the first electrode of the light-emitting element is connected to the connecting electrode through a second via hole penetrating the second insulating layer. The display panel further includes a data line, a first gate line, a second gate line, and a first initialization line, wherein the pixel circuit further includes a data writing transistor and a first reset transistor, the first electrode of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second electrode of the data writing transistor, and the gate of the data writing transistor is connected to the first gate line, The first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The display panel is provided with a dummy sub-pixel near an edge thereof, the dummy sub-pixel having a dummy drive transistor and a first dummy reset transistor, wherein the first dummy reset transistor is connected to a gate of the dummy drive transistor, The first dummy reset transistor is disconnected from the first initialization line; The ratio of the maximum dimension of the second via hole along the second direction to the maximum dimension of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.

48.

57. A display panel, characterized in that: include: A base substrate and a plurality of sub-pixels arranged on the base substrate, The sub-pixel includes a pixel opening, a pixel circuit and a light-emitting element connected to the pixel circuit, wherein the light-emitting element has a first electrode and a light-emitting functional layer, a first defining portion is provided between two adjacent pixel openings in a first direction, and a second defining portion is provided between two adjacent pixel openings in a second direction, wherein the first direction intersects with the second direction, The display panel further includes an insulating material layer, the insulating material layer is located on a side of the pixel circuit away from the base substrate, the insulating material layer includes a first insulating layer and a second insulating layer, the first insulating layer includes an organic material, the second insulating layer includes an organic material, and the first insulating layer is closer to the base substrate than the second insulating layer. The display panel further includes a connecting electrode, wherein the connecting electrode is located between the first insulating layer and the second insulating layer. The connecting electrode is connected to the pixel circuit through a first via hole penetrating the first insulating layer, and the first electrode of the light-emitting element is connected to the connecting electrode through a second via hole penetrating the second insulating layer. The light-emitting functional layer covers the side wall of the first defining portion and covers the side wall of the second defining portion. The ratio of the maximum dimension of the second via hole along the second direction to the maximum dimension of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.

48.

58. The display panel according to claim 57, characterized in that: The thickness of the first defining portion is smaller than that of the second defining portion, and the light-emitting functional layer further includes a portion covering a top wall of the first defining portion.

59. A display device, characterized in that: Comprising a display panel according to any one of claims 1-58.

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