Array substrate and liquid crystal display screen
By adapting the input end of the GIP circuit through the FPC pad, the problem of the existing LCD screen needing to delete other functional modules when meeting the GIP circuit layout requirements is solved, and the effect of improving the yield and display quality of the LCD screen is achieved.
Patent Information
- Application Number
- CN202421334459.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-12
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2034-06-12
AI Technical Summary
When existing LCD screens meet the layout requirements of GIP circuit control signal lines, they often need to delete the wiring of other functional modules, resulting in a decrease in the yield and display quality of LCD screens.
By connecting part of the input ends of the GIP circuit through the FPC pad, the control line layout space of the GIP module is saved, and other functional modules, such as cell test modules are used to route the saved space.
This solution effectively saves the control line layout space of the GIP module and improves the yield and display quality of the LCD screen.
Smart Images
Figure CN222672114U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of display panels, and in particular to an array substrate and a liquid crystal display screen. Background Art
[0002] Flat panel display devices have many advantages such as thin body, power saving, and no radiation, and have been widely used. Existing flat panel display devices mainly include liquid crystal display devices (LCD) and organic light emitting display devices (OLED). Thin film transistors (TFT) are an important component of flat panel display devices.
[0003] With the development of panel technology, narrow-border display panels that pursue a larger screen-to-body ratio have gradually become mainstream, and are moving towards borderless display. Currently, the borderless display panels on the market have a narrow black outer border on the periphery, under which the display driver circuit such as GIP (Gate Driver In Panel) is distributed.
[0004] Most of the existing display panel technologies use GIP circuits. The control signal lines of the GIP circuits come from the output of the IC control module. Due to the large number of lines, existing display panels often have the problem of insufficient wiring space.
[0005] In order to meet basic functional requirements, other circuits are often sacrificed and other peripheral functions are castrated. For example, in order to make GIP wiring more sufficient, the cell test circuit is abandoned. Although the wiring of basic functions is completed, it may reduce the yield of the LCD screen, thereby reducing the quality of the display screen.
[0006] In summary, a technical solution is needed to solve the above problems, which can not only meet the layout requirements of the GIP control signal line, but also will not sacrifice the layout space of other circuits, improve product reliability, and thus improve product competitiveness. Utility Model Content
[0007] In order to meet the layout requirements of the control lines of the GIP circuit, the existing liquid crystal display screens have cut down on the wiring of other functional modules, which results in a reduction in the yield of the liquid crystal display screen and a reduction in the display quality of the display screen.
[0008] In view of the above problems, an array substrate and a liquid crystal display are proposed. By transferring the input end of a part of the GIP circuit through an FPC pad, the layout space of the control line of the GIP module can be greatly saved. The saved layout space can be used for wiring other functions, such as the cell test module of the liquid crystal display, which is conducive to improving the yield and display quality of the liquid crystal display.
[0009] In a first aspect, an array substrate includes:
[0010] The first set of GIP modules;
[0011] IC pad;
[0012] FPC pad;
[0013] GIP control line;
[0014] The first group of GIP modules includes a plurality of GIP circuits, and output ends of the GIP circuits are electrically connected to odd-numbered row gate lines or even-numbered row gate lines of the array substrate respectively;
[0015] The IC pad is electrically connected to the FPC pad;
[0016] The GIP input terminal of the first group of GIP modules:
[0017] A portion is electrically connected to the IC pad via a corresponding GIP control line;
[0018] The other part is electrically connected to the FPC pad through the corresponding GIP control line, and is electrically connected to the IC pad after being transferred by the FPC pad.
[0019] In combination with the array substrate described in the first aspect of the utility model, in a first possible implementation manner, the ICpad includes:
[0020] The first set of IC pins;
[0021] The FPC pad includes:
[0022] The first set of FPC pins;
[0023] The first group of IC pins is electrically connected to the first group of FPC pins.
[0024] In combination with the first possible implementation of the first aspect of the utility model, in a second possible implementation, the IC pad further includes:
[0025] The second set of IC pins;
[0026] The second group of IC pins is configured on a first side of the first group of IC pins;
[0027] The GIP input terminal includes a first group of input terminals;
[0028] The GIP control lines include a first group of control lines;
[0029] The first group of input terminals is electrically connected to the second group of IC pins through the first group of control lines.
[0030] In combination with the second possible implementation of the first aspect of the utility model, in a third possible implementation, the FPC pad further includes:
[0031] The second set of FPC pins;
[0032] The second group of FPC pins is arranged on a second side of the first group of FPC pins;
[0033] The GIP input terminal also includes a second group of input terminals;
[0034] The GIP control lines also include a second group of control lines;
[0035] The second group of input terminals is electrically connected to the first ends of the second group of FPC pins through the second group of control lines.
[0036] In combination with the third possible implementation of the first aspect of the utility model, in a fourth possible implementation, the FPC pad further includes:
[0037] The third set of FPC pins;
[0038] The third group of FPC pins is arranged on the first side of the first group of FPC pins;
[0039] The FPC pad includes:
[0040] The first set of adapter cables;
[0041] The second ends of the second group of FPC pins are electrically connected to the first ends of the third group of FPC pins through the first group of adapter wires.
[0042] In combination with the fourth possible implementation manner of the first aspect of the utility model, in a fifth possible implementation manner, the IC pad further includes:
[0043] The third group of IC pins;
[0044] The third group of IC pins is configured on a first side of the second group of IC pins;
[0045] The second ends of the third group of FPC pins are electrically connected to the third group of IC pins through connecting wires.
[0046] In combination with the array substrate described in the first aspect of the utility model, in a sixth possible implementation manner, the number of the first group of input ends is equal to the number of the second group of input ends.
[0047] In a second aspect, a liquid crystal display screen comprises the array substrate described in the first aspect.
[0048] By implementing the array substrate and the liquid crystal display described in the utility model, the layout space of the control line of the GIP module can be greatly saved by switching the input end of a part of the GIP circuit through the FPC pad. The saved layout space can be used for wiring other functions, such as the cell test module of the liquid crystal display, which is beneficial to improving the yield rate and display quality of the liquid crystal display. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0050] Figure 1 is a schematic diagram of the structure of an array substrate in the prior art;
[0051] Figure 2 It is a schematic diagram of the wiring structure of the GIP module in the array substrate in the prior art;
[0052] Figure 3 It is a schematic diagram of the wiring structure of the GIP module in the array substrate of the present utility model. DETAILED DESCRIPTION
[0053] The following will be combined with the drawings in the utility model to clearly and completely describe the technical solution in the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the utility model.
[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0055] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.
[0056] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0057] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0058] Existing LCD screens, such as Figure 1 and Figure 2 , Figure 1 is a schematic diagram of the structure of an array substrate in the prior art, Figure 2 This is a schematic diagram of the wiring structure of the GIP module in the array substrate in the prior art. In order to meet the layout requirements of the control lines of the GIP circuit, the wiring of other functional modules is deleted, which leads to a decrease in the yield of the liquid crystal display and the display quality of the display.
[0059] In view of the above problems, an array substrate and a liquid crystal display screen are proposed.
[0060] In a first aspect, an array substrate, such as Figure 3 , Figure 3 The schematic diagram of the wiring structure of the GIP module in the array substrate of the utility model includes a first group of GIP modules 110, IC pad 130, FPC pad, and GIP control line 120; the first group of GIP modules 110 includes multiple GIP circuits 111, and the output ends of the GIP circuits 111 are respectively electrically connected to the odd-numbered row gate lines or the even-numbered row gate lines of the array substrate; the IC pad 130 is electrically connected to the FPC pad; the GIP input end of the first group of GIP modules 110: a part is electrically connected to the IC pad 130 through the corresponding GIP control line 120, and the other part is electrically connected to the FPC pad through the corresponding GIP control line 120, and is electrically connected to the IC pad 130 after being transferred by the FPC pad.
[0061] Further, the IC pad 130 includes a first group of IC pins 131 ; the FPC pad includes a first group of FPC pins 141 ; and the first group of IC pins 131 is electrically connected to the first group of FPC pins 141 .
[0062] like Figure 3 , the first group of FPC pins are arranged at the middle position on the left side of FPC pad 140 , and the first group of IC pins are arranged at the leftmost position of IC pad 130 .
[0063] Furthermore, the IC pad 130 also includes a second group of IC pins 132; the second group of IC pins 132 are configured on the first side of the first group of IC pins 131; the GIP input end includes a first group of input ends; the GIP control line 120 includes a first group of control lines 121; the first group of input ends is electrically connected to the second group of IC pins 132 through the first group of control lines 121.
[0064] The second group of IC pins 132 are arranged on the first side of the first group of IC pins 131, that is, Figure 3 The right side of the first group of IC pins 131. This layout is conducive to saving wiring space.
[0065] Furthermore, the FPC pad also includes a second group of FPC pins 142; the second group of FPC pins 142 are configured on the second side of the first group of FPC pins 141; the GIP input end also includes a second group of input ends; the GIP control line 120 also includes a second group of control lines 122; the second group of input ends is electrically connected to the first end of the second group of FPC pins 142 through the second group of control lines 122.
[0066] The second group of FPC pins 142 are arranged on the second side of the first group of FPC pins 141, that is, Figure 3 The left side of the first group of FPC pins 141, such a layout is conducive to saving wiring space.
[0067] By transferring the input end of a part of the GIP circuit through the FPC pad, the layout space of the control line of the GIP module can be greatly saved. The saved layout space 200 can be used for wiring other functions, such as the cell test module of the LCD display, which is beneficial to improving the yield and display quality of the LCD display.
[0068] Furthermore, the FPC pad also includes a third group of FPC pins 143; the third group of FPC pins 143 are configured on the first side of the first group of FPC pins 141; the FPC pad includes a first group of adapter wires 144; the second end of the second group of FPC pins 142 is electrically connected to the first end of the third group of FPC pins 143 through the first group of adapter wires 144.
[0069] Furthermore, the IC pad 130 further includes a third group of IC pins 133 ; the third group of IC pins 133 are arranged on a first side of the second group of IC pins 132 ; and the second ends of the third group of FPC pins 143 are electrically connected to the third group of IC pins 133 via connecting wires.
[0070] Preferably, the number of the first group of input terminals is equal to the number of the second group of input terminals.
[0071] In a second aspect, a liquid crystal display screen 100 includes the array substrate of the first aspect.
[0072] By implementing the array substrate and the liquid crystal display of the present invention, the layout space of the control line of the GIP module can be greatly saved by transferring a part of the input end of the GIP circuit 111 through the FPC pad. The saved layout space 200 can be used for wiring other functions, such as the cell test module of the liquid crystal display, which is beneficial to improving the yield rate and display quality of the liquid crystal display.
[0073] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. An array substrate, characterized in that it comprises: The first set of GIP modules; IC pad; FPC pad; GIP control line; The first group of GIP modules includes a plurality of GIP circuits, and output ends of the GIP circuits are electrically connected to odd-numbered row gate lines or even-numbered row gate lines of the array substrate respectively; The IC pad is electrically connected to the FPC pad; The GIP input terminal of the first group of GIP modules: A portion is electrically connected to the IC pad via a corresponding GIP control line; The other part is electrically connected to the FPC pad through the corresponding GIP control line, and is electrically connected to the IC pad after being transferred by the FPC pad.
2. The array substrate according to claim 1, characterized in that: The IC pad includes: The first set of IC pins; The FPC pad includes: The first set of FPC pins; The first group of IC pins is electrically connected to the first group of FPC pins.
3. The array substrate according to claim 2, characterized in that: The IC pad also includes: The second set of IC pins; The second group of IC pins is configured on a first side of the first group of IC pins; The GIP input terminal includes a first group of input terminals; The GIP control lines include a first group of control lines; The first group of input terminals is electrically connected to the second group of IC pins through the first group of control lines.
4. The array substrate according to claim 3, characterized in that: The FPC pad also includes: The second set of FPC pins; The second group of FPC pins is arranged on a second side of the first group of FPC pins; The GIP input terminal also includes a second group of input terminals; The GIP control lines also include a second group of control lines; The second group of input terminals is electrically connected to the first ends of the second group of FPC pins through the second group of control lines.
5. The array substrate according to claim 4, characterized in that: The FPC pad also includes: The third set of FPC pins; The third group of FPC pins is arranged on the first side of the first group of FPC pins; The FPC pad includes: The first set of adapter cables; The second ends of the second group of FPC pins are electrically connected to the first ends of the third group of FPC pins through the first group of adapter wires.
6. The array substrate according to claim 5, characterized in that: The IC pad also includes: The third group of IC pins; The third group of IC pins is configured on a first side of the second group of IC pins; The second ends of the third group of FPC pins are electrically connected to the third group of IC pins through connecting wires.
7. The array substrate according to any one of claims 1 to 6, characterized in that: The number of the first group of input terminals is equal to that of the second group of input terminals.
8. A liquid crystal display screen, characterized in that: Comprising the array substrate as claimed in claim 7.