SIP radio frequency module

Abstract

The utility model provides an SIP radio frequency module, and relates to the technical field of chip packaging, the SIP radio frequency module comprises a first substrate, a first chipset, a first conductive box dam and a second substrate, the first chipset is pasted on one side surface of the first substrate and is electrically connected with the first substrate; the first conductive box dam is arranged on the edge of the surface of one side of the first substrate and surrounds the chipset; one side of the second substrate is connected to one side, far away from the first substrate, of the first conductive box dam; wherein the first conductive box dam is integrally electroplated and formed on the edge of the first substrate, and the first substrate is electrically connected with the second substrate through the first conductive box dam. Compared with the prior art, the conductive box dam is integrally electroplated and formed on the edge of the substrate, so that the structural strength is improved, the connecting part does not need to occupy too much space, the overall height is relatively lower, and the stability of the stacking structure is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a SIP radio frequency module. Background Art

[0002] The inventors have found that the RF transceiver component is one of the core components of radar detection. One path sends out RF signals to form a transmitting path, and the other path receives reflected RF signals to form a receiving path, thereby realizing active detection of objects. With the rapid development of modern science and technology, there are higher requirements for the volume, weight, and performance of the radar system. In particular, the RF transceiver systems in the fields of shipborne, airborne, and missiles have a more significant demand for improved integration. Traditional RF components based on board-level surface mount cannot meet the needs of the new generation of systems, prompting RF transceiver components to develop in the direction of highly integrated, miniaturized, integrated, and lightweight SIP (system-level packaging).

[0003] The current SIP technology usually uses a ceramic substrate and a dam to hold the chip and then stack it. However, conventional technology usually requires additional conductive pillars to be designed in the middle of the dam to achieve interconnection between the upper and lower layers. In addition, the conventional dam can only be fixed on the ceramic substrate by sintering or welding. Welding or sintering requires a lot of volume, resulting in a high height, an overall stacking height that is too high, and poor stacking stability. Utility Model Content

[0004] The purpose of the utility model is to provide a SIP radio frequency module, which can use a conductive dam and electroplate the conductive dam integrally on the edge of a substrate, thereby improving the structural strength and eliminating the need for the connection to occupy too much space, thereby making the overall height relatively lower and improving the stability of the stacking structure.

[0005] The embodiment of the utility model is achieved as follows:

[0006] In a first aspect, the utility model provides a SIP radio frequency module, comprising:

[0007] a first substrate;

[0008] a first chipset, the first chipset being attached to a side surface of the first substrate and electrically connected to the first substrate;

[0009] A first conductive dam is disposed at an edge of a side surface of the first substrate and surrounds the chipset;

[0010] A second substrate, wherein one side of the second substrate is connected to a side of the first conductive dam away from the first substrate;

[0011] The first conductive dam is integrally formed at an edge of the first substrate, and the first substrate is electrically connected to the second substrate via the first conductive dam.

[0012] In an optional embodiment, the SIP RF module also includes a third substrate, a second conductive dam and a second chipset, the second chipset is attached to a side surface of the third substrate, the second conductive dam is arranged at an edge of a side surface of the third substrate, and the side of the second substrate away from the first conductive dam is connected to the second conductive dam and is spaced apart from the third substrate, wherein the second conductive dam is integrally formed by electroplating on the edge of the second substrate, and the third substrate is electrically connected to the second substrate through the second conductive dam.

[0013] In an optional embodiment, the first substrate includes a first dielectric layer, a first wiring layer and a second wiring layer, the first wiring layer and the second wiring layer are respectively arranged on both side surfaces of the first dielectric layer, the first conductive dam is integrally formed by electroplating on the edge of the second wiring layer, and the first chipset is attached to the second wiring layer and electrically connected to the second wiring layer.

[0014] In an optional embodiment, the second substrate includes a second dielectric layer, a third wiring layer and a fourth wiring layer, the third wiring layer and the fourth wiring layer are respectively arranged on both side surfaces of the second dielectric layer, the third wiring layer is connected to the first conductive dam, and the fourth wiring layer is connected to the second conductive dam.

[0015] In an optional embodiment, a first solder sheet is further provided on a side of the third wiring layer away from the second conductive dam, and the first conductive dam is soldered to the third wiring layer through the first solder sheet, and a second solder sheet is further provided on a side of the fourth wiring layer away from the first conductive dam, and the second conductive dam is soldered to the fourth wiring layer through the second solder sheet.

[0016] In an optional embodiment, the third substrate includes a third dielectric layer, a fifth wiring layer and a sixth wiring layer, the fifth wiring layer and the sixth wiring layer are respectively arranged on both side surfaces of the third dielectric layer, the second conductive dam is integrally electroplated on the edge of the fifth wiring layer, and the second chipset is attached to the fifth wiring layer and electrically connected to the fifth wiring layer.

[0017] In an optional implementation manner, a solder ball is further disposed on a side of the sixth wiring layer away from the second conductive dam.

[0018] In an optional embodiment, the first conductive dam is arranged around the edge of the first substrate to form a first inner cavity, and a first electromagnetic shielding partition is also provided on one side surface of the first substrate, and the first electromagnetic shielding partition divides the first inner cavity into a plurality of first shielding microcavities, and the first chip group is arranged in the plurality of first shielding microcavities.

[0019] In an optional embodiment, the second conductive dam is arranged around the edge of the third substrate to form a second inner cavity, and a second electromagnetic shielding partition is also provided on one side surface of the second substrate, and the second electromagnetic shielding partition divides the second inner cavity into a plurality of second shielding microcavities, and the second chip group is arranged in the plurality of second shielding microcavities.

[0020] In an optional embodiment, a heat dissipation hole is formed on the first substrate, and the heat dissipation hole is filled with a metal layer.

[0021] The beneficial effects of the embodiments of the utility model include:

[0022] The SIP radio frequency module provided by the embodiment of the utility model has a first conductive dam disposed on the edge of the first substrate, and the edge of the second substrate is connected to the first conductive dam, thereby forming a receiving cavity, and the first chipset is disposed in the receiving cavity and attached to the first substrate, wherein the first conductive dam is integrally electroplated and formed on the edge of the first substrate, which can avoid welding with the first substrate. Compared with the prior art, the utility model forms the conductive dam integrally electroplated on the edge of the substrate, thereby improving the structural strength, and the connection does not need to occupy too much space, so that the overall height is relatively lower, and the stability of the stacking structure is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of the structure of a SIP radio frequency module provided in an embodiment of the utility model;

[0025] Figure 2 A schematic diagram of the decomposed structure of a SIP radio frequency module provided in an embodiment of the utility model;

[0026] Figure 3 for Figure 1 A circuit diagram of the first chipset or the second chipset.

[0027] icon:

[0028] 100-SIP RF module; 110-first substrate; 111-first dielectric layer; 113-first wiring layer; 115-second wiring layer; 120-first chipset; 130-first conductive dam; 131-first electromagnetic shielding partition; 140-second substrate; 141-second dielectric layer; 143-third wiring layer; 145-fourth wiring layer; 147-first solder sheet; 149-second solder sheet; 150-third substrate; 151-third dielectric layer; 153-fifth wiring layer; 155-sixth wiring layer; 157-solder ball; 160-second conductive dam; 161-second electromagnetic shielding partition; 170-second chipset. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Generally, the components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the present invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0032] In the description of the present utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, or the orientation or position relationship in which the utility model product is usually placed when in use, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0033] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0034] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] The current SIP technology mainly includes HTCC (high temperature co-fired ceramic) technology, LTCC (low temperature co-fired ceramic) technology, and TSV (through silicon via) technology. HTCC has high thermal conductivity, but high conductor resistivity and slightly larger losses; LTCC has lower losses than HTCC, but lower thermal conductivity and higher costs than HTCC; TSV uses wafer-level packaging technology to achieve multi-layer packaging, but requires wafer processing capabilities, and the cost of a single tape-out is too high. As disclosed in the background technology, the SIP technology in the prior art usually uses a ceramic substrate and a dam to accommodate the chip, and the dam usually does not play a conductive role. Therefore, when multiple layers are stacked, it is necessary to additionally design the structure of the conductive column to achieve electrical interconnection between the upper and lower layers of the stack.

[0036] Furthermore, in conventional multi-layer stacking, the upper and lower layers of the dam need to be fixed by sintering and welding, and a large amount of solder is needed for welding, which requires a large welding space and occupies a large volume after welding, resulting in a high height of each layer of the dam, which in turn leads to a high overall height and poor stacking stability.

[0037] In addition, the multi-layer stacking structure in conventional technology, such as a three-layer stacking, adopts a sequential stacking structure, that is, the upper ceramic substrate is stacked on the lower dam, and the chip devices are usually attached to the ceramic substrate. This stacking structure will cause poor heat dissipation of the entire module and affect the heat dissipation performance.

[0038] In order to solve the above problems, the utility model provides a novel SIP radio frequency module, which is introduced in detail below.

[0039] Please refer to Figures 1 to 3This embodiment provides a SIP RF module 100, which can use a conductive dam and electroplate the conductive dam integrally on the edge of the substrate, thereby improving the structural strength, and the connection does not need to occupy too much space, so that the overall height is relatively lower and the stability of the stacking structure is improved.

[0040] In a first aspect, the utility model provides a SIP radio frequency module 100, comprising a first substrate 110, a first chipset 120, a first conductive dam 130 and a second substrate 140, wherein the first chipset 120 is attached to a side surface of the first substrate 110 and is electrically connected to the first substrate 110; the first conductive dam 130 is arranged at an edge of a side surface of the first substrate 110 and surrounds the chipset; one side of the second substrate 140 is connected to a side of the first conductive dam 130 away from the first substrate 110; wherein the first conductive dam 130 is integrally formed by electroplating on the edge of the first substrate 110, and the first substrate 110 is electrically connected to the second substrate 140 through the first conductive dam 130.

[0041] It should be noted that, in the embodiment of the utility model, a first conductive dam 130 is arranged at the edge of the first substrate 110, and the edge of the second substrate 140 is connected to the first conductive dam 130, so as to form a receiving cavity, and the first chip group 120 is arranged in the receiving cavity and attached to the first substrate 110, wherein the first conductive dam 130 is formed on the edge of the first substrate 110 by integral electroplating, so as to avoid welding with the first substrate 110. By integrally forming the conductive dam on the edge of the substrate by integral electroplating, the structural strength is improved, and welding is avoided at the connection, so that too much space does not need to be occupied, so that the overall height is relatively lower, and the stability of the stacking structure is improved.

[0042] Furthermore, the SIP RF module 100 also includes a third substrate 150, a second conductive dam 160 and a second chipset 170, the second chipset 170 is attached to a side surface of the third substrate 150, the second conductive dam 160 is arranged at an edge of a side surface of the third substrate 150, and the side of the second substrate 140 away from the first conductive dam 130 is connected to the second conductive dam and is spaced apart from the third substrate 150, wherein the second conductive dam 160 is integrally electroplated on the edge of the second substrate 140, and the third substrate 150 is electrically connected to the second substrate 140 through the second conductive dam 160.

[0043] It should be noted that in this embodiment, the first conductive dam 130 and the second conductive dam 160 are both metal dams, and the first conductive dam 130 is integrally fixed to the edge of the first substrate 110 by integrated electroplating, and the second conductive dam 160 is integrally fixed to the edge of the second substrate 140, which greatly improves the structural strength of the stack. Among them, the first conductive dam 130 and the second conductive dam 160 both have conductive properties, and can achieve electrical connection between the first substrate 110 and the second substrate 140, and the third substrate 150 and the second substrate 140, that is, the upper stack structure and the lower stack structure achieve signal interconnection through the middle second substrate 140.

[0044] In this embodiment, the first substrate 110 includes a first dielectric layer 111, a first wiring layer 113, and a second wiring layer 115. The first wiring layer 113 and the second wiring layer 115 are respectively arranged on both side surfaces of the first dielectric layer 111. The first conductive dam 130 is formed by electroplating on the edge of the second wiring layer 115. The first chip group 120 is attached to the second wiring layer 115 and is electrically connected to the second wiring layer 115. Specifically, the first dielectric layer 111 can be a ceramic substrate and adopt a DPC process (direct copper plating ceramic substrate), or a multilayer ceramic of a process such as HTCC / LTCC to achieve more wiring layers. Preferably, the first dielectric layer 111 can be made of 96 aluminum oxide material, and the thickness of the first dielectric layer 111 is between 0.1 mm and 1 mm. The upper surface and the lower surface of the first dielectric layer 111 are respectively electroplated to form a large area of ​​metal, and the corresponding metal pattern is etched to realize the extraction and isolation of the electrical signal to form the first wiring layer 113 and the second wiring layer 115, wherein the thickness of the first wiring layer 113 and the second wiring layer 115 is between 10 μm and 100 μm. The surface of the second wiring layer 115 is electroplated with a first conductive dam 130, and the thickness of the first conductive dam 130 is between 0.1 mm and 1 mm. The height of the dam needs to consider the chip height, the gold wire bonding height, and the air cavity height. The dams of different heights are realized by controlling the line of sight and the number of electroplating growth. Among them, the materials of the first wiring layer 113, the second wiring layer 115 and the first conductive dam 130 are generally copper, and the plating layer can be nickel-palladium-gold.

[0045] In this embodiment, the second substrate 140 includes a second dielectric layer 141, a third wiring layer 143, and a fourth wiring layer 145. The third wiring layer 143 and the fourth wiring layer 145 are respectively arranged on both side surfaces of the second dielectric layer 141. The third wiring layer 143 is connected to the first conductive dam 130, and the fourth wiring layer 145 is connected to the second conductive dam 160. The material of the second dielectric layer 141 can be the same as that of the first dielectric layer 111, and the materials of the third wiring layer 143 and the fourth wiring layer 145 can be the same as those of the first wiring layer 113 and the second wiring layer 115.

[0046] In this embodiment, a first solder sheet 147 is further provided on a side of the third wiring layer 143 away from the second conductive dam 160, and the first conductive dam 130 is soldered to the third wiring layer 143 through the first solder sheet 147. A second solder sheet 149 is further provided on a side of the fourth wiring layer 145 away from the first conductive dam 130, and the second conductive dam 160 is soldered to the fourth wiring layer 145 through the second solder sheet 149. Specifically, both the first solder sheet 147 and the second solder sheet 149 may be gold-tin solder sheets, and the first conductive dam 130 and the third wiring layer 143 are soldered by the first solder sheet 147, and the second conductive dam 160 and the fourth wiring layer 145 are soldered by the second solder sheet 149.

[0047] Furthermore, the third substrate 150 includes a third dielectric layer 151, a fifth wiring layer 153 and a sixth wiring layer 155, the fifth wiring layer 153 and the sixth wiring layer 155 are respectively arranged on both side surfaces of the third dielectric layer 151, the second conductive dam 160 is integrally formed by electroplating on the edge of the fifth wiring layer 153, and the second chipset 170 is attached to the fifth wiring layer 153 and electrically connected to the fifth wiring layer 153.

[0048] In this embodiment, a solder ball 157 is further disposed on one side of the sixth wiring layer 155 away from the second conductive dam 160. Specifically, the signal output can be led out in the form of BGA or QFN through the solder ball 157.

[0049] Further preferably, in this embodiment, the first dielectric layer 111, the second dielectric layer 141 and the third dielectric layer 151 can all adopt 0.5 mm thick 96 alumina ceramic, the metal wiring on the upper and lower surfaces of the ceramic substrate is copper-plated, and the thickness of each layer of copper plating is 65 μm. The SIP RF module 100 can be interconnected with the external model through the solder ball 157 to achieve BGA ball, and the diameter of the solder ball 157 is 0.45 mm.

[0050] In this embodiment, the first conductive dam 130 is arranged around the edge of the first substrate 110 to form a first inner cavity. A first electromagnetic shielding baffle 131 is also provided on one side surface of the first substrate 110. The first electromagnetic shielding baffle 131 divides the first inner cavity into a plurality of first shielding microcavities. The first chip group 120 is arranged in the plurality of first shielding microcavities. At the same time, the second conductive dam 160 is arranged around the edge of the third substrate 150 to form a second inner cavity. A second electromagnetic shielding baffle 161 is also provided on one side surface of the second substrate 140. The second electromagnetic shielding baffle 161 divides the second inner cavity into a plurality of second shielding microcavities. The second chip group 170 is arranged in the plurality of second shielding microcavities. The first electromagnetic shielding baffle 131 and the second electromagnetic shielding baffle 161 can be arranged separately or formed by electroplating growth together with the first conductive dam 130 and the second conductive dam 160.

[0051] Specifically, in this embodiment, the first inner cavity is located above the second inner cavity, and the first chipset 120 can be a driver amplifier chip, a power amplifier chip, a PMOS, a leakage voltage modulation chip, a gate voltage driver chip and other devices, and are all pasted on the second wiring layer 115. The chip can be bonded in the form of conductive glue, or it can be pasted in the form of gold-tin eutectic or nano-silver paste sintering. The first cavity realizes the functions of transmitting power amplification and transmitting power modulation of four channels. Each transmitting channel can be a first shielded microcavity alone, and the chips in the same microcavity are interconnected by gold wire bonding. The signal interconnection between different microcavities first leads the signal from the chip to the second wiring layer 115 through gold wire bonding, and then realizes conduction through the vertical interconnection of the first conductive dam 130 and the planar interconnection of the third wiring layer 143 and the fourth wiring layer 145.

[0052] It should be noted that the function of the driver amplifier chip and the power amplifier chip is to perform high-efficiency power saturation amplification on the transmitted microwave signal. The function of the drain voltage modulation chip is to provide the operating voltage of the drain of the power amplifier chip, and the function of the gate voltage driver chip is to provide the negative reference gate voltage of the power amplifier chip.

[0053] It is worth noting that in this embodiment, there are 4 transmitting channels in the first cavity, and each channel has 1 RF signal input Tin and 1 RF signal output Tout. After the RF input signal Tin of the transmitting channel is output by the amplitude and phase multifunction, it is transmitted to the transmitting input pin of the first cavity through a quasi-coaxial structure, and after being amplified by the driving amplifier and the power amplifier, it is transmitted to the corresponding output pin Tout through a quasi-coaxial structure. The output signal Tout of the power amplification is directly output to the solder ball 157 through a quasi-coaxial pass to ensure that the output power loss is minimized. The power supply and control signals required for the operation of the circuit are also transmitted to the inside of the SiP through the intermediate substrate and the metal dam layer.

[0054] In addition, the second chipset 170 can be a limiter chip, a low noise amplifier chip, an absorption load, an amplitude and phase multifunctional chip, an LDO chip and other devices, and they are all pasted on the fifth wiring layer 153. The second cavity realizes the reception of four channels of low noise amplification, phase shifting, attenuation, serial-to-parallel conversion, reception power modulation and other functions. The chip is pasted in the form of conductive glue, and can also be pasted in the form of gold-tin eutectic or nano-silver paste sintering. Each receiving channel of the second cavity is independently formed into a second shielded microcavity, and the amplitude and phase multifunctional chip and the LDO chip are independently formed into a microcavity. The chips in the same microcavity are interconnected by gold wire bonding to realize radio frequency and electrical signal interconnection. The electrical signal interconnection between different microcavities first leads the signal from the chip to the fifth wiring layer 153 through gold wire bonding, and then realizes conduction through the vertical interconnection of the through-holes in the third dielectric layer 151 and the planar interconnection of the sixth wiring layer 155.

[0055] It should be noted that the function of the limiter chip is to prevent the low-noise amplifier chip from burning when the received high-power microwave signal is input, and to cooperate with the absorption load to absorb the reflected RF signal; the function of the low-noise amplifier chip is to amplify the received weak RF signal with low noise; the function of the amplitude and phase multifunctional chip is to provide RF path and working status control for the transmission and output of the four channels; the LDO chip is a low-voltage linear voltage regulator chip, which provides stable voltage input for the amplitude and phase multifunctional chip.

[0056] It should also be noted that, in this embodiment, the first conductive dam 130 and the second conductive dam 160 can be grown by electroplating, and the first cavity and the second cavity can be formed by selectively growing the dam pattern, and the first shielding microcavity and the second shielding microcavity can be formed. In addition, the height of the chips and devices of the first chip group 120 in this embodiment is not higher than 400 μm, so as to further achieve miniaturization and thickness reduction of the overall structure.

[0057] It is worth noting that there are 4 receiving channels in the second cavity, each channel has a RF input signal Rin and a RF output signal Rout. The Rin of the receiving channel directly passes through the third dielectric layer 151 from the solder ball 157 to the fifth wiring layer 153, and the RF output signal Rout passes through the limiter and the low noise amplifier to the amplitude and phase multifunctional chip through the microstrip line. The input signal path of the low noise amplifier is short, and the measured path loss noise is ≤0.2dB.

[0058] Through the above design, the overall size of the X-band SIP RF module 100 is approximately 14.5mm*15.5mm*3.9mm, and the weight is ≤5g, achieving the design goals of high performance, low cost, and miniaturization.

[0059] In some embodiments, the amplitude and phase multifunction of the second cavity in the lower layer is a separate cavity. The self-developed amplitude and phase multifunction chip can be used to integrate phase shifting, attenuation, serial-to-parallel conversion, power modulation and other functions. The four independent T / R channels provide independent amplitude and phase control, and provide the working voltage of the low-noise amplifier chip. All RF signals are input / output via the COM port of the amplitude and phase multifunction chip, and the transmission, reception, attenuation and phase shifting working states of each channel can be controlled by the amplitude and phase multifunction wave control input.

[0060] In this embodiment, heat dissipation holes are provided on the first substrate 110, and the heat dissipation holes are filled with a metal layer. Specifically, since the first chipset 120 in this application is attached to the second wiring layer 115 of the first substrate 110, the first cavity in this embodiment can realize the rapid extraction of heat from the emission channel, and the heat generated by the first chipset 120 can be quickly transversely conducted through the metal layers of the first wiring layer 113 and the second wiring layer 115, and the 96 alumina ceramic used in the first dielectric layer 111 has a high thermal conductivity (~25W / m·K, compared with HTCC's ~17W / m·K and LTCC's ~2W / m·K). By densely drilling heat dissipation holes in the medium below the heat source and filling them with metal to form metal holes, the equivalent thermal conductivity in the vertical direction can be improved (~32W / m·K).

[0061] In other preferred embodiments of the present invention, a very short heat conduction path (0.1 mm-1 mm) can be achieved by attaching heat conducting materials and cooling equipment to the surface of the first wiring layer 113. At the same time, the output power of a single channel greater than 100 W can be achieved by replacing the dielectric layer material with aluminum nitride or silicon carbide.

[0062] It should be noted that in the SIP RF module 100 provided in this embodiment, a large current passes through the power amplifier chip of the upper first cavity during operation, and a large amount of heat is generated. By stacking the upper first cavity inverted, the heat generated by the power amplifier chip can be quickly exported from the SiP RF module through only one layer of ceramic substrate upward. The design of inverted bonding of high-power chips makes full use of the high thermal conductivity of the ceramic substrate, thereby reducing the impact of temperature on other chips in the cavity, so that the SIP RF module 100 can adapt to high-power applications, such as single-module transmission power ≥ 200W.

[0063] During the actual assembly, the first substrate 110 and the first conductive dam 130 can be prepared first, and the first chipset 120 can be attached. Then, the third substrate 150 and the second conductive dam 160 can be prepared, and the chipset can be attached. Then, the preformed gold-tin solder sheets can be attached to the upper and lower surfaces of the second substrate 140, that is, the third wiring layer 143 and the fourth wiring layer 145. After completing the pre-setting solder sheet process, the upper cavity and the lower cavity are respectively turned upside down on the corresponding surfaces of the middle substrate for stacking. After completing the airtight packaging, the lower cavity is lead-tin BGA ball planting (ball diameter 0.45mm), and finally the SIP RF module 100 is completed.

[0064] In summary, the beneficial effects of the embodiments of the present utility model include:

[0065] 1. A first conductive dam 130 is arranged at the edge of the first substrate 110, and the edge of the second substrate 140 is connected to the first conductive dam 130, so as to form a receiving cavity, and the first chipset 120 is arranged in the receiving cavity and attached to the first substrate 110, wherein the first conductive dam 130 is formed by electroplating on the edge of the first substrate 110, so as to avoid welding with the first substrate 110. Compared with the prior art, the utility model forms the conductive dam by electroplating on the edge of the substrate, which improves the structural strength, and the connection does not need to occupy too much space, so that the overall height is relatively lower and the stability of the stacking structure is improved. Specifically, the systematic design of the SIP RF module 100 is realized based on the DPC process, and the four-channel RF transceiver is realized based on the multi-layer stacking structure. Under the same function and performance indicators, the volume and weight are reduced by at least one order of magnitude compared with the traditional RF components, and miniaturized applications can be realized.

[0066] 2. The inverted design can conduct the heat generated by the power amplifier upward through the ceramic substrate, reducing the impact on other chips in the system and enabling high-power applications.

[0067] 3. The extremely short transmission path effectively reduces the transmission loss of the SIP RF module 100 and enables low-noise applications.

[0068] 4. The independently metallized microcavity has good electromagnetic shielding capability, so that the SIP RF module 100 has a high spatial isolation, avoiding the self-excitation of the power amplifier caused by spatial radiation, and realizing high isolation applications.

[0069] 5. The integrated electroplated metal dam reduces the area of ​​solder mask and welding metal dam compared to co-fired ceramics such as HTCC. More functional chips can be integrated in the same area, enabling high-integration applications.

[0070] 6. The distance between the pasted chip and the pad is short, which reduces the length of the gold wire and reduces the impact on the chip performance; the heat dissipation holes in the dielectric layer are filled with metal to not only dissipate heat, but also effectively suppress the generation of resonance, thereby achieving highly stable operation.

[0071] 7. Modular design can realize the full process automation and batch production of SIP RF module 100, improve the consistency of each RF module, reduce manual operation, and achieve high production efficiency and high yield rate.

[0072] 8. The modular design enables the SIP RF module 100 to be interconnected with the antenna and the signal processing module through the PCB, providing a basis for a highly integrated RF microsystem.

[0073] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A SIP radio frequency module, characterized in that: include: a first substrate; a first chipset, the first chipset being attached to a side surface of the first substrate and electrically connected to the first substrate; A first conductive dam is disposed at an edge of a side surface of the first substrate and surrounds the chipset; A second substrate, wherein one side edge of the second substrate is connected to a side of the first conductive dam away from the first substrate; The first conductive dam is integrally formed at an edge of the first substrate, and the first substrate is electrically connected to the second substrate via the first conductive dam.

2. The SIP radio frequency module according to claim 1, characterized in that: The SIP RF module also includes a third substrate, a second conductive dam and a second chipset, wherein the second chipset is attached to a side surface of the third substrate, the second conductive dam is arranged at an edge of a side surface of the third substrate, and a side of the second substrate away from the first conductive dam is connected to the second conductive dam and is spaced apart from the third substrate, wherein the second conductive dam is formed integrally by electroplating on the edge of the second substrate, and the third substrate is electrically connected to the second substrate through the second conductive dam.

3. The SIP radio frequency module according to claim 2, characterized in that: The first substrate includes a first dielectric layer, a first wiring layer and a second wiring layer, the first wiring layer and the second wiring layer are respectively arranged on both side surfaces of the first dielectric layer, the first conductive dam is integrally formed by electroplating on the edge of the second wiring layer, and the first chipset is attached to the second wiring layer and electrically connected to the second wiring layer.

4. The SIP radio frequency module according to claim 2, characterized in that: The second substrate includes a second dielectric layer, a third wiring layer and a fourth wiring layer. The third wiring layer and the fourth wiring layer are respectively arranged on both side surfaces of the second dielectric layer. The third wiring layer is connected to the first conductive dam, and the fourth wiring layer is connected to the second conductive dam.

5. The SIP radio frequency module according to claim 4, characterized in that: A first solder sheet is further provided on a side of the third wiring layer away from the second conductive dam, and the first conductive dam is soldered to the third wiring layer through the first solder sheet. A second solder sheet is further provided on a side of the fourth wiring layer away from the first conductive dam, and the second conductive dam is soldered to the fourth wiring layer through the second solder sheet.

6. The SIP radio frequency module according to claim 2, characterized in that: The third substrate includes a third dielectric layer, a fifth wiring layer and a sixth wiring layer, the fifth wiring layer and the sixth wiring layer are respectively arranged on both side surfaces of the third dielectric layer, the second conductive dam is formed integrally by electroplating on the edge of the fifth wiring layer, and the second chipset is attached to the fifth wiring layer and electrically connected to the fifth wiring layer.

7. The SIP radio frequency module according to claim 6, characterized in that: A solder ball is further disposed on a side of the sixth wiring layer away from the second conductive dam.

8. The SIP radio frequency module according to claim 2, characterized in that: The first conductive dam is arranged around the edge of the first substrate to form a first inner cavity. A first electromagnetic shielding partition is also arranged on one side surface of the first substrate. The first electromagnetic shielding partition divides the first inner cavity into a plurality of first shielding microcavities. The first chip group is arranged in the plurality of the first shielding microcavities.

9. The SIP radio frequency module according to claim 8, characterized in that: The second conductive dam is arranged around the edge of the third substrate to form a second inner cavity. A second electromagnetic shielding partition is also arranged on one side surface of the second substrate. The second electromagnetic shielding partition divides the second inner cavity into a plurality of second shielding microcavities. The second chip group is arranged in the plurality of second shielding microcavities.

10. The SIP radio frequency module according to claim 2, characterized in that: The first substrate is provided with a heat dissipation hole, and the heat dissipation hole is filled with a metal layer.

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