Power semiconductor device
By forming a plurality of second trenches on the substrate and designing a rectangular sheet-shaped first trenches, the problem of difficult to increase the channel density in the prior art in the medium and high voltage applications is solved, and the effect of reducing parasitic resistance and increasing the channel density is achieved.
Patent Information
- Application Number
- CN202420161543.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-23
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2034-01-23
AI Technical Summary
In medium and high voltage applications, existing shielded gate MOSFET devices are limited by the thickness of the shielded gate dielectric layer and the shielded gate filling capability in the trench, making it difficult to increase the channel density and approach the process limit.
A power semiconductor device is designed to increase the channel density by forming a plurality of second trenches on the substrate and in the region surrounded by the second trenches, the first trenches are located in the area surrounded by the second trenches, so as to make the plan view of the first trenches into a rectangular sheet shape.
It effectively reduces the parasitic resistance brought by the shielding gate, reduces delay, and increases channel density, avoiding process processing difficulties and reliability problems.
Smart Images
Figure CN222674847U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to a power semiconductor device. Background Art
[0002] Power semiconductor devices are often used in power management circuits such as switching power supplies, DC-DC, and AC-DC to achieve functions such as power conversion and control. VDMOS (Vertical double-diffused metal oxide semiconductor) field effect transistors are widely used due to their superior switching performance and high input impedance. VDMOS field effect transistors include a source region formed on the surface of a semiconductor layer and a drain region formed on the surface of a semiconductor substrate. In the on state, the current mainly flows longitudinally along the depth direction of the semiconductor substrate.
[0003] With the improvement of manufacturing technology, the cell width of shielded gate MOSFET devices has been continuously reduced. However, for medium and high voltage applications, the thickness of the shielded gate dielectric layer and the shielded gate filling capacity in the trench are limited, which is gradually approaching the process limit. This is a major challenge for shielded gate MOSFET devices to increase channel density. Utility Model Content
[0004] In view of the above problems, an object of the present invention is to provide a power semiconductor device to increase the channel density.
[0005] According to the utility model, a power semiconductor device is provided, comprising: a substrate, comprising a first surface and a second surface opposite to each other;
[0006] a semiconductor layer located on the first surface of the substrate;
[0007] a plurality of first trenches in the semiconductor layer;
[0008] A shielding gate dielectric layer and a shielding gate located in the plurality of first trenches, wherein the shielding gate dielectric layer covers the sidewalls and the bottom of the first trenches, and the shielding gate dielectric layer isolates the shielding gate from the semiconductor layer;
[0009] a plurality of second trenches in the semiconductor layer;
[0010] A control gate dielectric layer and a control gate located in the plurality of second trenches, wherein the control gate dielectric layer covers the sidewalls and the bottom of the second trenches, and the control gate dielectric layer isolates the control gate from the semiconductor layer;
[0011] a body region in the semiconductor layer, the body region being adjacent to upper portions of the plurality of first trenches and the plurality of second trenches;
[0012] a source region located in the body region;
[0013] a source electrode electrically connected to the source region and the shielding gate;
[0014] a drain electrode located on the second surface of the substrate; and
[0015] a gate electrode electrically connected to the control gate,
[0016] Among them, the multiple second grooves extend along the first direction and the second direction and are interconnected, the first direction and the second direction are perpendicular, each of the first grooves is located in the area surrounded by the second grooves, the top view of the first groove is a rectangle, and the ratio of the width to the length of the first groove is 1:1.2 to 1:2.
[0017] Optionally, a ratio of the width to the length of the first groove is 1:1.5.
[0018] Optionally, the plurality of first grooves are arranged in a matrix array or a diamond array.
[0019] Optionally, the plurality of second grooves include a first portion of second grooves extending along the first direction and arranged parallel to the second direction and a second portion of second grooves extending along the second direction and arranged parallel to the first direction, and the first portion of second grooves and the second portion of second grooves are arranged orthogonally.
[0020] Optionally, the plurality of second grooves include a first portion of second grooves extending along the first direction and a second portion of second grooves extending along the second direction, the first portion of second grooves are spaced apart along the first direction, and the first portion of second grooves in two adjacent rows in the second direction are staggered.
[0021] Optionally, the rectangle of the top view of the first groove includes at least one rounded corner, and the radius of the rounded corner is greater than or equal to one quarter of the width of the first groove and less than or equal to one half of the width of the first groove.
[0022] Optionally, a width of the first groove is 1.1 μm to 4.5 μm, a depth of the first groove is 5 μm to 20 μm, and a distance between two adjacent first grooves is 1 μm to 6 μm.
[0023] Optionally, a width of the first groove is 1.1 μm to 3.6 μm.
[0024] Optionally, the thickness of the shielding gate dielectric layer is 3800-20000 angstroms, and the distance between the shielding gate and the first surface of the semiconductor layer is 0 μm to 1.5 μm.
[0025] Optionally, a distance between the first groove and an adjacent second groove is 0.35 μm to 0.9 μm.
[0026] Optionally, the width of the second groove is 0.2 μm to 5 μm, the depth of the second groove is 0.8 μm to 2.5 μm, the spacing between two adjacent second grooves extending along the second direction is 3 μm to 5.5 μm, and the spacing between two adjacent second grooves extending along the first direction is 3 μm to 11 μm.
[0027] Optionally, the thickness of the control gate dielectric layer located at the bottom of the second trench is greater than or equal to the thickness of the control gate dielectric layer located at the sidewall of the second trench.
[0028] Optionally, the thickness of the control gate dielectric layer is 600 angstroms to 3000 angstroms, and the distance between the control gate and the first surface of the semiconductor layer is 0 μm to 0.2 μm.
[0029] Optionally, it also includes:
[0030] a first contact contacting the shield gate in the plurality of first trenches;
[0031] a second contact, contacting the source region between the first trench and the second trench, and electrically connected to the first contact to lead out the source electrode;
[0032] The third contact contacts the control gates in the plurality of second trenches to lead out the gate electrode.
[0033] Optionally, it also includes:
[0034] a covering dielectric layer, located on the first surface of the semiconductor layer and covering the source region, the first trench and the second trench, wherein the covering dielectric layer includes a first contact hole, a second contact hole and a third contact hole,
[0035] The first contact hole penetrates the covering dielectric layer and reaches the surface of the shielding gate, and the first contact hole is filled with the first contact.
[0036] The second contact hole penetrates the covering dielectric layer and reaches at least a portion of the surface of the source region, and the second contact hole is filled with the second contact.
[0037] The third contact hole penetrates the covering dielectric layer and reaches the surface of the control gate, and the third contact hole is filled with the third contact.
[0038] The source electrode is located on the surface of the covering dielectric layer and is connected to the first contact and the second contact;
[0039] The gate electrode is located on the surface of the covering dielectric layer and is connected to the third contact.
[0040] The power semiconductor device provided by the embodiment of the utility model arranges a plurality of second grooves along the first direction and the second direction and interconnects them, and each first groove is located in the area surrounded by the second grooves, so that the top view shape of the first groove is a rectangular sheet, which can reduce the parasitic resistance caused by the shielding grid, thereby reducing the delay caused by the parasitic resistance. Furthermore, the ratio of the width to the length of the first groove is 1:1.2 to 1:2, which avoids the situation where the photoresist attachment area of the first contact hole is small, and reduces the difficulty of process processing. In addition, the reliability problem caused by the consistency of process processing can also be avoided. Furthermore, the shielding grid is directly electrically connected to the source region and leads to the source electrode, avoiding the problem of opening uniformity during high-speed switching.
[0041] Furthermore, a transverse conductive channel is formed between adjacent first grooves, which increases the area of the mesa overcurrent and effectively increases the channel density.
[0042] Furthermore, the top view of the first groove is a rounded rectangle, and the radius of the rounded corner is greater than or equal to one-quarter of the width of the first groove and less than or equal to one-half of the width of the first groove, which can avoid overcurrent failure caused by local electron accumulation when the power semiconductor device is turned on. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0044] Figure 1 A schematic diagram showing a layout of a power semiconductor device is shown;
[0045] Figure 2 Show Figure 1 An enlarged schematic diagram of a partial layout of a power semiconductor device is shown;
[0046] Figure 3 Shown along Figure 2 Schematic diagram of the cross section taken along line AA';
[0047] Figure 4 Shown along Figure 2 Schematic diagram of the cross section taken along line BB';
[0048] Figure 5 An enlarged schematic diagram showing a partial layout of a power semiconductor device provided according to a first embodiment of the present disclosure;
[0049] Figure 6a Shown along Figure 5A schematic cross-sectional view of a power semiconductor device taken along line CC';
[0050] Figure 6b A schematic cross-sectional view showing an end portion of a second trench of a power semiconductor device provided according to a first embodiment of the present disclosure;
[0051] Figure 7 Show Figure 5 A partial three-dimensional schematic diagram of a power semiconductor device shown;
[0052] Figure 8 An enlarged schematic diagram showing a partial layout of a power semiconductor device provided according to a second embodiment of the present disclosure;
[0053] Figure 9a to Figure 9h Schematic cross-sectional views of power semiconductor devices provided by the first and second embodiments of the present disclosure at different stages in the manufacturing process are shown. DETAILED DESCRIPTION
[0054] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.
[0055] The specific implementation of the utility model is further described in detail below in conjunction with the drawings and embodiments.
[0056] Figure 1 A schematic diagram of the layout of a power semiconductor device is shown. Figure 2 Show Figure 1 An enlarged schematic diagram of a partial layout of a power semiconductor device is shown. Figure 3 Shown along Figure 2 Schematic diagram of the cross section taken along line AA'. Figure 4 Shown along Figure 2 Schematic diagram of the cross section taken along line BB'.
[0057] like Figure 1 As shown, the layout of the power semiconductor device includes a gate electrode region 111, a cell region, and a terminal region (including a transition region and a cut-off region). The cell region includes a plurality of strip grooves 201. The terminal region includes at least one annular groove, for example, two annular grooves, wherein the outermost annular groove is, for example, a cut-off region, which short-circuits the second type doping region to have the same potential as the drain electrode, thereby isolating leakage, thereby improving the reliability of the power semiconductor device; the transition region is an annular groove located between the cut-off region and the cell region, and the potential is partially connected to the source or completely floating.
[0058] Figure 2 for Figure 1 FIG. 1 is an enlarged schematic diagram of the rectangular frame area 11. Figure 2 As shown, the cell region of the power semiconductor device includes a plurality of strip-shaped trenches 201 , each of which includes a control gate lead-out region I and a shield gate lead-out region II, wherein the control gate lead-out region I is located at two ends of the trench 201 , for example.
[0059] Combination Figure 3 , Figure 4 As shown, the power semiconductor device includes: a substrate 210, a semiconductor layer 209 located on a first surface of the substrate 210, a plurality of trenches 201 located in the semiconductor layer 209, a shielding gate dielectric layer 205, a shielding gate 203, a control gate dielectric layer 204, and a control gate 202 located in the plurality of trenches 201, a body region 207 located in the semiconductor layer 209, and a source region 208 located in the body region 207. The shielding gate 203 and the control gate 202 are isolated by the control gate dielectric layer 204, the shielding gate 203 and the semiconductor layer 209 are isolated by the shielding gate dielectric layer 205, the control gate 202 and the semiconductor layer 209 are isolated by the control gate dielectric layer 204, and the control gate dielectric layer 204 also includes a portion located on the surface of the source region 208. The power semiconductor device also includes: a covering dielectric layer 206 covering the control gate dielectric layer 204 and the surface of the control gate 202, a first contact 212 located in the control gate lead-out region I and penetrating the covering dielectric layer 206 to reach the surface of the control gate 202, a gate electrode 222 located in the control gate lead-out region I and electrically connected to the first contact 212, a second contact 213 located in the shield gate lead-out region II and penetrating the covering dielectric layer 206 to reach the surface of the shield gate 203, a third contact 214 located in the shield gate lead-out region II and penetrating the covering dielectric layer 206 to reach the surface of the source region 208, a source electrode 221 electrically connected to the second contact 213 and the third contact 214, and a drain electrode 223 located on the second surface of the substrate 210.
[0060] Although the above-mentioned power semiconductor device can increase the doping concentration of the semiconductor layer 209 and reduce the on-resistance by assisting the depletion of the semiconductor layer 209 through the internal field plate (shielding gate 203), the width of the groove 201 cannot be further reduced in medium and high voltage applications, resulting in the table area proportion of the main overcurrent area cannot continue to increase, thus limiting the further optimization of the on-resistance.
[0061] The power semiconductor device provided by the present disclosure can further optimize the on-resistance of the shielded gate power semiconductor device and solve the problem of low channel density in the strip groove layout. Furthermore, it can also avoid the problem of weak breakdown points and long-term reliability caused by the deep depth of the shielding gate groove in the medium and high voltage field, as well as the problem of the shielding gate lead-out being limited by the small photoresist attachment area.
[0062] Figure 5A schematic diagram showing an enlarged partial layout of a power semiconductor device provided according to a first embodiment of the present disclosure. Figure 6a Shown along Figure 5 Schematic diagram of the cross-section of the power semiconductor device taken along line CC'. Figure 6b A schematic cross-sectional view shows an end portion of a second trench of a power semiconductor device provided according to a first embodiment of the present disclosure. Figure 7 Show Figure 5 A partial three-dimensional schematic diagram of a power semiconductor device is shown. In this embodiment, the power semiconductor device is described by taking a trench VDMOS device as an example, but the present disclosure is not limited thereto.
[0063] like Figure 5 As shown, a partial layout in the cell area of the power semiconductor device provided in the first embodiment is shown. In the first embodiment, the cell area of the power semiconductor device includes a plurality of rectangular sheet-shaped first grooves 101 and a plurality of strip-shaped second grooves 100. It can be understood that the top view shape of the groove is rectangular sheet-shaped and strip-shaped, and the depth of the groove extends along the direction perpendicular to the surface of the substrate. The first part of the second grooves 100 extends along the first direction and is arranged in parallel along the second direction, the second part of the second grooves 100 extends along the second direction and is arranged in parallel along the first direction, the first direction and the second direction are perpendicular, and the first part of the second grooves 100 are arranged at intervals along the first direction, and the first part of the second grooves of the two adjacent rows in the second direction are staggered. That is, the first part of the second grooves 100 extending in the first direction are arranged orthogonally to the second part of the second grooves 100 extending in the second direction, and the second grooves 100 arranged in the first direction and the second grooves 100 arranged in the second direction are connected to each other. Preferably, the spacing between adjacent second grooves 100 arranged along the first direction is equal, and the spacing between adjacent second grooves 100 arranged along the second direction is equal. Two adjacent second grooves 100 arranged along the first direction and two adjacent second grooves 100 arranged along the second direction form a "well" shape, and the four second grooves 100 enclose a rectangular area, and multiple second grooves 100 separate multiple rectangular areas, each first groove 101 is located in a rectangular area, and multiple first grooves 101 are arranged in a matrix array in the first direction and the second direction. Exemplarily, Figure 5 4 second grooves 100 extending along the first direction (X direction) and 5 second grooves 100 extending along the second direction (Y direction) are shown. The above 9 second grooves 100 are interconnected and separate multiple rectangular areas. Each first groove 101 is located in a rectangular area.
[0064] Exemplarily, the top view shape of the first groove 101 is a rectangle, and the ratio of the width a to the length b of the first groove 101 is 1:1.2 to 1:2. In a preferred embodiment, the ratio of the width a to the length b of the first groove 101 is 1:1.5.
[0065] In an alternative embodiment, the rectangular shape of the top view of the first groove 101 includes at least one rounded corner. The radius R of the rounded corner is greater than or equal to one quarter of the width a of the first groove 101, and less than or equal to one half of the width a of the first groove 101. Exemplarily, the top view shape of the first groove 101 is a rounded rectangle, and the radius size of each rounded corner is, for example, the same. Further, the ratio of the width a to the length b of the first groove 101 is 1:1.2 to 1:2. In a preferred embodiment, the ratio of the width a to the length b of the first groove 101 is 1:1.5.
[0066] Combination Figure 6a , Figure 6b , Figure 7 As shown, the power semiconductor device includes: a substrate 110, a semiconductor layer 109 located on the substrate 110, a plurality of first trenches 101 located in the semiconductor layer 109, a shielding gate dielectric layer 105 and a shielding gate 103 located in the plurality of first trenches 101, a plurality of second trenches 100 located in the semiconductor layer 109, a control gate dielectric layer (including a control gate dielectric layer 104a and a control gate dielectric layer 104b) and a control gate 102 located in the plurality of second trenches 100, a body region 107 located in the semiconductor layer 109, a source region 108 located in the body region 107, a source electrode 121 electrically connected to the source region 108 and the shielding gate 103, and a gate electrode 122 electrically connected to the control gate 102. The substrate 110 includes a first surface and a second surface opposite to each other, and the semiconductor layer 109 is located on the first surface of the substrate 110. It should be noted that at the end of the second trench 100 (i.e., the edge of the cell region), the source region 108 is not provided in the body region 107.
[0067] Furthermore, the power semiconductor device further includes: a first contact 113 in contact with the shield gate 103 in the plurality of first trenches 101, a second contact 114 in contact with the source region 108 between the first trench 101 and the second trench 100, a third contact 115 in contact with the control gate 102 in the plurality of second trenches 100, and a drain electrode 123 located on the second surface of the substrate 110. The second contact 114 is electrically connected to the first contact 113 to lead out the source electrode 121, and the third contact 115 leads out the gate electrode 122.
[0068] Further, the power semiconductor device further includes a covering dielectric layer 106, which is located on the first surface of the semiconductor layer 109 and covers the source region 108, the first trench 101 and the second trench 100, and the covering dielectric layer 106 includes a first contact hole, a second contact hole and a third contact hole. The first contact hole penetrates the covering dielectric layer 106 and reaches the surface of the shielding gate 103, and the first contact hole is filled with metal to form a first contact 113. The second contact hole penetrates the covering dielectric layer 106 and reaches the surface of at least part of the source region 108. For example, in this embodiment, the second contact hole reaches the surface of part of the source region 108 and the shielding gate dielectric layer 105, and the second contact hole is filled with metal to form a second contact 114. The third contact hole penetrates the covering dielectric layer 106 and reaches the surface of the control gate 102, and the third contact hole is filled with metal to form a third contact 115. Among them, the source electrode 121 is located on the surface of the covering dielectric layer 106 and is connected to the first contact 113 and the second contact 114, and the gate electrode 122 is located on the surface of the covering dielectric layer 106 and is connected to the third contact 115. A portion of the second contact 114 is located on the source region 108, and a portion is located on the shielding gate dielectric layer 105, which can reduce the cell width (pitch) and increase the current density. In other embodiments, the second contact 114 can also be located entirely on the source region 108. It should be noted that the gate electrode 122 located on the surface of the covering dielectric layer 106 is not in contact with the source electrode 121.
[0069] Furthermore, the gate electrode 122 may be directly led out through the third contact 115 , and may also be led out through multiple layers of metal without considering the processing cost and complexity.
[0070] The substrate 110 may be a silicon substrate, and its doping type is a first doping type, such as N-type doping. The silicon substrate is, for example, uniformly doped in the vertical direction.
[0071] The semiconductor layer 109 may be an epitaxial layer located on the first surface of the substrate 110 , and its doping type is a first doping type, such as N-type doping. The semiconductor layer 109 has a first surface and a second surface opposite to each other.
[0072] A plurality of first trenches 101 extend downward from the first surface of the semiconductor layer 109. Exemplarily, the depth of the first trenches 101 is 5 μm to 20 μm. The width of the first trenches 101 is 1.1 μm to 4.5 μm. In a preferred embodiment, the width of the first trenches 101 is 1.1 μm to 3.6 μm. The spacing d1 between two adjacent first trenches 101 is 1 μm to 6 μm.
[0073] The shielding gate dielectric layer 105 covers the sidewalls and the bottom of the first trench 101. The shielding gate 103 is located in the first trench 101. The shielding gate dielectric layer 105 isolates the shielding gate 103 from the semiconductor layer 109. Exemplarily, the thickness of the shielding gate dielectric layer 105 is 3800 angstroms to 20000 angstroms. The distance between the shielding gate 103 and the first surface of the semiconductor layer 109 is 0 μm to 1.5 μm.
[0074] Furthermore, the distance d2 between the first trench 101 and the adjacent second trench 100 is, for example, 0.35 μm to 0.9 μm.
[0075] A plurality of second trenches 100 extend downward from the first surface of the semiconductor layer 109. Exemplarily, the depth of the second trenches 100 is 0.8 μm to 2.5 μm. The width of the second trenches 100 is 0.2 μm to 5 μm. The spacing d3 between two adjacent second trenches 100 extending along the second direction is 3 μm to 5.5 μm, and the spacing d4 between two adjacent second trenches 100 extending along the first direction is 3 μm to 11 μm.
[0076] Exemplarily, the thickness of the control gate dielectric layer 104a at the bottom of the second trench 100 is greater than or equal to the thickness of the control gate dielectric layer 104b at the sidewall of the second trench 100. In an alternative embodiment, the thickness of the control gate dielectric layer 104a at the bottom of the second trench 100 is equal to the thickness of the control gate dielectric layer 104b at the sidewall of the second trench 100. The thickness of the control gate dielectric layer 104a and the control gate dielectric layer 104b is, for example, 600 angstroms to 3000 angstroms.
[0077] Furthermore, the distance between the control gate 102 and the first surface of the semiconductor layer 109 is 0 μm to 0.2 μm.
[0078] Further, the doping type of the control gate 102 is the first doping type, for example, a polysilicon layer with a high concentration of N-type doping, so that the resistance of the polysilicon is reduced to 5-20 ohms / square. The doping type of the shielding gate 103 is the first doping type, for example, a polysilicon layer with a high concentration of N-type doping, so that the resistance of the polysilicon is reduced to 5-20 ohms / square.
[0079] The body region 107 extends downward from the first surface of the semiconductor layer 109 and is located between the first trench 101 and the second trench 100 . The source region 108 is located in the body region 107 and has a first doping type, such as N-type doping.
[0080] The covering dielectric layer 106 may be at least one of undoped silicon glass (USG) and boronphosphorus-doped silicon glass (BPSG), and the thickness of the covering dielectric layer 106 is, for example, 2000 angstroms to 12000 angstroms. The materials of the first contact 113, the second contact 114, the third contact 115, the source electrode 121, the gate electrode 122, and the drain electrode 123 may be titanium, titanium nitride, tungsten, aluminum silicon, or aluminum copper.
[0081] The control gate dielectric layers 104 a , 104 b and the shield gate dielectric layer 105 may be made of any one of silicon dioxide, silicon nitride or a combination thereof, and the materials thereof may be the same or different.
[0082] The shielding gate in the power semiconductor device of the first embodiment is directly electrically connected to the source electrode through the first contact, thereby avoiding the problem of uneven turn-on in high-speed switching applications and improving reliability. At the same time, the length of the rectangular sheet-shaped shielding gate is reduced, so that the parasitic resistance of the shielding gate is effectively reduced, thereby reducing the delay caused by the parasitic resistance.
[0083] Furthermore, the ratio of the width to the length of the first trench is 1:1.2 to 1:2, and the length of the first trench is increased, which can avoid the situation where the photoresist attachment area of the first contact hole is small, and reduce the difficulty of process processing. And when the power semiconductor device is used in medium and high voltage, it can also avoid the problems of difficult shielding grid filling and easy voids caused by the increase in the depth of the first trench, thereby improving the reliability and consistency of the power semiconductor device. At the same time, the possibility of the breakdown stability problem caused by the incomplete depletion of the semiconductor layer below the second trench is also greatly reduced.
[0084] Furthermore, the first grooves are arranged in a straight line in the first direction and in a straight line in the second direction, thereby improving the consistency of the power semiconductor device.
[0085] Furthermore, the second grooves are arranged orthogonally, and in addition to having the same longitudinal conductive channels as in the prior art, transverse conductive channels are formed between adjacent first grooves, thereby increasing the area of the mesa overcurrent and effectively increasing the channel density.
[0086] Furthermore, the top view of the first groove is a rounded rectangle, and the radius of the rounded corner is greater than or equal to one quarter of the width of the first groove and less than or equal to one half of the width of the first groove, which can avoid overcurrent failure caused by local electron accumulation when the power semiconductor device is turned on.
[0087] Figure 8An enlarged schematic diagram showing a partial layout of a power semiconductor device provided according to a second embodiment of the present disclosure.
[0088] like Figure 8 As shown, a partial layout in the cell area of the power semiconductor device provided by the second embodiment is shown. In the second embodiment, the cell area of the power semiconductor device includes a plurality of rectangular sheet-shaped first grooves 101 and a plurality of strip-shaped second grooves 100. The plurality of second grooves 100 are arranged along the first direction and the second direction and are interconnected. Different from the first embodiment, the plurality of second grooves 100 are arranged at intervals along the first direction, and two adjacent rows of second grooves 100 in the second direction are staggered. Each first groove 101 is located in a rectangular area surrounded by the second grooves 100, and the plurality of first grooves 101 are arranged in a diamond array. Exemplarily, Figure 8 21 second grooves 100 extending along the first direction (X direction) and 5 second grooves 100 extending along the second direction (Y direction) are shown, as well as a plurality of first grooves 101 arranged in a rhombus array. The second grooves 100 are interconnected and separate into a plurality of rectangular areas, and each first groove 101 is located in a rectangular area.
[0089] That is, the second embodiment is different from the first embodiment only in the arrangement of the first grooves 101 and the second grooves 100. The rest can be implemented according to the implementation of the first embodiment and have the same technical effects as the first embodiment.
[0090] Figure 9a to Figure 9h Schematic cross-sectional views of power semiconductor devices provided by the first and second embodiments of the present disclosure at different stages in the manufacturing process are shown.
[0091] pass Figure 9a to Figure 9h The power semiconductor devices in the first embodiment and the second embodiment are prepared. It should be noted that the manufacturing steps of the power semiconductor device described below in the present disclosure are only illustrative and not limited thereto.
[0092] like Figure 9a As shown, a semiconductor layer 109 is formed on a substrate 110 , and a plurality of first trenches 101 are formed in the semiconductor layer 109 .
[0093] Exemplarily, the substrate 110 has a first surface and a second surface opposite to each other. A semiconductor layer 109 is formed on the first surface of the substrate 110. The substrate 110 may be a silicon substrate, whose doping type is a first doping type, such as N-type doping, and the silicon substrate is uniformly doped in the longitudinal direction, for example. The semiconductor layer 109 may be an epitaxial layer formed on the substrate 110, and both have the same doping type. The semiconductor layer 109 has a first surface and a second surface opposite to each other.
[0094] Specifically, a hard mask is deposited on the first surface of the semiconductor layer 109. The hard mask can be silicon dioxide or silicon nitride or a combination of the two. Then, a plurality of first grooves 101 are formed by etching downward from the first surface of the semiconductor layer 109 using a process such as plasma etching. The depth of the first groove 101 is 5 μm to 20 μm, and the width of the first groove 101 is 1.1 μm to 4.5 μm. In a preferred embodiment, the width of the first groove 101 is 1.1 μm to 3.6 μm. The spacing d1 between two adjacent first grooves 101 is 1 μm to 6 μm.
[0095] Furthermore, the top view shape of the first groove 101 is a rectangle, and the ratio of the width a to the length b of the first groove 101 is 1:1.2 to 1:2. In a preferred embodiment, the ratio of the width a to the length b of the first groove 101 is 1:1.5.
[0096] In an alternative embodiment, the rectangular shape of the top view of the first groove 101 includes at least one rounded corner. The radius R of the rounded corner is greater than or equal to one quarter of the width a of the first groove 101, and less than or equal to one half of the width a of the first groove 101. Exemplarily, the top view shape of the first groove 101 is a rounded rectangle, and the radius size of each rounded corner is, for example, the same. Further, the ratio of the width a to the length b of the first groove 101 is 1:1.2 to 1:2. In a preferred embodiment, the ratio of the width a to the length b of the first groove 101 is 1:1.5.
[0097] In other embodiments, for example, a sacrificial oxide layer may be grown in the first trench 101 to repair the lattice damage caused during the etching process, and then the sacrificial oxide layer may be removed by wet etching. Further, the temperature for growing the sacrificial oxide layer is 900° C. to 1000° C., and the thickness of the sacrificial oxide layer is 200 angstroms to 2000 angstroms.
[0098] like Figure 9b As shown, a shielding gate dielectric layer 105 and a shielding gate 103 are formed in the plurality of first trenches 101 , the shielding gate dielectric layer 105 covers the sidewalls and the bottom of the first trenches 101 , the shielding gate 103 fills the first trenches 101 , and the shielding gate dielectric layer 105 isolates the shielding gate 103 from the semiconductor layer 109 .
[0099] Exemplarily, a shielding gate dielectric layer 105 is formed by growing an oxide layer on the sidewall and bottom of the first trench 101 and the first surface of the semiconductor 109 by thermal oxidation. The thickness of the shielding gate dielectric layer 105 is 3800 angstroms to 20000 angstroms. The temperature of thermal oxidation to form the shielding gate dielectric layer 105 is 900° C. to 1150° C. Then, polysilicon is deposited on the surface of the shielding gate dielectric layer 105 and in the first trench 101, and then the polysilicon is etched to remove the polysilicon on the semiconductor layer 109, and the polysilicon in the first trench 101 is retained to form the shielding gate 103. The distance between the shielding gate 103 and the first surface of the semiconductor layer 109 is 0 μm to 1.5 μm. Then, the oxide layer on the first surface of the semiconductor layer 109 is removed or an oxide layer with a thickness of 200 angstroms to 500 angstroms is retained on the first surface of the semiconductor layer 109.
[0100] Furthermore, in order to reduce the parasitic resistance of the polysilicon used as the shield gate 103, the polysilicon is generally doped with a high concentration of N-type to reduce the resistance of the polysilicon to 5-20 ohms / square.
[0101] Furthermore, the shield gate dielectric layer 105 can also be directly deposited by LPCVD (Low Pressure Chemical Vapor Deposition) or SACVD (Sub-atmospheric Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition); or a portion of the thickness can be thermally oxidized, and then the remaining thickness is deposited by LPCVD or SACVD or PECVD. Subsequently, the deposited oxide layer is densified by high temperature of 900°C to 1150°C.
[0102] like Fig.9c As shown, a plurality of second trenches 100 are formed in the semiconductor layer 109 .
[0103] Exemplarily, a hard mask is deposited on the first surface of the semiconductor layer 109. The hard mask may be silicon dioxide or silicon nitride or a combination of the two. Then, a plasma etching process is used to etch downward from the first surface of the semiconductor layer 109 to form a plurality of second trenches 100. The depth of the second trenches 100 is 0.8 μm to 2.5 μm, and the width of the second trenches 100 is 0.2 μm to 5 μm.
[0104] Furthermore, the spacing d2 between the first trench 101 and the adjacent second trench 100 is 0.35 μm to 0.9 μm, the spacing d3 between two adjacent second trenches 100 extending along the second direction is 3 μm to 5.5 μm, and the spacing d4 between two adjacent second trenches 100 extending along the first direction is 3 μm to 11 μm.
[0105] In other embodiments, for example, a sacrificial oxide layer may be grown in the second trench 100 to repair the lattice damage caused during the etching process, and then the sacrificial oxide layer may be removed by wet etching. Further, the temperature for growing the sacrificial oxide layer is 900° C. to 1000° C., and the thickness of the sacrificial oxide layer is 200 angstroms to 1000 angstroms.
[0106] like Figure 9d As shown, a control gate dielectric layer and a control gate 102 are formed in the plurality of second trenches 100 , the control gate dielectric layer covers the sidewalls and bottom of the second trenches 100 , the control gate 102 fills the second trenches 100 , and the control gate dielectric layer isolates the control gate 102 from the semiconductor layer 109 .
[0107] Exemplarily, a control gate dielectric layer is formed by growing an oxide layer on the sidewall and bottom of the second trench 100 and the first surface of the semiconductor 109 by thermal oxidation. The thickness of the control gate dielectric layer 104b located on the sidewall of the second trench 101 and the control gate dielectric layer 104a located at the bottom of the second trench 101 are equal, which is 600 angstroms to 3000 angstroms. The temperature of thermal oxidation to form the control gate dielectric layer is 900°C to 1000°C. Further, the control gate dielectric layer can also be directly deposited by LPCVD (Low Pressure Chemical Vapor Deposition) or SACVD (Sub-atmospheric Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition); or a portion of the thickness can be thermally oxidized, and then the remaining thickness is deposited by LPCVD or SACVD or PECVD. The deposited oxide layer is then densified by heating it at a high temperature of 900°C to 1000°C.
[0108] In other embodiments, before growing an oxide layer of substantially equal thickness on the sidewall and bottom of the second trench 100, an oxide layer is first deposited by thermal oxidation, HDP, LPCVD, SACVD or PECVD or a combination thereof, and then the etching time is controlled to form a control gate dielectric layer 104a at the bottom of the second trench 100. At this time, the thickness of the control gate dielectric layer 104a at the bottom of the second trench 100 is greater than the thickness of the gate dielectric layer 104b at the sidewall of the second trench 100. This structure can reduce the capacitance between the gate and the drain, reduce the loss during the switching process, and improve the ability of the bottom of the second trench 100 to withstand high electric fields.
[0109] Then, polysilicon is deposited on the surface of the control gate dielectric layer located on the first surface of the semiconductor layer 109 and in the second trench 100, and then the polysilicon is etched to remove the polysilicon on the semiconductor layer 109, and the polysilicon in the second trench 100 is retained to form a control gate 102. The distance between the control gate 102 and the first surface of the semiconductor layer 109 is 0 μm to 0.2 μm. Then, the oxide layer on the first surface of the semiconductor layer 109 is removed or an oxide layer with a thickness of 100 angstroms to 300 angstroms is retained on the first surface of the semiconductor layer 109.
[0110] Furthermore, in order to reduce the parasitic resistance of the polysilicon used as the control gate 102, the polysilicon is generally doped with a high concentration of N-type to reduce the resistance of the polysilicon to 5-20 ohms / square.
[0111] In other embodiments, a plurality of second trenches 100 may be first formed in the semiconductor layer 109 , and then a control gate dielectric layer and a control gate 102 may be formed in the plurality of second trenches 100 . Subsequently, a plurality of first trenches 101 may be formed in the semiconductor layer 109 , and a shielding gate dielectric layer 105 and a shielding gate 103 may be formed in the plurality of first trenches 101 .
[0112] like Fig.9e As shown, a body region 107 is formed in the semiconductor layer 109 , and a source region 108 is formed in the body region 107 . The body region 107 extends inward from the first surface of the semiconductor layer 109 and is located in the semiconductor layer 109 between the first trench 101 and the second trench 100 .
[0113] Exemplarily, a photoresist is deposited, a photolithography area of the body region is exposed, and a second doping type is performed downward from the first surface of the semiconductor layer 109, for example, ions of a P-type doping type are implanted, and an annealing and pushing-pushing process is performed to form a body region 107 having a second doping type. Furthermore, the annealing and pushing-pushing process after the implantation of the body region 107 can be an annealing at 950° C. to 1150° C. or a rapid thermal annealing (RTA) at 900° C. to 1150° C.
[0114] Then, the photolithography area of the source region is exposed, and the first doping type is performed in the body region 107, such as implanting N-type doping type ions, and annealing is performed to form a highly doped source region 108 with the first doping type.
[0115] In other embodiments, the body region 107 may also be formed by general implantation (ie, implantation is performed on the entire semiconductor layer 109 ).
[0116] In an alternative embodiment, the first doping type is P-type doping and the second doping type is N-type doping.
[0117] like Figure 9f As shown, a covering dielectric layer 106 covering the source region 108 , the first trench 101 and the second trench 100 is formed on the first surface of the semiconductor layer 109 .
[0118] Exemplarily, a capping dielectric layer 106 is deposited on the first surface of the semiconductor layer 109. The capping dielectric layer 106 may be a combination of NSG (non-doped silica glass) and BPSG (boron phospho-silicate glass), and the thickness of the capping dielectric layer 106 is 2000-12000 angstroms.
[0119] In other embodiments, if the electrodes of the power semiconductor device are led out using multiple layers of metal, in this step, after depositing a covering dielectric layer and etching, a first metal layer is deposited and etched, and then a second covering dielectric layer is deposited.
[0120] like Figure 9g As shown, a first contact hole 113a penetrating through the covering dielectric layer 106 and reaching the surface of the shielding gate 103, and a second contact hole 114a penetrating through the covering dielectric layer 106 and reaching a portion of the source region 108 and the surface of the shielding gate dielectric layer 105 are formed. Figure 9h As shown, a third contact hole 115 a is formed which penetrates the covering dielectric layer 106 and reaches the surface of the control gate 102 .
[0121] Exemplarily, a photoresist is deposited, the contact hole region is exposed, and the covering dielectric layer 106 is etched by wet or dry etching to form a first contact hole 113a, a second contact hole 114a, and a third contact hole 115a. The first contact hole 113a reaches the surface of the shield gate 103, the second contact hole 114a reaches at least a portion of the surface of the source region 108, and the third contact hole 115a reaches the surface of the control gate 102.
[0122] Furthermore, for example, a high concentration of P-type dopants is injected through the second contact hole 114 a , and a contact region of the body region 107 is formed in the body region 107 after rapid thermal annealing at 900° C. to 1100° C. (not shown in the figure).
[0123] In other embodiments, if the electrodes of the power semiconductor device are led out using multiple layers of metal, the contact holes of the first dielectric layer and the contact holes of the second dielectric layer can be made in the same step, thereby reducing the number of process steps and the number of versions.
[0124] like Figure 6a As shown, the first contact hole 113a is filled with the first contact 113, the second contact hole 114a is filled with the second contact 114, and as shown in FIG. Figure 6b As shown, the third contact 115 is filled in the third contact hole 115a, and a source electrode 121 connected to the first contact 113 and the second contact 114 is formed on the surface of the covering dielectric layer 106, and a gate electrode 122 connected to the third contact 115 is formed, and a drain electrode 123 is formed on the second surface of the substrate 110. It should be noted that the gate electrode 122 located on the surface of the covering dielectric layer 106 is not in contact with the source electrode 121.
[0125] Illustratively, titanium, titanium nitride and tungsten are deposited in the first contact hole 113a, the second contact hole 114a and the third contact hole 115a to form tungsten plugs as the first contact 113, the second contact 114 and the third contact 115, metal is deposited, and finally etching is performed to form the gate electrode 122 and the source electrode 121.
[0126] Furthermore, the gate electrode 122 may be led out through a contact hole formed in the covering dielectric layer 106 , or may be led out through the first metal layer covering the control gate 102 at both ends of the second trench 100 .
[0127] The embodiments of the present invention are described above, and these embodiments do not describe all the details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A power semiconductor device, characterized in that: include: a substrate comprising opposing first and second surfaces; a semiconductor layer located on the first surface of the substrate; a plurality of first trenches in the semiconductor layer; A shielding gate dielectric layer and a shielding gate located in the plurality of first trenches, wherein the shielding gate dielectric layer covers the sidewalls and the bottom of the first trenches, and the shielding gate dielectric layer isolates the shielding gate from the semiconductor layer; a plurality of second trenches in the semiconductor layer; A control gate dielectric layer and a control gate located in the plurality of second trenches, wherein the control gate dielectric layer covers the sidewalls and the bottom of the second trenches, and the control gate dielectric layer isolates the control gate from the semiconductor layer; a body region in the semiconductor layer, the body region being adjacent to upper portions of the plurality of first trenches and the plurality of second trenches; a source region located in the body region; a source electrode electrically connected to the source region and the shielding gate; a drain electrode located on the second surface of the substrate; as well as a gate electrode electrically connected to the control gate, Among them, the multiple second grooves extend along the first direction and the second direction and are interconnected, the first direction and the second direction are perpendicular, each of the first grooves is located in the area surrounded by the second grooves, the top view of the first groove is a rectangle, and the ratio of the width to the length of the first groove is 1:1.2 to 1:
2.
2. The power semiconductor device according to claim 1, characterized in that: The ratio of the width to the length of the first groove is 1:1.
5.
3. The power semiconductor device according to claim 1 or 2, characterized in that: The plurality of first grooves are arranged in a matrix array or a diamond array.
4. The power semiconductor device according to claim 1 or 2, characterized in that: The plurality of second grooves include a first portion of second grooves extending along the first direction and arranged in parallel along the second direction and a second portion of second grooves extending along the second direction and arranged in parallel along the first direction, and the first portion of second grooves and the second portion of second grooves are arranged orthogonally.
5. The power semiconductor device according to claim 1 or 2, characterized in that: The plurality of second grooves include a first portion of second grooves extending along the first direction and a second portion of second grooves extending along the second direction. The first portion of second grooves are arranged at intervals along the first direction, and the first portion of second grooves in two adjacent rows in the second direction are staggered.
6. The power semiconductor device according to claim 1 or 2, characterized in that: The rectangle of the top view of the first groove includes at least one rounded corner, and the radius of the rounded corner is greater than or equal to one quarter of the width of the first groove and less than or equal to one half of the width of the first groove.
7. The power semiconductor device according to claim 1 or 2, characterized in that: The width of the first groove is 1.1 μm to 4.5 μm, the depth of the first groove is 5 μm to 20 μm, and the interval between two adjacent first grooves is 1 μm to 6 μm.
8. The power semiconductor device according to claim 7, characterized in that: The width of the first groove is 1.1 μm to 3.6 μm.
9. The power semiconductor device according to claim 1 or 2, characterized in that: The thickness of the shielding gate dielectric layer is 3800-20000 angstroms, and the distance between the shielding gate and the first surface of the semiconductor layer is 0 μm-1.5 μm.
10. The power semiconductor device according to claim 1 or 2, characterized in that: The distance between the first groove and the adjacent second groove is 0.35 μm to 0.9 μm.
11. The power semiconductor device according to claim 1 or 2, characterized in that: The width of the second groove is 0.2 μm to 5 μm, the depth of the second groove is 0.8 μm to 2.5 μm, the spacing between two adjacent second grooves extending along the second direction is 3 μm to 5.5 μm, and the spacing between two adjacent second grooves extending along the first direction is 3 μm to 11 μm.
12. The power semiconductor device according to claim 1 or 2, characterized in that: The thickness of the control gate dielectric layer located at the bottom of the second trench is greater than or equal to the thickness of the control gate dielectric layer located at the sidewall of the second trench.
13. The power semiconductor device according to claim 1 or 2, characterized in that: The thickness of the control gate dielectric layer is 600 angstroms to 3000 angstroms, and the distance between the control gate and the first surface of the semiconductor layer is 0 μm to 0.2 μm.
14. The power semiconductor device according to claim 1 or 2, characterized in that: Also includes: a first contact contacting the shield gate in the plurality of first trenches; a second contact, contacting the source region between the first trench and the second trench, and electrically connected to the first contact to lead out the source electrode; The third contact contacts the control gates in the plurality of second trenches to lead out the gate electrode.
15. The power semiconductor device according to claim 14, characterized in that: Also includes: a covering dielectric layer, located on the first surface of the semiconductor layer and covering the source region, the first trench and the second trench, wherein the covering dielectric layer includes a first contact hole, a second contact hole and a third contact hole, The first contact hole penetrates the covering dielectric layer and reaches the surface of the shielding gate, and the first contact hole is filled with the first contact. The second contact hole penetrates the covering dielectric layer and reaches at least a portion of the surface of the source region, and the second contact hole is filled with the second contact. The third contact hole penetrates the covering dielectric layer and reaches the surface of the control gate, and the third contact hole is filled with the third contact. The source electrode is located on the surface of the covering dielectric layer and is connected to the first contact and the second contact; The gate electrode is located on the surface of the covering dielectric layer and is connected to the third contact.