Nationwide two-way server mainboard based on Feiteng S5000C-64

Abstract

The utility model discloses a nationwide two-way server mainboard based on Feiteng S5000C-64. The nationwide two-way server mainboard comprises a master processor, a slave processor, a system disk, a network controller, a CPLD and a Feiteng BMC monitoring module, wherein the master processor is connected with a first slot, a second slot, a third slot, a fourth slot, an MCIO 7 slot and an MCIO 8 slot on the mainboard; the slave processor is connected with a fifth slot on the main board and MCIO slots 1 to MCIO slots 6; the master processor and the slave processor are connected with each other through a C2C channel; the system disk and the network controller are connected with the main processor; the CPLD is connected with the master processor and the slave processor; and the Feiteng BMC monitoring module is connected with the CPLD and the main processor. Processor firmware, BMC firmware, an operating system and the like used by the system are all domestic, autonomous and controllable, the rates of a memory channel and a PCIE channel of the system are greatly improved, and more PCIE resources can be used for IO expansion.

Description

Technical Field

[0001] The utility model relates to the technical field of domestic motherboard equipment, in particular to a domestic dual-channel server motherboard based on Feiteng S5000C-64. Background Art

[0002] The server provides computing or application services for other clients (such as office desktop computers, notebooks, ATM terminals and even large equipment such as train systems) in the network. The server has high-speed CPU computing power, long-term reliable operation, strong I / O external data throughput and better scalability.

[0003] The previous generation of Feiteng S2500 dual-core server has 8-channel DDR4 memory (maximum rate of 3200Mbps), 17 PCIE links 3.0 (maximum rate of 8Gbps), and 4 interconnection channels between Feiteng S2500, each channel has 4 links (maximum rate of 25Gbps). Therefore, the memory and PCIE data transmission bandwidth of Feiteng S2500 is limited, and the number of PCIE links cannot meet the growing demand. Feiteng S2500 is the previous generation of Feiteng dual-core server architecture, which can no longer keep up with the performance requirements of the current mainstream dual-core servers. Utility Model Content

[0004] The utility model provides a domestically produced dual-channel server motherboard based on Feiteng S5000C-64 to solve the technical problems mentioned in the background technology.

[0005] In order to achieve the above object, the technical solution of the utility model is implemented as follows:

[0006] The utility model provides a domestically produced dual-channel server motherboard based on Feiteng S5000C-64, comprising:

[0007] A main processor is electrically connected to the first to fourth slots and the MCIO 7 slot and the MCIO 8 slot on the mainboard;

[0008] The slave processor is electrically connected to the fifth slot and the MCIO 1 slot to the MCIO 6 slot on the mainboard; the master processor and the slave processor are interconnected via four C2C channels;

[0009] System disk, interconnected with the main processor, used to install and run the domestic operating system and store data;

[0010] A network controller, interconnected with the main processor, for external business network transmission;

[0011] CPLD, interconnected with the master processor and slave processor, used for power-on timing and reset control;

[0012] Feiteng BMC monitoring module is interconnected with CPLD and main processor.

[0013] Furthermore, the mainboard also includes an IO interface expansion bridge chip, and the IO interface expansion bridge chip is interconnected with the main processor through a PCIE interface.

[0014] Furthermore, the IO interface expansion bridge chip uses Feiteng X100, which integrates six USB3.0 interfaces and four SATA3.0 interfaces.

[0015] Furthermore, the Feiteng BMC monitoring module is integrated with a DDR4-SODIMM slot and is interconnected with the CPLD via an SPI interface, a UART interface, and a GPIO interface;

[0016] The Feiteng BMC monitoring module is interconnected with the main processor through the PCIE interface and connected to the main processor through the LPC interface to achieve level conversion;

[0017] The Feiteng BMC monitoring module is interconnected with the network controller through the NCSI interface;

[0018] The Feiteng BMC monitoring module is interconnected with the Feiteng X100 through a USB interface.

[0019] Furthermore, the Feiteng BMC monitoring module is connected to the domestic PHY chip via the RGMII interface, and the domestic PHY chip is connected to the Gigabit management electrical port via the RJ45 interface for remote monitoring and management;

[0020] The Feiteng BMC monitoring module is integrated with a VGA interface for connecting a VGA monitor.

[0021] Furthermore, the system disk is a solid state disk and is interconnected with the main processor via a PCIE interface.

[0022] Furthermore, the network controller adopts the Netcom WX1860AL2 controller and is interconnected with the main processor through a PCIE interface. The Netcom WX1860AL2 controller is integrated with two Gigabit electrical ports for external business network transmission.

[0023] Further, the CPLD is selected from Anlu CPLD, which is interconnected with the slave processor through LPC interface, SPI interface, UART interface, and GPIO interface, and is interconnected with the master processor through SPI interface, UART interface, and GPIO interface for data exchange;

[0024] Anlu CPLD is interconnected with Feiteng BMC monitoring module through SPI interface, UART interface and GPIO interface for data exchange.

[0025] Furthermore, the first to fifth slots are respectively a PCIE5.0X16 slot, two PCIE5.0X8 slots, a PCIE5.0X4 slot and a PCIE5.0X16 slot.

[0026] Furthermore, the master processor and the slave processor are each electrically connected to eight DDR5 RDIMM slots on the motherboard.

[0027] Beneficial effects of the utility model:

[0028] The utility model protects a domestically produced dual-channel server motherboard based on Feiteng S5000C-64. The processor firmware, Feiteng BMC monitoring module and other firmware and operating system used are all domestically produced and independently controllable, and are suitable for application fields such as safe and reliable data security.

[0029] The domestically produced dual-core server motherboard based on Feiteng S5000C-64 provides a wealth of expansion interfaces and high-performance computing and storage capabilities, and the hardware is all domestically produced and controllable. At the same time, compared with the previous generation Feiteng S2500 dual-core server platform, its memory channel and PCIE channel rates have been greatly improved, and there are more PCIE resources available for IO expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is the overall framework diagram of the utility model. DETAILED DESCRIPTION

[0031] In order to facilitate the understanding of the present invention, the present invention will be described more comprehensively with reference to the relevant drawings. The drawings provide preferred embodiments of the present invention. However, the present invention can be implemented in many other different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0032] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0033] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0034] Reference Figure 1 The embodiment of the present application provides a domestically produced dual-core server motherboard based on Feiteng S5000C-64, including:

[0035] A main processor is electrically connected to the first to fourth slots and the MCIO 7 slot and the MCIO 8 slot on the mainboard;

[0036] The slave processor is electrically connected to the fifth slot on the motherboard and the MCIO 1 slot to the MCIO 6 slot. The master processor and the slave processor are interconnected through four C2C high-speed channels (each channel is a PCIE5.0X8 link). The MCIO slot (including the MCIO 1 slot to the MCIO 8 slot) can be connected to the backplane to connect the NVMe solid-state drive. The processors (including the master processor and the slave processor) on the Feiteng S5000C-64 support native NVMe solid-state drive hot-swap.

[0037] System disk, interconnected with the main processor, used to install and run the domestic operating system and store data;

[0038] A network controller, interconnected with the main processor, for external business network transmission;

[0039] CPLD, interconnected with the master processor and slave processor, used for power-on timing and reset control;

[0040] Feiteng BMC monitoring module is interconnected with the dual-core server and main processor.

[0041] In some embodiments, the mainboard further includes an IO interface expansion bridge chip, and the IO interface expansion bridge chip is interconnected with the main processor via a PCIE interface.

[0042] In some embodiments, the IO interface expansion bridge chip uses Feiteng X100, which integrates six USB3.0 interfaces (four rear and two front) and four SATA3.0 interfaces.

[0043] In some embodiments, the Feiteng BMC monitoring module is integrated with a DDR4-SODIMM slot and is interconnected with a dual-channel server through low-speed interfaces such as an SPI interface, a UART interface, and a GPIO interface;

[0044] The Feiteng BMC monitoring module is interconnected with the main processor through the PCIE interface and connected to the main processor through the LPC interface to achieve level conversion;

[0045] The Feiteng BMC monitoring module is interconnected with the network controller through the NCSI interface;

[0046] The Feiteng BMC monitoring module is interconnected with the Feiteng X100 through a USB interface.

[0047] In some embodiments, the Feiteng BMC monitoring module is connected to the domestic PHY chip via the RGMII interface, and the domestic PHY chip is connected to the Gigabit management electrical port via the RJ45 interface for remote monitoring and management;

[0048] The Feiteng BMC monitoring module is integrated with a VGA interface for connecting a VGA monitor.

[0049] In addition, the Feiteng BMC monitoring module also performs monitoring and management functions such as voltage detection, temperature detection, fan speed control, timing control through the I2C interface and remote update of Feiteng firmware through the SPI interface.

[0050] In some embodiments, the system disk is a solid state disk, and is interconnected with the main processor via a PCIE interface. Preferably, the system disk is an M.2 solid state disk of Lugu Technology.

[0051] In some embodiments, the network controller uses the Netcom WX1860AL2 controller and is interconnected with the main processor via a PCIE interface. The Netcom WX1860AL2 controller is integrated with two Gigabit electrical ports for external business network transmission.

[0052] In some embodiments, the dual-channel server uses Anlu CPLD, and is interconnected with the slave processor through low-speed interfaces such as LPC interface, SPI interface, UART interface, GPIO interface, etc., and is interconnected with the master processor through low-speed interfaces such as SPI interface, UART interface, GPIO interface, etc., for data exchange;

[0053] Anlu CPLD is interconnected with Feiteng BMC monitoring module through low-speed interfaces such as SPI interface, UART interface, GPIO interface, etc. for data exchange.

[0054] In addition, Anlu CPLD is also responsible for functions such as signal level conversion, front panel LED indicator control and signal switching.

[0055] In some embodiments, the main processor is connected to an analog switch via a QSPI interface, and the analog switch is connected to the Feiteng firmware.

[0056] In some embodiments, the main processor and the Feiteng BMC monitoring module are connected to another analog switch through the II2C interface and the IIC interface respectively, and the analog switch is electrically connected to the real-time clock Xingweifan SD3068 through the II2C interface.

[0057] In some embodiments, the first to fifth slots are respectively a PCIE5.0X16 slot, two PCIE5.0X8 slots, a PCIE5.0X4 slot and a PCIE5.0X16 slot.

[0058] In some embodiments, the master processor and the slave processor are each electrically connected to eight DDR5 RDIMM slots on the motherboard; compatible with standard DDR5 UDIMM and RDIMM memory modules, and the memory rate can reach 4000Mbps.

[0059] The utility model protects a domestically produced dual-channel server motherboard based on Feiteng S5000C-64. The processor firmware, Feiteng BMC monitoring module and other firmware and operating system used are all domestically produced and independently controllable, and are suitable for application fields such as safe and reliable data security.

[0060] The domestically produced dual-core server motherboard based on Feiteng S5000C-64 provides a wealth of expansion interfaces and high-performance computing and storage capabilities, and the hardware is all domestically produced and controllable. At the same time, compared with the previous generation Feiteng S2500 dual-core server platform, its memory channel and PCIE channel rates have been greatly improved, and there are more PCIE resources available for IO expansion.

[0061] In addition, the new generation Feiteng S5000C-64 processor (including the main processor and the slave processor) adopted by the present invention has a memory channel that supports DDR5 memory modules. The speed of the memory module can reach 4000Mbps, which is significantly improved compared with the speed of the previous generation DDR4 memory module (3200Mbps); the new generation Feiteng S5000C-64 processor has 64 PCIE5.0 links, which is significantly improved compared with the 17 links of the previous generation PCIE3.0; the new generation PCIE5.0 speed can reach 32Gbps, which is significantly improved compared with the 8Gbps of the previous generation PCIE3.0; the new generation Feiteng S5000C-64 processors are interconnected by four C2C high-speed channels (each channel is a PCIE5.0X8 link), and the total data bandwidth is 32Gbps*8*4=1024Gbps, which is significantly improved compared with the total data bandwidth (25Gbps*4*4=400Gbps) of the previous generation of four channel interconnections (each channel is 25Gbps*4 links).

[0062] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited to this. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. In addition, the technical solutions between the various implementations of the utility model can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope of the utility model. Therefore, the protection scope of the utility model shall be based on the protection scope of the claims.

Claims

1. A domestically produced dual-core server motherboard based on Feiteng S5000C-64, characterized in that: include: A main processor is electrically connected to the first to fourth slots and the MCIO 7 slot and the MCIO 8 slot on the mainboard; The slave processor is electrically connected to the fifth slot and the MCIO 1 slot to the MCIO 6 slot on the mainboard; the master processor and the slave processor are interconnected via four C2C channels; System disk, interconnected with the main processor, used to install and run the domestic operating system and store data; A network controller, interconnected with the main processor, for external business network transmission; CPLD, interconnected with the master processor and slave processor; Feiteng BMC monitoring module is interconnected with CPLD and main processor.

2. The domestically produced dual-core server motherboard according to claim 1, characterized in that: It also includes an IO interface expansion bridge chip, which is interconnected with the main processor through a PCIE interface.

3. The domestically produced dual-core server motherboard according to claim 2, characterized in that: The IO interface expansion bridge chip uses Feiteng X100, which integrates six USB3.0 interfaces and four SATA3.0 interfaces.

4. The domestically produced dual-core server motherboard according to claim 2, characterized in that: The Feiteng BMC monitoring module is integrated with a DDR4-SODIMM slot and is interconnected with the CPLD through an SPI interface, a UART interface, and a GPIO interface; The Feiteng BMC monitoring module is interconnected with the main processor through the PCIE interface and connected to the main processor through the LPC interface to achieve level conversion; The Feiteng BMC monitoring module is interconnected with the network controller through the NCSI interface; The Feiteng BMC monitoring module is interconnected with the Feiteng X100 through a USB interface.

5. The domestically produced dual-socket server motherboard according to claim 1, characterized in that: The Feiteng BMC monitoring module is connected to the domestic PHY chip through the RGMII interface, and the domestic PHY chip is connected to the Gigabit management electrical port through the RJ45 interface for remote monitoring and management; The Feiteng BMC monitoring module is integrated with a VGA interface for connecting a VGA monitor.

6. The domestically produced dual-core server motherboard according to claim 1, characterized in that: The system disk adopts a solid state disk and is interconnected with the main processor through a PCIE interface.

7. The domestically produced dual-core server motherboard according to claim 1, characterized in that: The network controller adopts the Netcom WX1860AL2 controller and is interconnected with the main processor through a PCIE interface. The Netcom WX1860AL2 controller is integrated with two Gigabit electrical ports for external business network transmission.

8. The domestically produced dual-core server motherboard according to claim 1, characterized in that: Described CPLD is selected from Anlu CPLD, is interconnected with the slave processor through LPC interface, SPI interface, UART interface, GPIO interface, and is interconnected with the main processor through SPI interface, UART interface, GPIO interface, for data exchange; Anlu CPLD is interconnected with Feiteng BMC monitoring module through SPI interface, UART interface and GPIO interface for data exchange.

9. The domestically produced dual-core server motherboard according to claim 1, characterized in that: The first to fifth slots are respectively a PCIE5.0X16 slot, two PCIE5.0X8 slots, a PCIE5.0X4 slot and a PCIE5.0X16 slot.

10. The domestically produced dual-socket server motherboard according to any one of claims 1 to 9, characterized in that: The master processor and the slave processor are each electrically connected to eight DDR5 RDIMM slots on the motherboard.

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