Power device MOS stacked package Bumpless lead bonding structure
By setting wiring holes in the chip package and connecting the solder wires into it, the problem of bump limiting chip miniaturization in traditional packaging is solved, and a smaller package size and higher integration is achieved.
Patent Information
- Application Number
- CN202421145112.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-23
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-05-23
AI Technical Summary
In traditional chip packages, the bumps are located outside the chip, limiting the miniaturization of the chip and increasing the physical size of the package, especially in multi-layer packages.
By providing wiring holes on the stacked chip, the bonding wire is connected to the wiring holes, so that the bonding points of the bonding wire are located in the chip, thereby reducing the interference of the bumps to the gap between the chips and reducing the volume of the entire chip package.
It realizes the reduction of the package volume, improves the integration and functional density of the chip, and solves the problem of bump restricting chip miniaturization in traditional packaging.
Smart Images
Figure CN222690682U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip packaging, and in particular to a bumpless wire bonding structure of a power device MOS stacking package. Background Art
[0002] "Bumpless technology" is a technology in the field of microelectronics manufacturing that aims to solve the bump problem in traditional welding methods. In the chip packaging process, the traditional method is to connect the chip to the substrate through welding bumps (such as solder balls). This method has been used for many years, but as the chip size decreases and the performance requirements increase, the shortcomings of this method have gradually emerged. With the development of semiconductor technology, traditional bump technology faces some limitations, and these devices require highly integrated and compact packaging. In the packaging process, wire bonds are used to connect the pads on the chip to the pads on the substrate or the packaging substrate. Traditional bumps increase the distance between the chip and the substrate, which means that the wire bonds need to be longer to cross this distance, thereby increasing the volume of the wire bonds, and because a certain spacing needs to be maintained between the bumps, this also affects the wiring density of the wire bonds. Sufficient space is required between the wire bonds to prevent electrical short circuits and signal interference, which limits the density of the wire bonds and the flexibility of the wiring design. The height and diameter of each welding ball (bump) will increase the distance between the chip and the substrate. This will directly increase the overall thickness of the package, especially in multi-layer packages (such as 3D ICs), this effect is more significant. Therefore, the presence of traditional bumps increases the physical size of the package, which is not conducive to achieving a smaller and thinner package design. This is particularly important in modern electronic devices (such as smartphones and wearable devices).
[0003] To this end, it is necessary to propose a power device MOS stacked package Bumpless wire bonding structure that partially embeds the bump into the substrate, reduces the external volume, thereby reducing the interference of the bump on the chip and the substrate and reducing the space occupied by the bonding wire to solve the problem that the bump in the traditional package is located outside the chip, which is not conducive to the miniaturization of the chip. Utility Model Content
[0004] In view of this, it is necessary to provide a power device MOS stack package Bumpless wire bonding structure to solve the above problems.
[0005] The embodiment of the present application provides a power device MOS stack package Bumpless wire bonding structure, including:
[0006] A packaging substrate, wherein the packaging substrate has a mounting surface;
[0007] A stacked chip, wherein a plurality of the stacked chips are stacked on the mounting surface, a direction parallel to the mounting surface is referred to as a first direction, a distance a between one stacked chip and another adjacent stacked chip in the first direction satisfies the relationship a>0, a surface of the stacked chip in contact with the outside and parallel to the mounting surface is referred to as a wiring surface, and a wiring hole is provided on the wiring surface;
[0008] A welding wire is provided between two adjacent stacked chips, one end of the welding wire is provided in the wiring hole of one stacked chip, and the other end of the welding wire is provided in the wiring hole on another stacked chip adjacent to the stacked chip.
[0009] In at least one embodiment of the present application, a welding wire is provided between the stacked chip disposed on the packaging substrate and the packaging substrate, one end of the welding wire is provided in the wiring hole, and the other end of the welding wire is provided on the packaging substrate.
[0010] In at least one embodiment of the present application, it also includes:
[0011] A top chip, wherein the top chip is arranged on the stacked chip, and a plurality of the stacked chips are located between the top chip and the packaging substrate. A wiring bump is provided on a side of the top chip away from the stacked chip. The top chip and the stacked chip adjacent to the top chip are connected through the welding wire. When the welding wire is arranged between the top chip and the stacked chip adjacent to the top chip, one end of the welding wire is connected to the wiring bump, and the other end of the welding wire is connected to the wiring hole.
[0012] In at least one embodiment of the present application, the two ends of the bonding wire have platform portions, and when the bonding wire connects two adjacent stacked chips, the two platform portions of the bonding wire are respectively attached to the two stacked chips.
[0013] In at least one embodiment of the present application, when both ends of the welding wire are respectively connected to the packaging substrate and the stacked chip, the platform portion at one end of the welding wire is attached to the packaging substrate, and the platform portion at the other end of the welding wire is attached to the stacked chip.
[0014] In at least one embodiment of the present application, when both ends of the bonding wire are respectively connected to the top chip and the stacked chip, the platform portion at one end of the bonding wire is bonded to the top chip, and the platform portion at the other end of the bonding wire is bonded to the stacked chip.
[0015] In at least one embodiment of the present application, a conductive adhesive layer is provided between the stacked chip disposed on the packaging substrate and the packaging substrate, and the stacked chip is fixedly connected to the packaging substrate through the conductive adhesive layer.
[0016] In at least one embodiment of the present application, the wiring hole is filled with a conductive material, the bonding wire is in contact with the conductive material, and the conductive material connects the bonding wire and the stacked chip.
[0017] In at least one embodiment of the present application, a solder pad is provided on the stacked chip, and the wiring hole is opened on the solder pad.
[0018] In at least one embodiment of the present application, the bonding wire is made of gold, copper or aluminum, and the bonding wire is connected to the conductive material by laser welding or ultrasonic welding.
[0019] The above-mentioned power device MOS stacked package Bumpless wire bonding structure is provided with wiring holes on the stacked chips, and the welding wires are connected to the wiring holes so that the welding points of the welding wires are located inside the chips, thereby reducing the interference of the bumps on the gaps between the chips, and also enabling the welding wires to be set closer to the chips, thereby reducing the volume of the entire chip package, and solving the problem that the bumps in the traditional package are located outside the chip, which is not conducive to the miniaturization of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a structural stereogram of the bumpless wire bonding structure of the power device MOS stack package.
[0021] Main component symbols
[0022] 100. Bumpless wire bonding structure of MOS stacked package for power device; 1. Package substrate; 11. Mounting surface; 2. Stacked chips; 21. Wiring surface; 22. Solder pad; 221. Wiring hole; 3. Solder wire; 31. Platform; 4. Top chip; 41. Wiring bump; 5. Conductive adhesive layer; 6. Conductive material. DETAILED DESCRIPTION
[0023] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.
[0024] It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a central component at the same time. When a component is considered to be "located on" another component, it may be directly located on the other component or there may be a central component at the same time. The terms "top", "bottom", "upper", "lower", "left", "right", "front", "back", and similar expressions used herein are for illustrative purposes only.
[0025] The embodiment of the present application provides a power device MOS stack package Bumpless wire bonding structure, including:
[0026] A packaging substrate, wherein the packaging substrate has a mounting surface;
[0027] A stacked chip, wherein a plurality of the stacked chips are stacked on the mounting surface, a direction parallel to the mounting surface is referred to as a first direction, a distance a between one stacked chip and another adjacent stacked chip in the first direction satisfies the relationship a>0, a surface of the stacked chip in contact with the outside and parallel to the mounting surface is referred to as a wiring surface, and a wiring hole is provided on the wiring surface;
[0028] A welding wire is provided between two adjacent stacked chips, one end of the welding wire is provided in the wiring hole of one stacked chip, and the other end of the welding wire is provided in the wiring hole on another stacked chip adjacent to the stacked chip. The above-mentioned power device MOS stacked package Bumpless wire bonding structure is provided with wiring holes on the stacked chips, and the welding wire is connected to the wiring hole so that the welding point of the welding wire is located inside the chip, thereby reducing the interference of the bump on the gap between the chips, and also enabling the welding wire to be set closer to the chip when being set, thereby reducing the volume of the entire chip package, and solving the problem that the bump in the traditional package is located outside the chip, which is not conducive to the miniaturization of the chip.
[0029] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0030] See also Figure 1The embodiment of the present application provides a power device MOS stack package Bumpless wire bonding structure 100, comprising a package substrate 1, a stacked chip 2 and a bonding wire 3, wherein the package substrate 1 has a mounting surface 11. A plurality of the stacked chips 2 are stacked on the mounting surface 11, a direction parallel to the mounting surface 11 is referred to as a first direction, a distance a between one stacked chip 2 and another adjacent stacked chip 2 in the first direction satisfies the relationship a>0, a surface of the stacked chip 2 in contact with the outside and parallel to the mounting surface 11 is referred to as a wiring surface 21, and a wiring hole 221 is provided on the wiring surface 21. A bonding wire 3 is provided between two adjacent stacked chips 2, one end of the bonding wire 3 is provided in the wiring hole 221 of one stacked chip 2, and the other end of the bonding wire 3 is provided in the wiring hole 221 on another stacked chip 2 adjacent to the stacked chip 2.
[0031] Specifically, the first direction is a unidirectional direction, and the distance between the stacked chips 2 in the first direction is a, which also means that the stacked chips 2 are arranged equidistantly in the first direction. The package substrate 1 is the basis of the entire package structure, providing a stable mounting surface 11 for supporting and fixing the stacked chips 2. The package substrate 1 ensures the mechanical strength and stability of the entire stacked structure, protects the chip from the external environment, and provides a good heat dissipation path. Stacked chips are an important component for realizing multi-layer integration. Each chip is stacked on another chip, which increases the integration of the package. Through chip stacking, more functions can be integrated in a limited space, improving the performance and functional density of the device. In the power device MOS stacked package Bumpless wire bonding structure, the distance a refers to the distance between two adjacent stacked chips 2 in a direction parallel to the mounting surface 11 of the package substrate 1. Because the multiple stacked chips 2 are in a stacking relationship, the distance a makes the stacked chips 2 staggered. Due to the stacking relationship, each chip has a part of its surface in contact with the outside world, and these contact surfaces are the wiring surfaces 21. These wiring surfaces 21 are used to open wiring holes 221 and make electrical connections through welding wires 3. The wiring holes 221 on the wiring surface 21 are used to insert the bonding wires 3 to achieve electrical connection between adjacent chips. The wiring surface 21 provides a surface for fixing and mechanically supporting the bonding wires 3, ensuring the stability and reliability of the connection of the bonding wires 3. The wiring holes 221 are channels for inserting the bonding wires 3 to ensure electrical connection between chips. The wiring surface 21 provides a standardized connection interface, and the wiring holes 221 ensure the fixation and reliable connection of the bonding wires 3, improving the stability of the connection. The design of the wiring surface 21 and the wiring holes 221 is suitable for various multi-layer packaging structures, such as 3D integrated circuits, MEMS, etc.
[0032] Further, a wiring hole 221 is pre-designed and etched on the wiring surface 21 of the stacked chip 2. The position and size of the wiring hole 221 should be optimized according to the diameter of the welding wire 3 and the welding process. One end of the welding wire 3 is inserted into the wiring hole 221 of a stacked chip 2. The welding wire 3 is usually made of a material with good conductivity and mechanical strength, such as gold, copper or aluminum. Then, the other end of the welding wire 3 is inserted into the wiring hole 221 of the adjacent stacked chip 2. Use appropriate welding technology, such as laser welding or ultrasonic welding, to fix the welding wire 3. The welding point should be located in the wiring hole 221 to ensure reliable electrical connection and mechanical fixation between the welding wire 3 and the chip. At the same time, avoid the welding point interfering with the chip stacking.
[0033] In a specific example, a bonding wire 3 is disposed between the stacked chip 2 disposed on the packaging substrate 1 and the packaging substrate 1 , one end of the bonding wire 3 is disposed in the wiring hole 221 , and the other end of the bonding wire 3 is disposed on the packaging substrate 1 .
[0034] Specifically, because the stacked chips 2 are stacked on each other, only one stacked chip 2 in a group of stacked stacked chips 2 is directly disposed on the packaging substrate 1, and this stacked chip 2 directly disposed on the packaging substrate 1 is referred to as "the stacked chip 2 disposed on the packaging substrate 1". A welding wire 3 is disposed between the packaging substrate 1 and the stacked chip 2 directly disposed on the packaging substrate 1, and there may be one or more welding wires 3. These welding wires 3 are responsible for connecting the stacked chip 2 and the packaging substrate 1 to ensure reliable electrical connection and mechanical fixation between them. The fact that one end of the welding wire 3 is disposed in the wiring hole 221 indicates that one end of the welding wire 3 is inserted into the wiring hole 221 of the stacked chip 2. The wiring hole 221 is a small hole pre-designed on the wiring surface 21 of the stacked chip 2 for accommodating the welding wire 3 and providing a welding point. The other end of the welding wire 3 is disposed on the packaging substrate 1, which indicates that the other end of the welding wire 3 is connected to the packaging substrate 1. This is usually achieved by direct welding.
[0035] In a specific example, it also includes:
[0036] A top chip 4, wherein the top chip 4 is arranged on the stacked chip 2, and a plurality of the stacked chips 2 are located between the top chip 4 and the packaging substrate 1. A wiring bump 41 is provided on a side of the top chip 4 away from the stacked chip 2. The top chip 4 is connected to the stacked chip 2 adjacent to the top chip 4 through the welding wire 3. When the welding wire 3 is arranged between the top chip 4 and the stacked chip 2 adjacent to the top chip 4, one end of the welding wire 3 is connected to the wiring bump 41, and the other end of the welding wire 3 is connected to the wiring hole 221.
[0037] Specifically, this is an extra chip located on top of the stacked chip 2. Its function is to provide additional functions or processing capabilities, and it is usually arranged at the top position of the stacked chip 2. The top chip 4 is placed on top of the stacked chip 2, which means that multiple stacked chips 2 are located between the top chip 4 and the package substrate 1. A wiring bump 41 is provided on one side of the top chip 4 away from the stacked chip 2. The wiring bump 41 is usually referred to as a solder ball (bump), which is a protruding metal structure located on the surface of a chip or device for electrical connection. Solder balls are usually formed on the surface of the chip through a manufacturing process, and they can be metal spherical, columnar or other shaped structures. The top chip 4 is connected to the adjacent stacked chips 2 through welding wires 3. These welding wires 3 are responsible for transmitting signals between the top chip 4 and the stacked chips 2, and ensuring reliable electrical connections between them. The welding wires 3 are connected by connecting the wiring bumps 41 of the top chip 4 and the wiring holes 221 of the stacked chips 2. One end of the bonding wire 3 is connected to the connection bump 41 of the top chip 4 , and the other end is connected to the connection hole 221 of the stacked chip 2 adjacent to the top chip 4 .
[0038] In a specific example, the two ends of the bonding wire 3 have platform portions 31 . When the bonding wire 3 connects two adjacent stacked chips 2 , the two platform portions 31 of the bonding wire 3 are respectively attached to the two stacked chips 2 .
[0039] Specifically, the two ends of the welding wire 3 have platform parts 31. This means that the two ends of the welding wire 3 form a flat area, and the platform parts 31 are formed by adjusting the arc shape of the welding wire 3, and the arc shape of the welding wire 3 can be adjusted according to the shape and size of the connecting component. By controlling the welding process, such as laser welding or ultrasonic welding, the welding wire 3 can accurately adjust its shape to ensure that the platform parts 31 form a good fit with the package substrate 1 and the stacked chip 2. Adjusting the arc shape of the welding wire 3 can make the welding wire 3 more stable when connected, and ensure that there is enough contact area and contact force between the welding wire 3 and the connecting component. Compared with the main body of the welding wire 3, these platform parts 31 are wider and flatter. When the welding wire 3 is used to connect two adjacent stacked chips 2, the platform parts 31 at its two ends play a key role. The two platform parts 31 are respectively fitted with two adjacent stacked chips 2. The presence of the platform parts 31 helps to ensure a stable connection between the welding wire 3 and the stacked chip 2. They provide a wider contact area and enhance the mechanical stability between the welding wire 3 and the chip. In addition to providing a stable connection during the welding process, the platform portion 31 can also be used to save space, which is particularly important when stacking multiple chips in a limited space. Specifically, the design of the platform portion 31 allows the bonding wire 3 to occupy less vertical space between two adjacent stacked chips 2, thereby saving space in the vertical direction.
[0040] In a specific example, when both ends of the welding wire 3 are respectively connected to the packaging substrate 1 and the stacked chip 2, the platform portion 31 at one end of the welding wire 3 is attached to the packaging substrate 1, and the platform portion 31 at the other end of the welding wire 3 is attached to the stacked chip 2.
[0041] Specifically, one end of the welding wire 3 is connected to the packaging substrate 1 through the platform portion 31, and a close fit is formed between the platform portion 31 and the packaging substrate 1, and this fit ensures a firm connection between the welding wire 3 and the packaging substrate 1. This is usually achieved by welding, and welding can ensure a reliable electrical connection and mechanical fixation between the welding wire 3 and the packaging substrate 1. The platform portion 31 at the other end is fitted with the stacked chip 2: the platform portion 31 at the other end of the welding wire 3 is connected to the stacked chip 2, and a close fit is formed between the platform portion 31 and the chip, ensuring a firm connection between the welding wire 3 and the stacked chip 2. This fit is also usually achieved by welding, and welding can ensure a reliable electrical connection and mechanical fixation between the welding wire 3 and the stacked chip 2.
[0042] In a specific example, when both ends of the bonding wire 3 are respectively connected to the top chip 4 and the stacked chip 2 , the platform portion 31 at one end of the bonding wire 3 is bonded to the top chip 4 , and the platform portion 31 at the other end of the bonding wire 3 is bonded to the stacked chip 2 .
[0043] Specifically, one end of the bonding wire 3 is connected to the top chip 4 through the platform portion 31, and a fit is formed between the platform portion 31 and the top chip 4. This fit ensures a firm connection between the bonding wire 3 and the top chip 4. Usually, the platform portion 31 is designed to fit with the surface of the top chip 4 to ensure the stability of the connection. The platform portion 31 at the other end of the bonding wire 3 is connected to the stacked chip 2, and a fit is formed between the platform portion 31 and the chip. This fit ensures a firm connection between the bonding wire 3 and the stacked chip 2. The platform portion 31 is usually designed to fit with the surface of the stacked chip 2 to ensure the stability of the connection.
[0044] In a specific example, a conductive adhesive layer 5 is provided between the stacked chip 2 disposed on the packaging substrate 1 and the packaging substrate 1 , and the stacked chip 2 is fixedly connected to the packaging substrate 1 via the conductive adhesive layer 5 .
[0045] Specifically, the conductive adhesive layer 5 is located between the stacked chip 2 and the packaging substrate 1. It is a special material that has both adhesive properties and good electrical conductivity, and can achieve the conduction of electrical signals. Through the conductive adhesive layer 5, a stable connection is formed between the stacked chip 2 and the packaging substrate 1. The main function of the conductive adhesive layer 5 is to provide mechanical support and fixation to ensure that the stacked chip 2 is firmly fixed on the packaging substrate 1 to prevent it from moving or loosening during use. The conductive adhesive layer 5 can not only provide a stable connection, but also maintain good electrical conductivity. This means that electrical signals can be transmitted from the stacked chip 2 to the packaging substrate 1, or vice versa, without being hindered by the connection layer. This technology is common in the field of integrated circuit packaging, especially in complex devices that require stacking multiple chips to achieve higher performance and greater functions. By using the conductive adhesive layer 5, a close connection between chips can be achieved while maintaining good electrical performance.
[0046] In a specific example, the wiring hole 221 is filled with a conductive material 6 , the bonding wire 3 is in contact with the conductive material 6 , and the conductive material 6 connects the bonding wire 3 and the stacked chip 2 .
[0047] Specifically, the wiring holes 221 are small holes pre-designed on the wiring surface 21 of the stacked chip 2, which are used to accommodate the welding wires 3 and provide welding points. These wiring holes 221 are filled with conductive materials 6. This conductive material 6 is usually a metal or alloy with good conductivity, such as gold, copper, etc. Its main function is to provide good conductivity during the welding process to ensure that the electrical signal can be effectively transmitted. When the welding wire 3 is connected to the wiring hole 221, the welding wire 3 contacts the conductive material 6 filled in the wiring hole 221. This contact ensures the electrical connection between the welding wire 3 and the conductive material 6, thereby realizing the transmission of the electrical signal. This connection method usually uses welding or other appropriate fixing methods to ensure stability. The conductive material 6 filled in the wiring hole 221 is connected to the welding wire 3, and the welding wire 3 is connected to the stacked chip 2. This connection method ensures that the electrical signal is transmitted from the stacked chip 2 via the welding wire 3 to the conductive material 6 in the wiring hole 221, and finally reaches other components or circuits.
[0048] In a specific example, a bonding pad 22 is disposed on the stacked chip 2 , and the wiring hole 221 is opened on the bonding pad 22 .
[0049] Specifically, the pad 22 is a metal structure, usually located on the surface of the chip, for connecting the wire 3 or other electrical components. In this scenario, the pad 22 is set on the surface of the stacked chip 2. The pad 22 is usually made of a metal material, such as copper, which has good electrical conductivity and welding performance. The wiring hole 221 is a small hole pre-designed on the wiring surface 21 of the stacked chip 2, which is used to accommodate the wire 3 and provide a welding point. In this scenario, the wiring hole 221 is set on the pad 22, that is, on the surface of the pad 22. This design allows the wire 3 to be directly connected to the pad 22 and electrically connected to the stacked chip 2 through the wiring hole 221. During wafer manufacturing, the pad 22 position is etched and the corresponding conductive material 6 is added.
[0050] In a specific example, the bonding wire 3 is made of gold, copper or aluminum, and the bonding wire 3 is connected to the conductive material 6 by laser welding or ultrasonic welding.
[0051] Specifically, the welding wire 3 is made of metals such as gold, copper or aluminum. These metals have good electrical conductivity and mechanical strength, can effectively transmit current and provide stable connections. Laser welding is a high-energy welding method that instantly heats the welding part through a laser beam to melt it and form a weld. In this scenario, the connection between the welding wire 3 and the conductive material 6 can be achieved by laser welding. Laser welding provides a high-precision and high-efficiency welding process, which can accurately control the heating and cooling process of the welding area during the welding process, thereby ensuring the quality and stability of the welding. Ultrasonic welding uses ultrasonic vibrations to generate heat at the welding part, so that the surface of the material melts and forms a weld. In this scenario, the connection between the welding wire 3 and the conductive material 6 can also be achieved by ultrasonic welding. Ultrasonic welding generally has the advantages of fast welding speed, environmental friendliness, and no need for additional materials. It is suitable for scenarios with low requirements on welding materials and strict requirements on the environment.
[0052] The above is only an implementation method of the present application. It should be pointed out that a person skilled in the art can make improvements without departing from the inventive concept of the present application, but these improvements are within the scope of protection of the present application.
Claims
1. A power device MOS stack package Bumpless wire bonding structure, characterized in that: include: A packaging substrate, wherein the packaging substrate has a mounting surface; A stacked chip, wherein a plurality of the stacked chips are stacked on the mounting surface, a direction parallel to the mounting surface is referred to as a first direction, a distance a between one stacked chip and another adjacent stacked chip in the first direction satisfies the relationship a>0, a surface of the stacked chip in contact with the outside and parallel to the mounting surface is referred to as a wiring surface, and a wiring hole is provided on the wiring surface; A welding wire is provided between two adjacent stacked chips, one end of the welding wire is provided in the wiring hole of one stacked chip, and the other end of the welding wire is provided in the wiring hole on another stacked chip adjacent to the stacked chip.
2. The power device MOS stack package Bumpless wire bonding structure according to claim 1, characterized in that: A bonding wire is arranged between the stacked chip arranged on the packaging substrate and the packaging substrate, one end of the bonding wire is arranged in the wiring hole, and the other end of the bonding wire is arranged on the packaging substrate.
3. The power device MOS stack package Bumpless wire bonding structure according to claim 1, characterized in that: Also includes: A top chip, wherein the top chip is arranged on the stacked chip, and a plurality of the stacked chips are located between the top chip and the packaging substrate. A wiring bump is provided on a side of the top chip away from the stacked chip. The top chip and the stacked chip adjacent to the top chip are connected through the welding wire. When the welding wire is arranged between the top chip and the stacked chip adjacent to the top chip, one end of the welding wire is connected to the wiring bump, and the other end of the welding wire is connected to the wiring hole.
4. The power device MOS stack package bumpless wire bonding structure according to claim 3, characterized in that: The two ends of the bonding wire have platform parts. When the bonding wire connects two adjacent stacked chips, the two platform parts of the bonding wire are respectively attached to the two stacked chips.
5. The power device MOS stack package bumpless wire bonding structure according to claim 4, characterized in that: When both ends of the bonding wire are respectively connected to the packaging substrate and the stacked chip, the platform portion at one end of the bonding wire is attached to the packaging substrate, and the platform portion at the other end of the bonding wire is attached to the stacked chip.
6. The power device MOS stack package bumpless wire bonding structure according to claim 5, characterized in that: In the case where both ends of the bonding wire are respectively connected to the top chip and the stacked chip, the platform portion at one end of the bonding wire is attached to the top chip, and the platform portion at the other end of the bonding wire is attached to the stacked chip.
7. The power device MOS stack package bumpless wire bonding structure according to claim 1, characterized in that: A conductive adhesive layer is provided between the stacked chip disposed on the packaging substrate and the packaging substrate, and the stacked chip is fixedly connected to the packaging substrate through the conductive adhesive layer.
8. The power device MOS stack package bumpless wire bonding structure according to claim 1, characterized in that: The wiring holes are filled with conductive material, the bonding wires are in contact with the conductive material, and the conductive material connects the bonding wires and the stacked chips.
9. The power device MOS stack package bumpless wire bonding structure according to claim 1, characterized in that: A welding pad is arranged on the stacked chip, and the wiring hole is opened on the welding pad.
10. The power device MOS stack package bumpless wire bonding structure according to claim 8, characterized in that: The bonding wire is made of gold, copper or aluminum, and is connected to the conductive material by laser welding or ultrasonic welding.