Through-wall type frequency converter based on open-close type structure
By designing a wall-through circuit based on an open-close structure in the inverter, using components such as relays, PMOS tubes and buffer resistor circuits, the problems of impact interference and sparking during power-on inverter are solved, and higher stability and reliability are achieved.
Patent Information
- Application Number
- CN202420590554.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-26
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-03-26
AI Technical Summary
The existing inverters generate impact interference during power-on and the interference and spark phenomenon caused by the pressure difference between the two ends when the relay is absorbed and connected.
A wall-through frequency converter based on an open-close structure is designed. By setting a relay, PMOS tube and buffer resistor circuit between the MCU and the power supply circuit, an isolation transformer and a voltage divider bus voltage acquisition circuit are used to achieve high and low voltage isolation and multiple protection measures.
It effectively isolates high and low voltages, reduces the risk of sparks, improves the stability and reliability of the inverter, and ensures the stable operation of the circuit in harsh environments.
Smart Images
Figure CN222691583U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of frequency converters, in particular to a through-the-wall frequency converter based on an opening and closing structure. Background Art
[0002] The inverter is an electrical control device that is based on power electronic devices and guided by modern control theory. It adjusts the parameters of power electronic equipment through digital control and then controls electrical equipment such as motors. The use of inverters enables enterprises to optimize and upgrade their mechanical equipment and electrical equipment.
[0003] However, affected by the electronic interference in the operating environment, there is impact interference generated during the power-on process of the existing inverter and interference and sparking caused by the voltage difference at both ends when the relay is energized.
[0004] Therefore, a new technical solution is urgently needed to solve the above technical problems. Utility Model Content
[0005] The purpose of the utility model is to overcome the above-mentioned problems of the prior art and provide a through-the-wall inverter based on an open-and-close structure to solve the technical problems of impact interference generated during the power-on process of the inverter and interference and sparking caused by the pressure difference at both ends when the relay is energized in the prior art.
[0006] The above objectives are achieved through the following technical solutions:
[0007] A through-the-wall inverter based on an open-and-close structure comprises a power supply circuit and an MCU connected to each other, wherein a relay, a PMOS tube and a buffer resistor circuit are arranged between the MCU and the power supply circuit, and the buffer resistor circuit is connected in parallel with the relay and the PMOS tube;
[0008] One end of the buffer resistor circuit is connected to the power supply circuit, and the other end is connected to the isolation transformer. A divided-voltage bus voltage acquisition circuit is also connected to the isolation transformer, and the other end of the divided-voltage bus voltage acquisition circuit is connected to the MCU.
[0009] Furthermore, the buffer resistor circuit includes a fifth resistor and a sixth resistor connected in parallel with each other.
[0010] Furthermore, the second pin and the fifth pin of the relay are respectively connected to the two ends of the buffer resistance circuit, the fourth pin of the relay is connected to the collector of the third transistor, the base of the third transistor is connected to the MCU via the seventh resistor; the emitter of the third transistor is grounded.
[0011] Furthermore, a tenth diode is connected in parallel between the third pin and the fourth pin of the relay.
[0012] Furthermore, the D pole and the S pole of the PMOS tube are respectively connected to the two ends of the buffer resistor circuit, and the G pole of the PMOS tube is connected to the MCU via an isolation optical coupler.
[0013] Furthermore, the fourth pin of the isolation optocoupler is connected to the G pole of the PMOS tube, and the second pin of the isolation optocoupler is connected to the MCU; a fourth resistor and an eighth resistor are also connected in parallel between the first pin and the second pin of the isolation optocoupler.
[0014] Furthermore, a third resistor and a first diode are arranged between the isolation optocoupler and the MCU, the cathode of the first diode is connected to the MCU, the anode of the first diode is connected to one end of the third resistor, and the other end of the third resistor is connected to the second pin of the isolation optocoupler.
[0015] Furthermore, a first resistor, a second resistor, a ninth resistor and a tenth resistor are also provided at the G pole of the PMOS tube, and the first resistor, the second resistor, the ninth resistor and the tenth resistor constitute a voltage divider circuit.
[0016] Furthermore, the first pin of the isolation transformer is connected to the buffer resistance circuit, and the seventh pin of the isolation transformer is connected to the divided-voltage bus voltage collection circuit via a twenty-fourth diode.
[0017] Furthermore, the divided-voltage bus voltage acquisition circuit includes a twentieth resistor, a sixty-fourth resistor and a nineteenth resistor connected to each other, and is provided with an eleventh capacitor, a twelfth capacitor and a thirteenth capacitor for filtering.
[0018] The utility model provides a through-the-wall inverter based on an open-and-close structure, which adopts digital signal control, can effectively isolate high and low voltages, realize low-voltage signal control of high-voltage parts, and improve the safety and reliability of the inverter; through multiple protection measures and fault self-healing mechanism, it ensures the stable operation of the circuit in various harsh environments, and at the same time improves the ability to cope with abnormal situations such as overload and overvoltage of the circuit. This solution can effectively solve the impact interference generated during the power-on process of the inverter and the interference and sparking caused by the voltage difference at both ends when the relay is pulled in. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a circuit diagram of a through-the-wall frequency converter based on an open-and-close structure described in the utility model. DETAILED DESCRIPTION
[0020] The utility model is further described in detail below based on the accompanying drawings and embodiments. The described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0021] like Figure 1 As shown, the present solution provides a through-the-wall inverter based on an open-and-close structure, comprising a power supply circuit and an MCU connected to each other, characterized in that a relay U2, a PMOS tube Q1 and a buffer resistor circuit are arranged between the MCU and the power supply circuit, and the buffer resistor circuit is connected in parallel with the relay U2 and the PMOS tube Q1;
[0022] One end of the buffer resistor circuit is connected to the power supply circuit, and the other end is connected to the isolation transformer T1. The isolation transformer T1 is also connected to a divided-voltage bus voltage acquisition circuit, and the other end of the divided-voltage bus voltage acquisition circuit is connected to the MCU;
[0023] How it works
[0024] The PWR+ high-voltage direct current on one side of the power supply circuit powers on the system through the buffer resistor circuit, and the switching power supply enters the working state. At this time, the MCU works, and its PWR_ON pin switches to a high level, causing the PMOS tube Q1 to turn on;
[0025] The PWR+ voltage signal CVD enters the MCU through the isolation transformer T1 and the voltage-dividing bus voltage acquisition circuit. The MCU reads the current PWR+ voltage and triggers a relay pickup signal if the voltage reaches the threshold.
[0026] Although the relay U2 is not energized at this time, the voltages of PWR+ and P+ are almost equal. Also, because not only the buffer resistor circuit is connected but also the PMOS tube Q1 is turned on, no sparking will occur when the relay U2 is energized, thereby greatly improving the stability and controllability of the circuit.
[0027] When the power is off, when the MCU reads that the CVD signal is lower than the undervoltage threshold, the relay pickup signal is first cut off. At this time, the buffer resistor circuit is also connected to the PMOS tube Q1, so when the relay is cut off, the risk of ignition is reduced and the current flowing through the buffer resistor is reduced.
[0028] The buffer resistor circuit in this embodiment includes a fifth resistor R5 and a sixth resistor R6 connected in parallel with each other.
[0029] In this embodiment, the second pin and the fifth pin of the relay U2 are respectively connected to the two ends of the buffer resistor circuit, the fourth pin of the relay U2 is connected to the collector of the third transistor Q3, the base of the third transistor Q3 is connected to the MCU via the seventh resistor R7; the emitter of the third transistor Q3 is grounded;
[0030] It should be noted that the third transistor Q3 in this embodiment can control the flow of large current and transform the current of the relay U2 into a range that the control circuit can bear; and the seventh resistor R7 is used for current limiting to prevent the third transistor Q3 from being burned due to excessive current;
[0031] In this embodiment, the model of the relay U2 is MMBT4401LT1G, and the model of the seventh resistor R7 is RS-03K4700FT.
[0032] A tenth diode D10 is also connected in parallel between the third pin and the fourth pin of the relay U2 to provide a current loop for the relay U2.
[0033] In this embodiment, the D pole and S pole of the PMOS tube Q1 are respectively connected to the two ends of the buffer resistor circuit, and the G pole of the PMOS tube Q1 is connected to the MCU via the isolation optocoupler U1; the isolation optocoupler U1 is used for low-level conduction in this embodiment.
[0034] In this embodiment, the fourth pin of the isolation optocoupler U1 is connected to the G pole of the PMOS tube Q1, and the second pin of the isolation optocoupler U1 is connected to the MCU; the third pin of the isolation optocoupler U1 is grounded; a fourth resistor R4 and an eighth resistor R8 are also connected in parallel between the first pin and the second pin of the isolation optocoupler U1;
[0035] Specifically, in this embodiment, the fourth resistor R4 is a pull-up resistor, model RS-03K1002FT; the eighth resistor R8 is a current limiting resistor, model RS-03K6800FT.
[0036] In addition, a third resistor R3 and a first diode D1 are further provided between the isolation optocoupler U1 and the MCU, the cathode of the first diode D1 is connected to the MCU, the anode of the first diode D1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the second pin of the isolation optocoupler U1;
[0037] In this embodiment, the model of the first diode D1 is SS34, which is used to prevent the high level from flowing out of the MCU; the model of the third resistor R3 is RS-03K100JT, which is used for anti-interference.
[0038] A first resistor R1, a second resistor R2, a ninth resistor R9 and a tenth resistor R10 are also provided at the G pole of the PMOS tube Q1. The first resistor R1, the second resistor R2, the ninth resistor R9 and the tenth resistor R10 constitute a voltage divider circuit for adjusting the gate voltage of the PMOS tube Q1 to prevent overvoltage. A second voltage regulator tube D2 is also provided. The model of the second voltage regulator tube D2 is 1N4746, which is an 18V voltage regulator tube and is used to prevent overvoltage and play a protective role.
[0039] In this embodiment, the first pin of the isolation transformer T1 is connected to the buffer resistor circuit, and the seventh pin of the isolation transformer T1 is connected to the voltage-dividing bus voltage acquisition circuit via the twenty-fourth diode D24; the model of the isolation transformer T1 is BCK-109XJ; the twenty-fourth diode D24 is used for rectification and preventing voltage backflow.
[0040] The voltage-dividing bus voltage acquisition circuit in this embodiment includes a 20th resistor R20, a 64th resistor R64 and a 19th resistor R19 connected to each other for voltage division, and is provided with an 11th capacitor C11, a 12th capacitor C12 and a 13th capacitor C13 for filtering.
[0041] Among them, the model of the twentieth resistor R20 is RS-03K5901FT, the model of the sixty-fourth resistor R64 is RS-06K1003FT, and the model of the nineteenth resistor R19 is RS-03K3321FT; the model of the eleventh capacitor C11 is 0603CGA101J500NT, the model of the twelfth capacitor C12 is 0603B104K500NT, and the model of the thirteenth capacitor C13 is 0603B104K500NT.
[0042] The above description is only for illustrating the implementation mode of the present invention and is not intended to limit the present invention. For those skilled in the art, any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A through-the-wall inverter based on an open-and-close structure, comprising a power supply circuit and an MCU connected to each other, characterized in that: A relay (U2), a PMOS tube (Q1) and a buffer resistor circuit are arranged between the MCU and the power supply circuit, and the buffer resistor circuit, the relay (U2) and the PMOS tube (Q1) are connected in parallel with each other; One end of the buffer resistor circuit is connected to the power supply circuit, and the other end is connected to the isolation transformer (T1); a voltage-dividing bus voltage acquisition circuit is also connected to the isolation transformer (T1); and the other end of the voltage-dividing bus voltage acquisition circuit is connected to the MCU.
2. A through-the-wall inverter based on an open-and-close structure according to claim 1, characterized in that: The buffer resistor circuit includes a fifth resistor (R5) and a sixth resistor (R6) connected in parallel with each other.
3. A through-the-wall inverter based on an open-and-close structure according to claim 1 or 2, characterized in that: The second pin and the fifth pin of the relay (U2) are respectively connected to the two ends of the buffer resistor circuit, the fourth pin of the relay (U2) is connected to the collector of the third triode (Q3), the base of the third triode (Q3) is connected to the MCU via a seventh resistor (R7); and the emitter of the third triode (Q3) is grounded.
4. The through-the-wall inverter based on an open-and-close structure according to claim 3 is characterized in that: A tenth diode (D10) is also connected in parallel between the third pin and the fourth pin of the relay (U2).
5. A through-the-wall inverter based on an open-and-close structure according to claim 1 or 2, characterized in that: The D pole and the S pole of the PMOS tube (Q1) are respectively connected to the two ends of the buffer resistor circuit, and the G pole of the PMOS tube (Q1) is connected to the MCU via an isolation optical coupler (U1).
6. The through-the-wall inverter based on an open-and-close structure according to claim 5, characterized in that: The fourth pin of the isolation optocoupler (U1) is connected to the G pole of the PMOS tube (Q1), and the second pin of the isolation optocoupler (U1) is connected to the MCU; a fourth resistor (R4) and an eighth resistor (R8) are also connected in parallel between the first pin and the second pin of the isolation optocoupler (U1).
7. A through-the-wall inverter based on an open-and-close structure according to claim 6, characterized in that: A third resistor (R3) and a first diode (D1) are also provided between the isolation optocoupler (U1) and the MCU, the cathode of the first diode (D1) is connected to the MCU, the anode of the first diode (D1) is connected to one end of the third resistor (R3), and the other end of the third resistor (R3) is connected to the second pin of the isolation optocoupler (U1).
8. A through-the-wall frequency converter based on an open-and-close structure according to claim 5 or 6, characterized in that: A first resistor (R1), a second resistor (R2), a ninth resistor (R9) and a tenth resistor (R10) are also provided at the G pole of the PMOS tube (Q1), and the first resistor (R1), the second resistor (R2), the ninth resistor (R9) and the tenth resistor (R10) form a voltage divider circuit.
9. The through-the-wall inverter based on an open-and-close structure according to claim 1, characterized in that: The first pin of the isolation transformer (T1) is connected to the buffer resistor circuit, and the seventh pin of the isolation transformer (T1) is connected to the divided-voltage bus voltage acquisition circuit via a twenty-fourth diode (D24).
10. A through-the-wall inverter based on an open-and-close structure according to claim 9, characterized in that: The voltage-dividing bus voltage acquisition circuit includes a twentieth resistor (R20), a sixty-fourth resistor (R64) and a nineteenth resistor (R19) connected to each other, and is provided with an eleventh capacitor (C11), a twelfth capacitor (C12) and a thirteenth capacitor (C13) for filtering.