Rigid-flex board

Abstract

The utility model discloses a rigid-flex board, which comprises a flexible layer positioned in the middle and a first rigid layer positioned on one side of the flexible layer, and is characterized in that the first rigid layer comprises a first circuit and a first insulating layer, the first circuit is the outermost circuit in the circuits included in the first rigid layer, and the first insulating layer is arranged between the first circuit and the first insulating layer. The first insulating layer is arranged between the first circuit and the flexible layer in a spaced mode, and a part of the first insulating layer is filled in a circuit gap of the first circuit so that the first circuit can be embedded in the first insulating layer. The rigid-flex board provided by the utility model has the characteristics of high space utilization rate, high flatness, strong signal integrity and the like.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit boards, in particular to a soft-hard combination board. Background Art

[0002] A rigid-flex board is a composite circuit board that integrates the characteristics of a flexible circuit board and a rigid circuit board. From the perspective of layer layout, a rigid-flex board includes a flexible layer and a rigid layer. One side of the flexible layer has a first rigid layer, or both sides of the flexible layer have a first rigid layer and a second rigid layer. The flexible layer generally includes an outermost flexible layer protective material to separate the rigid layer from each other. The flexible layer protective material is generally PI (polyimide). Such a design not only ensures the flexibility of the substrate, but also provides sufficient rigidity to support electronic components. From the perspective of the plane layout, the rigid-flex board can be divided into two areas: a soft board area and a hard board area. The soft board area only contains a flexible layer, so it has a high bending ability and is suitable for application scenarios that require bending or folding. The hard board area is the combination of the flexible layer and the hard layer. It not only maintains a certain degree of flexibility, but also has the supporting performance of the hard layer, and is suitable as a carrier for electronic equipment. For more details on the structure of the rigid-flex board, please refer to the contents disclosed in the Chinese invention patent application "Method for manufacturing rigid-flex board and rigid-flex board" with application number 201911168531.0 (application publication number CN 112839451A).

[0003] In traditional rigid-flex PCBs, the outer layers are often directly exposed above the interlayer insulating material. This design has several significant limitations. First, it leads to low space utilization, limiting the further miniaturization and integration of electronic equipment. Second, the flatness of the circuit board is affected, which may cause assembly problems and affect the stability of the overall device. In addition, due to the exposure of the wires, the interference during signal transmission increases, thereby reducing the integrity and reliability of the signal. At the same time, this layout is not conducive to electromagnetic compatibility, which may cause performance degradation when the device works in a complex electromagnetic environment. In view of these problems, it is particularly urgent to improve the traditional rigid-flex PCB to meet the needs of modern electronic products for high performance, high reliability and compact size. Utility Model Content

[0004] The technical problem to be solved by the utility model is to propose a rigid-flexible board with high space utilization rate in view of the above technical status quo.

[0005] The technical solution adopted by the utility model to solve the above technical problems is: a soft-rigid combination board, including a flexible layer located in the middle and a first hard layer located on one side of the flexible layer, characterized in that the first hard layer includes a first circuit and a first insulating layer, the first circuit is the outermost circuit among the circuits included in the first hard layer, the first insulating layer is spaced between the first circuit and the flexible layer, and part of the first insulating layer is filled in the circuit gap of the first circuit so that the first circuit is buried in the first insulating layer.

[0006] Preferably, the surface of the first circuit on the outer side is flush with the surface of the first insulating layer on the outer side.

[0007] Optionally, the rigid-flex board is further provided with a conductive through hole, which passes through the circuits of all layers of the rigid-flex board, and the hole wall of the conductive through hole is provided with a conductive circuit, which is electrically connected to the circuits of all layers of the rigid-flex board.

[0008] Furthermore, the rigid-flex board further includes a second rigid layer located on the opposite side of the flexible layer from the first rigid layer, the second rigid layer includes a fourth circuit, the fourth circuit includes a fourth conductor layer, a fourth seed layer and a fourth electroplating layer, the fourth seed layer and the fourth electroplating layer extend into the hole wall of the conductive through hole, thereby forming the conductive circuit. The second rigid layer further includes a fourth insulating layer, and the fourth insulating layer is spaced between the fourth circuit and the flexible layer.

[0009] Alternatively, the rigid-flexible board is further provided with a conducting blind hole, which penetrates the insulating material between two adjacent layers of circuits, the bottom surface of the conducting blind hole is the circuit surface of the adjacent layer, and the conducting blind hole is filled with an electroplated layer as a conducting circuit. The second rigid layer includes a fourth circuit, and the fourth circuit is connected to the circuit of the flexible layer by a third conducting blind hole. The fourth circuit includes a fourth conductor layer, a fourth seed layer and a fourth electroplating layer. The fourth seed layer and the fourth electroplating layer extend into and fill the hole of the third conducting blind hole, thereby forming a conducting circuit connecting the fourth circuit and the circuit of the flexible layer. The flexible layer includes a third circuit and a second circuit, and the third circuit is connected to the second circuit by a second conducting blind hole, and the second circuit is connected to the first circuit by a first conducting blind hole.

[0010] More specifically, the rigid-flex board further includes an ink layer, and the ink layer covers all exposed surfaces of the circuits.

[0011] Preferably, the ink layer has a window at a location where the circuit needs to be connected to other electrical components, and the window is covered with a surface treatment layer.

[0012] Compared with the prior art, the present invention saves space for the rigid-flexible board by embedding the first circuit in the first insulating layer, so that it can accommodate more circuit elements while maintaining the original functions, or provide more possibilities for future expansion and upgrading. Moreover, by embedding the circuit, the present invention avoids the protrusions or depressions that may be caused by traditional circuits, thereby ensuring the flatness of the circuit board, reducing the equipment failure rate and extending the service life. The structure of the present invention also helps to reduce the loss and interference of the signal during the transmission process, thereby improving the integrity and reliability of the signal, ensuring the stable operation of the equipment, and improving the accuracy of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a cross-sectional schematic diagram of the first embodiment of the utility model;

[0014] Figure 2 It is a cross-sectional schematic diagram of the second embodiment of the present utility model. DETAILED DESCRIPTION

[0015] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0016] Embodiment 1

[0017] This embodiment takes the processing of a four-layer rigid-flexible board as an example, the flexible layer III is located in the middle layer, and the first rigid layer I and the second rigid layer II are respectively provided on both sides of the flexible layer III, wherein the first circuit L1 is the circuit of the first rigid layer I, the second circuit L2 and the third circuit L3 are the circuits of the flexible layer III, and the fourth circuit L4 is the circuit of the second rigid layer II. This embodiment specifically includes the following steps:

[0018] S1. Substrate blanking: The substrate includes a substrate insulating layer, a substrate conductor layer and a substrate seed layer from the inner layer to the outer layer, and the core plate of the substrate (composed of a substrate insulating layer and a substrate conductor layer) and the substrate seed layer can be separated. The thickness of the core plate is designed according to product requirements, preferably 10 to 300 μm; the substrate seed layer is made of copper in this embodiment, and the thickness can be selected from 2 μm, 3 μm, and 5 μm.

[0019] S2. Lamination: Laminating the first dry film layer on the substrate seed layer. The type and thickness of the photoresist to be used here need to be designed according to the actual product. This embodiment is described by taking Hitachi RD1229 (29 μm thick pattern selective plating photoresist) as an example.

[0020] S3, exposure: exposing the non-first line L1 pattern area of ​​the first dry film layer, so that the photoresist in the exposed area of ​​the first dry film layer is irradiated with light and fuses.

[0021] S4, development: using a sodium carbonate solution to expose the substrate seed layer at the bottom of the first line L1 pattern from the unexposed area of ​​the first dry film layer (the exposed area of ​​the first dry film layer that cannot be dissolved and has undergone fusion) .

[0022] S5, electroplating: a selective plating circuit is made on the exposed substrate seed layer, and the plating layer forms the first circuit L1. The copper plating thickness is determined according to product requirements, and the thickness is generally lower than the photoresist thickness of the first dry film layer.

[0023] S6, film removal: removing the exposed area of ​​the first dry film layer to expose the substrate seed layer 3 in the non-first line L1 pattern area.

[0024] S7, pressure transmission: The first composite substrate is bonded to the first line L1 through an insulating adhesive material, and the gap between the first lines L1 is filled. The insulating adhesive material here forms a first insulating layer 5, which plays an insulating role. The insulating adhesive material can be epoxy resin or pure glue. The first composite substrate is composed of solid copper facing the first line L1 side, the middle first PI layer 7 and the second conductor layer facing the flexible layer III side. The first PI layer 7 is used as a protective material for the flexible layer III. The solid copper is used as a cover protection material here, and the area covered by it corresponds to the soft board area B of the finished product of the hard-soft board, which can effectively prevent the insulating adhesive material from bonding the first PI layer 7 and causing subsequent cover difficulties. In addition, other metals, as long as they meet the requirements of being processable and removable, such as nickel, tin, titanium-copper alloy, etc., can also be used as cover protection materials. The first composite substrate can be obtained by cutting through FCCL and etching one side of the conductor layer into solid copper here.

[0025] S8, lamination: hot press photoresist on the surface of the second conductor layer 8 to form a second dry film layer. The type and thickness of the photoresist selected here should be designed according to the actual product. This embodiment takes Hitachi RD1229 (thickness 29μm pattern selective plating photoresist) as an example for description.

[0026] S9, exposure: exposing the second line L2 pattern area of ​​the second dry film layer, so that the photoresist in the exposure area 9b of the second dry film layer is irradiated with light and fuses.

[0027] S10, development: using a sodium carbonate solution to develop the unexposed areas of the second dry film layer (the exposed areas of the second dry film layer where fusion has occurred cannot be dissolved).

[0028] S11, etching: etching the area of ​​the second conductor layer not protected by the second dry film layer (i.e., the area corresponding to the unexposed area 9a of the second dry film layer), and the remaining part of the second conductor layer after etching forms the second line L2. The etching process can be acid, alkali ordinary etching, vacuum etching, two-fluid etching, etc.

[0029] S12, film removal: removing the exposed area of ​​the second dry film layer, that is, the second dry film layer 9 remaining outside the second line L2.

[0030] S13, lamination: The third conductor layer is bonded to the second line L2 through an insulating adhesive material, and the gap between the second lines L2 is filled. The insulating adhesive material here forms a second insulating layer 10, which plays an insulating role. The insulating adhesive material can be epoxy resin or pure glue. The third conductor layer uses a copper foil with a thickness of 2 to 36 μm, which is selected according to customer needs and product design.

[0031] S14, lamination: hot press photoresist on the surface of the third conductor layer to form a third dry film layer. The type and thickness of the photoresist selected here should be designed according to the actual product. This embodiment takes Hitachi RD1229 (thickness 29μm pattern selective plating photoresist) as an example for description.

[0032] S15, exposure: exposing the third line L3 pattern area of ​​the third dry film layer, so that the photoresist in the exposed area of ​​the third dry film layer is irradiated with light and fuses.

[0033] S16, development: using a sodium carbonate solution to develop the unexposed areas of the third dry film layer (the exposed areas of the third dry film layer where fusion has occurred cannot be dissolved).

[0034] S17, etching: etching the area of ​​the third conductor layer not protected by the third dry film layer (i.e., the area corresponding to the unexposed area of ​​the third dry film layer), and the remaining part of the third conductor layer after etching forms the third line L3. The etching process can be acid, alkali ordinary etching, vacuum etching, two-fluid etching, etc.

[0035] S18, film removal: removing the exposed area of ​​the third dry film layer, that is, the third dry film layer remaining outside the third line L3.

[0036] S19, laminating the cover film: Laminating the cover film on the third line L3, the cover film is composed of the second PI layer 14 and the AD glue, and the AD glue is used to bond and fill the gap of the third line L3 and form the third insulating layer 13. The cover film can protect the outer surface and line of the circuit board, prevent environmental factors (such as moisture, dust and chemicals) from damaging the circuit, and also provide electrical insulation. The type and specification of the cover film can be selected according to customer needs or design.

[0037] S20, lamination: The fourth conductor layer 16 is bonded to the cover film through an insulating adhesive material, and the insulating adhesive material is avoided in the soft board area B. The insulating adhesive material here forms the fourth insulating layer 15, which plays an insulating role. The insulating adhesive material can be epoxy resin or pure glue. The fourth conductor layer 16 uses a copper foil with a thickness of 2 to 36 μm, which is selected according to customer needs and product design.

[0038] S21, depaneling: separating the core board of the substrate from the substrate seed layer, and removing the core board.

[0039] S22, removing the seed layer: removing the substrate seed layer to expose the first insulating layer 5 and the outer surface of the first line L1.

[0040] S23, drilling: Drilling a conductive through hole 17 on the surface of the fourth conductor layer 16 to penetrate all layers of circuits. The drilling process can be mechanical through hole drilling, laser through hole drilling, die punching, laser through blind hole drilling, etc. This embodiment takes mechanical through hole drilling as an example. The aperture of the conductive through hole 17 is generally 0.075 to 2.0 mm according to product design requirements.

[0041] S24, depositing seed layer: depositing the fourth seed layer 18 on the upper and lower surfaces of the product and the wall of the conductive through hole, the purpose is to make it conductive as a transition layer for the subsequent addition of conductors. The process can be chemical deposition method, vacuum coating method. The fourth seed layer 18 can be made of titanium, copper, nickel, etc., or alloy layers of different metals. This embodiment takes copper as an example for explanation.

[0042] S25, lamination: hot laminating photoresist on the surface of the fourth seed layer 18 to form a fourth dry film layer. The type and thickness of the photoresist selected here should be designed according to the actual product. This embodiment takes Hitachi RD1229 (29 μm thick pattern selective plating photoresist) as an example for description.

[0043] S26, exposure: exposing the entire plane area of ​​the fourth dry film layer close to the first line L1, so that the photoresist in the exposed area of ​​the fourth dry film layer is irradiated with light and fuses.

[0044] S27, development: using a sodium carbonate solution to develop the unexposed areas of the fourth dry film layer (the exposed areas of the fourth dry film layer where fusion has occurred cannot be dissolved).

[0045] S28, electroplating: the fourth seed layer 18 is electroplated on the whole board and the hole wall is copper plated to form a fourth electroplating layer 20 to achieve interlayer conduction of each layer of circuits. The copper plating thickness is based on customer needs or product design.

[0046] S29, film removal: removing the exposed area 19b of the fourth dry film layer, that is, the fourth dry film layer 19 in the entire plane area close to the first line L1.

[0047] S30, removing the seed layer: removing the unadded fourth seed layer 18, that is, the fourth seed layer 18 covered by the exposed area of ​​the fourth dry film layer during the electroplating process in S28.

[0048] S31, uncovering: using a laser uncovering process to remove the insulating adhesive material of the first hard layer I of the soft board area B, the flexible layer III of the soft board area B is protected by the solid copper covering of the first combined substrate and is not damaged.

[0049] S32, lamination: hot laminating the photoresist on the product surface to form the fifth dry film layer. The type and thickness of the photoresist selected here should be designed according to the actual product. This embodiment takes Hitachi RD1229 (thickness 29μm pattern selective plating photoresist) as an example for explanation.

[0050] S33, exposure: exposing the fourth line L4 pattern area of ​​the fifth dry film layer close to the fourth electroplating layer 20, and exposing the non-covered window area of ​​the fifth dry film layer, so that the photoresist in the exposed area 21b of the fifth dry film layer is irradiated with light and fuses.

[0051] S34, development: using a sodium carbonate solution to expose the fourth electroplating layer 20 in the fourth line L4 region and the solid copper of the first composite substrate in the unexposed area of ​​the fifth dry film layer (the exposed area of ​​the fifth dry film layer where fusion has occurred cannot be dissolved).

[0052] S35, etching: etching the areas of the fourth electroplating layer 20, the fourth seed layer 18 and the fourth conductor layer 16 that are not protected by the fifth dry film layer, and the remaining parts of the fourth electroplating layer 20, the fourth seed layer 18 and the fourth conductor layer 16 after etching form the fourth line L4 and the conductive line located in the conductive via 17. At the same time, the solid copper is also removed in this etching step because it is not covered by the fifth dry film layer. The etching process can be acid, alkali ordinary etching, vacuum etching, two-fluid etching, etc.

[0053] S36, film removal: removing the exposed area of ​​the fifth dry film layer.

[0054] S37, solder mask: The circuit is covered with ink solder mask, and the ink forms an ink layer 22 on the circuit surface. The optional processes include screen ink printing and DFSR dry film ink. The former has the advantage of stable process and the disadvantage of large circuit height difference; the latter has the advantage of a smoother surface and the disadvantage of unstable process. The appropriate process can be selected according to customer needs.

[0055] S38, exposure: exposing the non-window pad area to make the non-window area of ​​the ink layer 22 fuse under ultraviolet light. The solder mask window design can be ON PAD or OPEN PAD. This embodiment is described with ON PAD window design.

[0056] S39, development: using sodium carbonate solution to expose the pads in the unexposed areas of the ink layer (the exposed areas of the ink layer where fusion has occurred cannot be dissolved).

[0057] S40, surface treatment: the pad surface is treated to form a surface treatment layer 23. Common surface treatment processes include nickel-palladium-gold, gold plating, OSP, double surface treatment, etc., gold plating is preferred for welding, and nickel-palladium-gold is preferred for wire bonding, which is selected according to the customer's product design.

[0058] According to the above process steps, a rigid-flex board with embedded circuits can be made. Figure 1 The hard-flex board is divided along the thickness direction, including a flexible layer III located in the middle and a first hard layer I and a second hard layer II located on both sides.

[0059] The first rigid layer I includes a first circuit L1 and a first insulating layer 5. The first insulating layer 5 separates the first circuit L1 from the flexible layer III, and the gaps between the first circuits L1 are filled with the first insulating layer 5 so that the first circuit L1 is buried in the first insulating layer 5. The outer surface of the first circuit L1 is flush with the outer surface of the first insulating layer 5.

[0060] The flexible layer III includes the second line L2, the third line L3, the second insulating layer 10, the third insulating layer 13, the first PI layer 7 and the second PI layer 14. The first PI layer 7 and the second PI layer 14 are respectively located at the outermost parts of the two sides of the flexible layer III, and the second line L2, the third line L3, the second insulating layer 10 and the third insulating layer 13 are sandwiched and protected therein. The first PI layer 7 is located on the side close to the first hard layer I, and the second PI layer 14 is located on the side close to the second hard layer II. The second insulating layer 10 is spaced between the second line L2 and the third line L3, and the line gap of the second line L2 is filled with the second insulating layer 10. The third insulating layer 13 is spaced between the third line L3 and the second PI layer 14, and the line gap of the third line L3 is filled with the third insulating layer 13.

[0061] The second rigid layer II includes a fourth line L4 and a fourth insulating layer 15. The fourth insulating layer 15 is located inside the fourth line L4 and separates the fourth line L4 from the flexible layer III. The fourth line layer L4 includes a fourth conductor layer 16, a fourth seed layer 18 and a fourth electroplating layer 20 located outside the fourth insulating layer 15.

[0062] The rigid-flexible board is divided along the board plane direction, including a rigid board area A and a flexible board area B. The rigid board area A includes the first rigid layer I, the second rigid layer II and the flexible layer III, while the flexible board area B does not include the first rigid layer I and the second rigid layer II. The rigid board area A is provided with a conductive through hole 17 for conducting all layer circuits, and the conductive through hole 17 is provided with a through hole conductive circuit L 1～4 , conduction line L 1～4 The fourth conductor layer 16 , the fourth seed layer 18 and the fourth electroplating layer 20 are included in the portion located in the through hole 17 .

[0063] The rigid-flex board also includes an ink layer 22, which covers the surface of each circuit exposed from the insulating layer, and has windows where the circuit needs to be connected to other electrical components. The window is surface treated and covered with a surface treatment layer 23.

[0064] The manufacturing process for each line other than the first line L1 is not limited to the etching method, and a semi-additive method, a modified semi-additive method, an etching method, etc. can be selected according to product requirements.

[0065] The conduction of each circuit layer is not limited to the method of drilling through holes, and the method of drilling blind holes described in the second embodiment below can also be used. In addition, a combination of blind holes and through holes can also be used.

[0066] Inspired by the scheme of this embodiment, a hard-flex board with more circuit layers can also be produced. For example, to produce a hard-flex board with six circuit layers, it is only necessary to produce two layers of circuits in the first hard layer I according to the conventional process before S7 pressure transmission, and the subsequent steps are carried out according to this embodiment. After the covering film is pressed in S19, the two layers of circuits in the second hard layer II are produced according to the conventional process. The subsequent steps are also carried out according to the operation of this embodiment to complete the uncovering to realize the window of the soft board area B in the first hard layer I.

[0067] The present invention is still applicable after the distribution of the hard layer and the circuit distribution of the hard layer are flexibly changed, such as the case where only one side of the flexible layer III has the first hard layer I and the other side has no hard layer; or the case where the first hard layer I has one circuit layer and the second hard layer II has three circuit layers, etc.

[0068] Embodiment 2

[0069] This embodiment takes the processing of a four-layer rigid-flexible board as an example, wherein the first circuit L1 is the circuit of the first rigid layer I, the second circuit L2 and the third circuit L3 are the circuits of the flexible layer III, and the fourth circuit L4 is the circuit of the second rigid layer II. This embodiment specifically includes the following steps:

[0070] S1 to S6 are the same as those in the first embodiment.

[0071] S7, pressure transmission: The first composite substrate is bonded to the first line L1 through an insulating adhesive material, and the gap between the first lines L1 is filled. The insulating adhesive material here forms a first insulating layer 5, which plays an insulating role. The insulating adhesive material can be epoxy resin or pure glue. The first composite substrate is composed of solid copper facing the first line L1, the middle first PI layer 7 and the second conductor layer 8 facing the flexible layer III. The first PI layer 7 is used as a protective material for the flexible layer III. The solid copper is used as a cover protection material here, and the area covered by it corresponds to the soft board area B of the finished product of the hard-soft board, which can effectively prevent the insulating adhesive material from bonding the first PI layer 7 and causing subsequent cover difficulties. In addition, other metals, as long as they meet the requirements of being processable and removable, such as nickel, tin, titanium-copper alloy, etc., can also be used as cover protection materials. The first composite substrate can be obtained by cutting the FCCL and etching one side of the conductor layer into solid copper here. In addition to metals, tape can also be used as a cover protection material. If the adhesive tape is used, then in the subsequent process S38 the adhesive tape will be removed when the cover is opened, and S39-S43 can be omitted, and S44 can be directly performed.

[0072] S8, drilling: The surface of the second conductor layer 8 is drilled with a CO2 laser process to form a first conductive blind hole 24, the bottom surface of which is the first line L1. The diameter of the first conductive blind hole 24 is determined according to customer needs and product design.

[0073] S9, depositing seed layer: depositing the second seed layer 25 on the upper and lower surfaces of the product and the wall and bottom of the first conductive blind hole 24, in order to make it conductive as a transition layer for subsequent conductor addition. The process options include chemical deposition method and vacuum coating method. The material of the second seed layer 25 can be titanium, copper, nickel, etc., or alloy layers of different metals. This embodiment takes copper as an example for explanation.

[0074] S10, hole filling electroplating: the second seed layer 25 is subjected to whole-board electroplating to form a second electroplating layer 26, and the first conductive blind via 24 is filled to achieve interlayer conduction between the first circuit L1 and the subsequently manufactured second circuit L2. The copper plating thickness is determined according to customer requirements or product design.

[0075] S11, lamination: hot lamination photoresist on the surface of the second electroplating layer 26 to form a second dry film layer. The type and thickness of the photoresist selected here should be designed according to the actual product. This embodiment takes Hitachi RD1229 (thickness 29μm pattern selective plating photoresist) as an example for description.

[0076] S12, exposure: exposing the second line L2 pattern area of ​​the second dry film layer, so that the photoresist in the exposed area of ​​the second dry film layer is irradiated with light and fuses.

[0077] S13, development: using sodium carbonate solution to dissolve the unexposed area of ​​the second dry film layer (the exposed area of ​​the second dry film layer where fusion has occurred cannot be dissolved)

[0078] S14, etching: etching the areas of the second electroplating layer 26, the second seed layer 25 and the second conductor layer 8 that are not protected by the second dry film layer (i.e., the areas corresponding to the unexposed areas of the second dry film layer), and the remaining parts of the second electroplating layer 26, the second seed layer 25 and the second conductor layer 8 after etching form the second circuit L2 and the conducting circuit located in the first conducting blind hole 24. The etching process may include acid or alkali ordinary etching, vacuum etching, two-fluid etching, etc.

[0079] S15, film removal: removing the exposed area of ​​the second dry film layer, that is, the second dry film layer remaining outside the second line L2.

[0080] S16, lamination: The third conductor layer 11 is bonded to the second line L2 through an insulating adhesive material, and the gap between the second lines L2 is filled. The insulating adhesive material here forms the second insulating layer 10, which plays an insulating role. The insulating adhesive material can be epoxy resin or pure glue. The third conductor layer 11 uses a copper foil with a thickness of 2 to 36 μm, which is selected according to customer needs and product design.

[0081] S17, drilling: The surface of the third conductor layer 11 is drilled with a CO2 laser process to form a second conductive blind hole 27, the bottom surface of which is the second line L2. The diameter of the second conductive blind hole 27 is determined according to customer needs and product design.

[0082] S18, depositing seed layer: depositing the third seed layer 28 on the upper and lower surfaces of the product and the wall and bottom of the second conductive blind hole 27 as a transition layer for the subsequent addition of conductors. The process can be chemical deposition method or vacuum coating method. The material of the third seed layer 28 can be titanium, copper, nickel, etc., or alloy layers of different metals. This embodiment takes copper as an example for explanation.

[0083] S19, hole filling electroplating: perform whole board electroplating on the surface of the third seed layer 28 to form a third electroplating layer 29, and fill the second conductive blind hole 27 to achieve interlayer conduction between the second line L2 and the subsequently manufactured third line L3. The copper plating thickness is based on customer needs or product design.

[0084] S20, lamination: hot press photoresist on the surface of the third electroplating layer 29 to form a third dry film layer. The type and thickness of the photoresist selected here should be designed according to the actual product. This embodiment takes Hitachi RD1229 (thickness 29μm pattern selective plating photoresist) as an example for description.

[0085] S21, exposure: exposing the third line L3 pattern area of ​​the third dry film layer, so that the photoresist in the exposed area of ​​the third dry film layer is irradiated with light and fuses.

[0086] S22, development: using a sodium carbonate solution to develop the unexposed areas of the third dry film layer (the exposed areas of the third dry film layer where fusion has occurred cannot be dissolved).

[0087] S23, etching: etching the areas of the third electroplating layer 29, the third seed layer 28 and the third conductor layer 11 that are not protected by the third dry film layer (i.e., the areas corresponding to the unexposed areas of the third dry film layer), and the remaining parts of the third electroplating layer 29, the third seed layer 28 and the third conductor layer 11 after etching form the third line L3 and the conducting line located in the second conducting blind hole 27. The etching process may be acid or alkali ordinary etching, vacuum etching, two-fluid etching, etc.

[0088] S24, film removal: removing the exposed area of ​​the third dry film layer, that is, the third dry film layer remaining outside the third line L3.

[0089] S25, pressure transfer: the second composite substrate is pressed onto the third line L3 through the insulating adhesive material, and the second composite substrate comprises a second PI layer 14 facing one side of the flexible layer and a fourth conductor layer 16 facing the opposite side. The insulating adhesive material fills the gap of the third line L3 and forms the third insulating layer 13. The insulating adhesive material can be epoxy resin or pure glue. The fourth conductor layer 16 uses a copper foil with a thickness of 2 to 36 μm, which is selected according to customer needs and product design.

[0090] S26, drilling: The surface of the fourth conductor layer 16 is drilled with a CO2 laser process to form a third conductive blind via 30, the bottom surface of which is the third line L3. The diameter of the third conductive blind via 30 is determined according to customer needs and product design.

[0091] S27, depositing a seed layer: depositing a fourth seed layer 18 on the upper and lower surfaces of the product and the wall and bottom of the third conductive blind hole 30 as a transition layer for subsequent conductor addition. The process can be chemical deposition or vacuum coating. The fourth seed layer 18 can be made of titanium, copper, nickel, etc., or alloy layers of different metals. This embodiment takes copper as an example for illustration.

[0092] S28, hole filling electroplating: perform whole-board electroplating on the surface of the fourth seed layer 18 to form a fourth electroplating layer 20, and fill the third conductive blind hole 30 to achieve interlayer conduction between the third line L3 and the subsequently manufactured fourth line L4. The copper plating thickness is determined according to customer needs or product design.

[0093] S29, lamination: hot laminating photoresist on the surface of the fourth electroplating layer 20 to form a fourth dry film layer. The type and thickness of the photoresist selected here should be designed according to the actual product. This embodiment takes Hitachi RD1229 (thickness 29μm pattern selective plating photoresist) as an example for description.

[0094] S30, exposure: exposing the fourth line L4 pattern area of ​​the fourth dry film layer, so that the photoresist in the exposed area of ​​the fourth dry film layer is irradiated with light and fuses.

[0095] S31, development: using a sodium carbonate solution to develop the unexposed areas of the fourth dry film layer (the exposed areas of the fourth dry film layer where fusion has occurred cannot be dissolved).

[0096] S32, etching: etching the areas of the fourth electroplating layer 20, the fourth seed layer 18 and the fourth conductor layer 16 that are not protected by the fourth dry film layer (i.e., the areas corresponding to the unexposed areas of the third dry film layer), and the remaining parts of the fourth electroplating layer 20, the fourth seed layer 18 and the fourth conductor layer 16 after etching form the fourth line L4 and the conducting line located in the third conducting blind hole 30. The etching process may include acid or alkali ordinary etching, vacuum etching, two-fluid etching, etc.

[0097] S33, film removal: removing the exposed area of ​​the fourth dry film layer, that is, the fourth dry film layer remaining outside the fourth line L4.

[0098] S34, lamination: hot-pressing photoresist on the product surface to form a fifth dry film layer to protect the circuit when removing the seed layer in S36.

[0099] S35, separating the boards: separating the core board of the substrate from the substrate seed layer, and removing the core board.

[0100] S36, removing the seed layer: removing the substrate seed layer to expose the first insulating layer 5 and the outer surface of the first line L1.

[0101] S37, film removal: removing the fifth dry film layer.

[0102] S38, uncovering: using a laser uncovering process to remove the insulating adhesive material of the first hard layer I of the soft board area B, the flexible layer III of the soft board area B is protected by the solid copper covering of the first combined substrate and is not damaged.

[0103] S39, lamination: hot laminating the photoresist on the product surface to form the sixth dry film layer. The type and thickness of the photoresist selected here should be designed according to the actual product. This embodiment takes Hitachi RD1229 (thickness 29μm pattern selective plating photoresist) as an example for explanation.

[0104] S40, exposure: exposing the non-covered window area of ​​the sixth dry film layer, so that the photoresist in the exposed area 31b of the sixth dry film layer is irradiated with light and fuses.

[0105] S41, development: using a sodium carbonate solution to expose the solid copper of the first composite substrate in the unexposed area of ​​the sixth dry film layer (the exposed area of ​​the sixth dry film layer where fusion has occurred cannot be dissolved).

[0106] S42, etching: etching away the solid copper. The etching process can be acid, alkali ordinary etching, vacuum etching, two-fluid etching, etc.

[0107] S43, film removal: removing the exposed area of ​​the sixth dry film layer.

[0108] S44, solder mask: The circuit is covered with ink solder mask, and the ink forms an ink layer 22 on the circuit surface. The optional processes include screen ink printing and DFSR dry film ink. The former has the advantage of stable process and the disadvantage of large circuit height difference; the latter has the advantage of a smoother surface and the disadvantage of unstable process. The appropriate process can be selected according to customer needs.

[0109] S45, exposure: exposing the non-window pad area to make the non-window area of ​​the ink layer 22 fuse under ultraviolet light. The solder mask window design can be either ON PAD or OPEN PAD. This embodiment is described using the ON PAD window design.

[0110] S46, development: using sodium carbonate solution to expose the pads in the unexposed areas of the ink layer (the exposed areas of the ink layer where fusion has occurred cannot be dissolved).

[0111] S47, surface treatment: treat the pad surface to form a surface treatment layer 23. Common surface treatment processes include nickel-palladium-gold, gold plating, OSP, double surface treatment, etc. Gold plating is preferred for welding, and nickel-palladium-gold is preferred for wire bonding, which is selected according to the customer's product design.

[0112] According to the above process steps, a rigid-flex board with embedded circuits can be made. Figure 2 As shown. The difference between the rigid-flexible board of this embodiment and the rigid-flexible board of the first embodiment is that the conductive blind hole of this embodiment uses the hole-filling plating layer as the conductive circuit to connect the adjacent layer circuits to each other. The second circuit L2 includes the second conductor layer 8, the second seed layer 25 and the second electroplating layer 26 outside the hole wall of the first conductive blind hole 24, and the third circuit L3 includes the third conductor layer 11, the third seed layer 28 and the third electroplating layer 29 outside the hole wall of the second conductive blind hole 27. The first conductive blind hole 24 is filled with the first conductive circuit L1 for connecting the first circuit L1 and the second circuit L2. 12 The second conductive blind hole 27 is filled with a second conductive line L2 for conducting the second line L2 and the third line L3. 23 The third conductive blind hole 30 is filled with a third conductive line L3 for conducting the third line L3 and the fourth line L4. 34, which includes portions of the fourth seed layer 18 and the fourth electroplating layer 20 in the third conductive blind via hole 30 .

[0113] The manufacturing process for each line other than the first line L1 is not limited to the etching method, and a semi-additive method, a modified semi-additive method, an etching method, etc. can be selected according to product requirements.

[0114] The conduction of each circuit layer is not limited to the method of drilling blind holes, and the method of drilling through holes described in the above embodiment 1 can also be used. In addition, a combination of blind holes and through holes can also be used.

[0115] Inspired by the scheme of this embodiment, a rigid-flex board with more circuit layers can also be made. For example, to make a rigid-flex board with six circuit layers, it is only necessary to make two layers of circuits of the first rigid layer I according to the conventional process before pressure transmission in S7, and the subsequent steps are operated according to this embodiment, and after pressure transmission in S25, two layers of circuits of the second rigid layer II are made according to the conventional process, and the subsequent steps are also operated according to this embodiment to complete the uncovering to realize the window opening of the soft board area B in the first rigid layer I. The present invention is still applicable after the distribution of the rigid layer and the distribution of the circuits of the rigid layer are flexibly changed, such as the case where only one side of the flexible layer III has the first rigid layer I and the other side does not have a rigid layer; or the case where the first rigid layer I has one circuit and the second rigid layer II has three circuits, etc.

Claims

1. A rigid-flexible board, comprising a flexible layer in the middle and a first rigid layer on one side of the flexible layer, characterized in that: The first rigid layer includes a first circuit and a first insulating layer. The first circuit is the outermost circuit among the circuits included in the first rigid layer. The first insulating layer is spaced between the first circuit and the flexible layer. Part of the first insulating layer fills the circuit gap of the first circuit so that the first circuit is buried in the first insulating layer.

2. The rigid-flex board according to claim 1, characterized in that: The surface of the first circuit on the outer side is flush with the surface of the first insulating layer on the outer side.

3. The rigid-flex board according to claim 1, characterized in that: The rigid-flex board is also provided with a conductive through hole, which passes through the circuits of all layers of the rigid-flex board. The hole wall of the conductive through hole is provided with a conductive circuit, which is electrically connected to the circuits of all layers of the rigid-flex board.

4. The rigid-flex board according to claim 3, characterized in that: It also includes a second hard layer located on the opposite side of the flexible layer to the first hard layer, the second hard layer includes a fourth circuit, the fourth circuit includes a fourth conductor layer, a fourth seed layer and a fourth electroplating layer, the fourth seed layer and the fourth electroplating layer extend into the hole wall of the conductive through hole, thereby forming the conductive circuit.

5. The rigid-flex board according to claim 4, characterized in that: The second rigid layer further includes a fourth insulating layer, and the fourth insulating layer is spaced between the fourth circuit and the flexible layer.

6. The rigid-flex board according to claim 5, characterized in that: The rigid-flex board is also provided with a conducting blind hole, which penetrates the insulating material between two adjacent layers of circuits, the bottom surface of the conducting blind hole is the circuit surface of the adjacent layer, and the conducting blind hole is filled with an electroplated layer as a conducting circuit.

7. The rigid-flex board according to claim 6, characterized in that: The second hard layer includes a fourth circuit, and the fourth circuit is connected to the circuit of the flexible layer through a third conductive blind hole. The fourth circuit includes a fourth conductor layer, a fourth seed layer and a fourth electroplating layer. The fourth seed layer and the fourth electroplating layer extend into and fill the hole of the third conductive blind hole, thereby forming a conductive circuit that connects the fourth circuit with the circuit of the flexible layer.

8. The rigid-flex board according to claim 7, characterized in that: The flexible layer includes a third circuit and a second circuit. The third circuit is connected to the second circuit via a second conductive blind via, and the second circuit is connected to the first circuit via a first conductive blind via.

9. The rigid-flex board according to claim 1, characterized in that: The rigid-flex board also includes an ink layer, which covers all exposed surfaces of the circuits.

10. The rigid-flex board according to claim 9, characterized in that: The ink layer has a window at a position where the circuit needs to be connected with other electrical components, and the window is covered with a surface treatment layer.

Images