Display device

Abstract

A display device is provided. The display device may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include: a pixel circuit layer including a first transistor, a second transistor, and a third transistor disposed on a substrate; a bridge pattern disposed on a gate electrode of the first transistor and a source electrode of the second transistor, a first end of the bridge pattern being electrically connected to the source electrode of the second transistor and a second end of the bridge pattern being electrically connected to the gate electrode of the first transistor; a first alignment electrode and a second alignment electrode disposed on the pixel circuit layer; and a plurality of light emitting elements disposed on the first alignment electrode and the second alignment electrode, and electrically connected to at least one of the first transistor, the second transistor, and the third transistor. The second alignment electrode may be supplied with a low potential voltage and overlap the bridge pattern in plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0071794, filed on Jun. 2, 2023, the entire disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a display device. Background Art

[0004] Recently, as interest in information display increases, research and development of display devices have been ongoing. Utility Model Content

[0005] Various embodiments of the present disclosure may provide a display device having improved reliability.

[0006] An embodiment of the present disclosure may provide a display device, the display device including a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged adjacent to each other. Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include a pixel circuit layer and a bridge pattern, a first alignment electrode and a second alignment electrode, and a plurality of light-emitting elements, the pixel circuit layer including a first transistor, a second transistor, and a third transistor arranged on a substrate, the bridge pattern being arranged on a gate electrode of the first transistor and a source electrode of the second transistor, the first end of the bridge pattern being electrically connected to the source electrode of the second transistor and the second end of the bridge pattern being electrically connected to the gate electrode of the first transistor, the first alignment electrode and the second alignment electrode being arranged on the pixel circuit layer and spaced apart from each other, and a plurality of light-emitting elements being arranged on the first alignment electrode and the second alignment electrode, and being electrically connected to at least one of the first transistor, the second transistor, and the third transistor. The second alignment electrode may be supplied with a low potential voltage and overlap the bridge pattern in a plan view.

[0007] In an embodiment, the pixel circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer sequentially stacked on the substrate. The source electrode of the second transistor may be arranged on the first insulating layer, the gate electrode of the first transistor may be arranged on the second insulating layer, the bridge pattern may be arranged on the third insulating layer, and the second alignment electrode may be arranged on the fifth insulating layer.

[0008] In an embodiment, the first end of the bridge pattern may be electrically connected to the source electrode of the second transistor through a first contact hole formed through the second insulating layer and the third insulating layer. The second end of the bridge pattern may be electrically connected to the gate electrode of the first transistor through a second contact hole formed through the third insulating layer.

[0009] In an implementation, the second alignment electrode may overlap the first contact hole and the second contact hole.

[0010] In an implementation, the second alignment electrode may overlap the second contact hole and not overlap the first contact hole.

[0011] In an implementation, the second alignment electrode may overlap the first contact hole and not overlap the second contact hole.

[0012] In an embodiment, each of the first subpixel, the second subpixel, and the third subpixel may include a contact electrode arranged on a third insulating layer, a fourth insulating layer and a fifth insulating layer arranged on the contact electrode and each including a contact portion exposing the contact electrode, and a first alignment electrode and a second alignment electrode arranged on the fifth insulating layer and a plurality of light emitting elements and electrically connected to the plurality of light emitting elements.

[0013] In an embodiment, at least one electrode of the plurality of electrodes may be electrically connected to the contact electrode through a contact portion.

[0014] In an embodiment, the plurality of electrodes may include a first electrode, a second electrode, a third electrode, a fourth electrode, and a fifth electrode spaced apart from each other. The first electrode may include an anode of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the fifth electrode includes a cathode of the corresponding sub-pixel. The at least one electrode may include the first electrode.

[0015] In an embodiment, each of the first subpixel, the second subpixel, and the third subpixel may include a first sub-electrode disposed on (or in) the same layer as the second electrode and electrically connected to the second electrode, a second sub-electrode disposed on (or in) the same layer as the third electrode and electrically connected to the third electrode, a third sub-electrode disposed on (or in) the same layer as the fourth electrode and electrically connected to the fourth electrode, and a fourth sub-electrode disposed on (or in) the same layer as the fifth electrode and electrically connected to the fifth electrode. The fourth sub-electrode of the first sub-pixel may be electrically connected to the fourth sub-electrode of the second sub-pixel.

[0016] In an implementation, the first to fifth electrodes and the first to fourth sub-electrodes may include the same material.

[0017] In an embodiment, the bridge pattern of the first sub-pixel, the bridge pattern of the third sub-pixel, and the bridge pattern of the second sub-pixel may be sequentially arranged in the second direction in a plan view. The second alignment electrode may have a plate shape, extend in the second direction, and overlap with the bridge pattern of the first sub-pixel, the bridge pattern of the third sub-pixel, and the bridge pattern of the second sub-pixel.

[0018] In an embodiment, in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, the gate electrode of the first transistor, the source electrode of the second transistor, and the bridge pattern electrically connected to each other may form a first node. The second alignment electrode may be a shielding member to prevent parasitic capacitance from occurring between first nodes of sub-pixels arranged adjacent to each other in the second direction among the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0019] In an embodiment, for each of the first, second, and third subpixels, the display device may further include a data line configured to transmit a data signal and extending in the second direction. The data line may have a width of about 7 μm in the first direction intersecting the second direction.

[0020] In an embodiment, the display device may further include a first color conversion layer arranged in a first subpixel and a first color filter arranged on the first color conversion layer, a second color conversion layer arranged in a second subpixel and a second color filter arranged on the second color conversion layer, and a third color conversion layer arranged in a third subpixel and a third color filter arranged on the third color conversion layer.

[0021] Embodiments of the present disclosure may provide a display device, the display device comprising: a substrate; a first sub-pixel, a third sub-pixel, and a second sub-pixel arranged adjacent to each other in a second direction, each including an emission region and a non-emission region and arranged on the substrate; a first data line configured to apply a data signal to the first sub-pixel, a second data line configured to apply a data signal to the second sub-pixel, and a third data line configured to apply a data signal to the third sub-pixel; a plurality of light-emitting elements arranged in the emission region of each of the first to third sub-pixels; a first transistor, a second transistor, and a third transistor positioned between the substrate and the plurality of light-emitting elements and electrically connected to the plurality of light-emitting elements; a bridge pattern electrically connecting a gate electrode of the first transistor and a source electrode of the second transistor; a first alignment electrode and a second alignment electrode positioned between the bridge pattern and the plurality of light-emitting elements and arranged to be spaced apart from each other; and a plurality of electrodes arranged on the first alignment electrode and the second alignment electrode and electrically connected to the plurality of light-emitting elements. In a plan view, the second alignment electrode may overlap with the bridge pattern of the first sub-pixel, the bridge pattern of the second sub-pixel, and the bridge pattern of the third sub-pixel.

[0022] In an implementation, the first alignment electrode may be a floating electrode, and the second alignment electrode may be supplied with a low potential voltage.

[0023] In an embodiment, the display device may further include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer arranged between the substrate and the first alignment electrode and sequentially stacked on the substrate. The source electrode of the second transistor may be arranged on the first insulating layer, the gate electrode of the first transistor may be arranged on the second insulating layer and the bridge pattern may be arranged on the third insulating layer, and the first alignment electrode and the second alignment electrode may be arranged on the fifth insulating layer. The first end of the bridge pattern may be electrically connected to the source electrode of the second transistor through a first contact hole formed through the second insulating layer and the third insulating layer. The second end of the bridge pattern may be electrically connected to the gate electrode of the first transistor through a second contact hole formed through the third insulating layer.

[0024] In an implementation, the second alignment electrode may overlap the first contact hole and the second contact hole in a plan view.

[0025] In an implementation, the first, second, and third data lines may be sequentially arranged in a first direction intersecting the second direction. Each of the first, second, and third data lines may have a width of about 7 μm in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic perspective view showing a light emitting element according to an embodiment.

[0027] Figure 2 It is shown Figure 1 Schematic cross-sectional view of a light-emitting element.

[0028] Figure 3 is a schematic plan view showing a display device according to an embodiment.

[0029] Figure 4 It is shown Figure 3 Schematic cross-sectional view of each of the pixels shown in FIG.

[0030] Figure 5 It is shown that the Figure 3 A schematic circuit diagram of the electrical connection relationship of components in each of the pixels shown in FIG.

[0031] Figure 6 is a schematic plan view showing a pixel circuit layer of a pixel according to an embodiment.

[0032] Figure 7 is shown only in Figure 6 Schematic plan view of components in the first conductive layer in a pixel of .

[0033] Figure 8 are transistors shown and only include Figure 6Schematic plan view of components in the second conductive layer in a pixel of .

[0034] Fig. 9 is along Figure 6 A schematic cross-sectional view taken along line II'.

[0035] Fig.10 is a schematic plan view showing a display element layer of a pixel according to an embodiment.

[0036] Fig.11 It is shown Fig.10 Schematic plan view of a first sub-pixel.

[0037] Fig.12 is along Fig.11 A schematic cross-sectional view taken along line II-II'.

[0038] Fig.13 is a schematic cross-sectional view showing first to third sub-pixels according to an embodiment.

[0039] Fig.14 It is shown based on Figure 6 Schematic plan view of a pixel including an alignment electrode.

[0040] Fig.15 yes Fig.14 Schematic enlarged view of a portion of EA.

[0041] Fig.16 is along Fig.15 A schematic cross-sectional view taken along line III-III'.

[0042] Fig.17 According to another embodiment Fig.14 Schematic enlarged view of a portion of EA.

[0043] Fig.18 is along Fig.17 Schematic cross-sectional view taken along line IV-IV'.

[0044] Fig.19 According to another embodiment Fig.14 Schematic enlarged view of a portion of EA.

[0045] Fig. 20 is along Fig.19 A schematic cross-sectional view taken along line V-V'. DETAILED DESCRIPTION

[0046] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific mode of practice, and it should be appreciated that all changes, equivalents and substitutes that do not depart from the technical scope of the present disclosure are included in the present disclosure.

[0047] Throughout the present disclosure, throughout the various figures and embodiments of the present disclosure, similar reference numerals refer to similar parts. For the clarity of the illustration, the size of the elements in the accompanying drawings may be exaggerated. It will be understood that, although the terms "first", "second", etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0048] It will also be understood that when the terms "comprise", "include", "have", etc. are used in this specification, the existence of the stated features, integers, steps, operations, elements, components and / or combinations thereof is described, but the existence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof is not excluded. In addition, in the case where a first part such as a layer, film, zone or plate is arranged on a second part, the first part may not only be directly on the second part, but also a third part may be placed between them. In addition, in the case where it is stated that a first part such as a layer, film, zone or plate is formed on a second part, the surface of the second part on which the first part is formed is not limited to the upper surface of the second part, but may include other surfaces such as the side surface or the lower surface of the second part. Conversely, in the case where a first part such as a layer, film, zone or plate is below the second part, the first part may not only be directly below the second part, but also a third part may be placed between them.

[0049] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings in order to describe the present disclosure in detail so that a person skilled in the art to which the present disclosure belongs can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

[0050] Figure 1 is a schematic perspective view showing a light emitting element LD according to an embodiment. Figure 2 It is shown Figure 1 Schematic cross-sectional view of a light emitting element LD.

[0051] Reference Figure 1 and Figure 2, the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be implemented as an emission stack (or referred to as a "stacked pattern") formed by sequentially stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0052] The light emitting element LD may be formed in a shape extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end EP1 and a second end EP2 opposite to each other with respect to the longitudinal direction. For example, the second semiconductor layer 13 may be arranged on the first end EP1 of the light emitting element LD, and the first semiconductor layer 11 may be arranged on the second end EP2 of the light emitting element LD. However, the present disclosure is not limited to the foregoing examples.

[0053] The light emitting element LD can be provided in various shapes. Figure 1 As shown in , the light emitting element LD may have a rod-like shape, a bar-like shape, or a column-like shape that is long with respect to the longitudinal direction (eg, has an aspect ratio greater than 1). However, the present disclosure is not limited to the foregoing examples.

[0054] The light emitting element LD may include a light emitting diode (LED) manufactured to have an ultra-small size (eg, having a diameter D and / or a length L corresponding to a range from a nanometer scale to a micrometer scale).

[0055] In the case where the light emitting element LD is long relative to the longitudinal direction (for example, having an aspect ratio greater than 1), the diameter D of the light emitting element LD may be in the range of about 0.5 μm to 6 μm, and the length L of the light emitting element LD may be in the range of about 1 μm to 10 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto. The size of the light emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or the self-emitting display device to which the light emitting element LD is applied.

[0056] For example, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive dopant (or n-type dopant) such as Si, Ge, or Sn. However, the constituent material of the first semiconductor layer 11 is not limited thereto, and various other materials may be used to form the first semiconductor layer 11.

[0057] The active layer 12 may be arranged on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. The active layer 12 may emit light having a wavelength range from 400 nm to 900 nm and have a double heterojunction. In an embodiment, a cladding layer doped with a conductive dopant may be formed above or below the active layer 12 relative to the longitudinal direction of the light emitting element LD.

[0058] If an electric field having a certain voltage or more is applied between opposite ends of the light emitting element LD, the light emitting element LD can emit light by coupling of electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the foregoing principle, the light emitting element LD can be used as a light source (light emitting source) of various light emitting devices and a pixel of a display device.

[0059] The second semiconductor layer 13 may be arranged on the active layer 12 and include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer containing at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, or Ba. However, the material used to form the second semiconductor layer 13 is not limited thereto, and various other materials may be used to form the second semiconductor layer 13.

[0060] The first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses relative to the longitudinal direction of the light emitting element LD. For example, the first semiconductor layer 11 may have a thickness greater than that of the second semiconductor layer 13 relative to the longitudinal direction of the light emitting element LD, but the present disclosure is not limited thereto.

[0061] In an embodiment, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light emitting element LD may further include a contact electrode (hereinafter referred to as a "first contact electrode") disposed above the second semiconductor layer 13. In addition, in an embodiment, the light emitting element LD may further include an additional contact electrode (hereinafter referred to as a "second contact electrode") disposed on one end of the first semiconductor layer 11. Each of the first contact electrode and the second contact electrode may be an ohmic contact electrode, but the present disclosure is not limited thereto. In an embodiment, each of the first contact electrode and the second contact electrode may be a Schottky contact electrode. The first contact electrode and the second contact electrode may include a conductive material.

[0062] In an embodiment, the light emitting element LD may further include an insulating film 14. However, according to an embodiment, the insulating film 14 may be omitted, or may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0063] The insulating film 14 can prevent the active layer 12 from being short-circuited due to contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating film 14 can minimize surface defects of the light-emitting element LD, thereby improving the life and emission efficiency of the light-emitting element LD. In the case where a plurality of light-emitting elements LD are arranged in close contact with each other, the insulating film 14 can prevent an undesired short circuit from occurring between the light-emitting elements LD. The presence or absence of the insulating film 14 is not limited as long as the active layer 12 can be prevented from being short-circuited with an external conductive material.

[0064] The insulating film 14 may be provided to surround the entire outer peripheral surface of the emission stack including the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .

[0065] The insulating film 14 may include a transparent insulating material. Various materials having insulating properties may be used as the material of the insulating film 14. The insulating film 14 may have a single-layer structure or a multi-layer structure including a double-layer structure.

[0066] In an embodiment, the light emitting element LD may be implemented as a light emitting pattern having a core-shell structure.

[0067] The light emitting element LD can be used as a light source (or light source) of various display devices. The light emitting element LD can be manufactured by a surface treatment process.

[0068] Figure 3 is a schematic plan view showing a display device DD according to an embodiment. Figure 4 It is shown Figure 3 A schematic cross-sectional view of each of the pixels PXL shown in FIG.

[0069] exist Figure 3 and Figure 4 , for convenience, the display device DD (eg, the structure of the display panel DP provided in the display device DD) is schematically illustrated with the display area DA displaying an image as the center.

[0070] Reference Figures 1 to 4 According to a method of driving the light emitting element LD, the display device DD may be classified into a passive matrix type display device and an active matrix type display device. For example, in the case where the display device DD is implemented as an active matrix type display device, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light emitting element LD and a switching transistor configured to transmit a data signal to the driving transistor.

[0071] The display panel DP (or display device DD) may include pixels PXL arranged on a substrate SUB. Each of the pixels PXL may include at least one light emitting element LD.

[0072] The substrate SUB may include a transparent insulating material to allow light to be transmitted. The substrate SUB may be a rigid substrate or a flexible substrate.

[0073] For example, the rigid substrate may be one of a glass substrate (eg, a glass ceramic substrate, a crystallized glass substrate) and a quartz substrate.

[0074] The flexible substrate may be a film substrate or a plastic substrate including a polymer organic material. For example, the flexible substrate SUB may include at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0075] One region of the substrate SUB may be provided as a display area DA where the pixels PXL are arranged, and another region of the substrate SUB may be provided as a non-display area NDA.

[0076] The display area DA may be an area where pixels PXL for displaying an image are arranged.

[0077] The non-display area NDA may be arranged adjacent to the display area DA. The non-display area NDA may be provided on at least one side of the display area DA. For example, the non-display area NDA may surround the periphery (or edge) of the display area DA. In the non-display area NDA, a driver for driving each pixel PXL and a signal line for connecting each pixel PXL to the driver may be placed.

[0078] The pixels PXL may be provided in the display area DA on the substrate SUB. The pixels PXL may be arranged in the display area DA in a stripe arrangement or the like, but the present disclosure is not limited thereto.

[0079] Each pixel PXL may include a pixel circuit layer PCL, a display element layer DPL, and an optical layer LCL disposed on a substrate SUB.

[0080] A pixel circuit (refer to Figure 5 The pixel circuit PXC) may be arranged in the pixel circuit layer PCL.

[0081] The display element layer DPL may be disposed on the pixel circuit layer PCL. An emission component including a light emitting element LD configured to emit light (refer to Figure 5The emission unit EMU) may be arranged in the display element layer DPL. In the emission unit EMU, an electrode electrically connected to the light emitting element LD may be arranged (refer to Fig.10 ).

[0082] The optical layer LCL may be disposed on the display element layer DPL. The optical layer LCL may convert light emitted from the light emitting element LD into light having excellent color reproducibility and emit the converted light, thereby improving the light output efficiency of each pixel PXL. In an embodiment, the optical layer LCL may include a color conversion layer, a color filter, and the like, but the present disclosure is not limited thereto.

[0083] In a certain area of ​​the display area DA (for example, a pixel area provided with the pixel PXL), a plurality of sub-pixels SPX may be provided, for example, a first sub-pixel (refer to Figure 6 The first sub-pixel SPX1), the second sub-pixel (refer to Figure 6 The second sub-pixel SPX2) and the third sub-pixel (refer to Figure 6 The first sub-pixel SPX1 may be a red pixel. The second sub-pixel SPX2 may be a green pixel. The third sub-pixel SPX3 may be a blue pixel. However, the present disclosure is not limited to the aforementioned examples. The first sub-pixel SPX1 may include a first pixel circuit and a first emission component. The second sub-pixel SPX2 may include a second pixel circuit and a second emission component. The third sub-pixel SPX3 may include a third pixel circuit and a third emission component.

[0084] The first pixel circuit, the second pixel circuit, and the third pixel circuit and the first emission component, the second emission component, and the third emission component may be arranged on (or in) different layers and overlap each other. For example, the first pixel circuit, the second pixel circuit, and the third pixel circuit may be arranged in the pixel circuit layer PCL of the corresponding sub-pixel SPX. The first emission component, the second emission component, and the third emission component may be arranged in the display element layer DPL overlapping the pixel circuit layer PCL in the corresponding sub-pixel SPX.

[0085] Figure 5 It is shown that the Figure 3 Schematic circuit diagram of the electrical connection relationship of components in each of the pixels PXL shown in FIG.

[0086] For example, Figure 5 The electrical connection relationship of components included in the pixel PXL (or sub-pixel SPX) that can be adopted in the active matrix display device according to the embodiment is shown. Here, the connection relationship of the components of each pixel PXL (or each sub-pixel SPX) is not limited thereto.

[0087] Reference Figures 1 to 5The sub-pixel SPX (or pixel PXL) may include an emission part EMU configured to generate light having brightness corresponding to the data signal. In addition, the sub-pixel SPX may further include a pixel circuit PXC configured to drive the emission part EMU.

[0088] The emission unit EMU may include a first electrode ELT1 (or a first pixel electrode) electrically connected to a first driving power source VDD via a pixel circuit PXC and a first power line PL1, a fifth electrode ELT5 (or a second pixel electrode) connected to a second driving power source VSS via a second power line PL2, and a plurality of light emitting elements LD connected between the first electrode ELT1 and the second electrode ELT2. The first driving power source VDD and the second driving power source VSS may have different potentials to allow the light emitting element LD to emit light. For example, the first driving power source VDD may be a high potential power source, and the second driving power source VSS may be a low potential power source.

[0089] In an embodiment, the emission unit EMU may include at least one series connection stage. Each series connection stage may include a pair of electrodes (e.g., two electrodes) and at least one light emitting element LD connected in a forward direction between the pair of electrodes. The number of series connection stages forming the emission unit EMU and the number of light emitting elements LD forming each series connection stage are not particularly limited. For example, the number of light emitting elements LD forming the corresponding series connection stages may be the same or different from each other. The number of light emitting elements LD of each series connection stage is not particularly limited.

[0090] For example, the emission unit EMU may include a first series stage including at least one first light emitting element LD1, a second series stage including at least one second light emitting element LD2, a third series stage including at least one third light emitting element LD3, and a fourth series stage including at least one fourth light emitting element LD4.

[0091] The first series stage may include a first electrode ELT1, a second electrode ELT2 (or a first bridging electrode), and at least one first light emitting element LD1 connected between the first electrode ELT1 and the second electrode ELT2. Each first light emitting element LD1 may be connected between the first electrode ELT1 and the second electrode ELT2 in a forward direction. For example, a first end EP1 of the first light emitting element LD1 may be electrically connected to the first electrode ELT1. A second end EP2 of the first light emitting element LD1 may be electrically connected to the second electrode ELT2.

[0092] The second series stage may include a second electrode ELT2, a third electrode ELT3 (or a second bridging electrode), and at least one second light emitting element LD2 connected between the second electrode ELT2 and the third electrode ELT3. Each second light emitting element LD2 may be connected between the second electrode ELT2 and the third electrode ELT3 in the forward direction. For example, a first end EP1 of the second light emitting element LD2 may be electrically connected to the second electrode ELT2. A second end EP2 of the second light emitting element LD2 may be electrically connected to the third electrode ELT3.

[0093] The third series stage may include a third electrode ELT3, a fourth electrode ELT4 (or a third bridging electrode), and at least one third light emitting element LD3 connected between the third electrode ELT3 and the fourth electrode ELT4. Each third light emitting element LD3 may be connected between the third electrode ELT3 and the fourth electrode ELT4 in the forward direction. For example, a first end EP1 of the third light emitting element LD3 may be electrically connected to the third electrode ELT3. A second end EP2 of the third light emitting element LD3 may be electrically connected to the fourth electrode ELT4.

[0094] The fourth series stage may include a fourth electrode ELT4, a fifth electrode ELT5, and at least one fourth light emitting element LD4 connected between the fourth electrode ELT4 and the fifth electrode ELT5. Each fourth light emitting element LD4 may be connected between the fourth electrode ELT4 and the fifth electrode ELT5 in the forward direction. For example, a first end EP1 of the fourth light emitting element LD4 may be electrically connected to the fourth electrode ELT4. A second end EP2 of the fourth light emitting element LD4 may be electrically connected to the fifth electrode ELT5.

[0095] The first electrode (eg, the first electrode ELT1 ) of the emission component EMU may be an anode of the emission component EMU. The last electrode (eg, the fifth electrode ELT5 ) of the emission component EMU may be a cathode of the emission component EMU.

[0096] In the case where the light-emitting elements LD are connected to have a series / parallel structure, power efficiency can be improved compared to the case where the same number of light-emitting elements LD are connected only in parallel to each other. In addition, in the sub-pixel SPX in which the light-emitting elements LD are connected in a series / parallel structure, even if a short circuit defect or the like occurs in some series stages, sufficient brightness can be exhibited by the light-emitting elements LD of other series stages, so that the possibility of black spot defects occurring in the sub-pixel SPX can be reduced. However, the present disclosure is not limited thereto. The emission component EMU can be formed by connecting only the light-emitting elements LD in series. Alternatively, the emission component EMU can be formed by connecting only the light-emitting elements LD in parallel.

[0097] Each of the light emitting elements LD may include a first terminal EP1 (e.g., a p-type terminal) electrically connected to a first driving power source VDD via at least one electrode (e.g., a first electrode ELT1), a pixel circuit PXC, a first power line PL1, and / or the like, and a second terminal EP2 (e.g., an n-type terminal) electrically connected to a second driving power source VSS via at least one additional electrode (e.g., a fifth electrode ELT5), a second power line PL2, and the like. In other words, the light emitting element LD may be connected between the first driving power source VDD and the second driving power source VSS in a forward direction. The light emitting element LD connected in the forward direction may form an effective light source of the emission unit EMU.

[0098] The light emitting element LD may emit light having a brightness corresponding to the driving current when a driving current is supplied thereto through the corresponding pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply a driving current corresponding to a grayscale value to be represented in the corresponding frame to the emission unit EMU. The driving current supplied to the emission unit EMU may flow into the corresponding light emitting element LD. Therefore, each of the light emitting elements LD may emit light having a brightness corresponding to the current applied thereto, so that the emission unit EMU may represent a brightness corresponding to the driving current.

[0099] The pixel circuit PXC may be electrically connected to the scan line Si and the data line Dj of the corresponding sub-pixel SPX. For example, if the sub-pixel SPX is arranged on the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the sub-pixel SPX may be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In addition, the pixel circuit PXC may be electrically connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA.

[0100] The pixel circuit PXC may include first, second and third transistors T1, T2 and T3 and a storage capacitor Cst.

[0101] The first transistor T1 may be a driving transistor configured to control a driving current applied to the emission component EMU, and may be connected between the first driving power supply VDD and the emission component EMU. In detail, the first terminal of the first transistor T1 may be electrically connected to the first driving power supply VDD via the first power line PL1. The second terminal of the first transistor T1 may be electrically connected to the second node N2. The gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the emission component EMU from the first driving power supply VDD through the second node N2 in response to the voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode.

[0102] The second transistor T2 may be a switching transistor configured to select the sub-pixel SPX in response to the scan signal and activate the sub-pixel SPX, and may be electrically connected between the j-th data line Dj and the first node N1. The first terminal of the second transistor T2 may be electrically connected to the j-th data line Dj. The second terminal of the second transistor T2 may be electrically connected to the first node N1. The gate electrode of the second transistor T2 may be electrically connected to the i-th scan line Si. The first terminal of the second transistor T2 may be a drain electrode, and the second terminal of the second transistor T2 may be a source electrode.

[0103] In the case where a scan signal of a gate-on voltage (e.g., a high level voltage) is supplied from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the first node N1. The first node N1 may be a connection point where the second terminal (e.g., a source electrode) of the second transistor T2 and the gate electrode of the first transistor T1 are electrically connected to each other. The second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0104] The third transistor T3 can obtain a sensing signal through the jth sensing line SENj by electrically connecting the first transistor T1 to the jth sensing line SENj, and use the sensing signal to detect the characteristics of the sub-pixel SPX (such as the threshold voltage of the first transistor T1). Information related to the characteristics of each sub-pixel SPX can be used to compensate the image data so that the characteristic deviation between the sub-pixels SPX can be reduced. The second terminal of the third transistor T3 can be electrically connected to the second terminal of the first transistor T1. The first terminal of the third transistor T3 can be electrically connected to the jth sensing line SENj. The gate electrode of the third transistor T3 can be electrically connected to the i-th control line CLi. The first terminal of the third transistor T3 can be a drain electrode, and the second terminal of the third transistor T3 can be a source electrode.

[0105] The third transistor T3 may be an initialization transistor configured to initialize the second node N2 and may be turned on when a sensing control signal is supplied thereto from the i-th control line CLi to enable a voltage of an initialization power source to be transmitted to the second node N2.

[0106] The storage capacitor Cst may include a first storage electrode (or lower electrode) and a second storage electrode (or upper electrode). The first storage electrode may be electrically connected to the first node N1. The second storage electrode may be electrically connected to the second node N2. The storage capacitor Cst may be charged with a data voltage corresponding to a data signal to be supplied to the first node N1 during one frame period. Therefore, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0107] although Figure 5An embodiment in which all of the first transistor T1 , the second transistor T2 , and the third transistor T3 are N-type transistors is shown, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 , the second transistor T2 , and the third transistor T3 may be a P-type transistor.

[0108] The structure of the pixel circuit PXC may be changed in various ways.

[0109] In an embodiment, for the purpose of explanation, the horizontal direction (or X-axis direction) in a plane view will be designated as a first direction DR1, the vertical direction (or Y-axis direction) in the plane view will be designated as a second direction DR2, and the vertical direction perpendicular to the plane formed by the first direction DR1 and the second direction DR2 will be designated as a third direction DR3.

[0110] Figure 6 is a schematic plan view showing a pixel circuit layer PCL of a pixel PXL according to an embodiment. Figure 7 is shown only in Figure 6 Schematic plan view of components in the first conductive layer C1 in the pixel PXL. Figure 8 are transistors shown and only include Figure 6 Schematic plan view of components in the second conductive layer C2 in the pixel PXL. Fig. 9 is along Figure 6 A schematic cross-sectional view taken along line II'. Fig.10 is a schematic plan view showing a display element layer DPL of a pixel PXL according to an embodiment. Fig.11 It is shown Fig.10 Schematic plan view of a first sub-pixel SPX1. Fig.12 is along Fig.11 A schematic cross-sectional view taken along line II-II'.

[0111] exist Figures 6 to 12 In the defined term “pixel PXL”, not only components included in the pixel PXL but also a region where the components are provided (or where the components are located) are included.

[0112] Reference Figures 1 to 12 The pixel PXL may include a plurality of sub-pixels SPX. For example, the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0113] The first sub-pixel SPX1 may include a first pixel circuit PXC1 and a first emission component EMU1. The second sub-pixel SPX2 may include a second pixel circuit PXC2 and a second emission component EMU2. The third sub-pixel SPX3 may include a third pixel circuit PXC3 and a third emission component EMU3.

[0114] The pixel area PXA may include a first pixel circuit area PXCA1, a third pixel circuit area PXCA3, and a second pixel circuit area PXCA2 arranged along the second direction DR2. The first pixel circuit area PXCA1 may be an area where the first pixel circuit PXC1 is arranged. The second pixel circuit area PXCA2 may be an area where the second pixel circuit PXC2 is arranged. The third pixel circuit area PXCA3 may be an area where the third pixel circuit PXC3 is arranged.

[0115] The pixel area PXA may include a signal line area LA provided around each of the first pixel circuit area PXCA1 and the second pixel circuit area PXCA2 and / or in a portion of the pixel area PXA. For example, the signal line area LA may be provided at the upper side of the first pixel circuit area PXCA1 and the lower side of the second pixel circuit area PXCA2. The signal line area LA may be an area where some signal lines extending in the first direction DR1 are arranged. For example, in the signal line area LA, a scan line SC and a first horizontal power line PL1b extending in the first direction DR1 may be arranged.

[0116] The pixel area PXA may include first, second, and third emission areas EMA1, EMA2, and EMA3 arranged along the first direction DR1.

[0117] The first emission area EMA1 may be an area where light is emitted from the light emitting element LD driven by the first pixel circuit PXC1. The first emission area EMA1 may be an emission area of ​​the first sub-pixel SPX1. The second emission area EMA2 may be an area where light is emitted from the light emitting element LD driven by the second pixel circuit PXC2. The second emission area EMA2 may be an emission area of ​​the second sub-pixel SPX2. The third emission area EMA3 may be an area where light is emitted from the light emitting element LD driven by the third pixel circuit PXC3. The third emission area EMA3 may be an emission area of ​​the third sub-pixel SPX3.

[0118] The first emission area EMA1 , the second emission area EMA2 , and the third emission area EMA3 may form an emission area EMA of the pixel PXL.

[0119] The pixel area PXA may include a non-emission area NEA disposed adjacent to (or surrounding the periphery of) each of the first, second, and third emission areas EMA1, EMA2, and EMA3.

[0120] The pixel circuit layer PCL and the display element layer DPL may be arranged in the pixel PXL (or the pixel area PXA) on the substrate SUB. The pixel circuit layer PCL and the display element layer DPL may include a plurality of insulating layers. For example, the pixel circuit layer PCL may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, and a fifth insulating layer INS5 continuously stacked on the substrate SUB. The display element layer DPL may include a sixth insulating layer INS6 and a seventh insulating layer INS7 continuously stacked on the pixel circuit layer PCL.

[0121] The first insulating layer INS1 (or buffer layer) may be arranged on the entire surface of the substrate SUB. The first insulating layer INS1 may prevent impurities from diffusing into the first transistor T1, the second transistor T2, and the third transistor T3 included in the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. The first insulating layer INS1 may be an inorganic layer including an inorganic material. The first insulating layer INS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ). Although the first insulating layer INS1 may have a single-layer structure, the first insulating layer INS1 may have a multi-layer structure having at least two or more layers. Depending on the material or processing conditions of the substrate SUB, the first insulating layer INS1 may be omitted.

[0122] The second insulating layer INS2 (or gate insulating layer) may be arranged on the entire surface of the first insulating layer INS1. The second insulating layer INS2 may include the same material as that of the first insulating layer INS1, or may include a suitable (or selected) material among the materials exemplified as the constituent materials of the first insulating layer INS1. For example, the second insulating layer INS2 may be formed of an inorganic layer including an inorganic material.

[0123] The third insulating layer INS3 (or interlayer insulating layer) may be arranged on the entire surface of the second insulating layer INS2. The third insulating layer INS3 may include the same material as that of the first insulating layer INS1, or may include one or more suitable (or selected) materials among the materials exemplified as the constituent materials of the first insulating layer INS1.

[0124] The fourth insulating layer INS4 (or a passivation layer) may be disposed on the entire surface of the third insulating layer INS3. The fourth insulating layer INS4 may be an inorganic layer including an inorganic material or an organic layer including an organic material.

[0125] The fifth insulating layer INS5 (or the through hole layer) may be arranged on the entire surface of the fourth insulating layer INS4. The fifth insulating layer INS5 may be an inorganic layer including an inorganic material or an organic layer including an organic material. The inorganic layer may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x The organic layer may include, for example, at least one of polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0126] The sixth insulating layer INS6 may be disposed on the entire surface of the pixel circuit layer PCL. The sixth insulating layer INS6 may be formed of a single layer or a plurality of layers, and include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ) various inorganic materials (or substances).

[0127] The seventh insulating layer INS7 may be arranged on the sixth insulating layer INS6. The seventh insulating layer INS7 may include the same material as that of the sixth insulating layer INS6, or may include one or more suitable (or selected) materials among the materials exemplified as the constituent materials of the sixth insulating layer INS6. However, the present disclosure is not limited to the foregoing examples. For example, the seventh insulating layer INS7 may include an organic insulating layer including an organic material.

[0128] The pixel PXL may include at least one or more conductive layers arranged between the above-mentioned insulating layers. For example, the conductive layer may include a first conductive layer C1 arranged on a substrate SUB, a second conductive layer C2 arranged on a second insulating layer INS2, a third conductive layer C3 arranged on a third insulating layer INS3, a fourth conductive layer C4 arranged on a fifth insulating layer INS5, and a fifth conductive layer C5 arranged on a seventh insulating layer INS7. However, the insulating layer and the conductive layer are not limited to those of the previous embodiments. In some embodiments, in addition to the insulating layer and the conductive layer, other insulating layers and other conductive layers may be arranged on the substrate SUB. The first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 may be arranged in the pixel circuit layer PCL of the pixel PXL. The fourth conductive layer C4 and the fifth conductive layer C5 may be arranged in the display element layer DPL of the pixel PXL.

[0129] Signal lines electrically connected to the pixels PXL may be formed on the substrate SUB. The signal lines may transmit certain signals (or certain voltages) to the pixels PXL. For example, the signal lines may include scan lines SC, data lines D1, D2, and D3, power lines PL, and initialization power lines IPL.

[0130] The scan signal and the sensing control signal may be selectively applied to the scan line SC. The scan line SC may extend in the first direction DR1. The scan line SC may be formed of a third conductive layer C3. The third conductive layer C3 may be formed of a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and oxides thereof or alloys thereof.

[0131] The scan line SC may be disposed on the sub-scan line SS1 and may be electrically connected to the sub-scan line SS1 through a contact hole. For example, the scan line SC may be electrically connected to the sub-scan line SS1 through a contact hole formed through the third insulating layer INS3.

[0132] The sub-scan line SS1 may extend in the second direction DR2. The sub-scan line SS1 may be formed of a second conductive layer C2. The second conductive layer C2 may be formed of a single-layer structure or a multi-layer structure made of molybdenum (Mo), copper (Cu), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and oxides thereof or alloys thereof. For example, the second conductive layer C2 may have a multi-layer structure formed by continuously or sequentially stacking titanium (Ti), copper (Cu), and / or indium tin oxide (ITO).

[0133] In an embodiment, the sub-scan line SS1 may be provided integrally with the second gate electrode GE2 of the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. For example, a portion of the sub-scan line SS1 may be the second gate electrode GE2 of the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. Therefore, the sub-scan line SS1 may be connected to the second gate electrode GE2 of the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3.

[0134] In addition, the sub-scan line SS1 may be provided integrally with the third gate electrode GE3 of the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. For example, another portion of the sub-scan line SS1 may be the third gate electrode GE3 of the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. Therefore, the sub-scan line SS1 may be connected to the third gate electrode GE3 of the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3.

[0135] Since the sub-scan line SS1 is electrically connected to the scan line SC through the contact hole, the scan line SC may be electrically connected to some components (e.g., the second transistor T2 and the third transistor T3) of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 via the sub-scan line SS1. In this case, the scan line SC may supply a scan signal to the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 during a driving period of the light emitting element LD, and may supply a sensing control signal to the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 during a sensing period.

[0136] The sub scan line SS1 may be a common component commonly provided to the first pixel circuit PXC1 , the second pixel circuit PXC2 , and the third pixel circuit PXC3 .

[0137] The data lines D1, D2, and D3 may include first, second, and third data lines D1, D2, and D3 extending in the second direction DR2 and spaced apart from each other in the first direction DR1. Each of the first, second, and third data lines D1, D2, and D3 may be supplied with a corresponding data signal.

[0138] The first data line D1 may be electrically connected to the second transistor T2 of the first pixel circuit PXC1. The second data line D2 may be electrically connected to the second transistor T2 of the second pixel circuit PXC2. The third data line D3 may be electrically connected to the second transistor T2 of the third pixel circuit PXC3. Each of the first data line D1, the second data line D2, and the third data line D3 may be formed of a first conductive layer C1. The first conductive layer C1 may include the same material as that of the third conductive layer C3, or may include one or more suitable materials among the materials exemplified as the constituent materials of the third conductive layer C3, but the present disclosure is not limited thereto.

[0139] The first data line D1, the second data line D2, and the third data line D3 may have similar or identical line widths in the first direction DR1 at least in the pixel area PXA. For example, the first data line D1 may have a line width d1 of about 7 μm, the second data line D2 may have a line width d2 of about 7 μm, and the third data line D3 may have a line width d3 of about 7 μm.

[0140] The line width d1 of the first data line D1, the line width d2 of the second data line D2, and the line width d3 of the third data line D3 may be designed to be smaller than the line width of the data line arranged in a typical pixel. For example, the data line arranged in a typical pixel is designed to have a line width of about 10.5 μm. In an embodiment, the first data line D1, the second data line D2, and the third data line D3 may be designed to have a line width of about 7 μm at least in the pixel area PXA.

[0141] The power lines PL may include a first power line PL1 and a second power line PL2 .

[0142] The first driving power supply ( Figure 5 A voltage of a first driving power source VDD) may be applied to the first power line PL1. The first power line PL1 may include a first vertical power line PL1a and a first horizontal power line PL1b arranged in different layers and electrically connected to each other through a contact hole. For example, the first vertical power line PL1a may extend in the second direction DR2 and be formed by the first conductive layer C1. The first horizontal power line PL1b may extend in the first direction DR1 and be formed by the third conductive layer C3.

[0143] The first horizontal power line PL1b may include a dummy line PL1c protruding in the second direction DR2 and overlapping the first vertical power line PL1a (that is, the dummy line PL1c may be branched from the first horizontal power line PL1b). The dummy line PL1c may be formed by the third conductive layer C3. The first horizontal power line PL1b and the dummy line PL1c may be integrally formed and connected to each other. The dummy line PL1c may be electrically connected to the first vertical power line PL1a through a contact hole penetrating the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. The first power line PL1 may have a mesh structure because the first vertical power line PL1a and the first horizontal power line PL1b are connected to each other.

[0144] The first vertical power line PL1a and the dummy line PL1c may overlap the first additional conductive pattern ACP1 extending in the second direction DR2 and may be electrically connected to the first additional conductive pattern ACP1 through the contact holes.

[0145] The first additional conductive pattern ACP1 may be formed of the second conductive layer C2 and may be electrically connected to the dummy line PL1c through a contact hole formed through the third insulating layer INS3.

[0146] The first vertical power line PL1a may be electrically connected to the first additional conductive pattern ACP1 and the dummy line PL1c, and thus implemented as a three-layer structure. Therefore, the line resistance of the first vertical power line PL1a may be reduced, resulting in reduced signal distortion.

[0147] The first horizontal power line PL1 b may be connected to the floating pattern FTP of each of the first, second and third emission parts EMU1 , EMU2 and EMU3 through a via hole VIH formed through the fourth and fifth insulating layers INS4 and INS5 .

[0148] The second driving power supply ( Figure 5 The voltage of the second driving power source VSS) may be applied to the second power line PL2. The second power line PL2 may extend in the second direction DR2. The second power line PL2 may overlap each of the second additional conductive pattern ACP2 and the seventh conductive pattern CP7 extending in the second direction DR2. The second power line PL2 may be formed by the first conductive layer C1. The second additional conductive pattern ACP2 may be formed by the second conductive layer C2. The seventh conductive pattern CP7 may be formed by the third conductive layer C3.

[0149] The second power line PL2, the second additional conductive pattern ACP2, and the seventh conductive pattern CP7 arranged in different layers may be electrically connected to each other. For example, the seventh conductive pattern CP7 may be electrically connected to the second power line PL2 through a contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. The second additional conductive pattern ACP2 may be electrically connected to the seventh conductive pattern CP7 through a contact hole formed through the third insulating layer INS3. The second power line PL2 may be electrically connected to the second additional conductive pattern ACP2 and the seventh conductive pattern CP7, and thus implemented as a three-layer structure. Therefore, the line resistance of the second power line PL2 may be reduced, resulting in reduced signal distortion.

[0150] The initialization power line IPL may extend in the second direction DR2. Figure 5 The j-th sensing line SENj described. The voltage of the initialization power source may be applied to the initialization power line IPL. The initialization power line IPL may be formed of the first conductive layer C1. In an embodiment, the initialization power line IPL may overlap with the eighth conductive pattern CP8 extending in the second direction DR2 and may be electrically connected to the eighth conductive pattern CP8 through a contact hole.

[0151] The eighth conductive pattern CP8 may be formed of the third conductive layer C3 and may be electrically connected to the initialization power line IPL through a contact hole penetrating the first, second, and third insulating layers INS1, INS2, and INS3.

[0152] The eighth conductive pattern CP8 may include a first sub-electrode SUE1 and a second sub-electrode SUE2 extending in the first direction DR1 (that is, the first sub-electrode SUE1 and the second sub-electrode SUE2 may be branched from the eighth conductive pattern CP8). The first sub-electrode SUE1 and the second sub-electrode SUE2 may be formed integrally with the eighth conductive pattern CP8 formed by the third conductive layer C3. The first sub-electrode SUE1 may extend from the eighth conductive pattern CP8 along the first direction DR1 and be positioned on the upper side of the second additional conductive pattern ACP2. The second sub-electrode SUE2 may extend from the eighth conductive pattern CP8 along the first direction DR1 and be positioned on the lower side of the second additional conductive pattern ACP2.

[0153] A first end of the first sub-electrode SUE1 extends from the eighth conductive pattern CP8 and is electrically connected to the initialization power line IPL. A second end of the first sub-electrode SUE1 is electrically connected to the third drain electrode DE3 of the third transistor T3 of the first pixel circuit PXC1 through a contact hole formed through the second and third insulating layers INS2 and INS3.

[0154] A first end of the second sub-electrode SUE2 may extend from the eighth conductive pattern CP8 and be electrically connected to the initialization power line IPL. A second end of the second sub-electrode SUE2 may be electrically connected to the third drain electrode DE3 of the third transistor T3 of each of the second pixel circuit PXC2 and the third pixel circuit PXC3 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3.

[0155] The initialization power line IPL may be electrically connected to the eighth conductive pattern CP8 and thus implemented as a double-layer structure. Therefore, the line resistance of the initialization power line IPL may be reduced, resulting in reduced signal distortion.

[0156] The first power line PL1 , the second power line PL2 , the initialization power line IPL, the sub-scan line SS1 , and the scan line SC may be common components commonly provided in the first pixel circuit PXC1 , the second pixel circuit PXC2 , and the third pixel circuit PXC3 .

[0157] Each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. For example, the first pixel circuit PXC1 may include a first transistor T1, a second transistor T2, a third transistor T3, and a first storage capacitor Cst1. The second pixel circuit PXC2 may include a first transistor T1, a second transistor T2, a third transistor T3, and a second storage capacitor Cst2. The third pixel circuit PXC3 may include a first transistor T1, a second transistor T2, a third transistor T3, and a third storage capacitor Cst3.

[0158] The first transistor T1 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may correspond to Figure 5 The second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may correspond to Figure 5 The third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may correspond to Figure 5 The third transistor T3.

[0159] The first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may have substantially similar or identical structures. Hereinafter, the first pixel circuit PXC1 among the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 will be described as a representative example, and the description of the second pixel circuit PXC2 and the third pixel circuit PXC3 will be simplified.

[0160] The first pixel circuit PXC1 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , and a first storage capacitor Cst1 .

[0161] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , and a first drain electrode DE1 .

[0162] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 through the first conductive pattern CP1. The first gate electrode GE1 may be formed of the second conductive layer C2.

[0163] The first conductive pattern CP1 may be arranged in a region corresponding to the first node N1, which is a connection portion where the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 are electrically connected to each other. The first conductive pattern CP1 may be formed by the third conductive layer C3. The first end of the first conductive pattern CP1 may be electrically connected to the first gate electrode GE1 through a contact hole formed through the third insulating layer INS3. The second end of the first conductive pattern CP1 may be electrically connected to the second source electrode SE2 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. The first conductive pattern CP1 may be a bridge pattern BRP configured to electrically connect the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 to each other. The first conductive pattern CP1 (or the bridge pattern BRP), the first gate electrode GE1 of the first transistor T1, and the second source electrode SE2 of the second transistor T2 may constitute the first node N1 of the first pixel circuit PXC1.

[0164] Each of the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, or the like. Each of the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the first source electrode SE1 and the first drain electrode DE1 may be formed of a semiconductor layer doped with impurities. The first active pattern ACT1 may be formed of an undoped semiconductor layer.

[0165] The first active pattern ACT1 , the first source electrode SE1 , and the first drain electrode DE1 may be disposed on the first insulating layer INS1 .

[0166] The first active pattern ACT1 may be a channel region of the first transistor T1 overlapping the first gate electrode GE1 .

[0167] The first source electrode SE1 may be connected to a first end of the first active pattern ACT1 The first source electrode SE1 may be electrically connected to the first upper electrode UE1 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3 .

[0168] The first drain electrode DE1 may be connected to the second end of the first active pattern ACT1 The first drain electrode DE1 may be electrically connected to the dummy line PL1c of the first horizontal power line PL1b through a contact hole formed through the second and third insulating layers INS2 and INS3.

[0169] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0170] The second gate electrode GE2 may be formed of the second conductive layer C2. The second gate electrode GE2 may be formed integrally with the sub-scan line SS1 and correspond to a certain area of ​​the sub-scan line SS1. Since the sub-scan line SS1 is electrically connected to the scan line SC through the contact hole, a certain signal (e.g., a scan signal) applied to the scan line SC may be applied to the second gate electrode GE2.

[0171] Each of the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be a semiconductor pattern formed of amorphous silicon, an oxide semiconductor, or the like. Each of the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the second source electrode SE2 and the second drain electrode DE2 may be formed of a semiconductor layer doped with impurities. The second active pattern ACT2 may be formed of an undoped semiconductor layer. The second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be provided and / or formed on the first insulating layer INS1.

[0172] The second active pattern ACT2 may be a channel region of the second transistor T2 overlapping the second gate electrode GE2 .

[0173] The second source electrode SE2 may be connected to a first end of the second active pattern ACT2 The second source electrode SE2 may be electrically connected to the first gate electrode GE1 through the first conductive pattern CP1.

[0174] The second drain electrode DE2 may be connected to the second end of the second active pattern ACT2. The second drain electrode DE2 may be electrically connected to the first data line D1 through the second conductive pattern CP2.

[0175] The second conductive pattern CP2 may be formed of the third conductive layer C3. A first end of the second conductive pattern CP2 may be electrically connected to the first data line D1 through a contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. A second end of the second conductive pattern CP2 may be electrically connected to the second drain electrode DE2 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. The second drain electrode DE2 and the first data line D1 may be electrically connected to each other through the second conductive pattern CP2.

[0176] The third transistor T3 may include a third gate electrode GE3 , a third active pattern ACT3 , a third source electrode SE3 , and a third drain electrode DE3 .

[0177] The third gate electrode GE3 may be formed of the second conductive layer C2. The third gate electrode GE3 may be formed integrally with the sub-scan line SS1 and corresponds to another certain region of the sub-scan line SS1. Since the sub-scan line SS1 is connected to the scan line SC through the contact hole, a certain signal (e.g., a sensing control signal) applied to the scan line SC may be ultimately supplied to the third gate electrode GE3.

[0178] The third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may each be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, or the like. Each of the third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the third source electrode SE3 and the third drain electrode DE3 may be formed of a semiconductor layer doped with impurities. The third active pattern ACT3 may be formed of an undoped semiconductor layer.

[0179] The third active pattern ACT3 , the third source electrode SE3 , and the third drain electrode DE3 may be disposed on the first insulating layer INS1 .

[0180] The third active pattern ACT3 may correspond to a channel region of the third transistor T3 overlapping the third gate electrode GE3 .

[0181] The third source electrode SE3 may be connected to the first end of the third active pattern ACT3 The third source electrode SE3 may be electrically connected to the first upper electrode UE1 through a contact hole formed through the second and third insulating layers INS2 and INS3 .

[0182] The third drain electrode DE3 may be connected to the second end of the third active pattern ACT3 The third drain electrode DE3 may be electrically connected to the first sub-electrode SUE1 through a corresponding contact hole.

[0183] The first storage capacitor Cst1 may include a first lower electrode LE1 and a first upper electrode UE1. The first storage capacitor Cst1 may correspond to Figure 5 The storage capacitor Cst.

[0184] The first lower electrode LE1 may be provided integrally with the first gate electrode GE1. In this case, the first lower electrode LE1 may be a certain region of the first gate electrode GE1. The first lower electrode LE1 may be formed of the second conductive layer C2.

[0185] A first bottom metal pattern BML1 may be disposed under the first lower electrode LE1. The first bottom metal pattern BML1 and the first lower electrode LE1 may overlap each other.

[0186] The first bottom metal pattern BML1 may be formed of the first conductive layer C1. The first bottom metal pattern BML1 may be electrically connected to the first upper electrode UE1 through a contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. The first bottom metal pattern BML1 may be electrically connected to the first contact electrode CNE1 through another contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0187] The first contact electrode CNE1 may be formed of the third conductive layer C3. The first contact electrode CNE1 may be electrically connected to the first bottom metal pattern BML1 through a contact hole. The first contact electrode CNE1 may be electrically connected to the first electrode ELT1 of the first emission unit EMU1 through a first contact portion CNT1 formed through the fourth insulating layer INS4, the fifth insulating layer INS5, the sixth insulating layer INS6, and the seventh insulating layer INS7.

[0188] The first upper electrode UE1 may be arranged to overlap the first lower electrode LE1 in a plan view and have a size (or surface area) larger than that of the first lower electrode LE1, but the present disclosure is not limited thereto. In a plan view, the first upper electrode UE1 may overlap each of the first source electrode SE1 and the third source electrode SE3. The first upper electrode UE1 may be formed of a third conductive layer C3.

[0189] The first upper electrode UE1 may be electrically connected to the first bottom metal pattern BML1 through a contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. In addition, the first upper electrode UE1 may be electrically connected to the first source electrode SE1 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. In addition, the first upper electrode UE1 may be electrically connected to the third source electrode SE3 through another contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. The first upper electrode UE1, the first bottom metal pattern BML1, the first source electrode SE1, and the third source electrode SE3 may be electrically connected to each other.

[0190] The second pixel circuit PXC2 may include a first transistor T1, a second transistor T2, a third transistor T3, and a second storage capacitor Cst2.

[0191] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , and a first drain electrode DE1 .

[0192] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 .

[0193] The first active pattern ACT1 may be a channel region of the first transistor T1 .

[0194] The first source electrode SE1 may be connected to the first active pattern ACT1 The first source electrode SE1 may be electrically connected to the second upper electrode UE2 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3 .

[0195] The first drain electrode DE1 may be connected to the first active pattern ACT1 The first drain electrode DE1 may be electrically connected to the dummy line PL1c of the first horizontal power line PL1b through a contact hole formed through the second and third insulating layers INS2 and INS3.

[0196] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0197] The second gate electrode GE2 may be integrally provided with the sub-scan line SS1 and electrically connected with the scan line SC. The second gate electrode GE2 may be formed of a second conductive layer C2.

[0198] The second active pattern ACT2 may be a channel region of the second transistor T2 .

[0199] The second source electrode SE2 may be connected to the second active pattern ACT2 The second source electrode SE2 may be electrically connected to the first gate electrode GE1 through the third conductive pattern CP3.

[0200] The third conductive pattern CP3 may be arranged in a region corresponding to the first node N1, which is a connection portion where the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 are electrically connected to each other. The third conductive pattern CP3 may be formed by the third conductive layer C3. The first end of the third conductive pattern CP3 may be electrically connected to the second source electrode SE2 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. The second end of the third conductive pattern CP3 may be electrically connected to the first gate electrode GE1 through a contact hole formed through the third insulating layer INS3. The third conductive pattern CP3 may be a bridge pattern BRP configured to electrically connect the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 to each other. The third conductive pattern CP3 (or bridge pattern BRP), the first gate electrode GE1 of the first transistor T1, and the second source electrode SE2 of the second transistor T2 may constitute the first node N1 of the second pixel circuit PXC2.

[0201] The second drain electrode DE2 may be connected to the second active pattern ACT2. The second drain electrode DE2 may be electrically connected to the second data line D2 through the fourth conductive pattern CP4.

[0202] The fourth conductive pattern CP4 may be formed of the third conductive layer C3. A first end of the fourth conductive pattern CP4 may be electrically connected to the second data line D2 through a contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. A second end of the fourth conductive pattern CP4 may be electrically connected to the second drain electrode DE2 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. The second drain electrode DE2 and the second data line D2 may be electrically connected to each other through the fourth conductive pattern CP4.

[0203] The third transistor T3 may include a third gate electrode GE3 , a third active pattern ACT3 , a third source electrode SE3 , and a third drain electrode DE3 .

[0204] The third gate electrode GE3 may be formed of the second conductive layer C2. The third gate electrode GE3 may be integrally formed with the sub-scan line SS1, and electrically connected to the scan line SC.

[0205] The third active pattern ACT3 may be a channel region of the third transistor T3 .

[0206] The third source electrode SE3 may be connected to the third active pattern ACT3 The third source electrode SE3 may be electrically connected to the second upper electrode UE2 through a contact hole formed through the second and third insulating layers INS2 and INS3 .

[0207] The third drain electrode DE3 may be coupled to the third active pattern ACT3 The third drain electrode DE3 may be electrically connected to the second sub-electrode SUE2 through a corresponding contact hole.

[0208] The second storage capacitor Cst2 may include a second lower electrode LE2 and a second upper electrode UE2. The second storage capacitor Cst2 may correspond to Figure 5 The storage capacitor Cst.

[0209] The second lower electrode LE2 may be formed integrally with the first gate electrode GE1. In this case, the second lower electrode LE2 may be a certain region of the first gate electrode GE1. The second lower electrode LE2 may be formed of the second conductive layer C2.

[0210] A second bottom metal pattern BML2 may be disposed under the second lower electrode LE2. The second bottom metal pattern BML2 and the second lower electrode LE2 may overlap each other.

[0211] The second bottom metal pattern BML2 may be formed of the first conductive layer C1. The second bottom metal pattern BML2 may be electrically connected to the second upper electrode UE2 through a contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. The second bottom metal pattern BML2 may be electrically connected to the second contact electrode CNE2 through another contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0212] The second contact electrode CNE2 may be formed of the third conductive layer C3. The second contact electrode CNE2 may be electrically connected to the second bottom metal pattern BML2 through a contact hole. The second contact electrode CNE2 may be electrically connected to the first electrode ELT1 of the second emission unit EMU2 through a second contact portion CNT2 formed through the fourth insulating layer INS4, the fifth insulating layer INS5, the sixth insulating layer INS6, and the seventh insulating layer INS7.

[0213] The second upper electrode UE2 may be arranged to overlap with the second lower electrode LE2 in a plan view and have a size (or surface area) larger than that of the second lower electrode LE2, but the present disclosure is not limited thereto. In a plan view, the second upper electrode UE2 may overlap with each of the first source electrode SE1 and the third source electrode SE3. The second upper electrode UE2 may be formed of a third conductive layer C3.

[0214] The second upper electrode UE2 , the second bottom metal pattern BML2 , the first source electrode SE1 , and the third source electrode SE3 may be electrically connected to each other.

[0215] The third pixel circuit PXC3 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , and a third storage capacitor Cst3 .

[0216] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , and a first drain electrode DE1 .

[0217] The first gate electrode GE1 may be electrically connected to the second source electrode SE2 of the second transistor T2 .

[0218] The first active pattern ACT1 may be a channel region of the first transistor T1 .

[0219] The first source electrode SE1 may be connected to the first active pattern ACT1 The first source electrode SE1 may be electrically connected to the third upper electrode UE3 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3 .

[0220] The first drain electrode DE1 may be connected to the first active pattern ACT1 The first drain electrode DE1 may be electrically connected to the dummy line PL1c of the first horizontal power line PL1b through a contact hole formed through the second and third insulating layers INS2 and INS3.

[0221] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0222] The second gate electrode GE2 may be integrally provided with the sub-scan line SS1 and electrically connected with the scan line SC. The second gate electrode GE2 may be formed of a second conductive layer C2.

[0223] The second active pattern ACT2 may be a channel region of the second transistor T2 .

[0224] The second source electrode SE2 may be connected to the second active pattern ACT2 The second source electrode SE2 may be electrically connected to the first gate electrode GE1 through the fifth conductive pattern CP5.

[0225] The fifth conductive pattern CP5 may be arranged in a region corresponding to the first node N1, which is a connection portion where the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 are electrically connected to each other. The fifth conductive pattern CP5 may be formed by the third conductive layer C3. The first end of the fifth conductive pattern CP5 may be electrically connected to the first gate electrode GE1 through a contact hole formed through the third insulating layer INS3. The second end of the fifth conductive pattern CP5 may be electrically connected to the second source electrode SE2 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. The fifth conductive pattern CP5 may be a bridge pattern BRP configured to electrically connect the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 to each other. The fifth conductive pattern CP5 (or the bridge pattern BRP), the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 may constitute the first node N1 of the third pixel circuit PXC3.

[0226] The second drain electrode DE2 may be connected to the second active pattern ACT2. The second drain electrode DE2 may be electrically connected to the third data line D3 through the sixth conductive pattern CP6.

[0227] The sixth conductive pattern CP6 may be formed by the third conductive layer C3. A first end of the sixth conductive pattern CP6 may be electrically connected to the third data line D3 through a contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. A second end of the sixth conductive pattern CP6 may be electrically connected to the second drain electrode DE2 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. The second drain electrode DE2 and the third data line D3 may be electrically connected to each other through the sixth conductive pattern CP6.

[0228] The third transistor T3 may include a third gate electrode GE3 , a third active pattern ACT3 , a third source electrode SE3 , and a third drain electrode DE3 .

[0229] The third gate electrode GE3 may be formed of the second conductive layer C2. The third gate electrode GE3 may be integrally formed with the sub-scan line SS1, and electrically connected to the scan line SC.

[0230] The third active pattern ACT3 may be a channel region of the third transistor T3 .

[0231] The third source electrode SE3 may be connected to the third active pattern ACT3 The third source electrode SE3 may be electrically connected to the third upper electrode UE3 through a contact hole formed through the second and third insulating layers INS2 and INS3 .

[0232] The third drain electrode DE3 may be coupled to the third active pattern ACT3 The third drain electrode DE3 may be electrically connected to the second sub-electrode SUE2 through a corresponding contact hole.

[0233] The third storage capacitor Cst3 may include a third lower electrode LE3 and a third upper electrode UE3. The third storage capacitor Cst3 may correspond to Figure 5 The storage capacitor Cst.

[0234] The third lower electrode LE3 may be formed integrally with the first gate electrode GE1. In this case, the third lower electrode LE3 may be a certain region of the first gate electrode GE1. The third lower electrode LE3 may be formed of the second conductive layer C2.

[0235] A third bottom metal pattern BML3 may be disposed under the third lower electrode LE3. The third bottom metal pattern BML3 and the third lower electrode LE3 may overlap each other.

[0236] The third bottom metal pattern BML3 may be formed of the first conductive layer C1. The third bottom metal pattern BML3 may be electrically connected to the third upper electrode UE3 through a contact hole formed through the first, second, and third insulating layers INS1, INS2, and INS3.

[0237] The third upper electrode UE3 may be arranged to overlap the third lower electrode LE3 in a plan view and have a size (or surface area) larger than that of the third lower electrode LE3, but the present disclosure is not limited thereto. In a plan view, the third upper electrode UE3 may overlap each of the first source electrode SE1 and the third source electrode SE3. The third upper electrode UE3 may be formed of a third conductive layer C3.

[0238] The third upper electrode UE3 , the third bottom metal pattern BML3 , the first source electrode SE1 , and the third source electrode SE3 may be electrically connected to each other.

[0239] In an implementation, the third upper electrode UE3 may be electrically connected to the connection pattern CNP through a contact hole formed through the first, second, and third insulating layers INS1, INS2, and INS3.

[0240] The connection pattern CNP may be formed of the first conductive layer C1. A first end of the connection pattern CNP may be electrically connected to the third upper electrode UE3 through a contact hole. A second end of the connection pattern CNP may be electrically connected to the third contact electrode CNE3 through a contact hole formed through the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0241] The third contact electrode CNE3 may be formed of the third conductive layer C3. The third contact electrode CNE3 may be electrically connected to the connection pattern CNP through a contact hole. The third contact electrode CNE3 may be electrically connected to the first electrode ELT1 of the third emission part EMU3 through a third contact portion CNT3 formed through the fourth insulating layer INS4, the fifth insulating layer INS5, the sixth insulating layer INS6, and the seventh insulating layer INS7.

[0242] Each of the first pixel circuit PXC1 , the second pixel circuit PXC2 , and the third pixel circuit PXC3 may be electrically connected to a corresponding emission component through a contact portion CNT and a contact electrode CNE.

[0243] The first emission unit EMU1 may be electrically connected to the first contact electrode CNE1 through the first contact portion CNT1. The first contact electrode CNE1 may be electrically connected to the first bottom metal pattern BML1 through the contact hole. The first bottom metal pattern BML1 may be electrically connected to the first upper electrode UE1 of the first pixel circuit PXC1 through the contact hole. The first electrode ELT1 (or the first pixel electrode) of the first emission unit EMU1 may be electrically connected to the first contact electrode CNE1 through the first contact portion CNT1, and thus electrically connected to the first upper electrode UE1 of the first pixel circuit PXC1 electrically connected to the first contact electrode CNE1.

[0244] The second emission unit EMU2 may be electrically connected to the second contact electrode CNE2 through the second contact portion CNT2. The second contact electrode CNE2 may be electrically connected to the second bottom metal pattern BML2 through the contact hole. The second bottom metal pattern BML2 may be electrically connected to the second upper electrode UE2 of the second pixel circuit PXC2 through the contact hole. The first electrode ELT1 (or the first pixel electrode) of the second emission unit EMU2 may be electrically connected to the second contact electrode CNE2 through the second contact portion CNT2, and thus electrically connected to the second upper electrode UE2 of the second pixel circuit PXC2 electrically connected to the second contact electrode CNE2.

[0245] The third emission unit EMU3 may be electrically connected to the third contact electrode CNE3 through the third contact portion CNT3. The third contact electrode CNE3 may be electrically connected to the connection pattern CNP through the contact hole. The connection pattern CNP may be electrically connected to the third upper electrode UE3 of the third pixel circuit PXC3 through the contact hole. The first electrode ELT1 (or the first pixel electrode) of the third emission unit EMU3 may be electrically connected to the third contact electrode CNE3 through the third contact portion CNT3, and thus electrically connected to the third upper electrode UE3 of the third pixel circuit PXC3 electrically connected to the third contact electrode CNE3.

[0246] Each of the first contact electrode CNE1, the second contact electrode CNE2, and the third contact electrode CNE3 may be formed of a third conductive layer C3 and may be disposed on the third insulating layer INS3. Each of the first contact electrode CNE1, the second contact electrode CNE2, and the third contact electrode CNE3 may have a multilayer structure formed by continuously or sequentially stacking, for example, titanium, copper, and / or indium tin oxide. In this case, since the contact resistance due to the oxide layer (for example, the aluminum oxide layer) can be improved, the problem of heat generated from the contact portion CNT and the reduction in brightness of the display device DD can be alleviated.

[0247] The first contact portion CNT1, the second contact portion CNT2, and the third contact portion CNT3 may have substantially similar or identical structures. Fig. 9 The second contact CNT2 among the first contact CNT1 , the second contact CNT2 , and the third contact CNT3 is described as a representative example, and descriptions of the first contact CNT1 and the third contact CNT3 will be simplified.

[0248] The fourth insulating layer INS4 may be arranged on the second contact electrode CNE2. The fourth insulating layer INS4 may include a second contact portion CNT2 formed by removing a certain area of ​​the fourth insulating layer INS4 at least in the emission area EMA to allow a certain area of ​​the second contact electrode CNE2 to be exposed. The fifth insulating layer INS5 may be arranged on the fourth insulating layer INS4. The fifth insulating layer INS5 may have a certain area removed to allow a certain area of ​​the second contact electrode CNE2 to be exposed. The sixth insulating layer INS6 may be arranged on the fifth insulating layer INS5. The sixth insulating layer INS6 may have a certain area removed to allow a certain area of ​​the second contact electrode CNE2 to be exposed. The seventh insulating layer INS7 may be arranged on the sixth insulating layer INS6. The seventh insulating layer INS7 may have a certain area removed to allow a certain area of ​​the second contact electrode CNE2 to be exposed.

[0249] The first electrode ELT1 may be arranged on the seventh insulating layer INS7. The first electrode ELT1 may directly contact the second contact electrode CNE2 exposed by the second contact portion CNT2. In the case where the second contact electrode CNE2 of the second pixel circuit PXC2 formed by the third conductive layer C3 (or source-drain conductive layer) directly contacts the first electrode ELT1 of the second emission unit EMU2 formed by the fifth conductive layer C5, the contact resistance may be minimized so that the heat generation problem and the brightness degradation problem of the display device DD can be reduced.

[0250] In the following, reference will be made to Figures 10 to 12The emission parts of the pixel PXL are described in detail. The pixel PXL may include a first emission part EMU1, a second emission part EMU2, and a third emission part EMU3 positioned in the display element layer DPL.

[0251] Each of the first emission unit EMU1, the second emission unit EMU2, and the third emission unit EMU3 may include a light emitting element LD electrically connected to a corresponding pixel circuit to emit light, and an electrode (or an electrode pattern) electrically connected to the light emitting element LD.

[0252] The display element layer DPL may include a bank BNK disposed in the non-emission area NEA.

[0253] The bank BNK may be a pixel defining layer as a structure defining (or dividing) the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3. The bank BNK may define the position of the light emitting element LD during the process of forming (or putting) the light emitting element LD into each sub-pixel SPX. For example, since the emission area of ​​each sub-pixel SPX is defined by the bank BNK, a mixed solution (e.g., ink) including a target amount and / or type of the light emitting element LD may be formed (or put) into the corresponding emission area.

[0254] In an embodiment, the bank BNK may include at least one light blocking material and / or reflective material (or scattering material) to prevent a light leakage defect in which light leaks between adjacent sub-pixels SPX. In an embodiment, the bank BNK may include a transparent material (or substance). The transparent material may include, for example, polyamide resin, polyimide resin, and the like, but the present disclosure is not limited thereto. In an embodiment, in order to improve the efficiency of light emitted from each sub-pixel SPX, a separate reflective material layer may be provided and / or formed on the bank BNK.

[0255] The bank BNK may include an opening area exposing a component arranged under the bank BNK in the pixel area PXA. The first emission area EMA1, the second emission area EMA2, and the third emission area EMA3 may be defined by the opening area of ​​the bank BNK, respectively. The first emission area EMA1, the second emission area EMA2, and the third emission area EMA3 may correspond to the opening area of ​​the bank BNK, respectively.

[0256] Since the bank BNK is arranged in the non-emission area NEA between the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3, the area where the light emitting element LD is to be arranged (or put into) can be determined. Therefore, in the step of forming the light emitting element LD to the pixel PXL, the light emitting element LD can be prevented from being formed to an undesired area, and the light emitting element LD can be effectively formed to each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3.

[0257] An electrode separation area ESA may be disposed in the non-emission area NEA of each subpixel SPX. The electrode separation area ESA may be an area where the first alignment electrode ALE1 in each subpixel SPX is separated from the first alignment electrode ALE1 in the subpixels SPX arranged in the same pixel column.

[0258] Each of the first emission component EMU1, the second emission component EMU2, and the third emission component EMU3 may include an electrode ELT, a light emitting element LD electrically connected to the electrode ELT, and an alignment electrode ALE arranged at a position corresponding to the electrode ELT. In each of the first emission component EMU1, the second emission component EMU2, and the third emission component EMU3, a first electrode ELT1 (or a first pixel electrode), a second electrode ELT2 (or a first bridging electrode), a third electrode ELT3 (or a second bridging electrode), a fourth electrode ELT4 (or a third bridging electrode), and a fifth electrode ELT5 (or a second pixel electrode), a light emitting element LD, and a first alignment electrode ALE1 and a second alignment electrode ALE2 may be arranged. According to the structure of the first emission component EMU1, the second emission component EMU2, and the third emission component EMU3, the electrode ELT and / or the alignment electrode ALE may each be changed in various ways in terms of quantity, shape, size, arrangement structure, etc.

[0259] The alignment electrode ALE, the light emitting element LD, and the electrode ELT may be provided in the listed order based on one surface of the substrate SUB on which the first, second, and third subpixels SPX1, SPX2, and SPX3 are positioned, but the present disclosure is not limited thereto.

[0260] The alignment electrode ALE may include a first alignment electrode ALE1 and a second alignment electrode ALE2 spaced apart from each other in the first direction DR1. The first alignment electrode ALE1 and the second alignment electrode ALE2 may extend in the second direction DR2. In each of at least the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be arranged in the order of the second alignment electrode ALE2, the first alignment electrode ALE1, and the second alignment electrode ALE2 in the first direction DR1.

[0261] After the light emitting element LD is supplied and aligned in each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3, the first alignment electrode ALE1 may be separated from the floating pattern FTP. In detail, before the light emitting element LD is aligned in each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3, the first alignment electrode ALE1 may be formed integrally with the floating pattern FTP to form a first alignment line for aligning the light emitting element LD. The floating pattern FTP may be electrically connected to the first horizontal power line PL1b of the pixel circuit layer PCL through the through hole VIH. The first alignment electrode ALE1 and the floating pattern FTP may be formed by the fourth conductive layer C4. After the process of aligning the light emitting element LD has been completed, the first alignment line may be cut in the electrode separation area ESA arranged close to the floating pattern FTP so that the first alignment line may be divided into the first alignment electrode ALE1 and the floating pattern FTP. In addition, the first alignment line may be cut in the electrode separation area ESA between adjacent pixel rows so that the first alignment electrodes ALE1 of adjacent sub-pixels SPX can be separated from each other. After alignment of the light emitting element LD, the first alignment electrode ALE1 may be electrically insulated from other electrodes and thus floated.

[0262] The second alignment electrode ALE2 may be electrically connected to the second power line PL2 of the pixel circuit layer PCL before or after the alignment of the light emitting element LD. Therefore, the second alignment electrode ALE2 may be supplied with an alignment signal from the second power line PL2 before the alignment of the light emitting element LD, and may be supplied with a voltage of the second driving power supply VSS after the alignment of the light emitting element LD. The second alignment electrode ALE2 may be formed of a fourth conductive layer C4.

[0263] The bank pattern BNP may be arranged under the first alignment electrode ALE1 and the second alignment electrode ALE2 to change the surface profile (or shape) of the first alignment electrode ALE1 and the second alignment electrode ALE2 so as to guide the light emitted from the light emitting element LD in the image display direction of the display device DD. The bank pattern BNP may be a supporting member for supporting the first alignment electrode ALE1 and the second alignment electrode ALE2, respectively.

[0264] The bank pattern BNP may be arranged on the fifth insulating layer INS5 of the pixel circuit layer PCL. Each of the bank patterns BNP may be formed by a separate pattern individually arranged under each of the first alignment electrode ALE1 and the second alignment electrode ALE2 so that the separate pattern overlaps a portion of a corresponding one of the first alignment electrode ALE1 and the second alignment electrode ALE2. In an embodiment, the bank pattern BNP may be formed by an integral pattern having an opening or a recess corresponding to an area between the first alignment electrode ALE1 and the second alignment electrode ALE2 in each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3, and is generally integrally formed in the display area DA.

[0265] Since the bank pattern BNP is provided under corresponding certain regions of the alignment electrode ALE, corresponding certain regions of the alignment electrode ALE may protrude in an upward direction of the pixel PXL (ie, in the third direction DR3 ) in a region where the corresponding bank pattern BNP is formed.

[0266] Each of the bank patterns BNP may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. However, the material of the bank pattern BNP is not limited to the foregoing embodiments. In an embodiment, the bank pattern BNP may include a conductive material (or a conductive substance). The shape of the bank pattern BNP may be changed in various ways within a range capable of improving the efficiency of light emitted from the light emitting element LD.

[0267] The first alignment electrode ALE1 and the second alignment electrode ALE2 may each be formed of a material having a reflectivity (or a certain reflectivity) that allows light emitted from the light emitting element LD to travel in the image display direction of the display device DD. For example, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed of a conductive material (or substance). The conductive material may include an opaque metal suitable for reflecting light emitted from the light emitting element LD in the image display direction of the display device DD (or the upward direction of the display element layer DPL), but is not limited thereto.

[0268] Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be provided and / or formed in the form of a single-layer structure, but is not limited thereto. In an embodiment, the first alignment electrode ALE1 and the second alignment electrode ALE2 may each be provided and / or formed to have a multi-layer structure formed by stacking at least two materials among metals, alloys, conductive oxides, and conductive polymers.

[0269] In the case where the bank pattern BNP and / or the alignment electrode ALE include a reflective material, a reflective wall structure may be formed around the light emitting element LD. Therefore, light emitted from the light emitting element LD may be emitted in an upward direction of each sub-pixel SPX (e.g., in a front direction of the display panel DP including a predetermined viewing angle range), so that the light output efficiency of the display device DD (or display panel DP) may be improved.

[0270] In the following, we will base on Fig.11 and Fig.12 The configuration of the first sub-pixel SPX1 will be described below. For the sake of convenience, repeated explanation of the same configuration as that described above will be omitted.

[0271] The light emitting element LD may be arranged and / or aligned in the first emission area EMA1 of the first sub-pixel SPX1.

[0272] The light emitting element LD may be arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2. In a plan view, each of the light emitting elements LD may include a first end EP1 and a second end EP2 located on respective opposite ends of the light emitting element LD (or facing each other) in a longitudinal direction of the light emitting element LD (e.g., in a first direction DR1). A second semiconductor layer (or a p-type semiconductor layer) including a p-type semiconductor layer may be arranged on the first end EP1 (or p-type end). Figure 1 A second semiconductor layer 13 in the middle) and a first semiconductor layer ( Figure 1 The first semiconductor layer 11 in the embodiment of the present invention.

[0273] The light emitting element LD may be formed in the first emission area EMA1 through an inkjet printing scheme, a slit coating scheme, or other various schemes.

[0274] The light emitting element LD may include a first light emitting element LD1 , a second light emitting element LD2 , a third light emitting element LD3 , and a fourth light emitting element LD4 .

[0275] The first light emitting element LD1 may be aligned between the upper left end region of the first alignment electrode ALE1 and the second alignment electrode ALE2, and electrically connected to the first electrode ELT1 and the second electrode ELT2. The first light emitting element LD1 may include a first end EP1 disposed adjacent to the first alignment electrode ALE1 and a second end EP2 disposed adjacent to the second alignment electrode ALE2. The first end EP1 of the first light emitting element LD1 may be electrically connected to the first electrode ELT1. The second end EP2 of the first light emitting element LD1 may be electrically connected to the second electrode ELT2.

[0276] The second light emitting element LD2 may be aligned between the lower left end region of the first alignment electrode ALE1 and the second alignment electrode ALE2, and electrically connected to the second electrode ELT2 and the third electrode ELT3. The second light emitting element LD2 may include a first end EP1 arranged adjacent to the first alignment electrode ALE1 and a second end EP2 arranged adjacent to the second alignment electrode ALE2. The first end EP1 of the second light emitting element LD2 may be electrically connected to the second electrode ELT2. The second end EP2 of the second light emitting element LD2 may be electrically connected to the third electrode ELT3.

[0277] The third light emitting element LD3 may be aligned between the lower right end region of the first alignment electrode ALE1 and the second alignment electrode ALE2, and electrically connected to the third electrode ELT3 and the fourth electrode ELT4. The third light emitting element LD3 may include a first end EP1 arranged adjacent to the first alignment electrode ALE1 and a second end EP2 arranged adjacent to the second alignment electrode ALE2. The first end EP1 of the third light emitting element LD3 may be electrically connected to the third electrode ELT3. The second end EP2 of the third light emitting element LD3 may be electrically connected to the fourth electrode ELT4.

[0278] The fourth light emitting element LD4 may be aligned between the upper right end region of the first alignment electrode ALE1 and the second alignment electrode ALE2, and electrically connected to the fourth electrode ELT4 and the fifth electrode ELT5. The fourth light emitting element LD4 may include a first end EP1 arranged adjacent to the first alignment electrode ALE1 and a second end EP2 arranged adjacent to the second alignment electrode ALE2. The first end EP1 of the fourth light emitting element LD4 may be electrically connected to the fourth electrode ELT4. The second end EP2 of the fourth light emitting element LD4 may be electrically connected to the fifth electrode ELT5.

[0279] As described above, the first end EP1 of each of the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3, and the fourth light emitting element LD4 may be arranged adjacent to the corresponding first alignment electrode ALE1. The second end EP2 of each of the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3, and the fourth light emitting element LD4 may be arranged adjacent to the corresponding second alignment electrode ALE2.

[0280] Each of the first, second, third and fourth light emitting elements LD1, LD2, LD3 and LD4 may be formed of a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size ranging from nanometer to micrometer, for example.

[0281] The electrodes ELT may be provided at least in the first emission area EMA1, and each may be provided at a position corresponding to at least one alignment electrode ALE and the light emitting element LD. For example, the electrodes ELT may be formed on the alignment electrode ALE and / or the light emitting element LD in such a manner that each of the electrodes ELT overlaps with the corresponding alignment electrode ALE and / or the corresponding light emitting element LD, whereby the electrodes ELT may be electrically connected to the light emitting element LD.

[0282] The first electrode ELT1 (or the first pixel electrode) may be disposed on the first region (eg, the upper left region) of the first alignment electrode ALE1 and the first end EP1 of the first light emitting element LD1 and thus be electrically connected to the first end EP1 of the first light emitting element LD1. The first electrode ELT1 may be formed of the fifth conductive layer C5.

[0283] The second electrode ELT2 may be arranged on a first region (e.g., an upper end region) of the second alignment electrode ALE2 facing the first region of the first alignment electrode ALE1 and on the second end EP2 of the first light emitting element LD1, and thus electrically connected to the second end EP2 of the first light emitting element LD1. In addition, the second electrode ELT2 may be arranged on a second region (e.g., a lower left end region) of the first alignment electrode ALE1 and on the first end EP1 of the second light emitting element LD2, and thus electrically connected to the first end EP1 of the second light emitting element LD2. For example, the second electrode ELT2 may be a first bridging electrode that electrically connects the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2 to each other in the first emission region EMA1. To this end, the second electrode ELT2 may have a curved shape. For example, the second electrode ELT2 may have a curved or bent structure at a boundary between a region where at least one first light emitting element LD1 is arranged and a region where at least one second light emitting element LD2 is arranged. The second electrode ELT2 may be formed by the fifth conductive layer C5.

[0284] The third electrode ELT3 may be arranged on the second region (e.g., the lower end region) of the second alignment electrode ALE2 and the second end EP2 of the second light emitting element LD2, and thus electrically connected to the second end EP2 of the second light emitting element LD2. In addition, the third electrode ELT3 may be arranged on the third region (e.g., the lower right end region) of the first alignment electrode ALE1 and the first end EP1 of the third light emitting element LD3, and thus electrically connected to the first end EP1 of the third light emitting element LD3. For example, the third electrode ELT3 may be a second bridging electrode that electrically connects the second end EP2 of the second light emitting element LD2 and the first end EP1 of the third light emitting element LD3 to each other in the first emission region EMA1. To this end, the third electrode ELT3 may have a curved shape. For example, the third electrode ELT3 may have a curved or bent structure at a boundary between a region where at least one second light emitting element LD2 is arranged and a region where at least one third light emitting element LD3 is arranged. The third electrode ELT3 may be formed by the fifth conductive layer C5.

[0285] The fourth electrode ELT4 may be arranged on the second region (e.g., the lower end region) of the second alignment electrode ALE2 facing the third region of the first alignment electrode ALE1 and on the second end EP2 of the third light emitting element LD3, and thus electrically connected to the second end EP2 of the third light emitting element LD3. In addition, the fourth electrode ELT4 may be arranged on the fourth region (e.g., the upper right end region) of the first alignment electrode ALE1 and on the first end EP1 of the fourth light emitting element LD4, and thus electrically connected to the first end EP1 of the fourth light emitting element LD4. For example, the fourth electrode ELT4 may be a third bridging electrode that electrically connects the second end EP2 of the third light emitting element LD3 and the first end EP1 of the fourth light emitting element LD4 to each other in the first emission region EMA1. To this end, the fourth electrode ELT4 may have a curved shape. For example, the fourth electrode ELT4 may have a curved or bent structure at a boundary between a region where at least one third light emitting element LD3 is arranged and a region where at least one fourth light emitting element LD4 is arranged. The fourth electrode ELT4 may be formed by the fifth conductive layer C5.

[0286] The fifth electrode ELT5 may be disposed on the first region (eg, upper region) of the second alignment electrode ALE2 and the second end EP2 of the fourth light emitting element LD4 and thus be electrically connected to the second end EP2 of the fourth light emitting element LD4. The fifth electrode ELT5 may be formed of a fifth conductive layer C5.

[0287] In this way, the light emitting elements LD aligned between the alignment electrodes ALE can be connected in a desired form by using the electrode ELT. For example, the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3 and the fourth light emitting element LD4 can be continuously electrically connected in series by using the electrode ELT.

[0288] The first electrode ELT1 of the first subpixel SPX1 may be electrically connected to the first contact electrode CNE1 through the first contact portion CNT1. The first electrode ELT1 of the second subpixel SPX2 may be electrically connected to the second contact electrode CNE2 through the second contact portion CNT2. The first electrode ELT1 of the third subpixel SPX3 may be electrically connected to the third contact electrode CNE3 through the third contact portion CNT3. The electrode ELT of each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be a driving electrode provided to drive the light emitting element LD arranged in the emission region of the corresponding subpixel SPX.

[0289] The first emitting unit EMU1 may further include a sub-electrode SLT electrically connected to the electrode ELT. The sub-electrode SLT may include a first sub-electrode SLT1, a second sub-electrode SLT2, a third sub-electrode SLT3, and a fourth sub-electrode SLT4. The first sub-electrode SLT1 may be electrically connected to the second electrode ELT2. The second sub-electrode SLT2 may be electrically connected to the third electrode ELT3. The third sub-electrode SLT3 may be electrically connected to the fourth electrode ELT4. The fourth sub-electrode SLT4 may be electrically connected to the fifth electrode ELT5.

[0290] The first sub-electrode SLT1, the second sub-electrode SLT2, the third sub-electrode SLT3, and the fourth sub-electrode SLT4 may be formed by the fifth conductive layer C5. The first sub-electrode SLT1 may be formed integrally with the second electrode ELT2, and thus connected to the second electrode ELT2. The second sub-electrode SLT2 may be formed integrally with the third electrode ELT3, and thus connected to the third electrode ELT3. The third sub-electrode SLT3 may be formed integrally with the fourth electrode ELT4, and thus connected to the fourth electrode ELT4. The fourth sub-electrode SLT4 may be formed integrally with the fifth electrode ELT5, and thus connected to the fifth electrode ELT5. However, the present disclosure is not limited to the foregoing examples.

[0291] In the case where a sub-electrode SLT electrically connected to the electrode ELT is provided, a dark spot defect of the first sub-pixel SPX1 (or pixel PXL) can be alleviated. The sub-electrode SLT can be arranged above the bank BNK and can overlap with the bank BNK. For example, each of the first sub-electrode SLT1, the second sub-electrode SLT2, the third sub-electrode SLT3, and the fourth sub-electrode SLT4 can be arranged above the bank BNK and can overlap with the bank BNK in a plan view.

[0292] At least one of the sub-electrodes SLT of the first sub-pixel SPX1 may be electrically connected to at least one of the sub-electrodes SLT of the adjacent sub-pixel SPX. For example, the fourth sub-electrode SLT4 of the first sub-pixel SPX1 may be electrically connected to the fourth sub-electrode SLT4 of the second sub-pixel SPX2.

[0293] At least one of the sub-electrodes SLT of the sub-pixel SPX can be electrically connected to at least one of the sub-electrodes SLT of the adjacent sub-pixel SPX through the intermediate electrode IE. For example, the fourth sub-electrode SLT4 of the first sub-pixel SPX1 can be electrically connected to the fourth sub-electrode SLT4 of the second sub-pixel SPX2 through the intermediate electrode IE.

[0294] The intermediate electrode IE may be arranged on a boundary between adjacent sub-pixels SPX or in a space between adjacent sub-pixels SPX (e.g., in a non-emission area NEA), and may be connected to at least one of the sub-electrodes SLT of each of the adjacent sub-pixels SPX. The intermediate electrode IE may be provided integrally with at least one of the sub-electrodes SLT of the sub-pixel SPX and arranged in the same layer as the at least one of the sub-electrodes SLT of the sub-pixel SPX, but the present disclosure is not limited thereto. The intermediate electrode IE may be formed by a fifth conductive layer C5.

[0295] The fourth sub-electrode SLT4 of the first sub-pixel SPX1 may be spaced apart from the fourth sub-electrode SLT4 of the second sub-pixel SPX2. The fourth sub-electrode SLT4 of the first sub-pixel SPX1 and the fourth sub-electrode SLT4 of the second sub-pixel SPX2 may be electrically connected to each other through the intermediate electrode IE. The intermediate electrode IE may be provided integrally with the fourth sub-electrode SLT4 of the first sub-pixel SPX1 and / or the fourth sub-electrode SLT4 of the second sub-pixel SPX2, and arranged on (or in) the same layer as the fourth sub-electrode SLT4 of the first sub-pixel SPX1 and / or the fourth sub-electrode SLT4 of the second sub-pixel SPX2, but the present disclosure is not limited thereto.

[0296] Although the case where the sub-electrode SLT of the third sub-pixel SPX3 is separated from the sub-electrode SLT of the first sub-pixel SPX1 and / or the sub-electrode SLT of the second sub-pixel SPX2 is shown, the present disclosure is not limited thereto. In an embodiment, at least one of the sub-electrodes SLT of the third sub-pixel SPX3 may be electrically connected to at least one of the sub-electrode SLT of the first sub-pixel SPX1 and / or the sub-electrode SLT of the second sub-pixel SPX2.

[0297] The bridge wire BRL may be arranged between adjacent sub-pixels SPX (or pixels PXL) provided on different pixel rows. The bridge wire BRL may extend in the first direction DR1 and may be electrically connected to at least one of the electrodes ELT of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The bridge wire BRL may be formed by a fifth conductive layer C5. The bridge wire BRL may be electrically connected to a second power line PL2 of the pixel circuit layer PCL and may be supplied with a voltage of a second driving power supply VSS.

[0298] In an embodiment, the fifth electrode ELT5 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be electrically connected to the bridge line BRL. The fifth electrode ELT5 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be formed integrally with the bridge line BRL, and may diverge from the bridge line BRL and extend in the second direction DR2. The bridge line BRL and the corresponding fifth electrodes ELT5 of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may form a grid structure. Since the bridge line BRL and the fifth electrode ELT5 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are electrically connected to each other, the fifth electrode ELT5 of the first sub-pixel SPX1, the fifth electrode ELT5 of the second sub-pixel SPX2, and the fifth electrode ELT5 of the third sub-pixel SPX3 may be electrically connected to each other.

[0299] As described above, when the fifth electrodes ELT5 which are cathodes are connected to each other and to the bridge wire BRL to form a grid structure between the electrodes ELT of adjacent sub-pixels SPX, the number of contacts on the bridge wire BRL can be reduced so that the design space can be ensured in a display device with high resolution, the contact resistance can be reduced, and electrostatic discharge can be improved.

[0300] In the following, reference will be made to Fig.12 The stack structure (or cross-sectional structure) of the first sub-pixel SPX1 is described in detail.

[0301] The first sub-pixel SPX1 may include a display part LEL including a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

[0302] The pixel circuit layer PCL and the display element layer DPL may be disposed on one surface of the substrate SUB and overlap each other.

[0303] The pixel circuit layer PCL may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, and a fifth insulating layer INS5 which are sequentially stacked on the substrate SUB.

[0304] The display element layer DPL may include a bank pattern BNP, first and second alignment electrodes ALE1 and ALE2 , a light emitting element LD, an electrode ELT, a sixth insulating layer INS6 , a seventh insulating layer INS7 , and / or a sub-electrode SLT.

[0305] The bank pattern BNP may be disposed on the fifth insulating layer INS5 of the pixel circuit layer PCL and may have reflectivity. For example, the bank pattern BNP together with the first alignment electrode ALE1 and the second alignment electrode ALE2 disposed above the bank pattern BNP may be used as a reflector to guide light emitted from the light emitting element LD in a desired direction, so that the light output efficiency of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be improved.

[0306] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be disposed on the bank pattern BNP.

[0307] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be arranged on the same plane and have the same thickness in the third direction DR3 . The first alignment electrode ALE1 and the second alignment electrode ALE2 may be simultaneously formed through the same process.

[0308] A sixth insulating layer INS6 may be disposed on the first alignment electrode ALE1 and the second alignment electrode ALE2 .

[0309] A sixth insulating layer INS6 may be provided and / or formed on the entire surfaces of the first and second alignment electrodes ALE1 and ALE2.

[0310] The bank BNK may be disposed on the sixth insulating layer INS6 .

[0311] The bank BNK may be disposed on the sixth insulating layer INS6 in the non-emission area NEA. The bank BNK may surround the first emission area EMA1 of the first sub-pixel SPX1.

[0312] The light emitting element LD may be disposed on the sixth insulating layer INS6. The light emitting element LD may be disposed on the sixth insulating layer INS6 between adjacent alignment electrodes ALE.

[0313] The light emitting element LD may include a first light emitting element LD1 , a second light emitting element LD2 , a third light emitting element LD3 , and a fourth light emitting element LD4 .

[0314] The seventh insulating layer INS7 (or insulating pattern) may be disposed on each of the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3, and the fourth light emitting element LD4. The seventh insulating layer INS7 may be disposed on each of the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3, and the fourth light emitting element LD4, and partially covers the outer peripheral surface (or surface) of each of the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3, and the fourth light emitting element LD4, so that the first end EP1 and the second end EP2 of each of the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3, and the fourth light emitting element LD4 are exposed to the outside.

[0315] A seventh insulating layer INS7 may be provided in the emission area EMA and / or formed on the sixth insulating layer INS6.

[0316] The seventh insulating layer INS7 may include an inorganic layer including an inorganic material or an organic layer including an organic material. For example, the seventh insulating layer INS7 may include an active layer ( Figure 1 The seventh insulating layer INS7 may be formed of an organic layer to protect the active layer 12 of the first light emitting element LD1 from external oxygen, water or the like. However, the present disclosure is not limited thereto. The seventh insulating layer INS7 may be formed of an organic layer according to design conditions and similar factors of a display device DD (or display panel DP) to which the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3 and the fourth light emitting element LD4 are applied. The seventh insulating layer INS7 may have a single-layer or multi-layer structure.

[0317] In the case where there is a gap (or space) between the sixth insulating layer INS6 and the light emitting element LD before forming the seventh insulating layer INS7, the gap may be filled with the seventh insulating layer INS7 during the process of forming the seventh insulating layer INS7.

[0318] Since the seventh insulating layer INS7 is formed on the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3 and the fourth light emitting element LD4 which are completely aligned in the first emission area EMA1, the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3 and the fourth light emitting element LD4 can be prevented from being removed from their aligned positions.

[0319] The electrode ELT may be formed on opposite ends of the light emitting element LD (ie, on the first end EP1 and the second end EP2 that are not covered by the seventh insulating layer INS7 ).

[0320] The first electrode ELT1, the second electrode ELT2, the third electrode ELT3, the fourth electrode ELT4 and / or the fifth electrode ELT5 may be formed by a fifth conductive layer C5 disposed on the seventh insulating layer INS7. The first electrode ELT1, the second electrode ELT2, the third electrode ELT3, the fourth electrode ELT4 and / or the fifth electrode ELT5 may be formed simultaneously by the same process.

[0321] Each of the electrodes ELT may be formed of various transparent conductive materials. For example, each of the electrodes ELT may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide, and may be substantially transparent or translucent to provide satisfactory transmittance. Figure 1 ) may be emitted outside the display panel DP.

[0322] The sub-electrode SLT may be arranged in the same layer as the corresponding electrode ELT, and may have the same material as that of the electrode ELT. The sub-electrode SLT and the electrode ELT electrically connected to each other may be integrally formed through the same process.

[0323] Fig.13 is a schematic cross-sectional view showing a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 according to an embodiment.

[0324] For example, Fig.13 shows that include the reference provided in Figures 10 to 12 The optical layer of the partition wall WL, the color conversion layer CCL, the color filter layer CFL and / or the overcoat layer OC on the display part LEL of each sub-pixel SPX described. The optical layer may correspond to Figure 4 Optical layer LCL.

[0325] Reference Figures 1 to 13 , a partition wall WL (e.g., a "dam structure" or a "wall structure") may be arranged on the display part LEL for the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. For example, the partition wall WL may be arranged between the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 or on a boundary between the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, and include openings arranged in regions corresponding to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, respectively. Each of the openings of the partition wall WL may provide a space in which a color conversion layer CCL can be provided.

[0326] The partition wall WL may include an organic material (or substance) such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the present disclosure is not limited thereto. The partition wall WL may include an organic material (or substance) including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ) various inorganic materials (or substances).

[0327] In an embodiment, the partition wall WL may include at least one light blocking material and / or reflective material. Therefore, light leakage between adjacent sub-pixels SPX may be prevented. For example, the partition wall WL may include at least one black matrix material and / or color filter material. For example, the partition wall WL may be formed of a black opaque pattern capable of preventing transmission of light. In an embodiment, a reflective layer (not shown) or the like may be formed on a surface (e.g., a side wall) of the partition wall WL to increase the light efficiency of each sub-pixel SPX.

[0328] The color conversion layer CCL may be disposed on the display part LEL including the light emitting element LD in the opening of the partition wall WL. The color conversion layer CCL may include a first color conversion layer CCL1 disposed in the first subpixel SPX1, a second color conversion layer CCL2 disposed in the second subpixel SPX2, and a light scattering layer LSL disposed in the third subpixel SPX3.

[0329] In an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a light emitting element LD configured to emit light of the same color. For example, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a light emitting element LD configured to emit light of a third color (or blue light). Since the color conversion layer CCL including color conversion particles is arranged in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, a full-color image can be displayed.

[0330] The first color conversion layer CCL1 may include first color conversion particles for converting the third color light emitted from the light emitting element LD into the first color light. For example, the first color conversion layer CCL1 may include a plurality of first quantum dots QD1 dispersed in a matrix material such as a base resin.

[0331] In the case where the light emitting element LD is a blue light emitting element configured to emit blue light and the first sub-pixel SPX1 is a red pixel, the first color conversion layer CCL1 may include a first quantum dot QD1 that may convert the blue light emitted from the blue light emitting element into red light. The first quantum dot QD1 may absorb the blue light, shift its wavelength according to energy transition, and thus emit red light. In an embodiment, in the case where the first sub-pixel SPX1 is one of pixels of other colors, the first color conversion layer CCL1 may include a first quantum dot QD1 corresponding to the color of the first sub-pixel SPX1.

[0332] The second color conversion layer CCL2 may include second color conversion particles for converting the third color light emitted from the light emitting element LD into the second color light. For example, the second color conversion layer CCL2 may include a plurality of second quantum dots QD2 dispersed in a matrix material such as a base resin.

[0333] In an embodiment, when the light emitting element LD is a blue light emitting element configured to emit blue light and the second sub-pixel SPX2 is a green pixel, the second color conversion layer CCL2 may include a second quantum dot QD2 that may convert the blue light emitted from the blue light emitting element into green light. The second quantum dot QD2 may absorb the blue light, shift its wavelength according to energy transition, and thus emit green light. In an embodiment, when the second sub-pixel SPX2 is one of the pixels of other colors, the second color conversion layer CCL2 may include a second quantum dot QD2 corresponding to the color of the second sub-pixel SPX2.

[0334] In an embodiment, when blue light having a relatively short wavelength in the visible light region is incident on each of the first quantum dot QD1 and the second quantum dot QD2, the absorption coefficient of the first quantum dot QD1 and the second quantum dot QD2 may be increased. Therefore, ultimately, the efficiency of light emitted from the first sub-pixel SPX1 and the second sub-pixel SPX2 may be improved, and satisfactory color reproducibility may be ensured. In addition, since the emission components of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are formed by light-emitting elements LD (e.g., blue light-emitting elements) configured to emit light of the same color, the efficiency of manufacturing the display device DD may be improved.

[0335] A light scattering layer LSL may be provided to effectively use the light of the third color (or blue light) emitted from the light emitting element LD. For example, when the light emitting element LD is a blue light emitting element configured to emit blue light and the third sub-pixel SPX3 is a blue pixel, the light scattering layer LSL may include at least one type of light scatterer SCT to effectively use the light emitted from the light emitting element LD.

[0336] For example, the light scattering layer LSL may include a plurality of light scatterers SCT dispersed in a matrix material such as a base resin. For example, the light scattering layer LSL may include a light scatterer SCT formed of a material such as silicon dioxide, but the constituent material of the light scatterer SCT is not limited thereto. The light scatterer SCT may be provided not only in the third sub-pixel SPX3 but may also be selectively included in the first color conversion layer CCL1 or the second color conversion layer CCL2. In an embodiment, the light scatterer SCT may be omitted and the light scattering layer LSL may be formed of a transparent polymer.

[0337] A first cover layer CPL1 may be disposed on the color conversion layer CCL. The first cover layer CPL1 may be provided over the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The first cover layer CPL1 may cover the color conversion layer CCL. The first cover layer CPL1 may prevent the color conversion layer CCL from being damaged or contaminated due to penetration of external impurities such as water or air.

[0338] The first capping layer CPL1 may be an inorganic layer including an inorganic material, and may be made of silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x ), silicon oxide (SiO x ), aluminum oxide (AlO x ), titanium oxide (TiO x ), silicon carbide oxide (SiO x C y ) or silicon oxynitride (SiO x N y )form.

[0339] A refractive index conversion layer OPL may be arranged on the first cover layer CPL1. The refractive index conversion layer OPL may play a role of recovering light provided from the color conversion layer CCL by total reflection and thus improving light extraction efficiency. Therefore, the refractive index conversion layer OPL may have a relatively low refractive index compared to the refractive index of the color conversion layer CCL. For example, the refractive index of the color conversion layer CCL may be approximately in the range of 1.6 to 2.0, and the refractive index of the refractive index conversion layer OPL may be approximately in the range of 1.1 to 1.3.

[0340] A second cover layer CPL2 may be disposed on the refractive index conversion layer OPL. The second cover layer CPL2 may be provided over the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The second cover layer CPL2 may cover the refractive index conversion layer OPL. The second cover layer CPL2 may prevent the refractive index conversion layer OPL from being damaged or contaminated due to penetration of external impurities such as water or air.

[0341] The second capping layer CPL2 may be an inorganic layer including an inorganic material, and may be made of silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x ), silicon oxide (SiO x ), aluminum oxide (AlO x ), titanium oxide (TiO x ), silicon carbide oxide (SiO x C y ) or silicon oxynitride (SiO x N y )form.

[0342] A planarization layer PLL may be disposed on the second cover layer CPL2. The planarization layer PLL may be provided over the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0343] The planarization layer PLL may include an organic material (or substance) such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the present disclosure is not limited thereto. The planarization layer PLL may include a silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ) various inorganic materials (or substances).

[0344] The color filter layer CFL may be disposed on the planarization layer PLL. The color filter layer CFL may include color filters CF1, CF2, and CF3 corresponding to the colors of the corresponding sub-pixels SPX. Since the color filters CF1, CF2, and CF3 corresponding to the corresponding colors of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are disposed, a full-color image may be displayed.

[0345] The color filter layer CFL may include a first color filter CF1 arranged in the first subpixel SPX1 and configured to allow light emitted from the first color conversion layer CCL1 to selectively pass therethrough, a second color filter CF2 arranged in the second subpixel SPX2 and configured to allow light emitted from the second color conversion layer CCL2 to selectively pass therethrough, and a third color filter CF3 arranged in the third subpixel SPX3 and configured to allow light emitted from the light scattering layer LSL to selectively pass therethrough.

[0346] The first color filter CF1 , the second color filter CF2 , and the third color filter CF3 may be a red color filter, a green color filter, and a blue color filter, respectively, but the present disclosure is not limited thereto.

[0347] The first color filter CF1 may overlap the display part LEL (or light emitting element LD) of the first sub-pixel SPX1 and the first color conversion layer CCL1 in the third direction DR3. The first color filter CF1 may include a color filter material for allowing light of the first color (or red light) to selectively pass therethrough. For example, in the case where the first sub-pixel SPX1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0348] The second color filter CF2 may overlap the display part LEL (or light emitting element LD) of the second sub-pixel SPX2 and the second color conversion layer CCL2 in the third direction DR3. The second color filter CF2 may include a color filter material for allowing light of the second color (or green light) to selectively pass through. For example, when the second sub-pixel SPX2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0349] The third color filter CF3 may overlap the display part LEL (or light emitting element LD) and the light scattering layer LSL of the third sub-pixel SPX3 in the third direction DR3. The third color filter CF3 may include a color filter material for allowing light of a third color (or blue light) to selectively pass therethrough. For example, in the case where the third sub-pixel SPX3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

[0350] A light blocking layer BM may be arranged between the first color filter CF1, the second color filter CF2, and the third color filter CF3. The light blocking layer BM may be arranged between the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 or on the boundary between the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The material of the light blocking layer BM is not particularly limited. Various light blocking materials including black matrix materials may be used to form the light blocking layer BM. In the case where the light blocking layer BM is formed between the first color filter CF1, the second color filter CF2, and the third color filter CF3, a color mixing defect visible from the front surface or the side surface of the display device DD may be prevented from occurring. In an embodiment, the light blocking layer BM may be omitted, and the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged to overlap each other between adjacent sub-pixels SPX, and thus serve as a light blocking member to prevent light interference between adjacent sub-pixels SPX.

[0351] The overcoat layer OC may be disposed on the color filter layer CFL. The overcoat layer OC may be provided over the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The overcoat layer OC may cover the lower components including the color filter layer CFL. The overcoat layer OC may prevent water or air from penetrating into the components of the lower layer. In addition, the overcoat layer OC may protect the components of the lower layer from foreign matter such as dust.

[0352] The outer coating layer OC may include an organic material (or substance) such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the present disclosure is not limited thereto. The outer coating layer OC may include an organic material (or substance) including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ) various inorganic materials (or substances).

[0353] Fig.14 It is shown based on Figure 6 Schematic plan view of a pixel PXL including an alignment electrode ALE. Fig.15 yes Fig.14 Schematic enlarged view of a portion of EA. Fig.16 is along Fig.15 A schematic cross-sectional view taken along line III-III'.

[0354] Reference Figures 14 to 16 The description will focus on the differences from the above-mentioned embodiments to avoid redundant description.

[0355] Reference Figures 1 to 16 , the pixel PXL may include a first conductive layer C1, a second conductive layer C2, a third conductive layer C3, and a fourth conductive layer C4 which are continuously formed on a certain surface of the substrate SUB.

[0356] The first conductive layer C1 may include a first vertical power line PL1a, a second power line PL2, an initialization power line IPL, a first data line D1, a second data line D2, a third data line D3, a first bottom metal pattern BML1, a second bottom metal pattern BML2, a third bottom metal pattern BML3, and a connection pattern CNP, which are arranged at positions spaced apart from each other on a substrate SUB.

[0357] The second conductive layer C2 may include first and second additional conductive patterns ACP1 and ACP2 , first and second and third lower electrodes LE1 , LE2 , and LE3 , and a sub-scan line SS1 , which are arranged at positions spaced apart from each other on the second insulating layer INS2 .

[0358] The third conductive layer C3 may include first to eighth conductive patterns CP1 to CP8, which are arranged at positions spaced apart from each other on the third insulating layer INS3, first and second sub-electrodes SUE1 and SUE2, first upper electrodes UE1, second upper electrodes UE2, third upper electrodes UE3, scan lines SC, first contact electrodes CNE1, second contact electrodes CNE2, and third contact electrodes CNE3.

[0359] The fourth conductive layer C4 may include a first alignment electrode ALE1 , a second alignment electrode ALE2 , and a floating pattern FTP that are arranged at positions spaced apart from each other on the fifth insulating layer INS5 .

[0360] The conductive pattern corresponding to the bridge pattern may be arranged in a region corresponding to the first node N1 of each sub-pixel SPX (or each pixel circuit) (e.g., a connection point between the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2). For example, the first conductive pattern CP1 may be positioned on the first node N1 of the first sub-pixel SPX1 (or the first pixel circuit PXC1). The third conductive pattern CP3 may be positioned on the first node N1 of the second sub-pixel SPX2 (or the second pixel circuit PXC2). The fifth conductive pattern CP5 may be positioned on the first node N1 of the third sub-pixel SPX3 (or the third pixel circuit PXC3).

[0361] In the first subpixel SPX1, the first conductive pattern CP1 may overlap with the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2. The first end of the first conductive pattern CP1 may be electrically connected to the second source electrode SE2 of the second transistor T2 through a first contact hole CH1 formed through the second insulating layer INS2 and the third insulating layer INS3. The second end of the first conductive pattern CP1 may be electrically connected to the first gate electrode GE1 of the first transistor T1 through a second contact hole CH2 formed through the third insulating layer INS3. The first node N1 may correspond to a region where the first contact hole CH1 and the second contact hole CH2 are located, and may be a connection point between the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2.

[0362] The second alignment electrode ALE2 may be arranged on the first node N1 of the first sub-pixel SPX1. For example, the second alignment electrode ALE2 may be arranged on the first conductive pattern CP1 (or the bridge pattern BRP) connecting the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 constituting the first node N1. The second alignment electrode ALE2 may be arranged on the first conductive pattern CP1 with the fourth insulating layer INS4 and the fifth insulating layer INS5 interposed therebetween. In a plan view, the second alignment electrode ALE2 may overlap the first conductive pattern CP1 and the first contact hole CH1 and the second contact hole CH2 on the first node N1. In a plan view, the second alignment electrode ALE2 may partially overlap the first conductive pattern CP1 and may completely overlap the first contact hole CH1 and the second contact hole CH2 on the first node N1. For example, in a plan view, the second alignment electrode ALE2 may overlap the first edge of the first conductive pattern CP1 and may not overlap the second edge opposite to the first edge along the second direction DR2.

[0363] In the second subpixel SPX2, the third conductive pattern CP3 may overlap with the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2. The first end of the third conductive pattern CP3 may be electrically connected to the second source electrode SE2 of the second transistor T2 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. The second end of the third conductive pattern CP3 may be electrically connected to the first gate electrode GE1 of the first transistor T1 through a contact hole formed through the third insulating layer INS3. The first node N1 may correspond to a region where the aforementioned contact hole is located, and may be a connection point between the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2.

[0364] The second alignment electrode ALE2 may be disposed on the first node N1 of the second sub-pixel SPX2. For example, the second alignment electrode ALE2 may be disposed on the third conductive pattern CP3 (or bridge pattern BRP) connecting the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 constituting the first node N1. The second alignment electrode ALE2 may be disposed on the fifth insulating layer INS5. In a plan view, the second alignment electrode ALE2 may overlap the third conductive pattern CP3 and the aforementioned contact hole on the first node N1.

[0365] In the third subpixel SPX3, the fifth conductive pattern CP5 may overlap the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2. The first end of the fifth conductive pattern CP5 may be electrically connected to the second source electrode SE2 of the second transistor T2 through a contact hole formed through the second insulating layer INS2 and the third insulating layer INS3. The second end of the fifth conductive pattern CP5 may be electrically connected to the first gate electrode GE1 of the first transistor T1 through a contact hole formed through the third insulating layer INS3. The first node N1 may correspond to a region where the aforementioned contact hole is located, and may be a connection point between the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2.

[0366] The second alignment electrode ALE2 may be disposed on the first node N1 of the third sub-pixel SPX3. For example, the second alignment electrode ALE2 may be disposed on the fifth conductive pattern CP5 positioned on the first node N1. The second alignment electrode ALE2 may be disposed on the fifth insulating layer INS5. The second alignment electrode ALE2 may overlap with the fifth conductive pattern CP5 (or bridge pattern BRP) connecting the first gate electrode GE1 of the first transistor T1 and the second source electrode SE2 of the second transistor T2 constituting the first node N1.

[0367] The second alignment electrode ALE2 may be electrically connected to the second power line PL2. The voltage of the second driving power source VSS may be applied to the second alignment electrode ALE2 from the second power line PL2. The second alignment electrode ALE2 may extend in the second direction DR2 and may have a plate shape overlapping the first conductive pattern CP1, the fifth conductive pattern CP5, and the third conductive pattern CP3 arranged in the second direction DR2 to cover all of the first conductive pattern CP1, the fifth conductive pattern CP5, and the third conductive pattern CP3.

[0368] In an embodiment, the second alignment electrode ALE2 may be used as a shielding member to reduce or minimize a coupling capacitance (e.g., a parasitic capacitance) occurring between the first node N1 of the first subpixel SPX1 and the first node N1 of the third subpixel SPX3. In addition, the second alignment electrode ALE2 may be used as a shielding member to reduce or minimize a coupling capacitance occurring between the first node N1 of the third subpixel SPX3 and the first node N1 of the second subpixel SPX2.

[0369] In detail, since the second alignment electrode ALE2 configured to receive the voltage of the second driving power source VSS is arranged on the first node N1 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, it is possible to reduce or prevent a phenomenon in which a change in the voltage (or signal) applied to the first node N1 of the first sub-pixel SPX1 causes a change in the voltage (or signal) applied to the first node N1 of the third sub-pixel SPX3, which is an adjacent sub-pixel SPX. In addition, since the second alignment electrode ALE2 configured to receive the voltage of the second driving power source VSS is arranged on the first node N1 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, it is possible to reduce or prevent a change in the voltage (or signal) applied to the first node N1 of the third sub-pixel SPX3 causes a change in the voltage (or signal) applied to the first node N1 of the second sub-pixel SPX2, which is an adjacent sub-pixel SPX.

[0370] Therefore, the second alignment electrode ALE2 can be used as a shielding component to reduce or minimize the coupling capacitance (e.g., parasitic capacitance) occurring between the first node N1 of the first subpixel SPX1 and the first node N1 of the third subpixel SPX3, and the coupling capacitance (e.g., parasitic capacitance) occurring between the first node N1 of the third subpixel SPX3 and the first node N1 of the second subpixel SPX2.

[0371] Furthermore, the second alignment electrode ALE2 may be positioned on the first node N1 of the first subpixel SPX1 to overlap the first node N1 in a plan view, thereby reducing or minimizing coupling capacitance occurring between the first node N1 and the contact portion CNT of the adjacent subpixel SPX.

[0372] According to the aforementioned embodiment, the parasitic capacitance of each sub-pixel SPX can be reduced, thereby enhancing the display device (see Figure 3 The reliability of the display device DD).

[0373] According to the aforementioned embodiment, the line width of each of the first data line D1 electrically connected to the first sub-pixel SPX1, the second data line D2 electrically connected to the second sub-pixel SPX2, and the third data line D3 electrically connected to the third sub-pixel SPX3 can be reduced (for example, from about 10.5 μm in the conventional art to about 7 μm in the embodiment), thereby reducing the surface area occupied by the first data line D1, the second data line D2, and the third data line D3 in each pixel PXL. In this case, the reduced surface area (or size) of the first data line D1, the second data line D2, and the third data line D3 in each pixel PXL can be used to ensure the surface area of ​​the storage capacitor of the corresponding pixel PXL.

[0374] Specifically, in the first subpixel SPX1, the reduced surface areas of the first data line D1, the second data line D2, and the third data line D3 may be used to increase the surface area of ​​the first bottom metal pattern BML1 and the corresponding surface areas of the first lower electrode LE1 overlapping the first bottom metal pattern BML1 and the first upper electrode UE1 overlapping the first lower electrode LE1. Therefore, the overlapping surface areas of the first bottom metal pattern BML1, the first lower electrode LE1, and the first upper electrode UE1 overlapping each other with the insulating layer interposed therebetween are further increased, thereby resulting in an increase in the capacitance of the first storage capacitor Cst1.

[0375] In the second subpixel SPX2, the reduced surface areas of the first data line D1, the second data line D2, and the third data line D3 may be used to increase the surface area of ​​the second bottom metal pattern BML2 and the corresponding surface areas of the second lower electrode LE2 overlapping the second bottom metal pattern BML2 and the second upper electrode UE2 overlapping the second lower electrode LE2. Therefore, the overlapping surface areas of the second bottom metal pattern BML2, the second lower electrode LE2, and the second upper electrode UE2 overlapping each other with the insulating layer interposed therebetween are further increased, thereby resulting in an increase in the capacitance of the second storage capacitor Cst2.

[0376] In the third subpixel SPX3, the reduced surface areas of the first data line D1, the second data line D2, and the third data line D3 may be used to increase the surface area of ​​the third bottom metal pattern BML3 and the corresponding surface areas of the third lower electrode LE3 overlapping the third bottom metal pattern BML3 and the third upper electrode UE3 overlapping the third lower electrode LE3. Therefore, the overlapping surface areas of the third bottom metal pattern BML3, the third lower electrode LE3, and the third upper electrode UE3 overlapping each other with the insulating layer interposed therebetween are further increased, thereby resulting in an increase in the capacitance of the third storage capacitor Cst3.

[0377] Fig.17 According to another embodiment Fig.14Schematic enlarged view of a portion of EA. Fig.18 is along Fig.17 Schematic cross-sectional view taken along line IV-IV'. Fig.19 According to another embodiment Fig.14 Schematic enlarged view of a portion of EA. Fig. 20 is along Fig.19 A schematic cross-sectional view taken along line V-V'.

[0378] Figures 17 to 20 The embodiment shows Fig.15 and Fig.16 A modification of the embodiment shown in FIG. 1 regarding the overlapping area of ​​the second alignment electrode ALE2 and the first conductive pattern CP1 .

[0379] Figures 17 to 20 The description of the embodiment of will focus on the differences from the above-mentioned embodiment to avoid redundant description.

[0380] Reference Fig.14 and Figures 17 to 20 , the second alignment electrode ALE2 may be arranged on the first node N1 in the first subpixel SPX1. For example, the second alignment electrode ALE2 may be arranged on the first conductive pattern CP1 arranged in the region corresponding to the first node N1. The second alignment electrode ALE2 may be arranged on the first conductive pattern CP1 with the fourth insulating layer INS4 and the fifth insulating layer INS5 interposed therebetween.

[0381] The second alignment electrode ALE2 may partially overlap the first conductive pattern CP1 on the first node N1.

[0382] For example, Fig.17 and Fig.18 As shown in , in a plan view, the second alignment electrode ALE2 may overlap with the second contact hole CH2 and may not overlap with the first contact hole CH1. In a plan view, the second alignment electrode ALE2 may completely overlap with the second contact hole CH2 and may not overlap with the first contact hole CH1. In a plan view, the second alignment electrode ALE2 may overlap with the first edge of the first conductive pattern CP1 and the second contact hole CH2 on the first node N1. For example, the width of the second alignment electrode ALE2 in the region overlapping with the first gate electrode GE1 along the second direction DR2 may be greater than the width of the second alignment electrode ALE2 in the region overlapping with the second source electrode SE2 along the second direction DR2.

[0383] In an embodiment, if Fig.19 and Fig. 20As shown in , in a plan view, the second alignment electrode ALE2 may overlap with the first contact hole CH1, and may not overlap with the second contact hole CH2. In a plan view, the second alignment electrode ALE2 may completely overlap with the first contact hole CH1, and may not overlap with the second contact hole CH2. In a plan view, the second alignment electrode ALE2 may overlap with the first edge of the first conductive pattern CP1 and the first contact hole CH1 on the first node N1. For example, the width of the second alignment electrode ALE2 in the region overlapping with the first gate electrode GE1 along the second direction DR2 may be narrower than the width of the second alignment electrode ALE2 in the region overlapping with the second source electrode SE2 along the second direction DR2.

[0384] Since the second alignment electrode ALE2 to which the voltage of the second driving power supply VSS is applied is partially arranged on the first node N1 of the first sub-pixel SPX1, it is possible to reduce the phenomenon that the change of the voltage (or signal) applied to the first node N1 of the first sub-pixel SPX1 causes the change of the voltage applied to the first node N1 of the adjacent sub-pixel SPX.

[0385] In an embodiment, a conductive pattern (or a bridge pattern) positioned on the first node of each sub-pixel (e.g., a connection point where the gate electrode of the first transistor and the source electrode of the second transistor are electrically connected to each other) may overlap with an alignment electrode to which a certain voltage is applied, thereby reducing coupling capacitance (or parasitic capacitance) occurring at the first nodes of adjacent sub-pixels, thereby providing a display device with improved reliability.

[0386] In an embodiment, the capacitance of a storage capacitor of each sub-pixel may be enhanced, thereby making it possible to provide a display device with improved reliability.

[0387] The effects of the present disclosure are not limited to the foregoing contents, and other various effects are expected herein.

[0388] While various exemplary embodiments have been described above, those skilled in the art will appreciate that various modifications, additions, and substitutions are possible, without departing from the scope of the present disclosure.

[0389] Therefore, the embodiments disclosed in this specification are only for illustrative purposes, rather than limiting the technical spirit of the present disclosure. The scope of the present disclosure must be defined by the appended claims.

Claims

1. A display device, characterized in that: The display device comprises: a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged adjacent to each other, Wherein, each of the first sub-pixel, the second sub-pixel and the third sub-pixel comprises: a pixel circuit layer, the pixel circuit layer comprising a first transistor, a second transistor and a third transistor arranged on a substrate, a bridge pattern disposed on a gate electrode of the first transistor and a source electrode of the second transistor, a first end of the bridge pattern being electrically connected to the source electrode of the second transistor, and a second end of the bridge pattern being electrically connected to the gate electrode of the first transistor; a first alignment electrode and a second alignment electrode, the first alignment electrode and the second alignment electrode being arranged on the pixel circuit layer and spaced apart from each other; and a plurality of light emitting elements arranged on the first alignment electrode and the second alignment electrode and electrically connected to at least one of the first transistor, the second transistor, and the third transistor, The second alignment electrode is supplied with a low potential voltage and overlaps with the bridge pattern in a plan view.

2. The display device according to claim 1, characterized in that The pixel circuit layer includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer which are sequentially stacked on the substrate, and The source electrode of the second transistor is arranged on the first insulating layer, the gate electrode of the first transistor is arranged on the second insulating layer, the bridge pattern is arranged on the third insulating layer, and the second alignment electrode is arranged on the fifth insulating layer.

3. The display device according to claim 2, characterized in that: The first end of the bridge pattern is electrically connected to the source electrode of the second transistor through a first contact hole formed through the second insulating layer and the third insulating layer, and The second end of the bridge pattern is electrically connected to the gate electrode of the first transistor through a second contact hole formed through the third insulating layer.

4. The display device according to claim 3, characterized in that: The second alignment electrode overlaps the first contact hole and the second contact hole.

5. The display device according to claim 2, characterized in that: Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes: A contact electrode, wherein the contact electrode is arranged on the third insulating layer; the fourth insulating layer and the fifth insulating layer, the fourth insulating layer and the fifth insulating layer being arranged on the contact electrode and each including a contact portion exposing the contact electrode; and A plurality of electrodes are arranged on the first alignment electrode, the second alignment electrode, and the plurality of light emitting elements on the fifth insulating layer and are electrically connected to the plurality of light emitting elements.

6. The display device according to claim 1, characterized in that: The bridge pattern of the first sub-pixel, the bridge pattern of the third sub-pixel, and the bridge pattern of the second sub-pixel are sequentially arranged in a second direction in a plan view, and The second alignment electrode has a plate shape, extends in the second direction, and overlaps the bridge pattern of the first sub-pixel, the bridge pattern of the third sub-pixel, and the bridge pattern of the second sub-pixel.

7. The display device according to claim 6, characterized in that: In each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, the gate electrode of the first transistor, the source electrode of the second transistor, and the bridge pattern electrically connected to each other form a first node, and The second alignment electrode is a shielding member to prevent parasitic capacitance from occurring between the first nodes of sub-pixels that are adjacent to each other in the second direction among the first sub-pixel, the second sub-pixel, and the third sub-pixel.

8. The display device according to claim 1, characterized in that: For each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, the display device further includes a data line configured to transmit a data signal and extending in a second direction, The data line has a width of 7 μm in a first direction intersecting with the second direction.

9. A display device, characterized in that: The display device comprises: substrate; a first sub-pixel, a third sub-pixel, and a second sub-pixel, wherein the first sub-pixel, the third sub-pixel, and the second sub-pixel are arranged adjacent to each other in the second direction, each including an emission region and a non-emission region, and are arranged on the substrate; a first data line, a second data line and a third data line, wherein the first data line is configured to apply a data signal to the first sub-pixel, the second data line is configured to apply a data signal to the second sub-pixel, and the third data line is configured to apply a data signal to the third sub-pixel; a plurality of light emitting elements, the plurality of light emitting elements being arranged in the emission region of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel; a first transistor, a second transistor, and a third transistor, the first transistor, the second transistor, and the third transistor being positioned between the substrate and the plurality of light emitting elements and electrically connected to the plurality of light emitting elements; a bridge pattern electrically connecting a gate electrode of the first transistor and a source electrode of the second transistor; a first alignment electrode and a second alignment electrode, the first alignment electrode and the second alignment electrode being positioned between the bridge pattern and the plurality of light emitting elements and arranged to be spaced apart from each other; and a plurality of electrodes arranged on the first alignment electrode and the second alignment electrode and electrically connected to the plurality of light emitting elements, and The second alignment electrode overlaps the bridge pattern of the first sub-pixel, the bridge pattern of the second sub-pixel, and the bridge pattern of the third sub-pixel in a plan view.

10. The display device according to claim 9, characterized in that: The first alignment electrode is a floating electrode, and the second alignment electrode is supplied with a low potential voltage.

Images