Bus signal output device
By designing a bus signal output device including a command word receiving module, multiple register units and a digital-to-analog converter, the shortcomings of traditional devices in processing complex bus signals are solved, and the accurate reception of command words and flexible processing of different types of signals are realized, and the diversity and accuracy of signal output are improved.
Patent Information
- Application Number
- CN202421487833.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-04-01
- Estimated Expiration
- 2034-06-27
AI Technical Summary
When traditional signal output devices process complex bus signals, the command word reception and processing method is simple, and cannot accurately count the number of received data, resulting in insufficient analysis and allocation. At the same time, the storage unit design is not flexible enough to effectively process different types of effective bit data, limiting the diversity and accuracy of signal output.
A bus signal output device is designed, including a command word receiving module, a plurality of registering units and a digital-to-analog converter. The command word receiving module realizes accurate reception and counting of command words through the command word register and command word byte accumulator. A plurality of register units, including first and second effective bit registers, are able to process different types of signals respectively. The digital-to-analog converter converts the processed signal into an output signal.
Through this device, accurate reception and processing of command words is realized, ensuring the completeness and accuracy of data. The design of multiple register units allows for the flexibility of processing different types of signals, improving the diversity and accuracy of signal output. Digital-to-analog converters meet the needs of different types of output signals.
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Figure CN222704990U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of waveform generators, and in particular to a bus signal output device. Background Art
[0002] In modern electronic systems, it is crucial to process and output bus signals accurately and efficiently. With the continuous development of technology, the requirements for bus signal processing are getting higher and higher. Traditional signal output devices have gradually revealed many shortcomings when facing complex signal processing requirements. In past designs, the reception and processing methods of command words were relatively simple, and it might not be possible to accurately count the number of times data was received, resulting in inaccurate parsing and allocation of command words. At the same time, the design of the register unit may not be flexible enough to effectively process different types of valid bit data separately, limiting the diversity and accuracy of signal output. The digital-to-analog conversion link may also have problems such as low conversion accuracy, slow speed, or inability to adapt to a variety of complex signal inputs.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Utility Model Content
[0004] In view of at least one of the above technical problems, the present application provides a bus signal output device, which solves the problem that the reception and processing method of command words is relatively simple and may not be able to accurately count the number of received data, resulting in inaccurate analysis and allocation of command words. At the same time, the design of the register unit may not be flexible enough to effectively process different types of valid bit data separately, limiting the diversity and accuracy of signal output.
[0005] The embodiment of the present application provides a bus signal output device, including:
[0006] A command word receiving module, comprising: a command word register and a command word byte accumulator, wherein the command word register is connected to the command word byte accumulator, the command word register is configured to sequentially receive each byte of data in the command word, and the command word byte accumulator is configured to accumulate the number of times the command word register receives data;
[0007] A plurality of register units connected to the command word register, the command word register being further configured to output data to the register units in sequence according to the number of times of the command word byte accumulator;
[0008] Each of the register units comprises: a first valid bit register and a second valid bit register, wherein the first valid bit register and the second valid bit register are respectively connected to the command word register, the first valid bit register is configured to output a first signal, and the second valid bit register is configured to output a second signal;
[0009] The digital-to-analog converter is configured to convert the first signal and the second signal into an output signal.
[0010] One of the above technical solutions has at least one of the following advantages or beneficial effects: The bus signal output device realizes accurate reception and frequency counting of command words through the cooperation of the command word register and the command word byte accumulator in the command word receiving module, thereby ensuring the integrity and accuracy of the data. The command word register sequentially outputs data to the register unit according to the frequency value, thereby realizing orderly data transmission and distribution. By setting a plurality of register units, including a first valid bit register and a second valid bit register, different types of signals are processed separately and prepared for output. The first signal is output by the first valid bit register and the second signal is output by the second valid bit register, thereby realizing independent generation of a specific signal. The first signal and the second signal are converted into output signals by a digital-to-analog converter, thereby realizing the conversion of digital signals to analog signals, thereby meeting different types of output requirements.
[0011] In some possible implementations, the register unit further includes: a bus mode register, a baud rate register, a total number of valid bits register, and a frame interval register respectively connected to the command word register.
[0012] In some possible implementations, the register unit also includes: a baud rate accumulator, a first comparator, a bit output total accumulator, a second comparator, a frame interval time accumulator and a third comparator, the output end of the baud rate accumulator and the output end of the baud rate register are connected to the input end of the first comparator, the output end of the first comparator is connected to the input end of the bit output total accumulator, the output end of the bit output total accumulator and the output end of the valid bit total register are connected to the input end of the second comparator, the output end of the second comparator is connected to the input end of the frame interval time accumulator, the output end of the frame interval time accumulator and the output end of the frame interval register are connected to the input end of the third comparator, and the output end of the third comparator is connected to the input end of the baud rate accumulator.
[0013] In some possible implementations, the device further includes: a processor, the output end of the first valid bit register and the output end of the second valid bit register are connected to the processor, and the digital-to-analog converter is connected to the processor.
[0014] In some possible implementations, the device further includes: a clock module, configured to provide a 100 MHz clock.
[0015] The present invention will be further described below in conjunction with the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0017] Figure 1 A structural diagram of a bus signal output device provided in an embodiment of the present application;
[0018] Figure 2 A first structural diagram of a storage unit provided in an embodiment of the present application;
[0019] Figure 3 A second structural diagram of a storage unit provided in an embodiment of the present application;
[0020] Figure 4 for Figure 1 Schematic diagram of the bus signal output device;
[0021] Figure 5 for Figure 1 Schematic diagram of the storage unit in the middle;
[0022] Among them, 100, command word receiving module; 110, command word register; 120, command word byte accumulator; 200, register unit; 210, bus mode register; 220, baud rate register; 230, effective bit total register; 240, frame interval register; 250, first effective bit register; 260, second effective bit register; 270, baud rate accumulator; 280, bit output total accumulator; 290, frame interval time accumulator; 200a, first comparator; 200b, second comparator; 200c, third comparator; 300, digital-to-analog converter; 400, processor; 500, clock module; 510, crystal oscillator; 520, phase-locked loop; DETAILED DESCRIPTION
[0023] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.
[0024] In the present application, the input data is pre-encoded into a command word, and then the command word is input into the bus signal output device for decoding, and finally the signal is output. Among them, the command word is a byte or a group of bytes used for control and communication, which contains specific instructions and data to instruct the system or device to perform a certain operation. The command word is used for communication between the host computer and the FPGA, and is a way to achieve real-time parameter changes. In this embodiment, the command word is a four-channel command word, and each channel command word includes a bus mode part, a baud rate part, a total number of valid bits part, a frame interval time part, a first valid bit encoding part, and a second valid bit encoding part defined in sequence. Specifically:
[0025] Bus mode (CHx_Mode): 1 byte width, defines the type of the current bus signal (for example: 0x01 for UART, 0x02 for I2C, 0x03 for SPI, 0x04 for CAN, 0x05 for CAN-FD, 0x06 for LIN, 0x07 for FlexRay, 0x08 for SENT, 0x09 for I2S, 0x0A for 1553B, 0x0B for ARINC429, 0x0C for USB).
[0026] Baud rate (CHx_BaudRate): 3 bytes wide, defines the baud rate of the current bus signal. Assume that the FPGA clock frequency is Freq, in Hz, and the baud rate is Baud, in bps. The calculation formula is:
[0027]
[0028] Total number of effective bits (CHx_Bit_Sum): 2 bytes wide. Before converting the effective bit encoding segment into hexadecimal, calculate the total number of binary data bits in the segment, i.e. the total number of effective bits.
[0029] Frame interval time (CHx_Interval): 4 bytes wide, defines the time interval between each frame signal of the current bus signal. Assume that the FPGA clock frequency is Freq, unit Hz, and the baud rate is Tint, unit s. The calculation formula is:
[0030] CHx_Interval=Frep*Tint
[0031] The first significant bit code (CHx_1_Bit): 100 bytes wide, and together with the second significant bit code, defines the signal that the current bus will eventually output.
[0032] The second significant bit code (CHx_2_Bit): 100 bytes wide, and together with the first significant bit code, defines the signal that the current bus will eventually output.
[0033] It can be understood that the number of bytes of the command word of one channel is 210, and the number of bytes of the command word of four channels is 840.
[0034] Figure 1 A structural diagram of a bus signal output device provided in an embodiment of the present application; Figure 2 A first structural diagram of a storage unit provided in an embodiment of the present application; Figure 3 A second structural diagram of a storage unit provided in an embodiment of the present application; Figure 4 for Figure 1 Schematic diagram of the bus signal output device; Figure 5 for Figure 1 The schematic diagram of the register unit in FIG. Figures 1 to 5 As shown, the bus signal output device includes: a command word receiving module 100, a register unit 200, a digital-to-analog converter 300, a processor 400 and a clock module 500. The bus signal output device is specifically introduced as follows.
[0035] The command word receiving module 100 includes: a command word register 110 and a command word byte accumulator 120, the command word register 110 is connected to the command word byte accumulator 120, the command word register 110 is configured to receive each byte data in the command word in sequence, and the command word byte accumulator 120 is configured to accumulate the number of times the command word register 110 receives data.
[0036] A plurality of register units 200 connected to the command word register 110, the command word register 110 is further configured to output data to the register units 200 in sequence according to the times of the command word byte accumulator 120;
[0037] Each of the register units 200 includes: a first valid bit register 250 and a second valid bit register 260, wherein the first valid bit register 250 and the second valid bit register 260 are respectively connected to the command word register 110, the first valid bit register 250 is configured to output a first signal, and the second valid bit register 260 is configured to output a second signal;
[0038] The digital-to-analog converter 300 is configured to convert the first signal and the second signal into an output signal.
[0039] It is worth noting that when the value of the command word byte accumulator 120 is 840, the value of the command word byte accumulator 120 is cleared to zero, which means that a command word has been received.
[0040] For example, when the value of the command word byte accumulator 120 is 840, the value of the command word byte accumulator 120 is cleared. Subsequently, the processor 400 sends a signal to enable the first valid bit register 250 to start outputting the first signal and the second valid bit register 260 to output the second signal, and the first signal and the second signal are converted into an output signal.
[0041] The bus signal output device realizes accurate reception and frequency statistics of command words through the cooperation of the command word register 110 and the command word byte accumulator 120 in the command word receiving module 100, thereby ensuring the integrity and accuracy of the data. The command word register 110 outputs data to the register unit 200 in sequence according to the frequency value, thereby realizing orderly data transmission and distribution. By setting a plurality of register units 200, including a first valid bit register 250 and a second valid bit register 260, different types of signals are processed and prepared for output separately. The first valid bit register 250 outputs the first signal and the second valid bit register 260 outputs the second signal, thereby realizing independent generation of specific signals. The first signal and the second signal are converted into output signals through the digital-to-analog converter 300, thereby realizing the conversion of digital signals into analog signals, thereby meeting different types of output requirements.
[0042] The register unit 200 further includes: a bus mode register 210 , a baud rate register 220 , a total number of valid bits register 230 and a frame interval register 240 , which are respectively connected to the command word register 110 .
[0043] The register unit 200 further includes: a baud rate accumulator 270, a first comparator 200a, a bit output total accumulator 280, a second comparator 200b, a frame interval time accumulator 290 and a third comparator 200c. The output end of the baud rate accumulator 270 and the output end of the baud rate register 220 are connected to the input end of the first comparator 200a, the output end of the first comparator 200a is connected to the input end of the bit output total accumulator 280, the output end of the bit output total accumulator 280 and the output end of the effective bit total register 230 are connected to the input end of the second comparator 200b, the output end of the second comparator 200b is connected to the input end of the frame interval time accumulator 290, the output end of the frame interval time accumulator 290 and the output end of the frame interval register 240 are connected to the input end of the third comparator 200c, and the output end of the third comparator 200c is connected to the input end of the baud rate accumulator 270.
[0044] The device further includes: a processor 400, an output end of the first valid bit register 250 and an output end of the second valid bit register 260 are connected to the processor 400, and the digital-to-analog converter 300 is connected to the processor 400.
[0045] The device further includes: a clock module 500 for providing a 100 MHz clock, wherein the clock module 500 includes a crystal oscillator 510 and a phase-locked loop 520, the frequency of the crystal oscillator 510 is 50 MHz, and the phase-locked loop 520 is used to multiply the frequency of the crystal oscillator 510 to generate 100 MHz.
[0046] The command word receiving stage is introduced as follows.
[0047] Each time the command word register 110 receives a byte of data, that is, sequentially receives data from the first byte of the command word, the command word byte accumulator 120 accumulates 1. For example, if Figure 3As shown, when the command word register 110 receives the first byte data of the command word, the command word byte accumulator 120 accumulates 1, and the value of the command word byte accumulator 120 is 1, so the first byte data is input to the bus mode register 210 of the first register unit 200. When the command word register 110 receives the second byte data of the command word, the command word byte accumulator 120 accumulates 1, and the value of the command word byte accumulator 120 is 2, so the second byte data is input to the baud rate register 220 of the first register unit 200. When the command word register 110 receives the third byte data of the command word, the command word byte accumulator 120 accumulates 1, and the value of the command word byte accumulator 120 is 3, so the third byte data is input to the baud rate register 220 of the first register unit 200. After the first register unit 200 receives two hundred and ten bytes of data, the second register unit 200 starts to receive bytes of data, and so on, until the fourth register unit 200 receives eight hundred and forty bytes of data.
[0048] It is worth noting that when the value of the command word byte accumulator 120 is equal to 840, the value of the command word byte accumulator 120 is cleared, and an enable signal is output to the first valid bit register 250 and the second valid bit register 260 of each register unit 200 .
[0049] The output stage of the output signal is introduced as follows.
[0050] like Figure 4 As shown, the bus mode register 210 is used to determine the communication protocol. The first signal of the first valid bit register 250 and the second signal of the second valid bit register 260 jointly generate a control signal, which is converted into a DA value of a corresponding bus signal based on Table 1, which is a DA value table corresponding to the communication protocol and the control signal, and is converted into an output signal through the digital-to-analog converter 300.
[0051] In this embodiment, the control signal is composed of the first signal of the first valid bit register 250 and the second signal of the second valid bit register 260. The control signal is then converted into a DA value of a corresponding bus signal, and converted into an output signal through a digital-to-analog converter 300, as shown in Table 1, which is a DA value table corresponding to a communication protocol and a control signal.
[0052]
[0053] Table 1 is the DA value table corresponding to the communication protocol and control signal
[0054] Continue reading Figure 4In this embodiment, at a clock frequency of 100 MHz, the baud rate accumulator 270 accumulates 1 per clock cycle. When the baud rate accumulator 270 is equal to the baud rate register 220, the baud rate accumulator 270 is cleared, and the bit output total accumulator 280 accumulates 1. When the bit output total accumulator 280 is equal to the effective bit total register 230, a frame signal is output, a disable signal is output, and the frame interval time accumulator 290 starts to accumulate. When the frame interval time accumulator 290 is equal to the frame interval register 240, an enable signal is output to the baud rate accumulator 220, and a new frame signal cycle begins.
[0055] The bus mode register selects different bus signal outputs according to different values. The total number of bit outputs is accumulated as the subscript index of the first effective bit register to achieve the change of the output signal. The first effective bit register and the second effective bit register jointly control the DA value of the DAC, and then output the output signal.
[0056] In the description of the present application, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0057] In the description of the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0058] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.
[0059] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0060] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.
[0061] The above is only a preferred embodiment of the present application and does not constitute any formal limitation to the present application. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present application by using the above disclosed methods and technical contents without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, all equivalent changes made according to the shape, structure and principle of the present application without departing from the content of the technical solution of the present application should be included in the protection scope of the present application.
Claims
1. A bus signal output device, characterized in that: include: A command word receiving module, comprising: a command word register and a command word byte accumulator, wherein the command word register is connected to the command word byte accumulator, the command word register is configured to sequentially receive each byte of data in the command word, and the command word byte accumulator is configured to accumulate the number of times the command word register receives data; A plurality of register units connected to the command word register, the command word register being further configured to output data to the register units in sequence according to the number of times of the command word byte accumulator; Each of the register units comprises: a first valid bit register and a second valid bit register, wherein the first valid bit register and the second valid bit register are respectively connected to the command word register, the first valid bit register is configured to output a first signal, and the second valid bit register is configured to output a second signal; The digital-to-analog converter is configured to convert the first signal and the second signal into an output signal.
2. The bus signal output device according to claim 1, characterized in that: The register unit further comprises: a bus mode register, a baud rate register, a total number of valid bits register and a frame interval register respectively connected to the command word register.
3. The bus signal output device according to claim 2, characterized in that: The register unit also includes: a baud rate accumulator, a first comparator, a bit output total accumulator, a second comparator, a frame interval time accumulator and a third comparator. The output end of the baud rate accumulator and the output end of the baud rate register are connected to the input end of the first comparator, the output end of the first comparator is connected to the input end of the bit output total accumulator, the output end of the bit output total accumulator and the output end of the valid bit total register are connected to the input end of the second comparator, the output end of the second comparator is connected to the input end of the frame interval time accumulator, the output end of the frame interval time accumulator and the output end of the frame interval register are connected to the input end of the third comparator, and the output end of the third comparator is connected to the input end of the baud rate accumulator.
4. The bus signal output device according to claim 1, characterized in that: The device further includes: a processor, an output end of the first valid bit register and an output end of the second valid bit register are connected to the processor, and the digital-to-analog converter is connected to the processor.
5. The bus signal output device according to any one of claims 1 to 4, characterized in that: The device also includes: a clock module, used for providing a 100 MHz clock.