A wirelessly powered programmable high-speed and high-precision clock pulse generating circuit

Abstract

The utility model provides a wireless power-granting programmable high-speed and high-precision clock pulse generating circuit. It includes detection and filtering of external input signals, waveform shaping of demodulated signals, a clock control circuit for outputting timing signals, a central processing unit MCU for programming the output signal of the clock control circuit; a signal comparison circuit for high speed and low power consumption; and a voltage stabilizing circuit for the clock control circuit and the central processing unit MCU. The circuit adopts a programmable clock control circuit with a timing interrupt output, and the power consumption is extremely low when in sleep mode, which solves the problem of high power consumption of ordinary timing circuits. The waveform shaping circuit composed of the comparator inside the central processing unit MCU and the external additional circuit effectively filters out clutter interference and avoids the occurrence of bit errors, realizing wireless power granting and high-speed receiving and decoding capabilities. Once the power is granted, it can work normally for 10 seconds, reducing the module's dependence on power supply and expanding the application scenarios of the module.

Description

Technical Field

[0001] The utility model relates to the field of electronic technology, and specifically to a wireless power-granting programmable high-speed and high-precision clock pulse generating circuit. Background Art

[0002] In today's society, electronic automation and semiconductor technology are developing rapidly. The emergence of more and more automated equipment has replaced the previous manual control work, greatly improving the monitoring accuracy and work efficiency. At present, automated control equipment is almost everywhere, such as video surveillance, power monitoring, and safety monitoring in the engineering field, and is growing at a geometric rate. With economic development and social progress, the miniaturization, portability, and high performance of electrical appliances have become a development trend. At present, although many electrical appliances have intelligent functions such as timing, these appliances are generally expensive, large in size, high in power consumption, external power supply, poor performance, and inconvenient to use. How to optimize the timing circuit, make it miniaturized, cheap, portable, and achieve high performance, greatly broaden its application field, and become a major research direction for major electrical appliance manufacturers.

[0003] Energy saving, environmental protection and ease of use are the themes of development in all industries at present. The current common practice of energy saving and consumption reduction is to use two low-power timing modules embedded in or embedded in the control chip to achieve management, that is, after the electronic product completes normal work (high power mode), it immediately enters the sleep state (low power mode), and after the timing time, it exits the sleep state and enters the normal working state again, thereby achieving maximum energy saving and consumption reduction and easy use. Currently, wireless communication and contactless power granting are usually used to solve power supply and communication problems, that is, when the electronic product is close to the signal transmitter, it immediately receives energy, the circuit starts and works, and communicates with the transmitter to complete the wireless communication function without the need to introduce a power supply. However, most of the low-power implementation solutions for electronic products on the market are either at the 1mA level, or the timing accuracy of the timing module is not enough to meet the specific needs of specific occasions. In addition, the existing intelligent timing devices are fixedly installed on a certain device and require an external power supply. They can only be fixed by embedding and cannot be moved, which is inconvenient to move for use between different occasions. Therefore, there is an urgent need in the art to develop an intelligent timing device that can wirelessly grant power for accurate timing, is extremely power-saving, and can output high pulses. Utility Model Content

[0004] In view of the technical problems existing in the prior art, the purpose of the utility model is to provide a wireless power-granting programmable high-speed and high-precision clock pulse generating circuit. The circuit adopts a programmable clock control circuit with a timed interrupt output, and adopts wireless communication and wireless power granting to provide the energy required for the circuit to work. Wireless communication can also be performed while wireless power granting, and no external power supply is required, which completely solves the power supply problem of ordinary circuits. It is simple and convenient, and one power grant can last for at least 10 seconds of normal operation, which not only realizes extremely high-speed receiving and decoding capabilities, but also can set the timing value of the timer in a very short time while reducing the module's dependence on power.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] A wirelessly enabled programmable high-speed and high-precision clock pulse generating circuit, characterized in that it includes a detection and filtering circuit for an external input signal, a clock control circuit for outputting a timing signal, a central processing unit MCU for programming the time when the clock control circuit outputs the signal; a signal comparison circuit used in the MCU for high-speed and low-power push-pull output signal processing; and a voltage stabilizing circuit for providing stable power to the clock control circuit and the central processing unit MCU.

[0007] Preferably, the detection and filtering circuit for the external signal input includes a diode D5, a capacitor C6, a resistor R5, and signal input terminals J1 and J3; a signal output terminal info; the signal input terminals are J1 and J3; the signal output terminal is connected to pin 14 of the single-chip computer U2; the signal input terminal J1 is connected to the anode of D5; the signal input terminal J3 is connected to the cathode of D4; the signal output terminal info is connected to C6, R5, and one end of D5 at the same time, the other end of R5 is connected to 3.3V, and the other end of C6 is grounded.

[0008] Preferably, the external wireless energy granting circuit includes a rectifier diode pair D3, D4, a capacitor C1, resistors R00, R01, a voltage regulator diode D1, and the energy input end and the signal input end share terminals J1, J3; the energy input end is J1, J3; the energy input end J1 is connected to pin 3 of D3, pin 2 of D3 is connected to pin 2 of D4, one end of R00 and R01 is simultaneously connected (Vcc), and pin 1 of D3 is grounded; the energy input end J3 is connected to pin 3 of D4, and pin 1 of D4 is grounded; the energy output end, that is, pin 2 of D4 is connected to one end of R00 and R01 at the same time, the other end of R00 and R01 is connected to pin 1 of C1, C3, D1, and U1 at the same time, the other end of C1, C3, and D1 is simultaneously grounded, and pin 2 of U1 is grounded.

[0009] Preferably, the voltage stabilizing circuit for providing stable electric energy for the clock control circuit and the central processing unit MCU includes a voltage stabilizing chip U1, capacitors C2, C4, pins of U1 are 1, 2, 3, 4, 5, and the voltage stabilizing input terminal is pin 1 of U1; pins 3 and 4 of U1 are suspended, and pin 5 of U1 is the voltage stabilizing output terminal VDD, and the voltage stabilizing output terminal VDD (3.3V) is connected to one end of C2 and C4 at the same time, and the other ends of C2 and C4 are grounded.

[0010] Preferably, the decoding circuit includes a chip U2, capacitors C13, C14, resistors R15, R18, and R11, and the chip U2 includes pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20; the pin 11 of the chip U2 is connected to one end of R11, and the other end of R11 is connected to the pin 9 of U2; the pin 10 of U2 is connected to one end of R15 and R18 at the same time, and the other end of R15 is connected to VD D is connected, and the other end of R18 is connected to ground; Pin 1 of U2 is connected to the CK function pin of the programming port, and Pin 15 of U2 is connected to the CD function pin of the programming port; Pins 2, 6, 7, 8, 10, 13, 16, 18, and 19 of U2 are left floating; Pin 4 of U2 is connected to one end of C13 and C14; Pins 3, 12, and 17 of U2 are grounded; Pin 5 of U2 is connected to VDD; Pin 14 of U2 is connected to the signal INFO; Pin 20 of U2 is connected to one end of R16 and R17 at the same time.

[0011] Preferably, the timing pulse output circuit for providing sufficient energy for clock control includes a single-chip computer U1, capacitors C15, C12, resistors R10, R13, R16, R17, D6 (chip diode BAT54), and Q1 (thyristor MCR100); the Q1 (thyristor MCR100) includes an anode, a cathode and a control electrode, the pin 20 of U2 is connected to one end of R16 and R17 at the same time, and the other pin of R16 is grounded; the negative electrode of D6 is connected to one end of C12 and R13 and the cathode of Q1 at the same time, and the other ends of C12 and R13 are connected to a pin of DS1 at the same time, and the other pin of DS1 is grounded; R10 is connected to the anode of D6; the control electrode of Q1 is connected to one end of R17 and C15 at the same time, and the other end of C15 is grounded; the anode of Q1 is grounded; the positive electrode of D6 is connected to one end of R10, and the other end of R10 is connected to the Vcc power supply.

[0012] Preferably, the clock output drive circuit is characterized in that: when the anode node output of the thyristor is a high level and the 20 pin of the C8051F530 chip outputs a high level, the anode and cathode of the thyristor are turned on; when the anode node output of the thyristor is a low level and the Fire pin of the C8051F530 chip outputs a low level, the anode and cathode of the thyristor are disconnected.

[0013] Preferably, the clock pulse control circuit is characterized in that the anode node output of the thyristor is a level and the high level output of the 20th pin of the C8051F530 chip can be driven by the C8051F530 chip connected to the Fire pin.

[0014] Preferably, in the pulse generating circuit, the capacitor C12 is connected to the thyristor Q1 to achieve a one-time narrow pulse high current output.

[0015] Preferably, the single-chip microcomputer C8051F530 (U2) is connected to the signal detection circuit (D5, R5, C6) to perform signal detection and low-pass filtering, and through the internal comparator of the single-chip microcomputer C8051F530 (U2), rail-to-rail input and low offset voltage are used to achieve waveform shaping, thereby reducing the bit error rate and achieving extremely high-speed receiving and decoding capabilities.

[0016] Preferably, the central processing unit MCU is a single chip microcomputer C8051F530 (U2);

[0017] The single chip microcomputer C8051F530 (U2) is connected to the control electrode of the thyristor Q1 and is used to drive the node input of the single chip microcomputer to a high level or a low level so as to control the response state of the timing circuit.

[0018] The beneficial effects of the utility model are as follows:

[0019] 1. The wireless programmable low-power timing circuit of the utility model adopts a programmable clock control circuit with a timing interrupt output. The power consumption is extremely low when in sleep mode, which completely solves the problem of high power consumption of ordinary monitoring modules, saves energy to the maximum extent, saves costs, and is pollution-free.

[0020] 2. The utility model can achieve extremely high timing accuracy.

[0021] 3. The utility model has extremely high-speed receiving and decoding capabilities, can set the timing value of the timer in a very short time, and expands the application scenarios of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The specific implementation of the utility model is further described in detail below with reference to the accompanying drawings.

[0023] Figure 1 The utility model shows a schematic diagram of the principle of a wireless power-granting programmable high-speed and high-precision clock pulse generating circuit. DETAILED DESCRIPTION

[0024] In order to more clearly illustrate the utility model, the utility model is further described below in conjunction with preferred embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. Those skilled in the art should understand that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the utility model.

[0025] like Figure 1 As shown, in one embodiment of the utility model, a new type of wireless enabled programmable high-speed and high-precision clock pulse generating circuit is provided, including a detection and filtering circuit for an external input signal connected in sequence, a clock control circuit for outputting a timing signal, a central processing unit MCU for decoding the time of generating the output signal of the clock control circuit; and a linear voltage stabilizing circuit for providing stable power to the clock control circuit and the central processing unit MCU.

[0026] The detection and filtering circuit of the external input signal completes the detection and low-pass filtering of the input signal, and demodulates the data component in the signal from the carrier. The detection and filtering circuit of the external input signal includes a diode D5, a capacitor C6, a resistor R5, signal input terminals J1 and J3, and a signal output terminal info; the signal input terminals are J1 and J3; the signal output terminal is connected to the 14th pin of the single-chip computer U2; the signal input terminal J1 is connected to the anode of D5; the signal input terminal J3 is connected to the cathode of D4; the signal output terminal info is connected to one end of C6, R5, and D5 at the same time, the other end of R5 is connected to 3.3V, and the other end of C6 is grounded.

[0027] The voltage stabilizing circuit includes a voltage stabilizing chip U1, capacitors C2 and C4, pins of U1 are 1, 2, 3, 4 and 5, the voltage stabilizing input terminal is pin 1 of U1; pins 3 and 4 of U1 are suspended, pin 5 of U1 is the voltage stabilizing output terminal VDD, the voltage stabilizing output terminal VDD (3.3V) is connected to one end of C2 and C4 at the same time, and the other ends of C2 and C4 are grounded.

[0028] The decoding circuit includes a chip U2, capacitors C13, C14, resistors R15, R18, and R11. The chip U2 includes pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20; the pin 11 of the chip U2 is connected to one end of R11, and the other end of R11 is connected to the pin 9 of U2; the pin 10 of U2 is connected to one end of R15 and R18 at the same time, and the other end of R15 is connected to VDD , the other end of R18 is connected to ground; Pin 1 of U2 is connected to the CK function pin of the programming port, and Pin 15 of U2 is connected to the CD function pin of the programming port; Pins 2, 6, 7, 8, 10, 13, 16, 18, and 19 of U2 are suspended; Pin 4 of U2 is connected to one end of C13 and C14; Pins 3, 12, and 17 of U2 are grounded; Pin 5 of U2 is connected to VDD; Pin 14 of U2 is connected to the signal INFO; Pin 20 of U2 is connected to one end of R16 and R17 at the same time.

[0029] The timing pulse output circuit includes a single-chip computer U1, capacitors C15, C12, resistors R10, R13, R16, R17, a TVS tube D1, and a thyristor Q1; the thyristor Q1 includes an anode, a cathode and a control electrode, the pin 20 of the U1 is simultaneously connected to one end of R16 and R17, and the other pin of R16 is grounded; the negative electrode of D6 is simultaneously connected to one end of C12 and R13 and the cathode of Q1, and the other ends of C12 and R13 are simultaneously connected to a pin of DS1, and the other pin of DS1 is grounded; R10 is connected to the anode of D6; the control electrode of Q1 is simultaneously connected to one end of R17 and C15, and the other end of C15 is grounded; the anode of Q1 is grounded; the positive electrode of D6 is connected to the Vcc power supply.

[0030] The central processing unit MCU is a single-chip microcomputer C8051F530 (U2); the single-chip microcomputer C8051F530 (U2) is connected to the control electrode of the thyristor Q1 (SCR) and is used to drive the control electrode node to input a high level or a low level to control the switching state of the circuit.

[0031] In the utility model, the single-chip microcomputer C8051F530 (U2) performs programmable control on the clock control circuit. The single-chip microcomputer C8051F530 (U2) also has an external digital interface. The user can input control parameters through the external digital interface to realize customized automatic start time control. Under the action of the timing parameters, the MCU writes the next interrupt time to the timing interrupter chip according to the timing parameter value after each startup. The MCU is connected to the control electrode of the thyristor Q1 (SCR). After the device is started, the MCU drives the control electrode node of the thyristor Q1 (SCR) to output a high level to control the closed state of the circuit, and outputs a low level to disconnect the control circuit switch when necessary.

[0032] In the utility model, when the pin 20 of the C8051F530 (U2) chip outputs a high level, the anode and cathode of the thyristor are turned on; when the pin 20 of the C8051F530 (U2) chip outputs a low level, the anode and cathode of the thyristor are turned off;

[0033] The signal processing circuit adopts wireless communication, and performs signal demodulation through detection and low-pass filtering. The demodulated signal is sent to the internal comparator of the microcontroller through pin 14 of U2. The internal comparator performs waveform shaping, filters out unnecessary interference waves, reduces the bit error rate, and achieves extremely high-speed receiving and decoding capabilities, and sets the timing value of the timer in a very short time. It includes a signal processing device diode D5, a capacitor C6, a resistor R5, a decoding processor U2, the signal input terminals J1 and J3, and a signal output terminal info; the signal input terminals are J1 and J3; the signal output terminal is connected to the 14th pin of the single-chip computer U2; the signal input terminal J1 is connected to the anode of D5; the signal input terminal J3 is connected to the cathode of D4; the signal output terminal info is connected to one end of C6, R5 and D5 at the same time, the other end of R5 is connected to 3.3V, and the other end of C6 is grounded; the 9th pin of U2 is connected to the positive input terminal of the internal comparator, and is connected to one end of R15 and R18 at the same time, the other end of R15 is connected to VDD, and the other end of R18 is grounded; the 11th pin of U2 is connected to the output terminal of the internal comparator, and provides a shaped digital signal to the inside at the same time.

[0034] Obviously, the above-mentioned implementation of the utility model is only an example for clearly illustrating the utility model, and is not a limitation on the implementation methods of the utility model. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the utility model are still within the protection scope of the utility model.

[0035] The other parts of this embodiment are all prior art and will not be described in detail here.

Claims

1. A wirelessly enabled programmable high-speed and high-precision clock pulse generating circuit, characterized in that: It includes detection and filtering circuits for external input signals, energy extraction circuits, control circuits for outputting clock signals, and a central processing unit MCU for programming the time of outputting signals from the clock control circuit; A signal comparison circuit for high-speed, low-power push-pull output signal processing; and a voltage stabilization circuit for providing stable power to the clock control circuit and the central processing unit MCU.

2. According to claim 1, the wireless empowered programmable high-speed and high-precision clock pulse generating circuit is characterized in that: The detection and filtering circuit of the input signal includes a diode D5, a capacitor C6, a resistor R5, signal input terminals J1 and J3, and a signal output terminal info; the signal input terminals are J1 and J3; the signal output terminal is connected to pin 14 of the microcontroller U2; the signal input terminal J1 is connected to the anode of D5; the signal input terminal J3 is connected to the cathode of D4; the signal output terminal info is connected to C6, R5, and one end of D5 at the same time, the other end of R5 is connected to 3.3V, and the other end of C6 is grounded.

3. The wireless empowered programmable high-speed and high-precision clock pulse generating circuit according to claim 1, characterized in that: The energy extraction circuit includes a rectifier diode pair D3, D4, a capacitor C1, resistors R00, R01, a voltage regulator diode D1, and common terminals J1, J3 for the energy input end and the signal input end; the energy input end is J1, J3; The energy input terminal J1 is connected to the 3rd pin of D3, the 2nd pin of D3 and the 2nd pin of D4, one end of R00 and R01 are simultaneously connected to Vcc, and the 1st pin of D3 is grounded; The energy input terminal J3 is connected to pin 3 of D4, and pin 1 of D4 is grounded; the energy output terminal, i.e., pin 2 of D4, is connected to one end of R00 and R01 at the same time, and the other end of R00 and R01 is connected to pin 1 of C1, C3, D1, and U1 at the same time, and the other end of C1, C3, and D1 is grounded at the same time, and pin 2 of U1 is grounded.

4. The wireless empowered programmable high-speed and high-precision clock pulse generating circuit according to claim 1, characterized in that: The voltage stabilizing circuit for providing stable electric energy for the clock control circuit and the central processing unit MCU includes a voltage stabilizing chip U1, capacitors C2 and C4, pins 1, 2, 3, 4 and 5 of U1, and the voltage stabilizing input terminal is pin 1 of U1; pins 3 and 4 of U1 are suspended, and pin 5 of U1 is the voltage stabilizing output terminal VDD, which is connected to one end of C2 and C4 at the same time, and the other ends of C2 and C4 are grounded.

5. The wireless empowered programmable high-speed and high-precision clock pulse generating circuit according to claim 1, characterized in that: The decoding circuit after signal detection includes chip U2, capacitors C13, C14, resistors R15, R18, R11, and chip U2 includes pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20; pin 11 of chip U2 is connected to one end of R11, and the other end of R11 is connected to pin 9 of U2; pin 10 of U2 is connected to one end of R15 and R18 at the same time, and the other end of R15 is connected to V DD is connected, and the other end of R18 is connected to ground; Pin 1 of U2 is connected to the CK function pin of the programming port, and Pin 15 of U2 is connected to the CD function pin of the programming port; Pins 2, 6, 7, 8, 10, 13, 16, 18, and 19 of U2 are left floating; Pin 4 of U2 is connected to one end of C13 and C14; Pins 3, 12, and 17 of U2 are grounded; Pin 5 of U2 is connected to VDD; Pin 14 of U2 is connected to the signal INFO; Pin 20 of U2 is connected to one end of R16 and R17 at the same time.

6. The wireless empowered programmable high-speed and high-precision clock pulse generating circuit according to claim 1, characterized in that: The timing pulse output circuit for providing sufficient energy for clock control includes a single-chip computer U2, capacitors C15, C12, resistors R10, R13, R16, R17, D6, and a thyristor Q1; the thyristor Q1 includes an anode, a cathode, and a control electrode, the pin 20 of U2 is connected to one end of R16 and R17 at the same time, and the other pin of R16 is grounded; the negative electrode of D6 is connected to one end of C12 and R13 and the cathode of Q1 at the same time, and the other ends of C12 and R13 are connected to a pin of DS1 at the same time, and the other pin of DS1 is grounded; R10 is connected to the anode of D6; the control electrode of Q1 is connected to one end of R17 and C15 at the same time, and the other end of C15 is grounded; the anode of Q1 is grounded; the positive electrode of D6 is connected to one end of R10, and the other end of R10 is connected to a Vcc power supply.

7. The wireless empowered programmable high-speed and high-precision clock pulse generating circuit according to claim 6, characterized in that: When the anode node output of the thyristor is high level and the 20th pin of the C8051F530 chip outputs high level, the anode and cathode of the thyristor are turned on; when the anode node output of the thyristor is low level and the 20th pin of the C8051F530 chip outputs low level, the anode and cathode of the thyristor are disconnected.

8. The wirelessly enabled programmable high-speed and high-precision clock pulse generating circuit according to claim 6, characterized in that The anode node output of the thyristor is a level and the 20-pin output of the C8051F530 chip is a high level, both of which can be driven by the C8051F530 chip connected to the 20-pin.

9. The wireless empowered programmable high-speed and high-precision clock pulse generating circuit according to claim 7, characterized in that: The capacitor C12 is connected to the thyristor Q1 to achieve a one-time narrow pulse high current output.

Images