Shift register unit, gate drive circuit and display device

Abstract

Provided are a shift register unit, a gate drive circuit and a display device, the shift register unit comprising: an input circuit, an output circuit, a node potential control circuit, a discharge circuit and a reset circuit, at least one of the input circuit, the output circuit, the node potential control circuit, the discharge circuit and the reset circuit comprises a threshold voltage adjustable transistor, and the threshold voltage adjustable transistor comprises a substrate, a grid electrode, a source drain electrode and a bias electrode. Wherein the source and drain electrodes are arranged on the side, facing the grid electrode, of the substrate, the bias electrode is arranged on the side, deviating from the grid electrode, of the substrate, and the bias electrode is configured to receive bias voltage so as to adjust the threshold voltage of the threshold voltage adjustable transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a shift register unit, a gate driving circuit including the shift register unit, and a display device including the gate driving circuit. Background Art

[0002] Display devices such as liquid crystal displays and organic light-emitting displays generally include a gate driver disposed in a peripheral non-display area of ​​the display device or between adjacent pixels in a display area. The gate driver includes a plurality of cascaded shift register units, and the shift register units can obtain a scanning signal provided to each gate line based on an input clock signal.

[0003] Each level of shift register unit in the gate driver sequentially outputs a scan signal for each row of pixels. The stability or reliability of the scan signal is an important factor affecting the image display quality of the display device. Each shift register unit usually includes a plurality of thin film transistors. Changes in the parameters or performance of the thin film transistors will affect whether the shift register unit normally outputs the scan signal. However, for existing shift register units or gate drivers, little attention is paid to the adverse effects of changes in the threshold voltage of the thin film transistor on the output scan signal. Utility Model Content

[0004] The embodiments of the present application propose a shift register unit, a gate drive circuit including the shift register unit, and a display device including the gate drive circuit to alleviate the problem that the drift or change of the threshold voltage of the transistor device in the shift register unit has an adverse effect on the output scan signal.

[0005] According to various embodiments of the present application, a shift register unit includes: an input circuit, which is configured to be electrically connected to an input terminal and a first node to control the potential of the first node based on an input signal received from the input terminal; an output circuit, which is configured to receive a clock signal and is electrically connected to the first node, the second node, the output terminal and the first reference voltage terminal to provide an output signal to the output terminal based on the clock signal under the control of the potential of the first node and the potential of the second node; a node potential control circuit, which is configured to be electrically connected to the first node, the second node, the first reference voltage terminal, and the second reference voltage terminal to control the potential of the second node according to the second reference voltage provided by the second reference voltage terminal and the potential of the first node; a discharge circuit, which is configured to be electrically connected to the The first node, the second node and the first reference voltage terminal are connected to discharge the first node under the control of the potential of the second node; and a reset circuit is configured to receive a reset signal and is electrically connected to the first node to reset the first node under the control of the reset signal, at least one of the input circuit, the output circuit, the node potential control circuit, the discharge circuit and the reset circuit includes a threshold voltage adjustable transistor, the threshold voltage adjustable transistor includes a substrate, a gate, a source and a drain, and a bias electrode, wherein the source and the drain are arranged on a side of the substrate facing the gate, the bias electrode is arranged on a side of the substrate away from the gate, and the bias electrode is configured to receive a bias voltage to adjust the threshold voltage of the threshold voltage adjustable transistor.

[0006] In some embodiments, the threshold voltage adjustable transistor further includes an active layer located between the gate and the source and drain, and a substrate for supporting the gate, wherein the orthographic projection of the bias electrode on the substrate covers the orthographic projection of the active layer on the substrate.

[0007] In some embodiments, the threshold voltage adjustable transistor further includes a gate insulating layer, wherein the gate insulating layer is located between the source and drain and the substrate and covers the gate.

[0008] In some embodiments, the shift register unit also includes a threshold voltage compensation transistor and a bias voltage receiving end for receiving the bias voltage, the control end of the threshold voltage compensation transistor is electrically connected to the control end of the threshold voltage adjustable transistor, the input end, and one of the output ends of the output circuit, and the first end and the second end of the threshold voltage compensation transistor are electrically connected to the bias voltage receiving end and the bias electrode of the threshold voltage adjustable transistor, respectively.

[0009] In some embodiments, the shift register unit further includes a switch transistor connected in series with the threshold voltage compensation transistor, the switch transistor being used to control whether the bias voltage is provided to the bias electrode of the threshold voltage adjustable transistor via the threshold voltage compensation transistor.

[0010] In some embodiments, the threshold voltage adjustable transistor includes a first type of transistor with a positively drifted threshold voltage and a second type of transistor with a negatively drifted threshold voltage, the threshold voltage compensation transistor includes a first compensation transistor and a second compensation transistor, and the bias voltage receiving end includes a first voltage receiving end and a second voltage receiving end, wherein the control end of the first compensation transistor is electrically connected to the control end of the first type of transistor, the first end and the second end of the first compensation transistor are respectively electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor, the control end of the second compensation transistor is electrically connected to the control end of the second type of transistor, the first end and the second end of the second compensation transistor are respectively electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor, wherein the first voltage receiving end and the second voltage receiving end are respectively used to receive first voltages and second voltages that are different from each other.

[0011] In some embodiments, the threshold voltage adjustable transistor includes a first type of transistor whose threshold voltage drifts positively and a second type of transistor whose threshold voltage drifts negatively, the threshold voltage compensation transistor includes a first compensation transistor and a second compensation transistor, and the bias voltage receiving end includes a first voltage receiving end and a second voltage receiving end, wherein the control end of the first compensation transistor and the control end of the second compensation transistor are electrically connected to the first node, the input end of the input circuit or one of the output ends of the output circuit, the first end and the second end of the first compensation transistor are electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor, respectively, the first end and the second end of the second compensation transistor are electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor, respectively, wherein the first voltage receiving end and the second voltage receiving end are respectively used to receive first voltages and second voltages that are different from each other.

[0012] In some embodiments, the shift register unit includes a substrate for carrying the input circuit, the output circuit, the pull-up circuit, the pull-down circuit, the discharge circuit and the reset circuit, and the substrate includes a first area for arranging the first type of transistors and a second area for arranging the second type of transistors.

[0013] In some embodiments, the switching transistor includes a first switching transistor connected in series with the first compensation transistor, and a second switching transistor connected in series with the second compensation transistor, and the control end of the first switching transistor and the control end of the second switching transistor are electrically connected to a compensation enable end that provides a compensation enable signal.

[0014] In some embodiments, the input circuit includes a first transistor, the control terminal of the first transistor is electrically connected to the input terminal, the first terminal of the first transistor is electrically connected to the input terminal or the first control signal terminal, and the second terminal of the first transistor is electrically connected to the first node. The reset circuit includes a second transistor, the control terminal of the second transistor is used to receive a reset signal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the second control signal terminal or the first reference voltage terminal. The output circuit includes a third transistor, a fourth transistor and a capacitor, the control terminal of the third transistor is electrically connected to the first node, the first terminal of the third transistor is used to receive the clock signal, the second terminal of the third transistor is electrically connected to the output terminal, the control terminal of the fourth transistor is electrically connected to the second node, the first terminal and the second terminal of the fourth transistor are respectively electrically connected to the output terminal and the first reference voltage terminal, and the capacitor is electrically connected between the first node and the output terminal. The node potential control circuit includes a fifth transistor and a sixth transistor, the control terminal and the first terminal of the fifth transistor are electrically connected to the second reference voltage terminal, the second terminal of the fifth transistor is electrically connected to the second node, the control terminal of the sixth transistor is electrically connected to the first node, and the first terminal and the second terminal of the sixth transistor are respectively electrically connected to the second node and the first reference voltage terminal.

[0015] The discharge circuit includes a seventh transistor, a control end of the seventh transistor is electrically connected to the second node, a first end and a second end of the first transistor are electrically connected to the first node and the first reference voltage end, respectively, the first type of transistors includes the second transistor, the third transistor and the seventh transistor, and the second type of transistors includes the first transistor.

[0016] In some embodiments, the substrate further includes a third region, and the fourth transistor, the fifth transistor, and the sixth transistor are arranged in the third region.

[0017] Another embodiment of the present application provides a gate drive circuit, comprising a plurality of cascaded shift register units as described in the aforementioned embodiments, the gate drive circuit also comprising a threshold voltage compensation circuit, the threshold voltage compensation circuit comprising a threshold voltage compensation transistor and a bias voltage receiving end for receiving the bias voltage, the control end of the threshold voltage compensation transistor being electrically connected to the output end, the input end or one of the first nodes in each shift register unit, the first end and the second end of the threshold voltage compensation transistor being electrically connected to the bias voltage receiving end and the bias electrode of the threshold voltage adjustable transistor in each shift register unit, respectively.

[0018] In some embodiments, the threshold voltage adjustable transistor includes a first type of transistor with a positively drifting threshold voltage and a second type of transistor with a negatively drifting threshold voltage, the threshold voltage compensation transistor includes a first compensation transistor and a second compensation transistor, and the bias voltage receiving end includes a first voltage receiving end and a second voltage receiving end, wherein the control end of the first compensation transistor and the control end of the second compensation transistor are electrically connected to the output end, the input end or one of the first nodes in each shift register unit, the first end and the second end of the first compensation transistor are electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor, respectively, the first end and the second end of the second compensation transistor are electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor, respectively, wherein the first voltage receiving end and the second voltage receiving end are respectively used to receive first voltages and second voltages that are different from each other.

[0019] In some embodiments, the threshold voltage compensation circuit also includes a first switching transistor connected in series with the first compensation transistor, and a second switching transistor connected in series with the second compensation transistor, and the control end of the first switching transistor and the control end of the second switching transistor are electrically connected to a compensation enable end that provides a compensation enable signal.

[0020] In some embodiments, each shift register unit includes a substrate for carrying the input circuit, the output circuit, the pull-up circuit, the pull-down circuit, the discharge circuit and the reset circuit, and the substrate includes a first area for arranging the first type of transistors and a second area for arranging the second type of transistors.

[0021] Another embodiment of the present application provides a display device, comprising a gate driving circuit as described in any of the aforementioned embodiments.

[0022] These and other advantages of the present application will become apparent from and be elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Embodiments of the present application will now be described in more detail and with reference to the accompanying drawings, in which:

[0024] Figure 1A FIG. 1 illustrates a circuit structure block diagram of a shift register unit according to an embodiment of the present application;

[0025] Figure 1B schematically illustrates a partial cross-sectional view of a threshold voltage adjustable transistor in a shift register cell;

[0026] Figure 2A A specific circuit schematic diagram of a shift register unit according to an embodiment of the present application is illustrated;

[0027] Figure 2B The diagram shows the Figure 2A The signal timing diagram of the shift register unit shown;

[0028] Figure 3 FIG. 4 illustrates a specific circuit schematic diagram of a shift register unit according to another embodiment of the present application;

[0029] Figure 4 FIG. 4 illustrates a specific circuit schematic diagram of a shift register unit according to another embodiment of the present application;

[0030] Figure 5 The figure illustrates the electrical connection between the threshold voltage adjustable transistor and the threshold voltage compensation transistor in the shift register unit according to one embodiment of the present application;

[0031] Figure 6 The figure illustrates the electrical connection between the threshold voltage adjustable transistor and the threshold voltage compensation transistor in the shift register unit according to another embodiment of the present application;

[0032] Figure 7 The diagram illustrates electrical connections between a threshold voltage adjustable transistor, a threshold voltage compensation transistor, and a switch transistor in a shift register unit according to another embodiment of the present application;

[0033] Figure 8 The figure illustrates the electrical connection between the threshold voltage adjustable transistor, the threshold voltage compensation transistor, and the switch transistor in the shift register unit according to another embodiment of the present application;

[0034] Fig. 9 A partial plan view of a display device provided according to an embodiment of the present application is illustrated;

[0035] Fig.10Schematically shows the electrical connection between the first compensation transistor and the first type of transistor, and the electrical connection between the second compensation transistor and the second type of transistor of the shift register unit provided according to an embodiment of the present application;

[0036] Fig.11 FIG. 1 illustrates a partial circuit diagram of a shift register unit provided according to another embodiment of the present application;

[0037] Fig.12 FIG. 1 illustrates a partial circuit diagram of a shift register unit provided according to another embodiment of the present application;

[0038] Fig.13 It is used to illustrate the regional layout of each transistor in the shift register unit;

[0039] Fig.14 A plurality of shift register units for schematically illustrating cascade connection;

[0040] Fig.15 schematically shows the electrical connection relationship between the threshold voltage adjustable transistors and the corresponding threshold voltage compensation transistors in two cascaded shift register units; and

[0041] Fig.16 The figure schematically illustrates two shift register units and a threshold voltage compensation circuit in a gate driving circuit. DETAILED DESCRIPTION

[0042] The following description provides the specific details of various embodiments of the present application so that those skilled in the art can fully understand and implement the various embodiments of the present application. In some cases, the present application does not illustrate or describe in detail some structures or functions well known in the art to avoid these unnecessary descriptions from obscuring the description of the embodiments of the present application. The technical solution of the present application can be embodied in many different forms and purposes, and should not be limited to the embodiments described herein. These embodiments are provided to make the technical solution of the present application clear and complete, but the embodiments do not limit the scope of protection of this patent application.

[0043] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the utility model. However, it is obvious to those skilled in the art that the technical solution of the present application can be implemented without one or more of these details. Detailed steps and detailed structures are proposed in the following description to illustrate the technical solution proposed by the utility model. The terms used in the present application should be understood in their broadest reasonable manner, even if they are used in conjunction with the specific embodiments of the present application.

[0044] Here, some terms involved in the embodiments of the present application are first explained to facilitate understanding by those skilled in the art.

[0045] The "control end" mentioned in this article refers to the gate of the transistor for receiving the scanning signal. The transistor can be in the on state or the off state under the control of the signal received at its control end. The "first end" mentioned in this article refers to one of the two terminals of the transistor except the control end, and the "second end" refers to the other of the two terminals of the transistor except the control end. That is, the first end can be one of the source and drain of the transistor, and the second end can be the other of the source and drain of the transistor. The "display device" mentioned in this article can be an assembled display product with an image display function, or it can be a part of the components of a complete display product, but the part of the components includes the shift register unit or gate drive circuit described in the embodiment of the present application.

[0046] The embodiment of the present application provides a shift register unit, which includes an input circuit, an output circuit, a node potential control circuit, a discharge circuit and a reset circuit. The input circuit is configured to be electrically connected to an input terminal and a first node to control the potential of the first node based on an input signal received from the input terminal, the output circuit is configured to receive a clock signal and be electrically connected to the first node, the second node, the output terminal and the first reference voltage terminal to provide an output signal to the output terminal based on the clock signal under the control of the potential of the first node and the potential of the second node, the node potential control circuit is configured to be electrically connected to the first node, the second node, the first reference voltage terminal and the second reference voltage terminal to control the potential of the second node according to the second reference voltage provided by the second reference voltage terminal and the potential of the first node, the discharge circuit is configured to be electrically connected to the first node, the second node and the first reference voltage terminal to discharge the first node under the control of the potential of the second node, and the reset circuit is configured to receive a reset signal and be electrically connected to the first node to reset the first node under the control of the reset signal. At least one of the input circuit, the output circuit, the node potential control circuit, the discharge circuit and the reset circuit includes a threshold voltage adjustable transistor, which includes a substrate, a gate, a source and a drain, and a bias electrode, wherein the source and the drain are arranged on a side of the substrate facing the gate, the bias electrode is arranged on a side of the substrate away from the gate, and the bias electrode is configured to receive a bias voltage to adjust the threshold voltage of the threshold voltage adjustable transistor.

[0047] The inventor of the present application realizes that the threshold voltage of a transistor is related to its substrate bias voltage. Taking an N-type metal oxide transistor as an example, if the substrate and source of the transistor are connected to the ground line, the voltage difference V between the source and the substrate is SB is equal to zero, at which point the threshold voltage of the transistor is V th0 When the substrate voltage V B When the negative potential drops to less than zero, more positively charged holes are attracted to the vicinity of the substrate, leaving a large amount of immovable negative charge under the gate, which increases the width of the depletion layer. As the substrate bias voltage decreases, the total amount of charge in the depletion layer increases, resulting in a threshold voltage V th This is called the body effect of the transistor. Taking the body effect into account, the threshold voltage of the metal oxide transistor can be expressed as the following formula:

[0048]

[0049] Where V th0 That is, the threshold voltage when the voltage difference between the source and substrate of the transistor is zero. γ is the body effect factor, which is a constant and is related to the process of making the transistor. is the built-in potential.

[0050] Therefore, when the substrate bias voltage V B When the voltage is larger, the voltage difference between the source and the substrate V SB <0, transistor threshold voltage V th decreases, and when the substrate bias voltage V B When the voltage is large, the voltage difference between the source and the substrate V SB >0, transistor threshold voltage V th According to the body effect, the substrate bias voltage V B To adjust its threshold voltage.

[0051] For the shift register unit provided in the embodiment of the present application, at least one of the input circuit, output circuit, node potential control circuit, discharge circuit and reset circuit includes a threshold voltage adjustable transistor. In other words, among the transistors included in the shift register unit, there is at least one threshold voltage adjustable transistor, and the threshold voltage adjustable transistor includes the above-mentioned bias electrode, and the threshold voltage adjustable transistor can receive a bias voltage through the bias electrode, thereby adjusting the threshold voltage of the threshold voltage adjustable transistor. In particular, after the shift register unit has been running for a period of time, at least a part of the transistors therein may have a threshold voltage drift phenomenon. In the case where the shift register unit includes a threshold voltage adjustable transistor, by applying an appropriate bias voltage to the bias electrode of the threshold voltage adjustable transistor, the threshold voltage drift phenomenon can be improved, and the threshold of the transistor in the shift register unit can be stabilized, thereby improving the stability and reliability of the output signal of the shift register unit, and improving the quality of the image displayed by the display device using the shift register unit.

[0052] Figure 1A The circuit structure block diagram of the shift register unit is schematically shown as follows: Figure 1A As shown, the shift register unit includes an input circuit 101 , an output circuit 103 , a node potential control circuit 104 , a discharge circuit 105 and a reset circuit 102 . The input circuit 101 is electrically connected to the input terminal In and the first node N1 to control the potential of the first node N1 based on the input signal received from the input terminal In. The output circuit 103 is configured to receive the clock signal CLK and is electrically connected to the first node N1, the second node N2, the output terminal Out and the first reference voltage terminal Vr1 to provide an output signal to the output terminal Out based on the clock signal CLK under the control of the potential of the first node N1 and the potential of the second node N2. The node potential control circuit 104 is configured to be electrically connected to the first node N1, the second node N2, the first reference voltage terminal Vr1 and the second reference voltage terminal Vr2 to control the potential of the second node N2 according to the second reference voltage provided by the second reference voltage terminal Vr2 and the potential of the first node N1. The discharge circuit 105 is configured to be electrically connected to the first node N1, the second node N2 and the first reference voltage terminal Vr1 to discharge the first node N1 under the control of the potential of the second node N2. The reset circuit 102 receives the reset signal Re and is electrically connected to the first node N1 to reset the first node N1 under the control of the reset signal Re. The present application does not impose any specific restrictions on the specific circuits of the shift register unit. That is to say, as long as the various circuit units in the shift register unit can achieve corresponding functions, the input circuit 101, the output circuit 103, the node potential control circuit 104, the discharge circuit 105 and the reset circuit 102 can have any specific form of circuit structure.

[0053] As mentioned above, in the embodiment of the present application, at least a portion of the transistors include a bias electrode for receiving a bias voltage, thereby achieving adjustment of the threshold voltage of the portion of the transistors. In this article, such transistors are referred to as threshold voltage adjustable transistors. Figure 1B An example of a partial cross-sectional view of a threshold voltage adjustable transistor is schematically shown. Figure 1B As shown, the threshold voltage adjustable transistor includes a substrate SB, a gate GA, a source and drain (including a source SE and a drain DE) and a bias electrode PE, the source and drain are arranged on the side of the substrate SB facing the gate GA, the bias electrode PE is arranged on the side of the substrate PE away from the gate GA, and the bias electrode PE is configured to receive a bias voltage to adjust the threshold voltage of the threshold voltage adjustable transistor. In some embodiments, the threshold voltage adjustable transistor also includes an active layer located between the gate and the source and drain, and a substrate for carrying the gate, and the orthographic projection of the bias electrode on the substrate covers the orthographic projection of the active layer on the substrate. Further, the threshold voltage adjustable transistor also includes a gate insulating layer, the gate insulating layer is located between the source and drain and the substrate, and covers the gate. In some embodiments, the substrate SB includes an insulating material, and the insulating material can be the same as the material of the gate insulating layer.

[0054] like Figure 1B As shown, the threshold voltage adjustable transistor further includes a substrate GB (for example, a glass substrate made of glass material) and a gate insulating layer GI, wherein the gate insulating layer GI is located between the source and drain electrodes SE, DE and the gate electrode GA, and the substrate GB is located on the side of the gate electrode GA away from the source and drain electrodes to support the gate electrode GA. In fact, all other layers of the threshold voltage adjustable transistor can be supported by the substrate GB. The material of the bias electrode includes but is not limited to indium tin oxide ITO or a metal film layer. In some embodiments, as Figure 1B As shown, the threshold voltage adjustable transistor further includes an active layer AL located between the gate GA and the source and drain electrodes SE and DE, and the orthographic projection of the bias electrode PE on the substrate GB covers the orthographic projection of the active layer AL on the substrate GB. That is to say, in this embodiment, the bias electrode PE is located above the active layer AL, and the coverage area is as large as possible. The orthographic projection of the bias electrode PE on the substrate GB covers the orthographic projection of the active layer AL on the substrate GB, which means that the coverage range of the bias electrode includes the channel region of the threshold voltage adjustable transistor, thereby facilitating the ability to adjust the threshold voltage of the threshold voltage adjustable transistor by using the bias voltage via the bias electrode.

[0055] Figure 2A The figure shows the circuit schematic diagram of the specific circuit of the shift register unit. Figure 2AAs shown, the shift register unit includes an input circuit 201, an output circuit 203, a node potential control circuit 204, a discharge circuit 205 and a reset circuit 202. The input circuit 201 includes a first transistor M1, one of the first end and the second end of the first transistor M1 is electrically connected to its control end, the other of the first end and the second end of the first transistor is electrically connected to the first node N1, and the control end of the first transistor receives an input signal In. In another embodiment, Figure 2ADifferent from the example shown, one of the first end and the second end of the first transistor M1 is electrically connected to the first node N1, and the other of the first end and the second end of the first transistor M1 may not be electrically connected to its control end, but electrically connected to an appropriate fixed potential or pulse signal, as long as the control end of the first transistor M1 can be turned on when receiving the effective level of the input signal. The reset circuit 202 includes a second transistor M2, the control end of the second transistor M2 receives the reset signal Re, one of the first end and the second end of the second transistor M2 is electrically connected to the first node N1, the other of the first end and the second end of the second transistor M2 is electrically connected to the first reference voltage end to receive the first reference voltage Vr1, and the second transistor M2 and the first transistor M1 actually form a series connection relationship. The output circuit 203 includes a third transistor M3, a fourth transistor M4 and a capacitor C, one of the first end and the second end of the third transistor M3 is electrically connected to the output end, the other of the first end and the second end of the third transistor M3 is used to receive the clock signal CLK, the control end of the third transistor M3 is electrically connected to the first node N1, and the capacitor C is electrically connected between the first node N1 and the output end. One of the first and second ends of the fourth transistor M4 is electrically connected to the output end, the other of the first and second ends of the fourth transistor M4 is electrically connected to the first reference voltage end, and the control end of the fourth transistor M4 is electrically connected to the second node N2. The node potential control circuit 204 includes a fifth transistor M5 and a sixth transistor M6, one of the first and second ends of the fifth transistor M5 is electrically connected to its control end, and at the same time, the control end is also electrically connected to the second reference voltage end to receive the second reference voltage Vr2, the other of the first and second ends of the fifth transistor M5 is electrically connected to the second node N2, one of the first and second ends of the sixth transistor M6 is electrically connected to the second node N2, the other of the first and second ends of the sixth transistor M6 is electrically connected to the first reference voltage end, and the control end of the sixth transistor M6 is electrically connected to the first node N1. The discharge circuit 205 includes a seventh transistor M7, the control end of the seventh transistor M7 is electrically connected to the second node N2, one of the first and second ends of the seventh transistor is electrically connected to the first node N1, and the other of the first and second ends of the seventh transistor is electrically connected to the first reference voltage end. It can be seen that the third transistor M3 and the fourth transistor M4 are actually connected in series between the clock signal receiving terminal and the first reference voltage terminal, and the fifth transistor M5 and the sixth transistor M6 are actually connected in series between the second reference voltage terminal and the first reference voltage terminal.

[0056] Figure 2B The diagram shows Figure 2A An example of a signal timing diagram of a shift register unit is shown in FIG. In this example, Figure 2AEach transistor in the shift register unit shown is an N-type thin film transistor (eg, NMOS transistor), the first reference voltage Vr1 received by the first reference voltage terminal is a constant low level voltage, and the second reference voltage Vr2 received by the second reference voltage terminal is a constant high level voltage. Figure 2B The figure shows the signal timing diagram within a cycle. Figure 2B As shown, starting from time t1, the shift register unit receives a valid input signal, that is, the input signal In changes from a low level to a high level at time t1. Correspondingly, the control end of the first transistor M1 receives a high-level input signal and is turned on, the capacitor C is charged, and the potential PN1 of the first node N1 jumps from the initial low potential to a first higher potential. Further, the third transistor M3 and the sixth transistor M6 are turned on, and at this time, the potential PN2 of the second node N2 is the first reference voltage of the first reference voltage end, that is, the potential PN2 of the second node N2 is a low level. Therefore, the fourth transistor M4 and the seventh transistor M7 are in the off state. Since the clock signal CLK maintains a low level at this time, the output signal Out of the output end of the shift register unit maintains a low level. In addition, the reset signal Re maintains a low level at this time, so the second transistor M2 is in the off state. At time t2, the clock signal CLK jumps from a low level to a high level. Due to the bootstrap effect of the capacitor C, the potential PN1 of the first node N1 is pulled up from the previous first higher potential to the second higher potential. The third transistor M3 and the sixth transistor M6 remain in the on state, the potential PN2 of the second node N2 remains at the previous low level, and the fourth transistor M4 and the seventh transistor M7 remain in the off state. The output signal Out of the output end of the shift register unit jumps from the previous low level to the high level. At time t3, the clock signal CLK changes from a high level to a low level, and the output signal Out also changes from a high level to a low level accordingly. Similarly, due to the bootstrap effect of the capacitor C, the potential PN1 of the first node N1 starts to decrease from the previous second higher potential. When the potential PN1 of the first node N1 decreases to a low level (at time t4), the third transistor M3 and the sixth transistor M6 are turned off, and the potential PN2 of the second node N2 is not affected by the first reference voltage of the first reference voltage end at this time, and it changes from the previous low level to a high level. The potential PN2 of the second node N2 at a high level turns on the fourth transistor M4 and the seventh transistor M7, so that the output signal Out at the output terminal maintains a low level. In addition, the first node N1 will discharge to the first reference voltage terminal via the seventh transistor M7, reducing or clearing the charge accumulated on the first node N1. In addition, the second transistor M2 receives a valid reset signal Re (a high level between time t4 and time t5) at time t4 and turns on, ensuring that the output of the shift register unit is not affected by the change of the clock signal.

[0057] like Figure 2AThe shift register unit shown can be applied to a gate driving circuit, which may include a plurality of cascaded shift registers. Figure 2A The shift register unit shown, the output signal of each shift register unit can be provided as a scanning signal to one of the gate lines of the display device, for example, the output signal of each shift register unit can be used as a row scanning signal for turning on a row of pixels. The effective level (for example, high level) of the output signal of each shift register unit arrives in sequence according to the time sequence, thereby realizing the row scanning of each row of pixels of the display device.

[0058] Figure 3 The diagram shows the Figure 2A In this embodiment, in addition to being electrically connected to the input terminal and the first node N1, the input circuit is also electrically connected to the first signal terminal to receive the first signal VS1, the reset circuit receives the reset signal, and is electrically connected to the first node N1 and the second signal terminal to receive the second signal VS2. Figure 2A The embodiments shown are basically the same. The first signal VS1 and the second signal VS2 can be adjusted, for example, the first signal VS1 and the second signal VS2 are respectively set to a high level signal and a low level signal, or the first signal VS1 and the second signal VS2 are respectively set to a low level signal and a high level signal. Application Figure 2A The gate drive circuit of the shift register unit shown in the figure can realize unidirectional scanning of multiple rows of pixels by changing the levels of the first signal VS1 and the second signal VS2. Figure 3 The gate driving circuit of the shift register unit shown can implement bidirectional scanning of multiple rows of pixels (for example, from top to bottom, or from bottom to top).

[0059] Figure 4 Another example of a shift register unit is given, which includes an input circuit 401, a reset circuit 402, a discharge circuit 405, a node potential control circuit 404, and an output circuit 403. In this example, the node potential control circuit 404 includes a fifth transistor M6 and a sixth transistor M6 connected in series between the second reference voltage terminal and the first reference voltage terminal, an eighth transistor M8 and a ninth transistor M9 connected in series between the second reference voltage terminal and the first reference voltage terminal, the control terminals of the sixth transistor M6 and the ninth transistor M9 are both electrically connected to the first node N1, one of the first terminal and the second terminal of the eighth transistor M8 is electrically connected to its control terminal, and the other of the first terminal and the second terminal of the eighth transistor M8 is electrically connected to the control terminal of the fifth transistor. The connection point between the fifth transistor M6 and the sixth transistor M6 forms a second node N2. Regarding the first transistor M1, the second transistor M2, the seventh transistor M7, the third transistor M3, and the fourth transistor M4 in the shift register unit, their connection method is the same as Figure 2A The embodiments shown are basically the same and will not be described in detail here. Figure 4 In the shift register unit shown, the second reference voltage Vr2 received by the second reference voltage terminal is no longer a constant high-level voltage, but another clock signal complementary to the clock signal CLK. When the clock signal CLK is a square wave signal, the second reference voltage Vr2 is a square wave signal having the same duty cycle as the clock signal CLK but with an opposite phase.

[0060] According to some embodiments of the present application, the shift register unit also includes a threshold voltage compensation transistor and a bias voltage receiving end for receiving the bias voltage, the control end of the threshold voltage compensation transistor is electrically connected to the control end of the threshold voltage adjustable transistor, the input end, and one of the output ends of the output circuit, and the first end and the second end of the threshold voltage compensation transistor are respectively electrically connected to the bias voltage receiving end and the bias electrode of the threshold voltage adjustable transistor.

[0061] Figure 5 and Figure 6 An example of the electrical connection relationship between the threshold voltage adjustable transistor and the threshold voltage compensation transistor in the shift register unit is schematically shown. The threshold voltage adjustable transistor can be any transistor in the shift register unit, and the threshold voltage adjustable transistor is uniformly represented by the reference symbol MT, the control end of the threshold voltage adjustable transistor is represented by the reference symbol A, the first end and the second end of the threshold voltage adjustable transistor are represented by the reference symbols B and C respectively, and the bias electrode of the threshold voltage adjustable transistor for receiving the bias voltage is represented by the reference symbol PE. Figure 5 As shown, the control end of the threshold voltage compensation transistor Mb is electrically connected to the control end of the threshold voltage adjustable transistor MT, and the first end and the second end of the threshold voltage compensation transistor Mb are electrically connected to the bias voltage receiving end Vp and the bias electrode PE of the threshold voltage adjustable transistor, respectively. In this embodiment, the control end of the threshold voltage compensation transistor and the control end of the threshold voltage adjustable transistor are controlled by the same control signal, so when the threshold voltage adjustable transistor is turned on, the threshold voltage compensation transistor applies a bias voltage to the bias electrode of the threshold voltage adjustable transistor, thereby compensating or adjusting the threshold voltage of the threshold voltage adjustable transistor.

[0062] like Figure 6As shown, the control end of the threshold voltage compensation transistor Mb is electrically connected to the output end or the input end of the shift register unit, and the first end and the second end of the threshold voltage compensation transistor Mb are electrically connected to the bias voltage receiving end Vp and the bias electrode PE of the threshold voltage adjustable transistor, respectively. In this embodiment, the control end of the threshold voltage compensation transistor receives the aforementioned input signal or output signal, so when the shift register unit receives a valid input signal In or outputs a valid output signal Out, the threshold voltage compensation transistor applies a bias voltage to the bias electrode PE of the threshold voltage adjustable transistor, thereby compensating or adjusting the threshold voltage of the threshold voltage adjustable transistor.

[0063] The above-mentioned threshold voltage adjustable transistor can be as follows Figure 2A , Figure 3 or Figure 4 Any transistor in the circuit schematic diagram of the shift register unit shown. In practice, different threshold voltage drifts may occur in different transistors in the shift register unit. For example, in the case where the threshold voltage of the threshold voltage adjustable transistor MT drifts positively, a positive bias voltage can be applied to the bias voltage receiving terminal Vp, thereby controlling the threshold voltage of the threshold voltage adjustable transistor MT to move negatively, thereby achieving compensation for the positive drift of the threshold voltage, promoting the stability of the threshold voltage of the threshold voltage adjustable transistor MT, and improving the stability and reliability of the scan signal output by the shift register unit. On the contrary, in the case where the threshold voltage of the threshold voltage adjustable transistor MT drifts negatively, a negative bias voltage can be applied to the bias voltage receiving terminal Vp, thereby controlling the threshold voltage of the threshold voltage adjustable transistor MT to move positively, thereby achieving compensation for the negative drift of the threshold voltage.

[0064] According to another embodiment of the present application, the shift register unit further includes a switch transistor connected in series with the threshold voltage compensation transistor, and the switch transistor is used to control whether the bias voltage is provided to the bias electrode of the threshold voltage adjustable transistor via the threshold voltage compensation transistor. Figure 7 and Figure 8 The figure shows an example of the electrical connection relationship between the threshold voltage compensation transistor, the threshold voltage adjustable transistor, and the switch transistor in the shift register unit. Figure 7 Several articles Figure 8As shown, the shift register unit also includes a switching transistor Ms, which is connected in series with the threshold voltage compensation transistor Mb. The switching transistor Ms can control whether the bias voltage received from the bias voltage receiving end is provided to the bias electrode of the threshold voltage adjustable transistor via the threshold voltage compensation transistor Mb. The control end of the switching transistor Ms can be used to receive the control signal Vk, and the different levels of the control signal Vk can be used to control the on or off of the switching transistor Ms. In other words, in this embodiment, the switching transistor Ms or the control signal Vk may have an enabling function of whether to turn on the adjustment or compensation of the threshold voltage of the threshold voltage adjustable transistor, so the control signal Vk can also be called a compensation enable signal. When the threshold voltage of the threshold voltage adjustable transistor MT does not need to be adjusted or compensated, the control signal Vk can be used to turn off the switching transistor Ms, thereby preventing the transition compensation of the threshold voltage of the threshold voltage adjustable transistor and reducing power consumption. The on time of the switching transistor Ms can be set according to different conditions. For example, after the shift register unit runs for a preset period of time, the control signal Vk can be used to turn on the switch transistor Ms, thereby turning on the threshold voltage compensation transistor Mb to compensate or adjust the threshold voltage of the threshold voltage adjustable transistor. In other embodiments, the node potentials and / or output signals of certain shift register units in the gate drive circuit of the display device can be monitored, and it is determined whether to start the compensation or adjustment of the threshold voltage of the threshold voltage adjustable transistor based on the waveforms of the node potentials and / or the waveform changes of the output signals.

[0065] For example, Fig. 9 FIG. 1 is a partial plan view of a display device provided according to an embodiment of the present application. Fig. 9 As shown, the display device includes a display area AA and a non-display area outside the display area AA. The display device also includes gate drive circuits GC1 and GC2 located in the non-display area. In this embodiment, the gate drive circuits GC1 and GC2 are distributed on both sides of the display area AA. The gate drive circuits GC1 and GC2 may include a plurality of shift register units as described in any of the above embodiments. In addition, the display device also includes a shift register unit arranged in at least one of the four corners of its display surface. Fig. 9 The figure shows four shift register units respectively arranged in the four corners of the display surface. These four shift register units have the module structure shown in FIG. 1 and are all represented by reference numerals GOA. Fig. 9As shown, signal lines are respectively drawn from the first node N1, the second node and the output end of each shift register unit GOA, the first node N1, the second node and the output end of the two shift register units GOA on the left are electrically connected to the signal lines N1_L, N2_L and Out_L respectively, and the first node N1, the second node and the output end of the two shift register units GOA on the right are electrically connected to the signal lines N1_R, N2_R and Out_R respectively. Thus, the signals of the first node, the second node and the output end of the four shift register units GOA can be monitored via these signal lines. When it is monitored that the waveforms of the potentials of these nodes and / or the waveforms of the output signals deviate greatly from the expected waveforms of the potentials of these nodes and the output signals of the output ends, the compensation or adjustment of the threshold voltage of the threshold voltage adjustable transistor can be started.

[0066] The threshold changes of each transistor in the shift register unit may vary according to different transistors. For example, a portion of transistors may have a positive drift in threshold voltage, while another portion of transistors may have a negative drift in threshold voltage. Different threshold voltage adjustments or compensations may be performed for transistors with positive drift in threshold voltage and transistors with negative drift in threshold voltage. Therefore, in some embodiments, the threshold voltage adjustable transistor in the shift register unit includes a first type of transistor with positive drift in threshold voltage and a second type of transistor with negative drift in threshold voltage, the threshold voltage compensation transistor includes a first compensation transistor and a second compensation transistor, and the bias voltage receiving end includes a first voltage receiving end and a second voltage receiving end. Thus, different threshold voltage adjustments or compensations may be performed for the first type of transistor and the second type of transistor through the first voltage receiving end and the second voltage receiving end, the first compensation transistor and the second compensation transistor, respectively. Fig.10 The electrical connection between the first compensation transistor and the first type of transistor, and the electrical connection between the second compensation transistor and the second type of transistor in this embodiment are schematically shown. Fig.10As shown, the shift register unit GOA includes a first type transistor MT1 with a positive drift in threshold voltage and a second type transistor MT2 with a negative drift in threshold voltage, the threshold voltage compensation transistor includes a first compensation transistor Mb1 and a second compensation transistor Mb2, the bias voltage receiving end includes a first voltage receiving end Vp1 and a second voltage receiving end Vp2, the control end of the first compensation transistor Mb1 is electrically connected to the control end A of the first type transistor MT1, the first end and the second end of the first compensation transistor Mb2 are electrically connected to the first voltage receiving end Vp1 and the bias electrode of the first type transistor MT1, the control end of the second compensation transistor Mb1 is electrically connected to the control end of the second type transistor, the first end and the second end of the second compensation transistor Mb2 are electrically connected to the second voltage receiving end Vp1 and the bias electrode of the second type transistor MT2, and the first voltage receiving end Vp1 and the second voltage receiving end Vp2 are respectively used to receive first voltages and second voltages that are different from each other. In some embodiments, the first type transistor includes Figure 2A At least one of the second transistor M2, the third transistor M3 and the seventh transistor M7 in the shift register unit shown in the figure, the second type of transistor includes Figure 2A In the shift register unit shown, the first transistor M1 has a positive first voltage and a negative second voltage. Thus, the threshold voltage of the first type of transistor whose threshold voltage drifts positively can be reduced, while the threshold voltage of the second type of transistor whose threshold voltage drifts negatively can be increased. Fig.10 In the embodiment, the control end of the first compensation transistor is connected to the control end of the first type of transistor, and the control end of the second compensation transistor is connected to the control end of the second type of transistor. Alternatively, the first compensation transistor and the first type of transistor can be controlled by different control signals, and the second compensation transistor and the second type of transistor can be controlled by different control signals, for example, the control end of the first compensation transistor Mb1 and the control end of the second compensation transistor Mb2 can be electrically connected to the input end of the shift register unit to receive the input signal In or the output end to receive the output signal Out.

[0067] Fig.11 FIG. 2 shows a partial circuit of a shift register unit provided according to another embodiment of the present application. Fig.11As shown, the shift register unit GOA includes a first type of transistors MT11 and MT12 with a positive drift in threshold voltage and a second type of transistors MT21 and MT22 with a negative drift in threshold voltage, the threshold voltage compensation transistors include first compensation transistors Mb11 and Mb12 and second compensation transistors Mb21 and Mb22, the bias voltage receiving end includes a first voltage receiving end Vp1 and a second voltage receiving end Vp2, the shift register unit GOA also includes two switching transistors Ms1 and Ms2, the control ends of the switching transistors Ms1 and Ms2 are both controlled by a control signal Vk, the first compensation transistors Mb11 and Mb12 are connected in parallel, and then connected in series with the switching transistor Ms1, the second compensation transistors Mb21 and Mb22 are connected in parallel, and then connected in series with the switching transistor Ms2. The control ends of the first compensation transistors Mb11 and Mb12 are connected to nodes Z1 and Z2, respectively. For example, nodes Z1 and Z2 can be electrically connected to the gates of the first type transistors MT11 and MT12, respectively. The control ends of the second compensation transistors Mb21 and Mb22 are connected to nodes F1 and F2, respectively. For example, nodes F1 and F2 can be electrically connected to the gates of the second type transistors MT21 and MT22, respectively. Therefore, when the control ends of the switching transistors Ms1 and Ms2 receive a valid control signal Vk, and the control ends of the first compensation transistors Mb11 and Mb12 and the second compensation transistors Mb21 and Mb22 receive valid control signals and are turned on, the first voltage (at this time, a positive voltage) received from the first voltage receiving end Vp1 can be applied to the bias electrodes of the first type transistors MT11 and MT12 via the switching transistor Ms1 and the first compensation transistors Mb11 and Mb12, respectively, thereby compensating or adjusting the threshold voltages of the first type transistors MT11 and MT12, and the second voltage (at this time, a negative voltage) received from the second voltage receiving end Vp2 can be applied to the bias electrodes of the second type transistors MT21 and MT22 via the switching transistor Ms2 and the second compensation transistors Mb21 and Mb22, respectively, thereby compensating or adjusting the threshold voltages of the second type transistors MT21 and MT22.

[0068] Fig.12 FIG. 1 is a partial circuit diagram of a shift register unit provided according to another embodiment of the present application. Similar to the aforementioned embodiment, the threshold voltage adjustable transistor in the shift register unit includes a first type of transistor with a positive drift in the threshold voltage and a second type of transistor with a negative drift in the threshold voltage ( Fig.12The first and second types of transistors are not shown in the figure), the threshold voltage compensation transistor includes a first compensation transistor Mb1 and a second compensation transistor Mb2, the bias voltage receiving end includes a first voltage receiving end Vp1 and a second voltage receiving end Vp1, the control end of the first compensation transistor Mb1 and the control end of the second compensation transistor Mb2 are electrically connected to a node N, and the node N can be one of the first node in the shift register unit discussed with reference to Figure 1, the input end of the input circuit or the output end of the output circuit, the first end and the second end of the first compensation transistor Mb1 are electrically connected to the first voltage receiving end Vp1 and the bias electrode PE1 of the first type of transistor, respectively, the first end and the second end of the second compensation transistor Mb2 are electrically connected to the second voltage receiving end Vp2 and the bias electrode PE2 of the second type of transistor, and the first voltage receiving end and the second voltage receiving end are respectively used to receive first voltages and second voltages different from each other. Fig.12 The signal at the node N in may be the potential of the first node N1 in the shift register unit discussed with reference to FIG. 1 , an input signal In at the input end of the input circuit, or an output signal Out at the output end of the output circuit.

[0069] Continue to refer to Fig.12 In some embodiments, the switch transistor includes a first switch transistor Ms1 connected in series with the first compensation transistor Mb1, and a second switch transistor Ms2 connected in series with the second compensation transistor Mb2, and the control end of the first switch transistor Ms1 and the control end of the second switch transistor Ms2 are electrically connected to a compensation enable end that provides a compensation enable signal Vk. Thus, whether to start compensating the threshold voltages of the first type of transistor and the second type of transistor can be controlled according to the compensation enable signal Vk provided by the compensation enable end, and different voltages (the first voltage and the second voltage) can be used to respectively make different compensations or adjustments to the threshold voltages of the first type of transistor and the second type of transistor.

[0070] According to some embodiments of the present application, the shift register unit includes a substrate for carrying the input circuit, the output circuit, the pull-up circuit, the pull-down circuit, the discharge circuit and the reset circuit, and the substrate includes a first area for arranging the first type of transistors, and a second area for arranging the second type of transistors. The substrate of the threshold voltage adjustable transistor mentioned in the previous embodiment can be a part of the substrate mentioned in this embodiment, that is, the substrate of the threshold voltage adjustable transistor can extend on a plane to form the substrate in this embodiment. Alternatively, in another embodiment, the substrate mentioned in this embodiment is another supporting structure different from the substrate of the threshold voltage adjustable transistor. In this embodiment, the first type of transistors are concentrated in the first area, and the second type of transistors are concentrated in the second area, that is, all transistors with positive drift of threshold voltage in the shift register unit are arranged in the first area, and all transistors with negative drift of threshold voltage are arranged in the second area different from the first area. Fig.13 The first area A1 and the second area A2 of the substrate of the shift register unit are schematically shown. All transistors with positive drift of threshold voltage in the shift register unit are arranged in the first area A1. Therefore, the first area A1 can also be called the threshold voltage positive drift compensation area, and the second area A2 can also be called the threshold voltage negative drift compensation area. In this case, the same bias voltage (for example, a positive voltage) can be applied to the bias electrodes of each first-type transistor in the first area A1, and the same bias voltage (for example, a negative voltage) can be applied to the bias electrodes of each second-type transistor in the second area A2. At the same time, the integrated design of the bias electrodes of each first-type transistor and the integrated design of the bias electrodes of each second-type transistor can be realized, which is conducive to simplifying the manufacturing process of the bias electrodes of the threshold voltage adjustable transistors in the shift register unit. Fig.13 In the embodiment of the present invention, the substrate further includes a third area A3 located between the first area A and the second area A2. Transistors in the shift register unit whose threshold voltages do not drift or whose working characteristics are not easily changed can be concentrated in the third area A3. For transistors whose threshold voltages do not drift seriously or are not easily drifted, there is no need to compensate or adjust the threshold voltage. Therefore, the third area A3 can be called a threshold voltage non-compensation area. Fig.13 The partition layout for each transistor as shown in the embodiment can optimize the compensation for the threshold voltage of the threshold voltage adjustable transistor.

[0071] Next, combine Figure 2A and Figure 3 The first type of transistor and the second type of transistor are exemplarily described. Figure 2A or Figure 3As shown, the input circuit includes a first transistor M1, the control terminal of the first transistor M1 is electrically connected to the input terminal, the first terminal of the first transistor M1 is electrically connected to the input terminal or the first control signal terminal (a terminal for receiving the first control signal Vs1), and the second terminal of the first transistor M1 is electrically connected to the first node N1. The reset circuit includes a second transistor M2, the control terminal of the second transistor M2 is used to receive the reset signal Re, the first terminal of the second transistor M2 is electrically connected to the first node N1, and the second terminal of the second transistor M2 is electrically connected to the second control signal terminal (a terminal for receiving the second control signal Vs2) or the first reference voltage terminal. The output circuit includes a third transistor M3, a fourth transistor M4 and a capacitor C, the control terminal of the third transistor M3 is electrically connected to the first node N1, the first terminal of the third transistor M3 is used to receive the clock signal CLK, and the second terminal of the third transistor M3 is electrically connected to To the output end, the control end of the fourth transistor M4 is electrically connected to the second node N2, the first end and the second end of the fourth transistor M4 are electrically connected to the output end and the first reference voltage end, respectively, the capacitor C is electrically connected between the first node N1 and the output end, the node potential control circuit includes a fifth transistor M5 and a sixth transistor M5, the control end and the first end of the fifth transistor M5 are electrically connected to the second reference voltage end, the second end of the fifth transistor M5 is electrically connected to the second node N2, the control end of the sixth transistor M6 is electrically connected to the first node N1, the first end and the second end of the sixth transistor M6 are electrically connected to the second node N2 and the first reference voltage end, respectively, the discharge circuit includes a seventh transistor M7, the control end of the seventh transistor is electrically connected to the second node B2, the first end and the second end of the first transistor M1 are electrically connected to the first node N1 and the first reference voltage end. Through a large number of experimental monitoring and research, the inventors of the present application realize that the second transistor M2, the third transistor M3 and the seventh transistor M7 in the shift register unit are prone to positive threshold voltage drift, and the first transistor M1 is prone to negative threshold voltage drift. Therefore, in this embodiment, the first type of transistor includes the second transistor M2, the third transistor M3 or the seventh transistor M7, and the second type of transistor includes the first transistor M1. The threshold voltages of the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are not prone to drift. At this time, the second transistor M2, the third transistor M3 or the seventh transistor M7 can be centrally arranged in the aforementioned first region, and the fourth transistor M4, the fifth transistor M5 and the sixth transistor M5 are arranged in the aforementioned third region.

[0072] Another embodiment of the present application provides a gate driving circuit, comprising a plurality of shift register units as described in the aforementioned embodiments, wherein the shift register units are cascaded to output a plurality of scanning signals that are staggered in timing. Fig.14Four cascaded shift register units are schematically shown, each shift register unit includes an input terminal for receiving an input signal IN, a clock signal input terminal for receiving a clock signal CLK, a reset terminal for receiving a reset signal Re, and an output terminal for providing an output signal OUT (i.e., a scan signal), and the output signal OUT of the previous shift register unit is used as the input signal IN provided to the adjacent subsequent shift register unit. Signal lines SL1 and SL2 transmit clock signals and reset signals to each stage of the shift register unit, respectively. According to some embodiments of the present application, the gate drive circuit also includes a threshold voltage compensation circuit, and the threshold voltage compensation circuit may include a plurality of threshold voltage compensation transistors corresponding to each stage of the shift register unit, and the control terminal of each threshold voltage compensation transistor is electrically connected to the output terminal, the input terminal or one of the first nodes in the corresponding shift register unit, and the first terminal and the second terminal of the threshold voltage compensation transistor are electrically connected to the bias voltage receiving terminal and the bias electrode of the threshold voltage adjustable transistor in the corresponding shift register unit, respectively. For example, Fig.15 The electrical connection relationship between the threshold voltage adjustable transistor M3 and the corresponding threshold voltage compensation transistor Mb in two cascaded shift register units is schematically shown.

[0073] According to another embodiment of the present application, a threshold voltage compensation circuit in a gate drive circuit includes a threshold voltage compensation transistor and a bias voltage receiving terminal for receiving a bias voltage, a control terminal of the threshold voltage compensation transistor is electrically connected to the output terminal, the input terminal or one of the first nodes in each shift register unit, and a first terminal and a second terminal of the threshold voltage compensation transistor are electrically connected to the bias voltage receiving terminal and a bias electrode of the threshold voltage adjustable transistor in each shift register unit, respectively. That is, in this embodiment, the same threshold voltage adjustable transistors or threshold voltage adjustable transistors (e.g., first-class transistors) with the same threshold voltage drift characteristics in each shift register unit share a threshold voltage compensation transistor, thereby simplifying the design of the threshold voltage compensation circuit for the threshold voltage adjustable transistors of each level of shift register units.

[0074] According to another embodiment of the present application, the threshold voltage adjustable transistor includes a first type of transistor with a positively drifted threshold voltage and a second type of transistor with a negatively drifted threshold voltage, the threshold voltage compensation transistor includes a first compensation transistor and a second compensation transistor, the bias voltage receiving end includes a first voltage receiving end and a second voltage receiving end, the control end of the first compensation transistor and the control end of the second compensation transistor are electrically connected to the output end, the input end or one of the first nodes in each shift register unit, the first end and the second end of the first compensation transistor are electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor, respectively, the first end and the second end of the second compensation transistor are electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor, respectively, wherein the first voltage receiving end and the second voltage receiving end are respectively used to receive first voltages and second voltages that are different from each other. For example, Fig.16 The two shift register units and the threshold voltage compensation circuit in the gate driving circuit are schematically illustrated. Fig.16 As shown, each shift register unit includes a substrate for carrying the input circuit, the output circuit, the pull-up circuit, the pull-down circuit, the discharge circuit and the reset circuit, and the substrate includes a first area A1 for arranging the first type of transistors, and a second area A2 for arranging the second type of transistors. The first area A1 includes the first type of transistors with a positive drift in the threshold voltage, the second area A2 includes the second type of transistors with a negative drift in the threshold voltage, and the transistors whose threshold voltages do not need to be compensated or adjusted are arranged in the third area A3. Fig.16 As shown, the threshold voltage compensation transistor includes a first compensation transistor Mb1 and a second compensation transistor Mb2, the bias voltage receiving end includes a first voltage receiving end Vp1 and a second voltage receiving end Vp2, the control end of the first compensation transistor Mb1 and the control end of the second compensation transistor Mb2 are electrically connected to the output end in each shift register unit, the first end and the second end of the first compensation transistor Mb1 are electrically connected to the first voltage receiving end Vp1 and the bias electrode of the first type of transistor, respectively, the first end and the second end of the second compensation transistor Mb2 are electrically connected to the second voltage receiving end Vp1 and the bias electrode of the second type of transistor, respectively, the first voltage receiving end Vp1 and the second voltage receiving end Vp2 are used to receive first voltages and second voltages that are different from each other, respectively. Fig.16In the embodiment, each transistor in each shift register unit is arranged in different regions according to the threshold voltage drift characteristics. The first compensation transistor Mb1 and the second compensation transistor Mb2 can be used to achieve targeted compensation or adjustment of the threshold voltages of transistors in different regions. For example, the first voltage received by the first voltage receiving terminal Vp1 can be a positive voltage to promote the threshold voltage of the first type of transistors in the first area A1 to move negatively (lower the threshold voltage), and the second voltage received by the second voltage receiving terminal Vp2 can be a negative voltage to promote the threshold voltage of the second type of transistors in the second area A2 to move positively (increase the threshold voltage). At the same time, each shift register unit can share a threshold voltage compensation circuit, which is beneficial to the simplification of the structure of the gate drive circuit. Fig.16 In the embodiment, the control end of the first compensation transistor Mb1 and the control end of the second compensation transistor Mb2 are electrically connected to the output ends Out1 and Out2 in each shift register unit, but in other embodiments, the control end of the first compensation transistor Mb1 and the control end of the second compensation transistor Mb2 are electrically connected to the input end or the first node in each shift register unit.

[0075] Continue to refer to Fig.16 According to some embodiments of the present application, the threshold voltage compensation circuit further includes a first switch transistor Ms1 connected in series with the first compensation transistor Mb1, and a second switch transistor Ms2 connected in series with the second compensation transistor Mb2, and the control end of the first switch transistor Ms1 and the control end of the second switch transistor Ms2 are electrically connected to a compensation enable end that provides a compensation enable signal Vk. Therefore, through the compensation enable signal Vk received by the compensation enable end, the conduction and cutoff of the first switch transistor Ms1 and the second switch transistor Ms2 can be controlled, thereby controlling whether to apply a corresponding bias voltage to the bias electrode of the threshold voltage adjustable transistor in each shift register unit, so as to facilitate the user to control whether the threshold voltage compensation function is enabled.

[0076] It will be understood that although the terms first, second, third, etc. may be used herein to describe various devices, elements, components or parts, these devices, elements, components or parts should not be limited by these terms, and only represent the distinction in name. For example, the aforementioned first to seventh sub-package structures are only used to distinguish the names of the sub-package structures in different embodiments of the power amplifier device. In addition, the "electrical connection" mentioned herein includes "direct connection" or "indirect connection". Although the technical solution of the present application has been described in conjunction with some embodiments, the scope of protection of the present application is not limited to the specific form set forth herein, and the scope of the present application is defined by the attached claims.

Claims

1. A shift register unit, characterized in that: The shift register unit comprises: an input circuit configured to be electrically connected to an input terminal and a first node to control a potential of the first node based on an input signal received from the input terminal; an output circuit configured to receive a clock signal and electrically connected to the first node, the second node, an output terminal and a first reference voltage terminal to provide an output signal to the output terminal based on the clock signal under the control of the potential of the first node and the potential of the second node; a node potential control circuit configured to be electrically connected to the first node, the second node, the first reference voltage terminal, and a second reference voltage terminal to control the potential of the second node according to a second reference voltage provided by the second reference voltage terminal and the potential of the first node; a discharge circuit configured to be electrically connected to the first node, the second node, and the first reference voltage terminal to discharge the first node under the control of the potential of the second node; and a reset circuit configured to receive a reset signal and electrically connected to the first node to reset the first node under the control of the reset signal, At least one of the input circuit, the output circuit, the node potential control circuit, the discharge circuit and the reset circuit includes a threshold voltage adjustable transistor, which includes a substrate, a gate, a source and a drain, and a bias electrode, wherein the source and the drain are arranged on a side of the substrate facing the gate, the bias electrode is arranged on a side of the substrate away from the gate, and the bias electrode is configured to receive a bias voltage to adjust the threshold voltage of the threshold voltage adjustable transistor.

2. The shift register unit according to claim 1, characterized in that: The threshold voltage adjustable transistor further includes an active layer located between the gate and the source and drain, and a substrate for supporting the gate, wherein the orthographic projection of the bias electrode on the substrate covers the orthographic projection of the active layer on the substrate.

3. The shift register unit according to claim 2, characterized in that: The threshold voltage adjustable transistor further includes a gate insulating layer, wherein the gate insulating layer is located between the source and drain electrodes and the substrate and covers the gate electrode.

4. The shift register unit according to claim 1, characterized in that: The shift register unit also includes a threshold voltage compensation transistor and a bias voltage receiving end for receiving the bias voltage, the control end of the threshold voltage compensation transistor is electrically connected to the control end of the threshold voltage adjustable transistor, the input end, and one of the output ends of the output circuit, and the first end and the second end of the threshold voltage compensation transistor are electrically connected to the bias voltage receiving end and the bias electrode of the threshold voltage adjustable transistor, respectively.

5. The shift register unit according to claim 4, characterized in that: The shift register unit further includes a switch transistor connected in series with the threshold voltage compensation transistor, and the switch transistor is used to control whether the bias voltage is provided to the bias electrode of the threshold voltage adjustable transistor via the threshold voltage compensation transistor.

6. The shift register unit according to claim 5, characterized in that: The threshold voltage adjustable transistor includes a first type of transistor with a positive drift in the threshold voltage and a second type of transistor with a negative drift in the threshold voltage. The threshold voltage compensation transistor includes a first compensation transistor and a second compensation transistor. The bias voltage receiving end includes a first voltage receiving end and a second voltage receiving end, wherein the control end of the first compensation transistor is electrically connected to the control end of the first type of transistor, the first end and the second end of the first compensation transistor are respectively electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor, the control end of the second compensation transistor is electrically connected to the control end of the second type of transistor, the first end and the second end of the second compensation transistor are respectively electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor, wherein the first voltage receiving end and the second voltage receiving end are respectively used to receive first voltages and second voltages that are different from each other.

7. The shift register unit according to claim 5, characterized in that: The threshold voltage adjustable transistor includes a first type of transistor with a positive drift in the threshold voltage and a second type of transistor with a negative drift in the threshold voltage. The threshold voltage compensation transistor includes a first compensation transistor and a second compensation transistor. The bias voltage receiving end includes a first voltage receiving end and a second voltage receiving end, wherein the control end of the first compensation transistor and the control end of the second compensation transistor are electrically connected to the first node, the input end of the input circuit or one of the output ends of the output circuit. The first end and the second end of the first compensation transistor are electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor, respectively. The first end and the second end of the second compensation transistor are electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor, respectively, wherein the first voltage receiving end and the second voltage receiving end are respectively used to receive first voltages and second voltages that are different from each other.

8. The shift register unit according to claim 6 or 7, characterized in that: The shift register unit includes a substrate for carrying the input circuit, the output circuit, the discharge circuit and the reset circuit, and the substrate includes a first area for arranging the first type of transistors and a second area for arranging the second type of transistors.

9. The shift register unit according to claim 6 or 7, characterized in that: The switching transistor includes a first switching transistor connected in series with the first compensation transistor and a second switching transistor connected in series with the second compensation transistor, and the control end of the first switching transistor and the control end of the second switching transistor are electrically connected to a compensation enable end that provides a compensation enable signal.

10. The shift register unit according to claim 8, characterized in that: The input circuit includes a first transistor, a control terminal of the first transistor is electrically connected to the input terminal, a first terminal of the first transistor is electrically connected to the input terminal or a first control signal terminal, and a second terminal of the first transistor is electrically connected to the first node. The reset circuit includes a second transistor, a control terminal of the second transistor is used to receive a reset signal, a first terminal of the second transistor is electrically connected to the first node, and a second terminal of the second transistor is electrically connected to a second control signal terminal or the first reference voltage terminal. The output circuit includes a third transistor, a fourth transistor and a capacitor, the control terminal of the third transistor is electrically connected to the first node, the first terminal of the third transistor is used to receive the clock signal, the second terminal of the third transistor is electrically connected to the output terminal, the control terminal of the fourth transistor is electrically connected to the second node, the first terminal and the second terminal of the fourth transistor are electrically connected to the output terminal and the first reference voltage terminal, respectively, and the capacitor is electrically connected between the first node and the output terminal. The node potential control circuit includes a fifth transistor and a sixth transistor, wherein the control terminal and the first terminal of the fifth transistor are electrically connected to the second reference voltage terminal, the second terminal of the fifth transistor is electrically connected to the second node, the control terminal of the sixth transistor is electrically connected to the first node, and the first terminal and the second terminal of the sixth transistor are electrically connected to the second node and the first reference voltage terminal, respectively. The discharge circuit includes a seventh transistor, a control terminal of the seventh transistor is electrically connected to the second node, a first terminal and a second terminal of the first transistor are electrically connected to the first node and the first reference voltage terminal, respectively. The first type of transistors includes the second transistor, the third transistor and the seventh transistor, and the second type of transistors includes the first transistor.

11. The shift register unit according to claim 10, characterized in that: The substrate further includes a third region, and the fourth transistor, the fifth transistor, and the sixth transistor are arranged in the third region.

12. A gate driving circuit, comprising a plurality of cascaded shift register units according to any one of claims 1 to 3, characterized in that: The gate drive circuit also includes a threshold voltage compensation circuit, which includes a threshold voltage compensation transistor and a bias voltage receiving end for receiving the bias voltage, the control end of the threshold voltage compensation transistor is electrically connected to the output end, the input end or one of the first nodes in each shift register unit, and the first end and the second end of the threshold voltage compensation transistor are respectively electrically connected to the bias voltage receiving end and the bias electrode of the threshold voltage adjustable transistor in each shift register unit.

13. The gate driving circuit according to claim 12, characterized in that: The threshold voltage adjustable transistor includes a first type of transistor with a positive drift in the threshold voltage and a second type of transistor with a negative drift in the threshold voltage. The threshold voltage compensation transistor includes a first compensation transistor and a second compensation transistor. The bias voltage receiving end includes a first voltage receiving end and a second voltage receiving end, wherein the control end of the first compensation transistor and the control end of the second compensation transistor are electrically connected to the output end, the input end or one of the first nodes in each shift register unit, the first end and the second end of the first compensation transistor are electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor, respectively, and the first end and the second end of the second compensation transistor are electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor, respectively, wherein the first voltage receiving end and the second voltage receiving end are respectively used to receive first voltages and second voltages that are different from each other.

14. The gate driving circuit according to claim 13, characterized in that: The threshold voltage compensation circuit also includes a first switching transistor connected in series with the first compensation transistor, and a second switching transistor connected in series with the second compensation transistor, and the control end of the first switching transistor and the control end of the second switching transistor are electrically connected to a compensation enable end that provides a compensation enable signal.

15. The gate driving circuit according to claim 13, characterized in that: Each shift register unit includes a substrate for carrying the input circuit, the output circuit, the discharge circuit and the reset circuit, and the substrate includes a first area for arranging the first type of transistors and a second area for arranging the second type of transistors.

16. A display device, characterized in that: The display device comprises the gate driving circuit according to any one of claims 12-15.

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