A DSP Synchronous Clock Oscillator
By connecting the crystal oscillator to the clock driver, a DSP synchronous clock oscillator was designed, which solved the problem of insufficient clock signal stability and accuracy in the prior art, and achieved the effect of low phase noise and high data transmission accuracy.
Patent Information
- Application Number
- CN202421905301.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-07
- Publication Date
- 2025-04-04
- Estimated Expiration
- 2034-08-07
AI Technical Summary
There is a lack of specially designed crystal oscillators for clock signal stability, accuracy and low phase noise in high-speed data transmissions.
A DSP synchronous clock oscillator is designed to ensure that the signal can meet the input requirements of the DSP chip by connecting the crystal oscillator to the clock driver and using the clock driver to amplify or buffer the clock signal.
It realizes the provision of a stable clock signal source in high-speed data transmission, reduces phase noise, improves signal stability and data transmission accuracy.
Smart Images
Figure CN222721464U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a crystal oscillator, in particular to a DSP synchronous clock oscillator. Background Art
[0002] With the development of technology, the speed of data communication is constantly increasing, and the requirements for the stability and accuracy of clock signals are getting higher and higher. DSP chips are widely used in occasions that require high-speed data processing and real-time response, such as signal processing, communication systems, video processing, etc. In high-speed data transmission, the stability, accuracy and low phase noise of the clock signal are crucial to synchronize data flow and ensure signal integrity. However, there is currently no crystal oscillator designed for this purpose. Utility Model Content
[0003] The utility model aims to at least solve the technical problems existing in the prior art, and in particular innovatively proposes a DSP synchronous clock oscillator.
[0004] In order to achieve the above-mentioned purpose of the utility model, the utility model provides a DSP synchronous clock oscillator, comprising: a DSP chip, a crystal oscillator and a clock driver, wherein a clock signal transmitting end of the crystal oscillator is connected to a clock signal receiving end of the clock driver, and a clock signal transmitting end of the clock driver is connected to a high-speed serial communication interface of the DSP chip;
[0005] The clock signal generated by the crystal oscillator is transmitted to the clock driver through wires or PCB (printed circuit board)
[0006] , the clock driver receives the clock signal from the crystal oscillator and amplifies or buffers the signal as needed. Amplification can increase the signal amplitude to meet the input requirements of the DSP chip. Buffering can provide additional current driving capability while reducing the load dependence of the signal. The clock signal processed by the clock driver is distributed to the high-speed serial communication interface of the DSP chip (such as PCIe, SGMII, SRIO).
[0007] Furthermore, the high-speed serial communication interface of the DSP chip includes PCIe, SGMII, and SRIO.
[0008] Furthermore, the connection relationship between the DSP chip, the crystal oscillator and the clock driver includes:
[0009] The enable terminal CE of the crystal oscillator U12 is connected to the first end of the resistor R212, the second end of the resistor R212 is connected to the power supply VCC3.3V, the power supply terminal VDO of the crystal oscillator U12 is connected to the first end of the chip ferrite bead L12 and the first end of the capacitor C386, the second end of the chip ferrite bead L12 is connected to the power supply VCC3.3V, and the second end of the capacitor C386 is connected to the power ground;
[0010] Connecting the power supply terminal VDO of the crystal oscillator U12 to the chip ferrite bead L12 can convert high-frequency interference into heat energy and dissipate it.
[0011] The clock output terminal CLK of the crystal oscillator U12 is connected to the first end of the capacitor C387, the second end of the capacitor C387 is connected to the first end of the resistor R216 and the CLKINO+ of the clock driver D5, the inverted signal output terminal CLK* of the crystal oscillator U12 is connected to the first end of the capacitor C388, the second end of the capacitor C388 is connected to the second end of the resistor R216 and the CLKINO- of the clock driver D5;
[0012] The control terminal CLKIN_SEL0 of the external clock input source of the crystal oscillator U12 is connected to the first end of the resistor R219.
[0013] The control terminal CLKIN SEL1 of the external clock input source of the crystal oscillator U12 is connected to the first end of the resistor R215, and the second end of the resistor R219 and the second end of the resistor R215 are connected to the power ground;
[0014] The power supply terminal VCC1 of the crystal oscillator U12, the power supply terminal VCC2 of the crystal oscillator U12, the driver power supply terminal VCCOA1 of the crystal oscillator U12, the driver power supply terminal VCCOA2 of the crystal oscillator U12, the driver power supply terminal VCCOB1 of the crystal oscillator U12, the driver power supply terminal VCCOB2 of the crystal oscillator U12, and the internal power supply terminal VCCOC of the crystal oscillator U12 are all connected to the power supply VCC3.3V;
[0015] The reference output enable terminal REFOUT EN of the crystal oscillator U12 is connected to the first end of the resistor R214, the setting CLKOUTA group output type terminal CLKOUTA TYPE1 of the crystal oscillator U12 is connected to the first end of the resistor R213, the setting CLKOUTB group output type terminal CLKOUTB TYPE1 of the crystal oscillator U12 is connected to the first end of the resistor R217, and the second end of the resistor R214, the second end of the resistor R213, and the second end of the resistor R217 are connected to the power ground;
[0016] The output type terminal CLKOUTA_TYPE0 of the setting CLKOUTA group of the crystal oscillator U12 and the output type terminal CLKOUTB TYPE0 of the setting CLKOUTB group of the crystal oscillator U12 are connected to the power ground;
[0017] The first clock signal output terminal (CLKOUTA group differential output terminal) CLKOUTA0+ of the crystal oscillator U12 is connected to the first end of the capacitor C389, the first clock signal output terminal CLKOUTA0- of the crystal oscillator U12 is connected to the first end of the capacitor C393, the second clock signal output terminal CLKOUTA1+ of the crystal oscillator U12 is connected to the first end of the capacitor C390, the second clock signal output terminal CLKOUTA1- of the crystal oscillator U12 is connected to the first end of the capacitor C394, and the third clock signal output terminal CLKOUTA2+ of the crystal oscillator U12 is connected to the first end of the capacitor C391. The third clock signal output terminal CLKOUTA2- of the crystal oscillator U12 is connected to the first end of the capacitor C395, the fourth clock signal output terminal CLKOUTA3+ of the crystal oscillator U12 is connected to the first end of the capacitor C392, the fourth clock signal output terminal CLKOUTA3- of the crystal oscillator U12 is connected to the first end of the capacitor C396, the second end of the capacitor C389, the second end of the capacitor C393, the second end of the capacitor C390, the second end of the capacitor C394, the second end of the capacitor C391, the second end of the capacitor C395, the second end of the capacitor C392, and the second end of the capacitor C396 are all connected to the DSP chip.
[0018] The dedicated clock driver chip can ensure that the clock signals are homologous to each other, ensuring the signal quality and driving capability of each group of clocks. The crystal oscillator U12 is a differential crystal oscillator, and the output signal is an LVDS clock signal. The crystal oscillator and the clock driver use differential pair wiring to reduce signal degradation and electromagnetic interference.
[0019] Furthermore, in addition to the power supply terminal VCC1 of the crystal oscillator U12, the power supply terminal VCC2 of the crystal oscillator U12, the driver power supply terminal VCCOA1 of the crystal oscillator U12, the driver power supply terminal VCCOA2 of the crystal oscillator U12, the driver power supply terminal VCCOB1 of the crystal oscillator U12, the driver power supply terminal VCCOB2 of the crystal oscillator U12, and the internal power supply terminal VCCOC of the crystal oscillator U12 are all connected to the power supply VCC3.3V; the connection can also be made in the following ways:
[0020] The power supply end VCC1 of the crystal oscillator U12 and the power supply end VCC2 of the crystal oscillator U12 are connected to the first end of the chip ferrite bead L13, the first end of the capacitor C353, the first end of the capacitor C355, the first end of the capacitor C357, the first end of the capacitor C359, the first end of the capacitor C361, and the first end of the capacitor C363. The second end of the capacitor C353, the second end of the capacitor C355, the second end of the capacitor C357, the second end of the capacitor C359, the second end of the capacitor C361, and the second end of the capacitor C363 are connected to the power ground. The second end of the chip ferrite bead L13 is connected to the power supply VCC3.3V. The first end of the chip ferrite bead L14 is connected, the second end of the chip ferrite bead L14 is connected to the first end of the capacitor C354, the first end of the capacitor C356, the first end of the capacitor C358, the first end of the capacitor C360, the first end of the capacitor C362, the first end of the capacitor C364, the driver power supply terminal VCCOA1 of the crystal oscillator U12, and the driver power supply terminal VCCOA2 of the crystal oscillator U12, and the second end of the capacitor C354, the second end of the capacitor C356, the second end of the capacitor C358, the second end of the capacitor C360, the second end of the capacitor C362, and the second end of the capacitor C364 are connected to the power ground;
[0021] The driver power supply terminal VCCOB1 of the crystal oscillator U12 and the driver power supply terminal VCCOB2 of the crystal oscillator U12 are connected to the first end of the capacitor C365, the first end of the capacitor C367, the first end of the capacitor C369, the first end of the capacitor C371, the first end of the capacitor C373, the first end of the capacitor C375, and the first end of the chip ferrite bead L15, and the second end of the capacitor C365, the second end of the capacitor C367, the second end of the capacitor C369, the second end of the capacitor C371, the second end of the capacitor C373, and the second end of the capacitor C375 are connected to the power ground;
[0022] The second end of the chip ferrite bead L15 is connected to the power supply VCC3.3V and the first end of the chip ferrite bead L16. The second end of the chip ferrite bead L16 is connected to the internal power supply terminal VCCOC of the crystal oscillator U12, the first end of capacitor C366, the first end of capacitor C368, the first end of capacitor C370, the first end of capacitor C372, the first end of capacitor C374, and the first end of capacitor C376, and is connected to the second end of capacitor C366, the second end of capacitor C368, the second end of capacitor C370, the second end of capacitor C372, the second end of capacitor C374, and the second end of capacitor C376 to the power ground.
[0023] By connecting magnetic beads in series on the power supply, high-frequency interference is converted into heat energy and dissipated; and the main reason for using several capacitors in parallel on the power line is to filter out interference ripples in a wider frequency range, thereby improving the stability of the power supply and the electromagnetic compatibility of the system.
[0024] Furthermore, the model of the crystal oscillator U12 is SI534BC002369DG.
[0025] Furthermore, the model of the clock driver D5 is AU5411A-QMR.
[0026] Furthermore, the models of the ferrite beads L12, L13, L14, and L15 are all BLM21PG221SN1D.
[0027] Furthermore, the power supply VCC3.3V is provided by a power supply circuit, and the power supply circuit includes:
[0028] The voltage output pin VOUT1_0 of the buck regulator chip D19, the voltage output pin VOUT1_1 of the buck regulator chip D19 and the voltage output pin VOUT1_2 of the buck regulator chip D19 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C514 and the first end of the capacitor C567, the second end of the capacitor C514 and the second end of the capacitor C567 are grounded, the feedback pin FB1 of the buck regulator chip D19 is connected to the first end of the resistor R235, the second end of the resistor R235 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D19 is connected to the first end of the capacitor C511, the second end of the capacitor C511 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D19 is connected to the first end of the resistor R231, and the second end of the resistor R231 is connected to the internal power pin INTVCC1 of the buck regulator chip D19;
[0029] The voltage output pin VOUT2_0 of the buck regulator chip D19, the voltage output pin VOUT2_1 of the buck regulator chip D19 and the voltage output pin VOUT2_2 of the buck regulator chip D19 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C515 and the first end of the capacitor C568, the second end of the capacitor C515 and the second end of the capacitor C568 are grounded, the feedback pin FB2 of the buck regulator chip D19 is connected to the first end of the resistor R236, the second end of the resistor R236 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D19 is connected to the first end of the capacitor C512, the second end of the capacitor C512 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D19 is connected to the first end of the resistor R232; the first end of the resistor R232 is connected, and the second end of the resistor R232 is connected to the internal power pin INTVCC2 of the buck regulator chip D19;
[0030] The voltage output pin VOUT3_0 of the buck regulator chip D19, the voltage output pin VOUT3_1 of the buck regulator chip D19, and the voltage output pin VOUT3_2 of the buck regulator chip D19 output the power supply voltage VCC1.05V and are connected to the first end of the capacitor C516 and the first end of the capacitor C569, the second end of the capacitor C516 and the second end of the capacitor C569 are grounded, the feedback pin FB3 of the buck regulator chip D19 is connected to the first end of the resistor R237, the second end of the resistor R237 is grounded, the voltage tracking and soft start pin TRACK|SS3 of the buck regulator chip D19 is connected to the first end of the capacitor C513, the second end of the capacitor C513 is grounded, the power good indication terminal PGOOD3 of the buck regulator chip D19 is connected to the first end of the resistor R233, and the second end of the resistor R233 is connected to the internal power pin INTVCC3 of the buck regulator chip D19;
[0031] The voltage output pin VOUT4_0 of the buck regulator chip D19, the voltage output pin VOUT4_1 of the buck regulator chip D19 and the voltage output pin VOUT4_2 of the buck regulator chip D19 output the power supply voltage VCC3.3V and are connected to the first end of the capacitor C301 and the first end of the capacitor C302, the second end of the capacitor C301 and the second end of the capacitor C302 are grounded, the feedback pin FB4 of the buck regulator chip D19 is connected to the first end of the resistor R138, the second end of the resistor R138 is grounded, the voltage tracking and soft start pin TRACK|SS4 of the buck regulator chip D19 is connected to the first end of the capacitor C300, the second end of the capacitor C300 is grounded, the power good indication terminal PGOOD4 of the buck regulator chip D19 is connected to the first end of the resistor R137; the first end of the resistor R137 is connected, and the second end of the resistor R137 is connected to the internal power pin INTVCC4 of the buck regulator chip D19;
[0032] The voltage input pin VIN1_0 of the buck regulator chip D19, the voltage input pin VIN1_1 of the buck regulator chip D19, and the voltage input pin SVIN1 of the buck regulator chip D19 are connected to the power supply voltage VCC12V and the first end of the capacitor C507, the second end of the capacitor C507 is grounded, and the power good indication terminal PGOOD3 of the buck regulator chip D19 is connected to the enable terminal RUN1 of the buck regulator chip D19;
[0033] The voltage input pin VIN2_0 of the buck regulator chip D19, the voltage input pin VIN2_1 of the buck regulator chip D19, and the voltage input pin SVIN2 of the buck regulator chip D19 are connected to the power supply voltage VCC12V and the first end of the capacitor C508, and the second end of the capacitor C508 is grounded; the power good indication terminal PGOOD1 of the buck regulator chip D19 is connected to the enable terminal RUN2 of the buck regulator chip D19;
[0034] The voltage input pin VIN3_0 of the buck regulator chip D19, the voltage input pin VIN3_1 of the buck regulator chip D19, and the voltage input pin SVIN3 of the buck regulator chip D19 are connected to the power supply voltage VCC12V and the first end of the capacitor C509, and the second end of the capacitor C509 is grounded;
[0035] The voltage input pin VIN4_0 of the buck regulator chip D19, the voltage input pin VIN4_1 of the buck regulator chip D19, the voltage input pin SVIN4 of the buck regulator chip D19, and the enable pin RUN4 of the buck regulator chip D19 are connected to the power supply voltage VCC12V and the first end of the capacitor C510, and the second end of the capacitor C510 is grounded; the power good indication terminal PGOOD2 of the buck regulator chip D19 is connected to the enable terminal RUN4 of the buck regulator chip D19;
[0036] The internal power pin INTVCC1 of the buck regulator chip D19 is connected to the working mode configuration pin MODE1 of the buck regulator chip D19, and the internal power pin INTVCC2 of the buck regulator chip D19 is connected to the working mode configuration pin MODE2 of the buck regulator chip D19; the internal power pin INTVCC3 of the buck regulator chip D19 is connected to the working mode configuration pin MODE3 of the buck regulator chip D19, and the internal power pin INTVCC4 of the buck regulator chip D19 is connected to the working mode configuration pin MODE4 of the buck regulator chip D19;
[0037] The ground pin SGND of the buck regulator chip D19, the ground pin GND_0 of the buck regulator chip D19, the ground pin GND_1 of the buck regulator chip D19, the ground pin GND_2 of the buck regulator chip D19, the ground pin GND_3 of the buck regulator chip D19, the ground pin GND_4 of the buck regulator chip D19, the ground pin GND_5 of the buck regulator chip D19, the ground pin GND_6 of the buck regulator chip D19, the ground pin GND_7 of the buck regulator chip D19, the ground pin GND_8 of the buck regulator chip D19, the ground pin GND_9 of the buck regulator chip D The ground pin GND_10 of step-down voltage regulator chip D19, the ground pin GND_11 of step-down voltage regulator chip D19, the ground pin GND_12 of step-down voltage regulator chip D19, the ground pin GND_13 of step-down voltage regulator chip D19, the ground pin GND_14 of step-down voltage regulator chip D19, the ground pin GND_15 of step-down voltage regulator chip D19, the ground pin GND_16 of step-down voltage regulator chip D19, the ground pin GND_17 of step-down voltage regulator chip D19, the ground pin GND_18 of step-down voltage regulator chip D19, the ground pin GND_19 of step-down voltage regulator chip D19, and the ground pin GND_20 of step-down voltage regulator chip D19 are all grounded.
[0038] In summary, due to the adoption of the above technical solution, the combination of a crystal oscillator and a clock driver adopted in the utility model can provide a stable clock signal source, ensure system synchronization, reduce phase noise, and improve signal stability and data transmission accuracy.
[0039] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0041] Figure 1 It is a connection schematic diagram of the utility model.
[0042] Figure 2 It is a partial circuit connection schematic diagram of the utility model.
[0043] Figure 3 It is a partial circuit connection schematic diagram of the utility model.
[0044] Figure 4 This is a schematic diagram of the PCIe, SGMII and SRIO high-speed serial communication interfaces of the SDP chip of the utility model. Figure 4(a) is a schematic diagram of the PCIe interface of the SDP chip. Figure 4 (b) is a schematic diagram of the SRIO interface of the SDP chip. Figure 4 (c) is a schematic diagram of the SDP chip SGMII interface.
[0045] Figure 5 It is a schematic diagram of a power supply circuit of the utility model. DETAILED DESCRIPTION
[0046] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0047] The utility model proposes a crystal oscillator with reduced phase noise, such as Figure 1 As shown, including:
[0048] This application uses a crystal oscillator whose data is connected to a clock driver, which is connected to high-speed serial communication interfaces such as PCIe, SGMII, and SRIO. Using a clock driver between the crystal oscillator and the high-speed serial communication interface can ensure that the clock signal generated by the oscillator can be properly amplified or converted to meet the needs of the system. Especially in high-speed communication equipment or high-performance computing equipment, the quality of the clock signal is critical to system performance, so the use of a clock driver can ensure the stability and reliability of the signal. The model of the clock driver D5 is AU5411A-QMR, which takes into account factors such as frequency support, jitter performance, and output drive capability required by high-speed serial communication interfaces such as PCIe, SGMII, and SRIO. The relevant circuit connections are:
[0049] The circuit connection relationship of the crystal oscillator to reduce phase noise is as follows Figure 2 to Figure 4 As shown:
[0050] The enable terminal CE of the crystal oscillator U12 is connected to the first end of the resistor R212, the second end of the resistor R212 is connected to the power supply VCC3.3V, the power supply terminal VDO of the crystal oscillator U12 is connected to the first end of the chip ferrite bead L12 and the first end of the capacitor C386, the second end of the chip ferrite bead L12 is connected to the power supply VCC3.3V, and the second end of the capacitor C386 is connected to the power ground; the power supply terminal VDO of the crystal oscillator U12 is connected to the chip ferrite bead L12 to convert high-frequency interference into heat energy and dissipate it.
[0051] The clock output terminal CLK of the crystal oscillator U12 is connected to the first end of the capacitor C387, the second end of the capacitor C387 is connected to the first end of the resistor R216 and the CLKINO+ of the clock driver D5, the inverted signal output terminal CLK* (differential clock is used to resist common mode interference during transmission, which can ensure a higher clock data transmission frequency) of the crystal oscillator U12 is connected to the first end of the capacitor C388, and the second end of the capacitor C388 is connected to the second end of the resistor R216 and the CLKINO- of the clock driver D5;
[0052] The control terminal CLKIN_SEL0 of the external clock input source of the crystal oscillator U12 is connected to the first end of the resistor R219.
[0053] The control terminal CLKIN SEL1 of the external clock input source of the crystal oscillator U12 is connected to the first end of the resistor R215, and the second end of the resistor R219 and the second end of the resistor R215 are connected to the power ground; if CLKIN_SEL0 and CLKIN_SEL1 are both set to low level, then CLKIN0 may be selected as the input clock source. If CLKIN_SEL1 is set to high level and CLKIN_SEL0 is low level, then CLKIN1 may be selected as the input clock source. This selection mechanism allows system designers to select the appropriate clock source to drive the circuit according to needs, thereby improving the flexibility of the system.
[0054] The power supply end VCC1 of the crystal oscillator U12 and the power supply end VCC2 of the crystal oscillator U12 are connected to the first end of the chip ferrite bead L13, the first end of the capacitor C353, the first end of the capacitor C355, the first end of the capacitor C357, the first end of the capacitor C359, the first end of the capacitor C361, and the first end of the capacitor C363. The second end of the capacitor C353, the second end of the capacitor C355, the second end of the capacitor C357, the second end of the capacitor C359, the second end of the capacitor C361, and the second end of the capacitor C363 are connected to the power ground. The second end of the chip ferrite bead L13 is connected to the power supply VCC3.3V. The first end of the chip ferrite bead L14 is connected, the second end of the chip ferrite bead L14 is connected to the first end of the capacitor C354, the first end of the capacitor C356, the first end of the capacitor C358, the first end of the capacitor C360, the first end of the capacitor C362, the first end of the capacitor C364, the driver power supply terminal VCCOA1 of the crystal oscillator U12, and the driver power supply terminal VCCOA2 of the crystal oscillator U12, and the second end of the capacitor C354, the second end of the capacitor C356, the second end of the capacitor C358, the second end of the capacitor C360, the second end of the capacitor C362, and the second end of the capacitor C364 are connected to the power ground;
[0055] The driver power supply terminal VCCOB1 of the crystal oscillator U12 and the driver power supply terminal VCCOB2 of the crystal oscillator U12 are connected to the first end of the capacitor C365, the first end of the capacitor C367, the first end of the capacitor C369, the first end of the capacitor C371, the first end of the capacitor C373, the first end of the capacitor C375, and the first end of the chip ferrite bead L15, and the second end of the capacitor C365, the second end of the capacitor C367, the second end of the capacitor C369, the second end of the capacitor C371, the second end of the capacitor C373, and the second end of the capacitor C375 are connected to the power ground;
[0056] The second end of the chip ferrite bead L15 is connected to the power supply VCC3.3V and the first end of the chip ferrite bead L16, the second end of the chip ferrite bead L16 is connected to the internal power supply terminal VCCOC of the crystal oscillator U12, the first end of the capacitor C366, the first end of the capacitor C368, the first end of the capacitor C370, the first end of the capacitor C372, the first end of the capacitor C374, and the first end of the capacitor C376, and is connected to the second end of the capacitor C366, the second end of the capacitor C368, the second end of the capacitor C370, the second end of the capacitor C372, the second end of the capacitor C374, and the second end of the capacitor C376 to the power ground;
[0057] The reference output enable terminal REFOUT EN of the crystal oscillator U12 is connected to the first end of the resistor R214, the setting CLKOUTA group output type terminal CLKOUTA TYPE1 of the crystal oscillator U12 is connected to the first end of the resistor R213, the setting CLKOUTB group output type terminal CLKOUTB TYPE1 of the crystal oscillator U12 is connected to the first end of the resistor R217, and the second end of the resistor R214, the second end of the resistor R213, and the second end of the resistor R217 are connected to the power ground;
[0058] The output type terminal CLKOUTA_TYPE0 of the setting CLKOUTA group of the crystal oscillator U12 and the output type terminal CLKOUTB TYPE0 of the setting CLKOUTB group of the crystal oscillator U12 are connected to the power ground;
[0059] The first clock signal output terminal (CLKOUTA group differential output terminal) CLKOUTA0+ of the crystal oscillator U12 is connected to the first end of the capacitor C389, the first clock signal output terminal CLKOUTA0- of the crystal oscillator U12 is connected to the first end of the capacitor C393, the second clock signal output terminal CLKOUTA1+ of the crystal oscillator U12 is connected to the first end of the capacitor C390, the second clock signal output terminal CLKOUTA1- of the crystal oscillator U12 is connected to the first end of the capacitor C394, and the third clock signal output terminal CLKOUTA2+ of the crystal oscillator U12 is connected to the first end of the capacitor C391. The third clock signal output terminal CLKOUTA2- of the crystal oscillator U12 is connected to the first end of the capacitor C395, the fourth clock signal output terminal CLKOUTA3+ of the crystal oscillator U12 is connected to the first end of the capacitor C392, the fourth clock signal output terminal CLKOUTA3- of the crystal oscillator U12 is connected to the first end of the capacitor C396, and the second end of the capacitor C389, the second end of the capacitor C393, the second end of the capacitor C390, the second end of the capacitor C394, the second end of the capacitor C391, the second end of the capacitor C395, the second end of the capacitor C392, and the second end of the capacitor C396 are all connected to the DSP chip;
[0060] The model of the DSP chip is preferably ft_m6678, and the models of the ferrite beads L12, L13, L14, and L15 are all BLM21PG221SN1D, which are used to suppress high-frequency noise on the power line or signal line; the model of the crystal oscillator U12 is SI534BC002369DG, and the model of the clock driver D5 is AU5411A-QMR.
[0061] The power supply circuit can provide power VCC3.3V, as shown below Figure 5 As shown:
[0062] The voltage output pin VOUT1_0 of the buck regulator chip D19, the voltage output pin VOUT1_1 of the buck regulator chip D19 and the voltage output pin VOUT1_2 of the buck regulator chip D19 output the power supply voltage VCC1.8V and are connected to the first end of the capacitor C514 and the first end of the capacitor C567, the second end of the capacitor C514 and the second end of the capacitor C567 are grounded, the feedback pin FB1 of the buck regulator chip D19 is connected to the first end of the resistor R235, the second end of the resistor R235 is grounded, the voltage tracking and soft start pin TRACK|SS1 of the buck regulator chip D19 is connected to the first end of the capacitor C511, the second end of the capacitor C511 is grounded, the power good indication pin PGOOD1 of the buck regulator chip D19 is connected to the first end of the resistor R231, and the second end of the resistor R231 is connected to the internal power pin INTVCC1 of the buck regulator chip D19;
[0063] The voltage output pin VOUT2_0 of the buck regulator chip D19, the voltage output pin VOUT2_1 of the buck regulator chip D19 and the voltage output pin VOUT2_2 of the buck regulator chip D19 output the power supply voltage VCC1.5V and are connected to the first end of the capacitor C515 and the first end of the capacitor C568, the second end of the capacitor C515 and the second end of the capacitor C568 are grounded, the feedback pin FB2 of the buck regulator chip D19 is connected to the first end of the resistor R236, the second end of the resistor R236 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D19 is connected to the first end of the capacitor C512, the second end of the capacitor C512 is grounded, the power good indication terminal PGOOD2 of the buck regulator chip D19 is connected to the first end of the resistor R232; the first end of the resistor R232 is connected, and the second end of the resistor R232 is connected to the internal power pin INTVCC2 of the buck regulator chip D19;
[0064] The voltage output pin VOUT3_0 of the buck regulator chip D19, the voltage output pin VOUT3_1 of the buck regulator chip D19, and the voltage output pin VOUT3_2 of the buck regulator chip D19 output the power supply voltage VCC1.05V and are connected to the first end of the capacitor C516 and the first end of the capacitor C569, the second end of the capacitor C516 and the second end of the capacitor C569 are grounded, the feedback pin FB3 of the buck regulator chip D19 is connected to the first end of the resistor R237, the second end of the resistor R237 is grounded, the voltage tracking and soft start pin TRACK|SS3 of the buck regulator chip D19 is connected to the first end of the capacitor C513, the second end of the capacitor C513 is grounded, the power good indication terminal PGOOD3 of the buck regulator chip D19 is connected to the first end of the resistor R233, and the second end of the resistor R233 is connected to the internal power pin INTVCC3 of the buck regulator chip D19;
[0065] The voltage output pin VOUT4_0 of the buck regulator chip D19, the voltage output pin VOUT4_1 of the buck regulator chip D19 and the voltage output pin VOUT4_2 of the buck regulator chip D19 output the power supply voltage VCC3.3V and are connected to the first end of the capacitor C301 and the first end of the capacitor C302, the second end of the capacitor C301 and the second end of the capacitor C302 are grounded, the feedback pin FB4 of the buck regulator chip D19 is connected to the first end of the resistor R138, the second end of the resistor R138 is grounded, the voltage tracking and soft start pin TRACK|SS4 of the buck regulator chip D19 is connected to the first end of the capacitor C300, the second end of the capacitor C300 is grounded, the power good indication terminal PGOOD4 of the buck regulator chip D19 is connected to the first end of the resistor R137; the first end of the resistor R137 is connected, and the second end of the resistor R137 is connected to the internal power pin INTVCC4 of the buck regulator chip D19;
[0066] The voltage input pin VIN1_0 of the buck regulator chip D19, the voltage input pin VIN1_1 of the buck regulator chip D19, and the voltage input pin SVIN1 of the buck regulator chip D19 are connected to the power supply voltage VCC12V and the first end of the capacitor C507, the second end of the capacitor C507 is grounded, and the power good indication terminal PGOOD3 of the buck regulator chip D19 is connected to the enable terminal RUN1 of the buck regulator chip D19;
[0067] The voltage input pin VIN2_0 of the buck regulator chip D19, the voltage input pin VIN2_1 of the buck regulator chip D19, and the voltage input pin SVIN2 of the buck regulator chip D19 are connected to the power supply voltage VCC12V and the first end of the capacitor C508, and the second end of the capacitor C508 is grounded; the power good indication terminal PGOOD1 of the buck regulator chip D19 is connected to the enable terminal RUN2 of the buck regulator chip D19;
[0068] The voltage input pin VIN3_0 of the buck regulator chip D19, the voltage input pin VIN3_1 of the buck regulator chip D19, and the voltage input pin SVIN3 of the buck regulator chip D19 are connected to the power supply voltage VCC12V and the first end of the capacitor C509, and the second end of the capacitor C509 is grounded;
[0069] The voltage input pin VIN4_0 of the buck regulator chip D19, the voltage input pin VIN4_1 of the buck regulator chip D19, the voltage input pin SVIN4 of the buck regulator chip D19, and the enable pin RUN4 of the buck regulator chip D19 are connected to the power supply voltage VCC12V and the first end of the capacitor C510, and the second end of the capacitor C510 is grounded; the power good indication terminal PGOOD2 of the buck regulator chip D19 is connected to the enable terminal RUN4 of the buck regulator chip D19;
[0070] The internal power pin INTVCC1 of the buck regulator chip D19 is connected to the working mode configuration pin MODE1 of the buck regulator chip D19, and the internal power pin INTVCC2 of the buck regulator chip D19 is connected to the working mode configuration pin MODE2 of the buck regulator chip D19; the internal power pin INTVCC3 of the buck regulator chip D19 is connected to the working mode configuration pin MODE3 of the buck regulator chip D19, and the internal power pin INTVCC4 of the buck regulator chip D19 is connected to the working mode configuration pin MODE4 of the buck regulator chip D19;
[0071] The ground pin SGND of the buck regulator chip D19, the ground pin GND_0 of the buck regulator chip D19, the ground pin GND_1 of the buck regulator chip D19, the ground pin GND_2 of the buck regulator chip D19, the ground pin GND_3 of the buck regulator chip D19, the ground pin GND_4 of the buck regulator chip D19, the ground pin GND_5 of the buck regulator chip D19, the ground pin GND_6 of the buck regulator chip D19, the ground pin GND_7 of the buck regulator chip D19, the ground pin GND_8 of the buck regulator chip D19, the ground pin GND_9 of the buck regulator chip D The ground pin GND_10 of step-down voltage regulator chip D19, the ground pin GND_11 of step-down voltage regulator chip D19, the ground pin GND_12 of step-down voltage regulator chip D19, the ground pin GND_13 of step-down voltage regulator chip D19, the ground pin GND_14 of step-down voltage regulator chip D19, the ground pin GND_15 of step-down voltage regulator chip D19, the ground pin GND_16 of step-down voltage regulator chip D19, the ground pin GND_17 of step-down voltage regulator chip D19, the ground pin GND_18 of step-down voltage regulator chip D19, the ground pin GND_19 of step-down voltage regulator chip D19, and the ground pin GND_20 of step-down voltage regulator chip D19 are all grounded.
[0072] The model of the buck regulator chip D19 is LTM4644EY#PBF.
[0073] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.
Claims
1. A DSP synchronous clock oscillator, characterized in that: include: A DSP chip, a crystal oscillator and a clock driver, wherein a clock signal transmitting end of the crystal oscillator is connected to a clock signal receiving end of the clock driver, and a clock signal transmitting end of the clock driver is connected to a high-speed serial communication interface of the DSP chip; The clock signal generated by the crystal oscillator is transmitted to the clock driver through wires or PCB. The clock driver receives the clock signal from the crystal oscillator and amplifies or buffers the signal as needed.
2. A DSP synchronous clock oscillator according to claim 1, characterized in that: The high-speed serial communication interface of the DSP chip includes PCIe, SGMII, and SRIO.
3. A DSP synchronous clock oscillator according to claim 1, characterized in that: The connection relationship between the DSP chip, the crystal oscillator and the clock driver includes: The enable terminal CE of the crystal oscillator U12 is connected to the first end of the resistor R212, the second end of the resistor R212 is connected to the power supply VCC3.3V, the power supply terminal VDO of the crystal oscillator U12 is connected to the first end of the chip ferrite bead L12 and the first end of the capacitor C386, the second end of the chip ferrite bead L12 is connected to the power supply VCC3.3V, and the second end of the capacitor C386 is connected to the power ground; The clock output terminal CLK of the crystal oscillator U12 is connected to the first end of the capacitor C387, the second end of the capacitor C387 is connected to the first end of the resistor R216 and the CLKINO+ of the clock driver D5, the inverted signal output terminal CLK* of the crystal oscillator U12 is connected to the first end of the capacitor C388, the second end of the capacitor C388 is connected to the second end of the resistor R216 and the CLKINO- of the clock driver D5; The control terminal CLKIN_SEL0 of the external clock input source of the crystal oscillator U12 is connected to the first end of the resistor R219. The control terminal CLKIN SEL1 of the external clock input source of the crystal oscillator U12 is connected to the first end of the resistor R215, and the second end of the resistor R219 and the second end of the resistor R215 are connected to the power ground; The power supply terminal VCC1 of the crystal oscillator U12, the power supply terminal VCC2 of the crystal oscillator U12, the driver power supply terminal VCCOA1 of the crystal oscillator U12, the driver power supply terminal VCCOA2 of the crystal oscillator U12, the driver power supply terminal VCCOB1 of the crystal oscillator U12, the driver power supply terminal VCCOB2 of the crystal oscillator U12, and the internal power supply terminal VCCOC of the crystal oscillator U12 are all connected to the power supply VCC3.3V; The reference output enable terminal REFOUT EN of the crystal oscillator U12 is connected to the first end of the resistor R214, the setting CLKOUTA group output type terminal CLKOUTA TYPE1 of the crystal oscillator U12 is connected to the first end of the resistor R213, the setting CLKOUTB group output type terminal CLKOUTB TYPE1 of the crystal oscillator U12 is connected to the first end of the resistor R217, and the second end of the resistor R214, the second end of the resistor R213, and the second end of the resistor R217 are connected to the power ground; The output type terminal CLKOUTA_TYPE0 of the setting CLKOUTA group of the crystal oscillator U12 and the output type terminal CLKOUTB TYPE0 of the setting CLKOUTB group of the crystal oscillator U12 are connected to the power ground; The first clock signal output terminal CLKOUTA0+ of the crystal oscillator U12 is connected to the first end of the capacitor C389, the first clock signal output terminal CLKOUTA0- of the crystal oscillator U12 is connected to the first end of the capacitor C393, the second clock signal output terminal CLKOUTA1+ of the crystal oscillator U12 is connected to the first end of the capacitor C390, the second clock signal output terminal CLKOUTA1- of the crystal oscillator U12 is connected to the first end of the capacitor C394, the third clock signal output terminal CLKOUTA2+ of the crystal oscillator U12 is connected to the first end of the capacitor C391, and the crystal oscillator U1 2 is connected to the first end of capacitor C395, the fourth clock signal output terminal CLKOUTA3+ of the crystal oscillator U12 is connected to the first end of capacitor C392, the fourth clock signal output terminal CLKOUTA3- of the crystal oscillator U12 is connected to the first end of capacitor C396, the second end of capacitor C389, the second end of capacitor C393, the second end of capacitor C390, the second end of capacitor C394, the second end of capacitor C391, the second end of capacitor C395, the second end of capacitor C392, and the second end of capacitor C396 are all connected to the DSP chip.
4. A DSP synchronous clock oscillator according to claim 3, characterized in that: The power supply terminal VCC1 of the crystal oscillator U12, the power supply terminal VCC2 of the crystal oscillator U12, the driver power supply terminal VCCOA1 of the crystal oscillator U12, the driver power supply terminal VCCOA2 of the crystal oscillator U12, the driver power supply terminal VCCOB1 of the crystal oscillator U12, the driver power supply terminal VCCOB2 of the crystal oscillator U12, and the internal power supply terminal VCCOC of the crystal oscillator U12 are all connected to the power supply VCC3.3V; Alternatively, the power supply terminal VCC1 of the crystal oscillator U12 and the power supply terminal VCC2 of the crystal oscillator U12 are connected to the first end of the chip ferrite bead L13, the first end of the capacitor C353, the first end of the capacitor C355, the first end of the capacitor C357, the first end of the capacitor C359, the first end of the capacitor C361, and the first end of the capacitor C363, the second end of the capacitor C353, the second end of the capacitor C355, the second end of the capacitor C357, the second end of the capacitor C359, the second end of the capacitor C361, and the second end of the capacitor C363 are connected to the power ground, and the second end of the chip ferrite bead L13 is connected to the power supply VCC3.3V. The first end of the chip ferrite bead L14 is connected to the first end of the chip ferrite bead L14, the second end of the chip ferrite bead L14 is connected to the first end of the capacitor C354, the first end of the capacitor C356, the first end of the capacitor C358, the first end of the capacitor C360, the first end of the capacitor C362, the first end of the capacitor C364, the driver power supply terminal VCCOA1 of the crystal oscillator U12, and the driver power supply terminal VCCOA2 of the crystal oscillator U12, and the second end of the capacitor C354, the second end of the capacitor C356, the second end of the capacitor C358, the second end of the capacitor C360, the second end of the capacitor C362, and the second end of the capacitor C364 are connected to the power ground; The driver power supply terminal VCCOB1 of the crystal oscillator U12 and the driver power supply terminal VCCOB2 of the crystal oscillator U12 are connected to the first end of the capacitor C365, the first end of the capacitor C367, the first end of the capacitor C369, the first end of the capacitor C371, the first end of the capacitor C373, the first end of the capacitor C375, and the first end of the chip ferrite bead L15, and the second end of the capacitor C365, the second end of the capacitor C367, the second end of the capacitor C369, the second end of the capacitor C371, the second end of the capacitor C373, and the second end of the capacitor C375 are connected to the power ground; The second end of the chip ferrite bead L15 is connected to the power supply VCC3.3V and the first end of the chip ferrite bead L16. The second end of the chip ferrite bead L16 is connected to the internal power supply terminal VCCOC of the crystal oscillator U12, the first end of capacitor C366, the first end of capacitor C368, the first end of capacitor C370, the first end of capacitor C372, the first end of capacitor C374, and the first end of capacitor C376, and is connected to the second end of capacitor C366, the second end of capacitor C368, the second end of capacitor C370, the second end of capacitor C372, the second end of capacitor C374, and the second end of capacitor C376 to the power ground.
5. A DSP synchronous clock oscillator according to claim 3, characterized in that: The model of crystal oscillator U12 is S1534BC002369DG.
6. A DSP synchronous clock oscillator according to claim 3, characterized in that: The model of clock driver D5 is AU541 1A-QMR.
7. A DSP synchronous clock oscillator according to claim 3 or 4, characterized in that: The models of ferrite beads L12, L13, L14, and L15 are all BLM21PG221SN1D.