LED time-sharing circuit based on single control signal port

Abstract

The utility model provides an LED time-sharing circuit based on a single control signal port, and the circuit comprises a control signal end which receives a control signal of which the logic level alternately changes between a first logic level and a second logic level in a normal working mode; the first voltage output module comprises a control end, a power supply input end VCC and a first voltage output end HVIO1; the second voltage output module comprises a control end, a power supply input end VCC, a second voltage output end HVIO2 and a second power supply end; and the first output end of the logic control assembly is connected with the control end of the second voltage output module, and the second output end of the logic control assembly is connected with the second power supply end of the second voltage output module, so that a controllable path from the second power supply end of the second voltage output module to the grounding end is provided. Compared with the prior art, the time-sharing output of the power supply can be controlled through a single control signal port, so that the number of driving RGB is doubled, and the problem of large quiescent current in a sleep mode can be solved.

Description

[Technical field]

[0001] The utility model relates to the technical field of LED dimming, in particular to an LED time-sharing circuit based on a single control signal port. [Background technology]

[0002] With the continuous development of vehicle interior lighting, the number of RGB (Red Green Blue, i.e. multi-color LED) is also gradually increasing, which means that more constant current sources are needed, which increases the cost of the solution.

[0003] To solve this problem, a time-sharing circuit is added to double the number of RGBs driven by the LED Driver.

[0004] 1) Most of the existing technical solutions for time-sharing applications are integrated inside the LED Driver. Such LED Drivers have a large number of internal constant current sources and are costly. If the number of RGB is small, the price of such drivers is not cost-effective.

[0005] 2) The existing external time-sharing solution has requirements for the GPIO and VIN input voltages. The difference between the two needs to be less than the conduction voltage drop of the transistor Vbe. For some vehicle manufacturers, the existing solution has a major problem, which is that it cannot solve the problem of high static current in sleep mode. Please refer to Figure 1 As shown, it is a circuit diagram of an existing LED time-sharing circuit, which adopts an external time-sharing scheme. In the sleep mode, no matter what the state of the GPIO port is, there will be a loop input to the ground, such as Figure 1 As shown, the current will pass through the BE diode of the PNP transistor Q1, and then through the resistor R5, the diode D2 and the resistor R1 to the ground.

[0006] Therefore, it is necessary to propose a new technical solution to solve the above problems. [Contents of the utility model]

[0007] One of the purposes of the utility model is to provide an LED time-sharing circuit based on a single control signal port, which can not only control the power time-sharing output through a single control signal port, thereby doubling the number of driven RGB, but also solve the problem of large static current in sleep mode.

[0008] According to one aspect of the utility model, the utility model provides an LED time-sharing circuit based on a single control signal port, which includes: a control signal terminal, which receives a control signal whose logic level alternates between a first logic level and a second logic level in a normal working mode; a first voltage output module, which includes a control terminal, a power input terminal VCC and a first voltage output terminal HVIO1, when its control terminal is at a first logic level, the first voltage output module connects the power input terminal VCC and the first voltage output terminal HVIO1, when its control terminal is at a second logic level or a high impedance state, the first voltage output module disconnects the connection between the power input terminal VCC and the first voltage output terminal HVIO1, and the control terminal of the first voltage output module is connected to the control signal terminal; a second voltage output module, which includes a control terminal, a power input terminal VCC, a second voltage output terminal HVIO2 and a second power terminal; a logic control component, whose first output terminal is connected to the The control end of the second voltage output module is connected, and the second output end is connected to the second power supply end of the second voltage output module to provide a controllable path from the second power supply end of the second voltage output module to the ground end. In the normal working mode, when the control signal received at the control signal end is a first logic level, the control end of the second voltage output module is in a high impedance state, and the path from the second power supply end of the second voltage output module to the ground end is cut off. At this time, the second voltage output module disconnects the connection between the power input end VCC and the second voltage output end HVIO2; when the control signal received at the control signal end is a second logic level, the logic control module outputs the first logic level to the control end of the second voltage output module, and the path from the second power supply end of the second voltage output module to the ground end is turned on. At this time, the second voltage output module turns on the connection between the power input end VCC and the second voltage output end HVIO2.

[0009] Furthermore, in the sleep mode, the control signal terminal is configured to be in a high-impedance state, and the logic control component makes the control terminal of the second voltage output module in a high-impedance state, and at the same time cuts off the path from the second power supply terminal to the ground terminal of the second voltage output module, so that the second voltage output module disconnects the connection between the power input terminal VCC and the second voltage output terminal HVIO2; in the sleep mode, the control signal terminal is configured to be in a high-impedance state, so that the first voltage output module disconnects the connection between the power input terminal VCC and the first voltage output terminal HVIO1.

[0010] Further, the first voltage output module includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS tube Q1 and a transistor Q2; the second voltage output module includes a resistor R16, a resistor R17, a resistor R18, a resistor R19, a MOS tube Q10 and a transistor Q11; the logic control component includes a first logic control module, a second logic control module and a third logic control module, the first logic control module includes a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a MOS tube Q4 and a transistor Q3; the second logic control module includes a resistor R10, a resistor R11, a resistor R12, a MOS tube Q 5 and transistor Q6; the third logic control module includes resistor R13, resistor R14, resistor R15, resistor R20, resistor R21, resistor R22, resistor R23, transistor Q7, transistor Q8, transistor Q9 and transistor Q12; the first connection end of the MOS tube Q1 is connected to the power input end VCC, the second connection end thereof is connected to the first voltage output end HVIO1, and the control end thereof is connected to the first connection end of the transistor Q2 via the resistor R2; the control end of the transistor Q2 is connected to the control end of the first voltage output module via the resistor R3, and the second connection end thereof is grounded; one end of the resistor R1 is connected to the The first connection end of the MOS tube Q1 is connected to the first connection end of the MOS tube Q1, and the other end thereof is connected to the control end of the MOS tube Q1; one end of the resistor R4 is connected to the control end of the transistor Q2, and the other end thereof is connected to the second connection end of the transistor Q2; the first connection end of the MOS tube Q10 is connected to the power input end VCC, the second connection end thereof is connected to the second voltage output end HVIO2, and the control end thereof is connected to the first connection end of the transistor Q11 via the resistor R17; the control end of the transistor Q11 is connected to the control end of the second voltage output module via the resistor R18, and the second connection end thereof is connected to the second power input end of the second voltage output module end is connected; one end of the resistor R16 is connected to the first connection end of the MOS tube Q10, and the other end thereof is connected to the control end of the MOS tube Q10; one end of the resistor R19 is connected to the control end of the triode Q11, and the other end thereof is connected to the second connection end of the triode Q11; the first connection end of the triode Q3 is connected to the first connection end of the triode Q2, and the second connection end thereof is connected to one end of the resistor R9, and the control end thereof is connected to the first connection end of the MOS tube Q4 via the resistor R6; the control end of the MOS tube Q4 is connected to the control signal end via the resistor R7, and the second connection end thereof is grounded via the resistor R8;One end of the resistor R5 is connected to the first connection end of the transistor Q3, and the other end thereof is connected to the control end of the transistor Q3. The first connection end of the MOS transistor Q5 is connected to the power input end VCC via the resistor R10, and the control end thereof is connected to the other end of the resistor R9, and the second connection end thereof is grounded via the resistor R11. The first connection end of the transistor Q6 is connected to the power input end VCC, and the second connection end thereof is connected to the first output end of the logic control component. One end of the resistor R12 is connected to the second connection end of the MOS transistor Q5, the first connection end of the transistor Q8 is connected to the power input end VCC, and the control end thereof is connected to the other end of the resistor R12, and the second connection end thereof is connected to the ground via the resistor R20. The first connection end of the transistor Q9 is connected; the control end of the transistor Q9 is connected to the control end of the transistor Q6 through the resistor R13, and its second connection end is grounded through the resistors R22 and R23 in sequence; the first connection end of the transistor Q7 is connected to the control end of the transistor Q9, its control end is connected to the control signal end through the resistor R14, and its second connection end is grounded; one end of the resistor R15 is connected to the control end of the transistor Q7, and the other end is connected to the second connection end of the transistor Q7; the first connection end of the transistor Q12 is connected to the second output end of the logic control component through the resistor R21, its control end is connected to the connection node between the resistor R22 and the resistor R23, and its second connection end is grounded. ;

[0011] Further, in the normal working mode, when the control signal received by the control signal end is the first logic level, the MOS tube Q1 is turned on, the transistor Q2 is turned on, the transistor Q3 is turned off, the MOS tube Q4 is turned off, the MOS tube Q5 is turned off, the transistor Q6 is turned off, the transistor Q7 is turned on, the transistor Q8 is turned off, the transistor Q9 is turned off, the MOS tube Q10 is turned off, the transistor Q11 is turned off, and the transistor Q12 is turned off. At this time, the voltage of the power input terminal VCC is provided to the first voltage output terminal HVIO1 through the MOS tube Q1; in the normal working mode, when the control signal received by the control signal end is the second logic level, so The MOS tube Q1 is turned off, the transistor Q2 is turned off, the transistor Q3 is turned on, the MOS tube Q4 is turned on, the MOS tube Q5 is turned on, the transistor Q7 is turned off, the VBE diode of the transistor Q8 is turned on, the VBE diode of the transistor Q9 is turned on, the VBE diode of the transistor Q6 is turned on, the MOS tube Q10 is turned on, the transistor Q11 is turned on, and the transistor Q12 is turned on. At this time, the voltage of the power input terminal VCC is provided to the second voltage output terminal HVIO2 via the MOS tube Q10; when in the dormant state, the control signal terminal is set to a high impedance state. At this time, the transistor Q2 is turned off, the transistor Q7 is turned off, and the MOS tube Q4 is turned off.

[0012] Further, the MOS transistor Q1 is a PMOS transistor, and the first connection end, the second connection end and the control end of the MOS transistor Q1 are respectively the source, the drain and the gate of the PMOS transistor; the transistor Q2 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q2 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q3 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q3 are respectively the emitter, the collector and the base of the PNP transistor. The MOS tube Q4 is a PMOS tube, and the first connection end, the second connection end and the control end of the MOS tube Q4 are the source, the drain and the gate of the PMOS tube respectively; the MOS tube Q5 is an NMOS tube, and the first connection end, the second connection end and the control end of the MOS tube Q5 are the drain, the source and the gate of the NMOS tube respectively; the transistor Q6 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q6 are the collector, the emitter and the base of the NPN transistor respectively; the transistor Q6 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q6 are the collector, the emitter and the base of the NPN transistor respectively; The transistor Q7 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q7 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q8 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q8 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q9 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q9 are respectively the emitter, the collector and the base of the PNP transistor; The OS transistor Q10 is a PMOS transistor, and the first connection end, the second connection end and the control end of the MOS transistor Q10 are respectively the source, the drain and the gate of the PMOS transistor; the transistor Q11 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q11 are respectively the emitter, the collector and the base of the PNP transistor; the transistor Q12 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q12 are respectively the collector, the emitter and the base of the NPN transistor.

[0013] Furthermore, the LED is two multi-color LEDs, namely a first multi-color LED and a second multi-color LED, the anode of the first multi-color LED is connected to the first voltage output terminal HVIO1, and the cathode thereof is connected to the constant current source module; the anode of the second multi-color LED is connected to the second voltage output terminal HVIO2, and the cathode thereof is connected to the constant current source module.

[0014] Compared with the prior art, the utility model can not only control the time-sharing output of power through a single control signal port, thereby doubling the number of driven RGB, but also solve the problem of large static current in sleep mode.

Brief Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0016] Figure 1 It is a circuit diagram of an LED time-sharing circuit in the prior art;

[0017] Figure 2 This is a circuit diagram of an LED time-sharing circuit based on a single control signal port in one embodiment of the utility model;

[0018] Figure 3 FIG. 4 is a circuit diagram of an LED driving system in one embodiment of the present invention. [Specific implementation method]

[0019] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0020] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the utility model. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words "coupled", "connected", "connected" and "connected" in this document that indicate electrical connection all mean direct or indirect connection. For example, A is connected to B, which includes both direct electrical connection between A and B and connection between A and B through electrical components or circuits.

[0021] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0022] Please refer to Figure 2 As shown, it is a circuit diagram of an LED time-sharing circuit based on a single control signal port in one embodiment of the utility model. Figure 2The LED time-sharing circuit based on a single control signal port shown includes a control signal terminal gpio, a first voltage output module 210, a second voltage output module 220 and a logic control component (not labeled). The logic control component (not labeled) includes a first logic control module 232, a second logic control module 234 and a third logic control module 236.

[0023] Wherein, when the control signal terminal gpio is in normal working mode, it receives a control signal whose logic level alternates between a first logic level and a second logic level; the first voltage output module 210 includes a control terminal A, a power input terminal VCC and a first voltage output terminal HVIO1. When its control terminal A is at a first logic level, the first voltage output module 210 connects the power input terminal VCC and the first voltage output terminal HVIO1. When its control terminal A is at a second logic level or a high impedance state, the first voltage output module 210 disconnects the connection between the power input terminal VCC and the first voltage output terminal HVIO1. Wherein, the control terminal A of the first voltage output module 210 is connected to the control signal terminal gpio; the second voltage output module 220 includes a control terminal B, a power input terminal VCC, a second voltage output terminal HVIO2 and a second power terminal C; the first output terminal of the logic control component is connected to the control terminal B of the second voltage output module 220, and its second output The end is connected to the second power supply terminal C of the second voltage output module 220 to provide a controllable path to the ground terminal for the second power supply terminal C of the second voltage output module 220. In the normal working mode, when the control signal received by the control signal terminal gpio is the first logic level, the control terminal B of the second voltage output module 220 is in a high impedance state, and the path from the second power supply terminal C of the second voltage output module 220 to the ground terminal is cut off. At this time, the second voltage output module 220 disconnects the connection between the power input terminal VCC and the second voltage output terminal HVIO2; when the control signal received by the control signal terminal gpio is the second logic level, the logic control module outputs the first logic level to the control terminal B of the second voltage output module 220, and the path from the second power supply terminal C of the second voltage output module 220 to the ground terminal is turned on. At this time, the second voltage output module 220 turns on the connection between the power input terminal VCC and the second voltage output terminal HVIO2.

[0024] In sleep mode, the control signal terminal gpio is configured to a high impedance state, and the logic control component makes the control terminal B of the second voltage output module 220 a high impedance state, and at the same time cuts off the path from the second power supply terminal C of the second voltage output module 220 to the ground terminal, so that the second voltage output module 220 disconnects the connection between the power input terminal VCC and the second voltage output terminal HVIO2; in sleep mode, the control signal terminal gpio is configured to a high impedance state, so that the first voltage output module 210 disconnects the connection between the power input terminal VCC and the first voltage output terminal HVIO1.

[0025] exist Figure 2 In the specific embodiment shown, the first voltage output module 210 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS transistor Q1 and a transistor Q2; the second voltage output module 220 includes a resistor R16, a resistor R17, a resistor R18, a resistor R19, a MOS transistor Q10 and a transistor Q11; the first logic control module 232 includes a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a MOS transistor Q4 and a transistor Q3; the second logic control module 234 includes a resistor R10, a resistor R11, a resistor R12, a MOS transistor Q5 and a transistor Q6; the third logic control module 236 includes a resistor R13, a resistor R14, a resistor R15, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a transistor Q7, a transistor Q8, a transistor Q9 and a transistor Q12.

[0026] Among them, the first connection end of the MOS transistor Q1 is connected to the power input end VCC, the second connection end thereof is connected to the first voltage output end HVIO1, and the control end thereof is connected to the first connection end of the transistor Q2 via the resistor R2; the control end of the transistor Q2 is connected to the control end A of the first voltage output module 210 via the resistor R3, and the second connection end thereof is grounded; one end of the resistor R1 is connected to the first connection end of the MOS transistor Q1, and the other end thereof is connected to the control end of the MOS transistor Q1; one end of the resistor R4 is connected to the control end of the transistor Q2, and the other end thereof is connected to the second connection end of the transistor Q2.

[0027] The first connection end of the MOS transistor Q10 is connected to the power input end VCC, the second connection end thereof is connected to the second voltage output end HVIO2, and the control end thereof is connected to the first connection end of the transistor Q11 via the resistor R17; the control end of the transistor Q11 is connected to the control end B of the second voltage output module 220 via the resistor R18, and the second connection end thereof is connected to the second power supply end C of the second voltage output module 220; one end of the resistor R16 is connected to the first connection end of the MOS transistor Q10, and the other end thereof is connected to the control end of the MOS transistor Q10; one end of the resistor R19 is connected to the control end of the transistor Q11, and the other end thereof is connected to the second connection end of the transistor Q11.

[0028] The first connection end of the transistor Q3 is connected to the first connection end of the transistor Q2, the second connection end thereof is connected to one end of the resistor R9, and the control end thereof is connected to the first connection end of the MOS transistor Q4 via the resistor R6; the control end of the MOS transistor Q4 is connected to the control signal end gpio via the resistor R7, and the second connection end thereof is grounded via the resistor R8; one end of the resistor R5 is connected to the first connection end of the transistor Q3, and the other end thereof is connected to the control end of the transistor Q3.

[0029] The first connection end of the MOS tube Q5 is connected to the power input terminal VCC via the resistor R10, the control end thereof is connected to the other end of the resistor R9, and the second connection end thereof is grounded via the resistor R11; the first connection end of the transistor Q6 is connected to the power input terminal VCC, and the second connection end thereof is connected to the first output end of the logic control component (or the control end B of the second voltage output module 220); one end of the resistor R12 is connected to the second connection end of the MOS tube Q5.

[0030] The first connection end of the transistor Q8 is connected to the power input terminal VCC, the control end thereof is connected to the other end of the resistor R12, and the second connection end thereof is connected to the first connection end of the transistor Q9 via the resistor R20; the control end of the transistor Q9 is connected to the control end of the transistor Q6 via the resistor R13, and the second connection end thereof is grounded via the resistors R22 and R23 in sequence; the first connection end of the transistor Q7 is connected to the control end of the transistor Q9, the control end thereof is connected to the control signal terminal gpio via the resistor R14, and the second connection end thereof is grounded; one end of the resistor R15 is connected to the control end of the transistor Q7, and the other end thereof is connected to the second connection end of the transistor Q7; the first connection end of the transistor Q12 is connected to the second output end of the logic control component (or the second power supply end C of the second voltage output module 220) via the resistor R21, the control end thereof is connected to the connection node between the resistors R22 and R23, and the second connection end thereof is grounded.

[0031] exist Figure 2In the specific embodiment shown, the control signal terminal gpio is an I / O port; the MOS tube Q1 is a PMOS tube, and the first connection terminal, the second connection terminal and the control terminal of the MOS tube Q1 are respectively the source, the drain and the gate of the PMOS tube; the transistor Q2 is an NPN transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q2 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q3 is a PNP transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q3 are respectively the emitter, the collector and the base of the PNP transistor; the MOS tube Q4 is a PMOS tube, and the first connection terminal, the second connection terminal and the control terminal of the MOS tube Q4 are respectively the source, the drain and the gate of the PMOS tube; the MOS tube Q5 is an NMOS tube, and the MOS The first connection end, the second connection end and the control end of the transistor Q5 are respectively the drain, the source and the gate of the NMOS transistor; the transistor Q6 is an NPN transistor, the first connection end, the second connection end and the control end of the transistor Q6 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q7 is an NPN transistor, the first connection end, the second connection end and the control end of the transistor Q7 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q8 is an NPN transistor, the first connection end, the second connection end and the control end of the transistor Q8 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q9 is a PNP transistor, the first connection end, the second connection end and the control end of the transistor Q9 are respectively the emitter, the collector and the base of the PNP transistor;

[0032] The MOS transistor Q10 is a PMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the MOS transistor Q10 are respectively the source, the drain and the gate of the PMOS transistor; the transistor Q11 is a PNP transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q11 are respectively the emitter, the collector and the base of the PNP transistor; the transistor Q12 is an NPN transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q12 are respectively the collector, the emitter and the base of the NPN transistor.

[0033] The following is a detailed introduction Figure 2 The working principle of the LED time-sharing circuit based on a single control signal port is shown.

[0034] In normal working mode, when the control signal received by the control signal terminal gpio is at a high level (which can be called the first logic level of the control signal), the control signal terminal gpio is at a high level. At this time, the Vbe of the NPN transistor Q2 is greater than its conduction voltage, and the NPN transistor Q2 is turned on, thereby pulling down the voltage of the emitter of the NPN transistor Q2. The power input terminal VCC flows to the ground terminal GND through the voltage division of the resistors R1 and R2 through the NPN transistor Q2; obviously, the Vgs of the PMOS tube Q1 at this time meets its conduction condition, and the power input terminal VCC reaches the first voltage output terminal HVIO1 through the PMOS tube Q1 to supply power to the next stage. Since the emitter voltage of the NPN transistor Q2 is pulled down, the PNP transistor Q3 cannot be turned on (that is, the PNP transistor Q3 is turned off), resulting in the NMOS tube Q5 also being unable to be turned on (that is, the NMOS tube Q5 is turned off). Since the base level of NPN transistor Q8 is also low, NPN transistor Q8 cannot be turned on, and the power input terminal VCC cannot reach the emitter of PNP transistor Q9 through NPN transistor Q8, so PNP transistor Q9 is also cut off (or turned off), and similarly, NPN transistor Q12 is also cut off (or turned off). When the control signal terminal gpio is high, PMOS tube Q4 is turned off. When the control signal terminal gpio is at a high level, the NPN transistor Q7 reaches the conduction condition, causing the base level of the NPN transistor Q6 to be in a low state, so that the NPN transistor Q6 is cut off (or turned off), so that the control terminal B of the second voltage output module 220 is in a high impedance state, that is, the PNP transistor Q11 is also cut off (or turned off), therefore, the Vgs of the PMOS tube Q10 cannot meet its conduction condition, the PMOS tube Q10 is turned off, and the power input terminal VCC cannot reach the second voltage output terminal HVIO2 through the PMOS tube Q10 to supply power to the subsequent stage.

[0035] In the normal working mode, when the control signal received by the control signal terminal gpio is at a low level (which can be called the second logic level of the control signal), the control signal terminal gpio is at a low level. At this time, the NPN transistor Q2 and the PMOS transistor Q1 are both in the cut-off (or off) state. At this time, the power input terminal VCC cannot reach the first voltage output terminal HVIO1 through the PMOS transistor Q1 to supply power to the subsequent stage; the power input terminal VCC reaches the source of the PMOS transistor Q4 through the resistors R1, R2, R5 and R6. Since the control signal terminal gpio is at a low level, the Vgs of the PMOS transistor Q4 meets the conduction condition, so the PMOS transistor Q4 is turned on; after the PMOS transistor Q4 is turned on, the PNP transistor Q3 also meets the conduction condition, and the power input terminal VCC reaches the G pole (i.e., the gate) of the NMOS transistor Q5 through the PNP transistor Q3. The Vgs of the NMOS transistor Q5 is greater than Vgsth. After the NMOS transistor Q5 is turned on, the base voltage of the NPN transistor Q8 The voltage is high, and reaches the emitter of the PNP transistor Q9 through the Vbe diode of the NPN transistor Q8, and then reaches the base of the NPN transistor Q6 through the Vbe diode of the PNP transistor Q9, and then reaches the base of the PNP transistor Q11 through the Vbe diode of the NPN transistor Q6, that is, the power input terminal VCC reaches the base of the PNP transistor Q11 after a series of voltage drops (at this time, the control terminal B of the second voltage output module 220 is high ( Or called the first logic level), and the power input terminal VCC directly reaches the emitter of the PNP transistor Q11 through the resistors R16 and R17. At this time, the Vbe of the PNP transistor Q11 meets the conduction condition, the PNP transistor Q11 is turned on, and finally flows to the ground terminal GND through the NPN transistor Q12. At this time, the PMOS tube Q10 is turned on, and the power input terminal VCC reaches the second voltage output terminal HVIO2 through the PMOS tube Q10 to supply power to the subsequent stage.

[0036] In sleep mode, the control signal terminal gpio is configured to a high impedance state. At this time, the NPN transistor Q2, the NPN transistor Q7 and the PMOS transistor Q4 are all in a cut-off (or shut-off) state, and the power input terminal VCC cannot return to the ground terminal GND through the PNP transistor Q3, the NMOS transistor Q5 and the PNP transistor Q11, so that the static current is less than 100uA, solving the problem of excessive static current.

[0037] It can also be said that in the normal working mode, when the control signal received by the control signal terminal gpio is at a high level (which can be called the first logic level of the control signal), the MOS tube Q1 is turned on, the transistor Q2 is turned on, the transistor Q3 is turned off, the MOS tube Q4 is turned off, the MOS tube Q5 is turned off, the transistor Q6 is turned off, the transistor Q7 is turned on, the transistor Q8 is turned off, the transistor Q9 is turned off, the MOS tube Q10 is turned off, the transistor Q11 is turned off, and the transistor Q12 is turned off. At this time, the voltage of the power input terminal VCC is provided to the first voltage output terminal HVIO1 through the MOS tube Q1; in the normal working mode, when the control signal received by the control signal terminal gpio is at a low level (which can be called the second logic level of the control signal), the MOS tube Q1 is turned off. The transistor Q10 is turned on, the transistor Q11 is turned on, and the transistor Q12 is turned on. At this time, the voltage of the power input terminal VCC is provided to the second voltage output terminal HVIO2 through the MOS transistor Q10. When in the dormant state, the control signal terminal gpio is set to a high impedance state. At this time, the transistor Q2, the transistor Q7 and the MOS transistor Q4 are all in a cut-off (or turned-off) state, and the power input terminal VCC cannot return to the ground terminal GND through the transistor Q3, the MOS transistor Q5 and the transistor Q11.

[0038] Please refer to Figure 3 As shown, it is a circuit diagram of an LED driving system in one embodiment of the utility model. Figure 3 The LED driving system shown includes the following Figure 2 The LED time-sharing circuit 310 based on a single control signal port, two multi-color LEDs and a constant current source module 320 are shown. The two multi-color LEDs (i.e., two RGB) are respectively a first multi-color LED1 and a second multi-color LED2, wherein the anode of the first multi-color LED1 is connected to the first voltage output terminal HVIO1, and the cathode thereof is connected to the constant current source module 320; the anode of the second multi-color LED2 is connected to the second voltage output terminal HVIO2, and the cathode thereof is connected to the same constant current source module 320.

[0039] In summary, the LED time-sharing circuit based on a single control signal port provided by the utility model is an RGB external time-sharing driving circuit, which can double the number of driven RGB; the MCU (Microcontroller Unit) provides a gpio as a control signal, and the voltage of the power input terminal VIN is divided into two paths for use. When the gpio state is constantly switched, the first voltage output terminal HVIO1 and the second voltage output terminal HVIO2 are alternately turned on to play a time-sharing role. In addition, when in the sleep state, the control signal terminal gpio is set to a high impedance state. At this time, the transistor Q2, the transistor Q7 and the MOS tube Q4 are all in the cut-off (or turned off) state, and the power input terminal VCC cannot return to the ground terminal GND through the transistor Q3, the MOS tube Q5 and the transistor Q11, so that the static current is less than 100uA, so as to solve the problem of large static current in the sleep mode.

[0040] Based on the above analysis, the beneficial effects of the LED time-sharing circuit based on a single control signal port provided by the utility model are:

[0041] 1) In the case of limited resources, only one control signal end gpio is used to control RGB two-time division;

[0042] 2) Solved the problem of excessive static current in sleep mode.

[0043] It should be noted that any changes made by those skilled in the art to the specific implementation of the present invention do not deviate from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited to the aforementioned specific implementation.

Claims

1. An LED time-sharing circuit based on a single control signal port, characterized in that: It includes: A control signal terminal, which receives a control signal whose logic level alternately changes between a first logic level and a second logic level in a normal working mode; A first voltage output module, comprising a control terminal, a power input terminal VCC and a first voltage output terminal HVIO1. When the control terminal is at a first logic level, the first voltage output module connects the power input terminal VCC and the first voltage output terminal HVIO1. When the control terminal is at a second logic level or a high impedance state, the first voltage output module disconnects the power input terminal VCC and the first voltage output terminal HVIO1. The control terminal of the first voltage output module is connected to the control signal terminal. A second voltage output module, which includes a control terminal, a power input terminal VCC, a second voltage output terminal HVIO2 and a second power terminal; A logic control component, wherein a first output terminal is connected to the control terminal of the second voltage output module, and a second output terminal is connected to the second power supply terminal of the second voltage output module, so as to provide a controllable path from the second power supply terminal of the second voltage output module to the ground terminal. In a normal working mode, when the control signal received at the control signal terminal is a first logic level, the control terminal of the second voltage output module is in a high impedance state, and at the same time, the path from the second power supply terminal of the second voltage output module to the ground terminal is cut off. At this time, the second voltage output module disconnects the connection between the power input terminal VCC and the second voltage output terminal HVIO2; when the control signal received at the control signal terminal is a second logic level, the logic control component outputs the first logic level to the control terminal of the second voltage output module, and at the same time, the path from the second power supply terminal of the second voltage output module to the ground terminal is turned on. At this time, the second voltage output module turns on the connection between the power input terminal VCC and the second voltage output terminal HVIO2.

2. The LED time-sharing circuit based on a single control signal port according to claim 1, characterized in that: In the sleep mode, the control signal terminal is configured to be in a high impedance state, the logic control component makes the control terminal of the second voltage output module in a high impedance state, and at the same time cuts off the path from the second power supply terminal to the ground terminal of the second voltage output module, so that the second voltage output module disconnects the connection between the power input terminal VCC and the second voltage output terminal HVIO2; In the sleep mode, the control signal terminal is configured to be in a high impedance state, so that the first voltage output module disconnects the power input terminal VCC and the first voltage output terminal HVIO1.

3. The LED time-sharing circuit based on a single control signal port according to claim 2, characterized in that: The first voltage output module includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a MOS transistor Q1 and a transistor Q2; The second voltage output module includes a resistor R16, a resistor R17, a resistor R18, a resistor R19, a MOS transistor Q10 and a transistor Q11; The logic control component includes a first logic control module, a second logic control module and a third logic control module, wherein the first logic control module includes a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a MOS tube Q4 and a transistor Q3; the second logic control module includes a resistor R10, a resistor R11, a resistor R12, a MOS tube Q5 and a transistor Q6; the third logic control module includes a resistor R13, a resistor R14, a resistor R15, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a transistor Q7, a transistor Q8, a transistor Q9 and a transistor Q12; The first connection end of the MOS transistor Q1 is connected to the power input end VCC, the second connection end thereof is connected to the first voltage output end HVIO1, and the control end thereof is connected to the first connection end of the transistor Q2 via the resistor R2; the control end of the transistor Q2 is connected to the control end of the first voltage output module via the resistor R3, and the second connection end thereof is grounded; one end of the resistor R1 is connected to the first connection end of the MOS transistor Q1, and the other end thereof is connected to the control end of the MOS transistor Q1; one end of the resistor R4 is connected to the control end of the transistor Q2, and the other end thereof is connected to the second connection end of the transistor Q2, The first connection end of the MOS transistor Q10 is connected to the power input end VCC, the second connection end thereof is connected to the second voltage output end HVIO2, and the control end thereof is connected to the first connection end of the transistor Q11 via the resistor R17; the control end of the transistor Q11 is connected to the control end of the second voltage output module via the resistor R18, and the second connection end thereof is connected to the second power supply end of the second voltage output module; one end of the resistor R16 is connected to the first connection end of the MOS transistor Q10, and the other end thereof is connected to the control end of the MOS transistor Q10; one end of the resistor R19 is connected to the control end of the transistor Q11, and the other end thereof is connected to the second connection end of the transistor Q11, The first connection end of the transistor Q3 is connected to the first connection end of the transistor Q2, the second connection end thereof is connected to one end of the resistor R9, and the control end thereof is connected to the first connection end of the MOS transistor Q4 via the resistor R6; the control end of the MOS transistor Q4 is connected to the control signal end via the resistor R7, and the second connection end thereof is grounded via the resistor R8; one end of the resistor R5 is connected to the first connection end of the transistor Q3, and the other end thereof is connected to the control end of the transistor Q3. The first connection end of the MOS tube Q5 is connected to the power input terminal VCC via the resistor R10, the control end thereof is connected to the other end of the resistor R9, and the second connection end thereof is grounded via the resistor R11; the first connection end of the transistor Q6 is connected to the power input terminal VCC, and the second connection end thereof is connected to the first output end of the logic control component; one end of the resistor R12 is connected to the second connection end of the MOS tube Q5, The first connection end of the transistor Q8 is connected to the power input end VCC, the control end thereof is connected to the other end of the resistor R12, and the second connection end thereof is connected to the first connection end of the transistor Q9 via the resistor R20; the control end of the transistor Q9 is connected to the control end of the transistor Q6 via the resistor R13, and the second connection end thereof is grounded via the resistors R22 and R23 in sequence; the first connection end of the transistor Q7 is connected to the control end of the transistor Q9, the control end thereof is connected to the control signal end via the resistor R14, and the second connection end thereof is grounded; one end of the resistor R15 is connected to the control end of the transistor Q7, and the other end thereof is connected to the second connection end of the transistor Q7; the first connection end of the transistor Q12 is connected to the second output end of the logic control component via the resistor R21, the control end thereof is connected to the connection node between the resistor R22 and the resistor R23, and the second connection end thereof is grounded.

4. The LED time-sharing circuit based on a single control signal port according to claim 3, characterized in that: In the normal working mode, when the control signal received by the control signal terminal is at the first logic level, the MOS transistor Q1 is turned on, the transistor Q2 is turned on, the transistor Q3 is turned off, the MOS transistor Q4 is turned off, the MOS transistor Q5 is turned off, the transistor Q6 is turned off, the transistor Q7 is turned on, the transistor Q8 is turned off, the transistor Q9 is turned off, the MOS transistor Q10 is turned off, the transistor Q11 is turned off, and the transistor Q12 is turned off. At this time, the voltage of the power input terminal VCC is provided to the first voltage output terminal HVIO1 via the MOS transistor Q1; In the normal working mode, when the control signal received by the control signal terminal is at the second logic level, the MOS transistor Q1 is turned off, the transistor Q2 is turned off, the transistor Q3 is turned on, the MOS transistor Q4 is turned on, the MOS transistor Q5 is turned on, the transistor Q7 is turned off, the VBE diode of the transistor Q8 is turned on, the VBE diode of the transistor Q9 is turned on, the VBE diode of the transistor Q6 is turned on, the MOS transistor Q10 is turned on, the transistor Q11 is turned on, and the transistor Q12 is turned on. At this time, the voltage of the power input terminal VCC is provided to the second voltage output terminal HVIO2 via the MOS transistor Q10; When in the dormant state, the control signal terminal is set to a high impedance state. At this time, the transistor Q2 is turned off, the transistor Q7 is turned off, and the MOS transistor Q4 is turned off.

5. The LED time-sharing circuit based on a single control signal port according to claim 4, characterized in that: The MOS transistor Q1 is a PMOS transistor, and the first connection end, the second connection end and the control end of the MOS transistor Q1 are the source, the drain and the gate of the PMOS transistor respectively; The transistor Q2 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q2 are respectively the collector, the emitter and the base of the NPN transistor; The transistor Q3 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q3 are respectively the emitter, the collector and the base of the PNP transistor; The MOS tube Q4 is a PMOS tube, and the first connection end, the second connection end and the control end of the MOS tube Q4 are the source, the drain and the gate of the PMOS tube respectively; The MOS transistor Q5 is an NMOS transistor, and the first connection end, the second connection end and the control end of the MOS transistor Q5 are respectively the drain, the source and the gate of the NMOS transistor; The transistor Q6 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q6 are respectively the collector, the emitter and the base of the NPN transistor; The transistor Q7 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q7 are respectively the collector, the emitter and the base of the NPN transistor; The transistor Q8 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q8 are respectively the collector, the emitter and the base of the NPN transistor; The transistor Q9 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q9 are respectively the emitter, the collector and the base of the PNP transistor; The MOS transistor Q10 is a PMOS transistor, and the first connection end, the second connection end and the control end of the MOS transistor Q10 are the source, the drain and the gate of the PMOS transistor respectively; The transistor Q11 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q11 are respectively the emitter, the collector and the base of the PNP transistor; The transistor Q12 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q12 are respectively the collector, the emitter and the base of the NPN transistor.

6. The LED time-sharing circuit based on a single control signal port according to any one of claims 1 to 5, characterized in that: The LEDs are two multi-color LEDs, namely a first multi-color LED and a second multi-color LED. The anode of the first multi-color LED is connected to the first voltage output terminal HVIO1, and the cathode thereof is connected to the constant current source module; The anode of the second multi-color LED is connected to the second voltage output terminal HVIO2, and the cathode of the second multi-color LED is connected to the constant current source module.

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