Insulated gate bipolar transistor for inhibiting self-opening effect

Abstract

The utility model discloses an insulated gate bipolar transistor for inhibiting a self-opening effect, and relates to the technical field of semiconductors. The control grid is located at the top of the groove and mainly used for controlling opening of the groove, the shielding grid is located at the bottom of the groove and can reduce turn-off loss of the Miller capacitor during reverse turn-off, meanwhile, the shielding grid can be used for the charge balance effect between the grooves, an electric field can be adjusted during reverse turn-off, depletion is achieved, and the requirement for reverse voltage resistance is met. Compared with a traditional device cellular structure, a shielding grid and a control grid are introduced to be integrated in the same groove, and the cellular density is effectively improved. And meanwhile, the structure can reduce Miller capacitance Cres on the premise of not changing gate-emitter capacitance Cge, so that a relatively low Cre / Cge ratio is obtained, and the self turn on effect of simultaneous opening of an upper tube and a lower tube caused by voltage switching of the device in actual circuit application can be inhibited.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor power devices, in particular to an insulated gate bipolar transistor capable of suppressing a self-turn-on effect. Background Art

[0002] A large number of power rectifiers are used in switching power supplies. The performance of the power rectifier has an important impact on the overall performance of the switching power supply. The insulated gate bipolar transistor is a new type of composite device that integrates power field effect transistors and triodes on a single chip. The power field effect transistor is a voltage-driven unipolar device, which has the advantages of easy driving, fast speed, high input impedance, and good thermal stability, but its on-resistance is large and the current capacity is low; while the triode is a current-driven bipolar device, which has the characteristics of high blocking voltage and strong current carrying capacity, but the working speed is slow, the driving current is large, and the control circuit is more complicated. The insulated gate bipolar transistor combines the advantages of both, with the speed advantage of the field effect transistor and the current carrying capacity of the triode, and has better performance.

[0003] The active area of ​​the traditional insulated gate bipolar transistor chip includes two parts: trench gate and trench emitter. The proportion of trench gate and trench emitter will not only affect the dynamic characteristics of the device but also the application of the actual circuit. Specifically, the larger the proportion of trench gate, the gate-emitter capacitance Cge of the device will increase, the turn-on delay will become larger, and the Miller capacitance Cres will increase, resulting in increased switching loss; while the larger the proportion of trench emitter gate, the gate-emitter capacitance Cge and Miller capacitance Cres of the device will decrease, thereby reducing switching loss. However, in actual device development, it is not necessary to simply reduce Cgs and Cres to achieve low switching loss, because in actual circuit applications, any dv / dt appearing on the collector is coupled to the gate through a capacitive voltage divider composed of Miller capacitance Cres and gate-emitter capacitance Cge. In this action, if Cgs is small, it will cause a self-turn on phenomenon due to excessive voltage division, which will cause circuit damage. Therefore, the smaller Cres / Cge, the better.

[0004] However, due to the adjustment of the ratio of trench gate to trench emitter, the gate-emitter capacitance Cge and the Miller capacitance Cres always change in the same direction, which is not conducive to the adjustment of the ratio of Cres to Cge to suppress the self-turn-on effect of the device in actual circuit applications due to voltage switching, which causes the upper and lower tubes to be turned on at the same time. Utility Model Content

[0005] In view of the above problems, the utility model provides an insulated gate bipolar transistor with self-turn-on effect suppression, which effectively solves the problems of low active area trench gate area, low short-circuit characteristics, and self turn on in circuit applications.

[0006] The technical solution of the utility model is:

[0007] The feature is that a carrier storage layer is provided on the top of the substrate;

[0008] The carrier storage layer is provided with a plurality of first grooves, a plurality of second grooves and a third groove; the first grooves, the second grooves and the third grooves are interconnected to form a gate-shaped groove; the first grooves and the second grooves are respectively filled with a first polysilicon located below the notch, and a polysilicon oxide layer and a second polysilicon are sequentially provided on the top of the first polysilicon from bottom to top; the third polysilicon is filled in the third groove;

[0009] A Pbody layer is disposed on the carrier storage layer and is located at the side of the gate-shaped groove; an N+ layer is disposed on the top surface of the Pbody layer and is located at the side of the first groove close to the scribe line;

[0010] An interlayer dielectric layer is provided on the top of the gate-shaped trench; a first through hole, a second through hole and a third through hole are provided in the interlayer dielectric layer, and the second through hole is located between the first through hole and the third through hole; the first through hole and the third through hole respectively pass through the N+ layer and are connected to the Pbody layer in sequence, and the second through hole passes through the interlayer dielectric layer and is connected to the first polysilicon in the third trench;

[0011] The front metal layer covers the interlayer dielectric layer and is sequentially connected to the first through hole, the second through hole and the third through hole to form an emitter of the insulated gate bipolar transistor that suppresses the self-turn-on effect;

[0012] A first electric field stop layer and a second electric field stop layer are sequentially arranged at the bottom of the substrate.

[0013] Optionally, the substrate is a zone-melting single crystal wafer.

[0014] Optionally, the first polysilicon and the third polysilicon are connected to the emitter through a second through hole to form an emitter trench structure.

[0015] Optionally, the depths of the first groove, the second groove and the third groove are all 5000-5500nm.

[0016] Optionally, a top surface of the polysilicon oxide layer in the first trench and a top surface of the polysilicon oxide layer in the third trench are on the same horizontal plane.

[0017] Optionally, a top surface of the second polysilicon and a top surface of the third trench polysilicon are at the same horizontal plane.

[0018] Optionally, the thickness of the polysilicon oxide layer is 120-200 nm.

[0019] Optionally, the first through hole and the front metal layer form a first connection portion, the second through hole and the front metal layer form a second connection portion, and the third through hole and the front metal layer form a third connection portion.

[0020] Beneficial effects of the utility model:

[0021] The insulated gate bipolar transistor with self-turn-on effect suppression provided by the present application introduces a shield gate and a control gate integrated in the same trench compared to the traditional device cell structure, which not only effectively improves the cell density but also provides a new design method for the structural adjustment of the switch-off loss and short-circuit capability. The control gate located at the top of the trench is mainly used to realize the discharge of the current during the opening and short-circuit of the control channel. The shield gate located at the bottom of the trench can reduce the Miller capacitance and reduce the turn-off loss during reverse shutdown. It can also be used for the charge balance effect between the trenches, and will adjust the electric field to achieve depletion during reverse cutoff to achieve the reverse withstand voltage requirement. At the same time, the structure can reduce the Miller capacitance Cres without changing the gate-emitter capacitance Cge, thereby obtaining a lower Cres / Cge ratio, which helps to suppress the self turn on effect of the device in actual circuit applications due to voltage switching, which causes the upper and lower tubes to be turned on at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the cross-sectional structure of the utility model;

[0023] Figure 2 is a schematic diagram of the cross-sectional structure of step 2;

[0024] Figure 3 is a schematic diagram of a top-view cross-sectional structure of a first groove, a second groove and a third groove;

[0025] Figure 4 It is a schematic diagram of the cross-sectional structure of the photoresist mask layer remaining after etching on the top surface of the single crystal material;

[0026] Figure 5 is a schematic diagram of the cross-sectional structure of the first oxide layer formed on the inner wall of the gate-shaped trench;

[0027] Figure 6 is a schematic diagram of a cross-sectional structure of a first polysilicon filled in a gate-shaped trench;

[0028] Figure 7 is a schematic diagram of the cross-sectional structure of the first polysilicon etching back;

[0029] Figure 8 is a schematic diagram of a cross-sectional structure of a polysilicon oxide layer;

[0030] Fig. 9 It is a schematic diagram of the cross-sectional structure of forming a second polysilicon by depositing polysilicon and etching back;

[0031] Fig.10 It is a schematic diagram of the cross-sectional structure of the Pbody layer formed by ion implantation and high temperature annealing;

[0032] Fig.11 is a schematic diagram of the cross-sectional structure after the N+ layer is formed;

[0033] Fig.12 It is a schematic diagram of the cross-sectional structure after the interlayer dielectric layer and the front metal layer are deposited on the top surface of the zone melting single wafer;

[0034] In the figure, 1 is the front metal layer, 2 is the interlayer dielectric layer, 21 is the first trench, 22 is the second trench, 23 is the third trench, 3 is the N+ layer, 4 is the second polysilicon, 5 is the Pbody layer, 6 is the first polysilicon, 7 is the polysilicon oxide layer, 8 is the zone melting single crystal, 9 is the first electric field stop layer, 10 is the second electric field stop layer, 11 is the third polysilicon, 12 is the first through hole, 13 is the second through hole, 14 is the third through hole, 15 is the gate oxide layer, 16 is the carrier storage layer, and 17 is the photoresist mask layer. DETAILED DESCRIPTION

[0035] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0036] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0037] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0038] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0039] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0040] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0041] The insulated gate bipolar transistor for suppressing self-turn-on effect provided by the present application is exemplarily described below in conjunction with specific embodiments.

[0042] like Figure 1 As shown, the insulated gate bipolar transistor for suppressing self-turn-on effect provided in the embodiment of the present application includes a wafer zone melting single crystal material 8, and a carrier storage layer structure 16 is formed on the top surface of the zone melting single crystal layer by ion implantation and high temperature annealing before trench etching;

[0043] The carrier storage layer 16 is provided with a plurality of first grooves 21, a plurality of second grooves 22 and a third groove 23; the first grooves 21, the second grooves 22 and the third grooves 23 are interconnected to form a grid-shaped groove; the first grooves 21 and the second grooves 22 are respectively filled with a first polysilicon 6 located below the notch, and a polysilicon oxide layer 7 and a second polysilicon 4 are sequentially provided on the top of the first polysilicon 6 from bottom to top; the third groove 23 is filled with a third polysilicon 11 flush with the notch;

[0044] A Pbody layer 5 is provided on the top of the substrate and located at the side of the gate-shaped groove; an N+ layer 3 is provided on the top surface of the Pbody layer 5 and located at the side of the first groove 21 close to the scribe line;

[0045] An interlayer dielectric layer 2 is provided on the top of the gate-shaped trench; a first through hole 12, a second through hole 13 and a third through hole 14 are provided in the interlayer dielectric layer 2; the first through hole 12 and the third through hole 14 respectively pass through the N+ layer 3 and are connected to the Pbody layer 5 in sequence, and the second through hole 13 passes through the interlayer dielectric layer 2 and is connected to the first polysilicon 6 in the third trench 23;

[0046] The front metal layer 1 covers the interlayer dielectric layer 2 and is sequentially connected to the first through hole 12, the second through hole 13 and the third through hole 14 to form an emitter of the insulated gate bipolar transistor that suppresses the self-turn-on effect.

[0047] The first polysilicon 6 and the third polysilicon 11 are connected to the emitter through the second through hole 13 to form an emitter trench structure. The control gate 4 can be led out through the gate bus at the periphery of the chip and converged at the gate pad position of the chip for electrode lead-out of the packaging bonding wire.

[0048] The grooves are further defined as:

[0049] The depths of the first groove 21, the second groove 22 and the third groove 23 are all 5000-5500 nm.

[0050] The top surface of the polysilicon oxide layer 7 in the first trench 21 and the top surface of the polysilicon oxide layer 7 in the third trench 23 are at the same level.

[0051] The top surface of the second polysilicon 4 and the top surface of the third trench polysilicon 11 are at the same level.

[0052] The following is a detailed introduction to the preparation process of the insulated gate bipolar transistor with a shielded gate structure of the utility model in combination with an example:

[0053] A method for preparing an insulated gate bipolar transistor comprises the following steps:

[0054] Step 1, forming a carrier storage layer 16 on the top surface of the zone melting single crystal 8 by ion implantation and high temperature annealing;

[0055] Further, a prepared zone-melting single crystal material 8 is provided, and a device pattern is first transferred using a mask, and a carrier storage layer 16 is formed on the top surface of the zone-melting single crystal wafer 8 by ion implantation and high-temperature annealing;

[0056] Step 2, removing the exposed photoresist on the top surface of the zone-melting single wafer 8, performing grid-shaped groove etching on the zone-melting single wafer 8 to form a plurality of first grooves 21, a plurality of second grooves 22 and a plurality of third grooves 23;

[0057] Further, if Figure 2 As shown, firstly, a mask is used to transfer the device pattern, and then a first trench 21, a second trench 22 and a third trench 23 are etched on the first epitaxial layer 1 by dry etching to obtain a gate-shaped trench; as shown Figure 3As shown, the first trench 21, the second trench 22 and the third trench 23 are interconnected, which lays a foundation for the subsequent extraction of the first polysilicon 6 in the first trench 21 and the third trench 23 and the second polysilicon 11 in the second trench 22. According to different requirements for device withstand voltage, the trench depth is generally 5000 ~ 5500nm.

[0058] like Figure 4 As shown, the photoresist mask layer 17 remaining after etching the top surface of the single crystal material is removed.

[0059] Step 3, performing sacrificial oxidation and gate oxide growth on the inner wall of the gate-shaped trench to form a first oxide layer 15 on the inner wall of the gate-shaped trench;

[0060] Further, if Figure 5 As shown, in order to ensure the smoothness of the wall of the gate-shaped groove and the subsequent growth quality of the gate oxide, sacrificial oxidation will be performed first, and the thickness of the sacrificial oxidation is 120-130nm. Then the gate oxide is grown, and the first oxide layer 15 is formed on the inner wall of the gate-shaped groove by thermal growth, and the thickness of the first oxide layer 15 is 120-130nm. Since the first oxide layer 15 is grown in a high-temperature furnace tube, the top surface of the zone melting single crystal material 8 will also be naturally oxidized.

[0061] Step 4, polysilicon is deposited along the top surface of the zone melting single crystal wafer 8, so that the gate-shaped groove is filled with the first polysilicon 6; and polysilicon is etched back, wherein, except for the second groove 22, the first groove 21 and the third groove 23 are etched back to a position below the silicon surface;

[0062] Specifically, the first trench 21 and the third trench 23 are etched back to the silicon surface and then continue to be etched until they are 3.3 um to 3.5 um away from the bottom of the trench.

[0063] Further, if Figure 6 and Figure 7 As shown, polysilicon is deposited on the top surface of the first epitaxial layer 1, so that polysilicon 3 is filled in the gate-shaped groove to form a shielding gate. The shielding gate can deplete the carrier storage layer 16 between the gate-shaped grooves laterally, which is used for the charge balance effect between the grooves. It will adjust the electric field to achieve depletion during reverse cutoff, which is helpful for the reverse withstand voltage requirement. Then, polysilicon is deposited on the top surface of the zone melting single crystal 8, so that the gate-shaped groove is filled with polysilicon; and polycrystalline back etching is performed, wherein, except for the second groove 22, the first groove 21 and the third groove 23 are back-etched to the silicon surface and then continue to etch until the distance from the bottom of the groove is 3.3um~3.5um, that is, the shielding gate.

[0064] Step 5, such as Figure 8 and Fig. 9As shown, a polysilicon oxide layer 7 is formed in the first trench 21 and the third trench 23 by polycrystalline oxidation, and then polysilicon deposition and back etching are performed to form a second polysilicon 4, that is, a control gate for controlling the opening of the channel;

[0065] The thickness of the polysilicon oxide layer 7 is 120-200 nm.

[0066] Step 6, such as Fig.10 , forming a Pbody layer 5 on the top surface of the zone melting single crystal 8 by ion implantation and high temperature annealing;

[0067] Step 7, such as Fig.11 As shown, an N+ layer 3 is formed on the top surface of the zone melting single crystal 8 by ion implantation and high temperature annealing;

[0068] Step 8, such as Fig.12 As shown, an interlayer dielectric layer 2 is deposited on the top surface of the zone melting single crystal 8; and a first through hole 12, a second through hole 13 and a third through hole 14 are etched on the interlayer dielectric layer 2, and at the same time, a control gate 4 is led out through a gate bus through hole at the periphery of the chip and converges at the Gate pad position of the chip;

[0069] The thickness of the interlayer dielectric layer 2 is 1000-1100 nm.

[0070] Step 9, the first through hole 12 and the third through hole 14 sequentially pass through the interlayer dielectric layer 2 and the N+ layer 3 to contact the Pbody layer 5; the second through hole 13 passes through the interlayer dielectric layer 2 to contact the first polycrystalline layer 6;

[0071] Step 10, forming a front metal layer 1 on the interlayer dielectric layer 2;

[0072] Ti, TiN and tungsten are deposited in sequence in the through holes of the interlayer dielectric layer 2, and after the tungsten is etched back, a front metal is sputter-deposited on the top surface to form a front metal layer 1, and the first through hole 12 and the front metal layer 1 form a first connecting portion, the second through hole 13 and the front metal layer 1 form a second connecting portion, and the third through hole 14 and the front metal layer 1 form a third connecting portion.

[0073] Step 11, forming an electric field cutoff layer 9 on the bottom surface of the zone melting single crystal 8 by phosphorus ion implantation and laser annealing, and forming a hole injection layer 10 by boron ion implantation and laser annealing; finally forming a collector electrode on the bottom surface of the zone melting single crystal 8 by evaporating AlTi Ni Ag metal.

[0074] Regarding the contents disclosed in this case, there are a few points that need to be explained:

[0075] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;

[0076] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments;

[0077] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. An insulated gate bipolar transistor with suppressed self-turn-on effect, comprising a substrate, characterized in that: A carrier storage layer (16) is provided on the top of the substrate; The carrier storage layer (16) is provided with a plurality of first grooves (21), a plurality of second grooves (22) and a third groove (23); the first grooves (21), the second grooves (22) and the third grooves (23) are interconnected to form a grid-like groove; The first trench (21) and the second trench (22) are respectively filled with first polysilicon (6) located below the notch, and the top of the first polysilicon (6) is provided with a polysilicon oxide layer (7) and a second polysilicon (4) in order from bottom to top; the third trench (23) is provided with a filled third polysilicon (11); A Pbody layer (5) located on the side of the gate-shaped groove is provided on the carrier storage layer (16); an N+ layer (3) located on the top surface of the Pbody layer (5) is provided on the side of the first groove (21) close to the scribe line; An interlayer dielectric layer (2) is provided on the top of the gate-shaped trench; a first through hole (12), a second through hole (13) and a third through hole (14) are provided in the interlayer dielectric layer (2), and the second through hole (13) is located between the first through hole (12) and the third through hole (14); the first through hole (12) and the third through hole (14) respectively pass through the N+ layer (3) in sequence to be connected to the Pbody layer (5), and the second through hole (13) passes through the interlayer dielectric layer (2) to be connected to the first polysilicon (6) in the third trench (23); The front metal layer (1) covers the interlayer dielectric layer (2) and is sequentially connected to the first through hole (12), the second through hole (13) and the third through hole (14) to form an emitter of an insulated gate bipolar transistor that suppresses a self-turn-on effect; A first electric field stop layer (9) and a second electric field stop layer (10) are sequentially provided at the bottom of the substrate.

2. The insulated gate bipolar transistor with suppressed self-turn-on effect according to claim 1, characterized in that: The substrate is a zone-melting single crystal wafer (8).

3. The insulated gate bipolar transistor with suppressed self-turn-on effect according to claim 1, characterized in that: The first polysilicon (6) and the third polysilicon (11) are connected to the emitter through the second through hole (13) to form an emitter trench structure.

4. The insulated gate bipolar transistor with suppressed self-turn-on effect according to claim 3, characterized in that: The depths of the first groove (21), the second groove (22) and the third groove (23) are all 5000-5500 nm.

5. The insulated gate bipolar transistor with suppressed self-turn-on effect according to claim 1, characterized in that: The top surface of the polysilicon oxide layer (7) in the first groove (21) and the top surface of the polysilicon oxide layer (7) in the third groove (23) are located at the same horizontal plane.

6. The insulated gate bipolar transistor with suppressed self-turn-on effect according to claim 1, characterized in that: The top surface of the second polysilicon (4) and the top surface of the third polysilicon (11) are on the same horizontal plane.

7. The insulated gate bipolar transistor with suppressed self-turn-on effect according to claim 1, characterized in that: The thickness of the polysilicon oxide layer (7) is 120-200 nm.

8. The insulated gate bipolar transistor with suppressed self-turn-on effect according to claim 1, characterized in that: The first through hole (12) and the front metal layer (1) form a first connection portion, the second through hole (13) and the front metal layer (1) form a second connection portion, and the third through hole (14) and the front metal layer (1) form a third connection portion.

Images