VDMOS Devices

Abstract

A VDMOS device relates to the technical field of semiconductor devices. The VDMOS device comprises a substrate, an epitaxial layer arranged on the substrate, a P-well region arranged in the epitaxial layer and flush with the upper surface of the epitaxial layer, a first doped region and a second doped region arranged in the P-well region and flush with the upper surface of the P-well region, a source electrode located on the epitaxial layer and connected to the first doped region and the second doped region respectively, a drain electrode located on the side of the substrate away from the epitaxial layer, and a gate; the first doped region and the second doped region are arranged side by side; the gate comprises a first structure arranged on the epitaxial layer and a second structure arranged in the epitaxial layer, the first structure and the second structure are connected, and the second structure is arranged in a step-like manner along a first direction, and the first direction is the arrangement direction of the substrate and the epitaxial layer. The VDMOS device can improve the breakdown performance of the device while reducing the on-resistance.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a VDMOS device. Background Art

[0002] With the rapid development of power electronics technology towards high-frequency and high-power applications, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is widely used in switching power supplies, AC drives, variable frequency power supplies, computer equipment and other fields due to its advantages such as high withstand voltage, fast switching speed, simple driving, low driving power, good thermal stability and simple manufacturing process. Vertical diffusion of metal oxides (VDMOS) devices have become one of the mainstream devices of power MOSFET due to their high withstand voltage, simple manufacturing process and high reliability.

[0003] Conventional VDMOS devices use trench gate structures to improve the gate control capability of the device, eliminate the resistance of the JFET region, and greatly improve the current characteristics of the device. However, it will also generate a peak electric field at the bottom of the trench gate, causing the local electric field to increase, resulting in the device breakdown before reaching the theoretical breakdown voltage; and the conventional VDMOS device, due to the design of the trench gate, leads to a reduction in the length of the drift region, which reduces the withstand voltage of the device. In view of the above problems of the trench gate structure, in order to meet the requirements of the breakdown voltage of the device within the application range of high-voltage VDMOS, it is necessary to increase the thickness of the epitaxial layer of the device and reduce the concentration of the drift region. However, this method will cause the on-resistance to increase rapidly with the increase of the breakdown voltage to the power of 2.5, increase the on-state loss, and the drift region resistance accounts for more than half of the total device resistance. Therefore, the contradiction between the breakdown voltage and the on-resistance limits the development of VDMOS devices in power devices. Utility Model Content

[0004] The utility model aims to provide a VDMOS device, which can improve the breakdown performance of the device and reduce the on-resistance at the same time.

[0005] The embodiment of the utility model is achieved as follows:

[0006] In one aspect of the utility model, a VDMOS device is provided, which includes a substrate, an epitaxial layer disposed on the substrate, a P-well region disposed in the epitaxial layer and flush with the upper surface of the epitaxial layer, a first doping region and a second doping region disposed in the P-well region and flush with the upper surface of the P-well region, a source electrode disposed on the epitaxial layer and connected to the first doping region and the second doping region respectively, a drain electrode disposed on the side of the substrate away from the epitaxial layer, and a gate electrode; the first doping region and the second doping region are disposed side by side; the gate electrode includes a first structure disposed on the epitaxial layer and a second structure disposed in the epitaxial layer, the first structure and the second structure are connected, and the second structure is disposed in a step-like manner along a first direction, and the first direction is the arrangement direction of the substrate and the epitaxial layer. The VDMOS device can improve the breakdown performance of the device while reducing the on-resistance.

[0007] Optionally, the second structure includes at least two substructures connected in sequence along the first direction, and the widths of the at least two substructures gradually decrease along the direction from the epitaxial layer to the substrate.

[0008] Optionally, the epitaxial layer includes at least two ion-doped regions arranged along the first direction, and two adjacent ion-doped regions are connected to each other.

[0009] Optionally, the doping doses of the at least two ion-doped regions gradually decrease along the direction from the epitaxial layer toward the substrate.

[0010] Optionally, the ion doping concentration in each ion doping region gradually increases along the direction from the epitaxial layer toward the substrate.

[0011] Optionally, the at least two ion doping regions include a first ion doping region and a second ion doping region arranged along a first direction, the first ion doping region is located on a side of the second ion doping region away from the substrate, and the first ion doping region and the substructure of the second structure close to the substrate are arranged correspondingly.

[0012] Optionally, the doping concentration distribution of the first ion doping region satisfies the following formula:

[0013]

[0014] Among them, N FAD (x) is the doping concentration, ε s is the dielectric constant of silicon, E x is the electric field strength, x is the distance from the first position to the surface of the first ion-doped region away from the substrate, q is the electron charge, t αFP is the effect of the field plate structure on the equivalent thickness of the area it covers, t αFP =t / (α) 0.5 ,α is the field plate factor, α=t s / (ε si / ε fox )t fox +1,tfox is the field oxide thickness, t s is the thickness of the substrate, ε si is the dielectric constant of silicon, ε fox is the dielectric constant of the field oxide layer.

[0015] Optionally, the doping concentration distribution of the second ion doping region satisfies the following formula:

[0016]

[0017] Among them, N FAD (x) is the doping concentration, ε s is the dielectric constant of silicon, E x is the electric field strength, x is the distance from the first position to the surface of the first ion-doped region away from the substrate, L FP is the length of the first ion-doped region along the first direction, q is the electron charge, t is the effective characteristic thickness, V is the potential at the edge of the field plate, and the field plate is a substructure of the second structure close to the substrate.

[0018] Optionally, a field oxide layer and a gate oxide layer on the field oxide layer are further provided in the epitaxial layer; the field oxide layer is provided at the periphery of the field plate, the field plate is a substructure of the second structure close to the substrate, and the gate oxide layer is provided at the periphery of the remaining substructures.

[0019] Optionally, the thickness of the gate oxide layer is smaller than the thickness of the field oxide layer.

[0020] The beneficial effects of the utility model include:

[0021] The VDMOS device provided by the present application includes a substrate, an epitaxial layer arranged on the substrate, a P-well region arranged in the epitaxial layer and flush with the upper surface of the epitaxial layer, a first doped region and a second doped region arranged in the P-well region and flush with the upper surface of the P-well region, a source located on the epitaxial layer and connected to the first doped region and the second doped region respectively, a drain located on the side of the substrate away from the epitaxial layer, and a gate; the first doped region and the second doped region are arranged side by side; the gate includes a first structure arranged on the epitaxial layer and a second structure arranged in the epitaxial layer, the first structure and the second structure are connected, and the second structure is arranged in a step-like manner along a first direction, and the first direction is the arrangement direction of the substrate and the epitaxial layer. The present application arranges the second structure located in the epitaxial layer to be arranged in a step-like manner along the first direction. In this way, compared with the prior art that increases the thickness of the epitaxial layer of the device in order to improve the breakdown performance, the present application can solve the contradiction between the breakdown voltage and the on-resistance, and achieves the reduction of the on-resistance while improving the breakdown performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 One of the structural schematic diagrams of a VDMOS device provided in some embodiments of the utility model;

[0024] Figure 2 The second structural schematic diagram of the VDMOS device provided in some embodiments of the utility model.

[0025] Icon: 10-substrate; 20-epitaxial layer; 21-first ion doping region; 22-second ion doping region; 30-P well region; 40-first doping region; 50-second doping region; 60-source; 70-drain; 80-gate; 81-first structure; 82-second structure; 821-substructure; a-first direction; 91-field oxide layer; 92-gate oxide layer. DETAILED DESCRIPTION

[0026] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments, and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present invention, and will recognize the application of these concepts not specifically proposed herein. It should be understood that these concepts and applications are within the scope of the present invention.

[0027] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to divide an element from another element. For example, without departing from the scope of the present invention, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] It should be understood that when an element (such as a layer, region or substrate) is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extended onto another element, or there can also be an intervening element. On the contrary, when an element is referred to as "directly on another element" or "directly extending onto another element", there is no intervening element. Similarly, it should be understood that when an element (such as a layer, region or substrate) is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extended onto another element, or there can also be an intervening element. On the contrary, when an element is referred to as "directly on another element" or "extending directly onto another element", there is no intervening element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intervening element. On the contrary, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intervening element.

[0029] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0030] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the utility model. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" are intended to include the plural forms as well. It should also be understood that when used herein, the term "comprising" indicates the presence of the features, integers, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups of the above.

[0031] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the utility model belongs. It should also be understood that the terms used in this article should be interpreted as having the same meaning as they do in this specification and the relevant field, and should not be interpreted in an idealized or overly formal sense, unless clearly defined in this article.

[0032] Please refer to Figure 1 and Figure 2The present embodiment provides a VDMOS device, which includes a substrate 10, an epitaxial layer 20 disposed on the substrate 10, a P-well region 30 disposed in the epitaxial layer 20 and flush with the upper surface of the epitaxial layer 20, a first doping region 40 and a second doping region 50 disposed in the P-well region 30 and flush with the upper surface of the P-well region 30, a source 60 disposed on the epitaxial layer 20 and connected to the first doping region 40 and the second doping region 50 respectively, a drain 70 disposed on the side of the substrate 10 away from the epitaxial layer 20, and a gate 80; the first doping region 40 and the second doping region 50 are disposed side by side; the gate 80 includes a first structure 81 disposed on the epitaxial layer 20 and a second structure 82 disposed in the epitaxial layer 20, the first structure 81 and the second structure 82 are connected, and the second structure 82 is arranged in a step-like manner along a first direction a, and the first direction a is the arrangement direction of the substrate 10 and the epitaxial layer 20. The VDMOS device can improve the device breakdown performance while reducing the on-resistance.

[0033] Among them, the substrate 10, the epitaxial layer 20, and the first doping region 40 can adopt the first doping type, and the second doping region 50 can be the second doping type. Of course, they can also be interchanged, that is, the substrate 10, the epitaxial layer 20, and the first doping region 40 can adopt the second doping type, and the second doping region 50 can be the first doping type, and this application does not limit this.

[0034] Furthermore, in this embodiment, the doping concentration of the substrate 10 may be greater than the doping concentration of the epitaxial layer 20 , that is, the substrate 10 may be heavily doped and the epitaxial layer 20 may be lightly doped.

[0035] In this embodiment, both the first doping region 40 and the second doping region 50 may be heavily doped. The materials of the substrate 10 and the epitaxial layer 20 are not specifically limited in this application, and those skilled in the art may determine them as needed.

[0036] In this embodiment, the gate 80 includes a first structure 81 and a second structure 82, wherein the first structure 81 and the second structure 82 are connected to each other, and the first structure 81 is disposed above the epitaxial layer 20, and the second structure 82 is disposed in the epitaxial layer 20. That is, the gate 80 of the present application adopts a trench gate structure.

[0037] In this embodiment, the second structure 82 is arranged in a stepped manner. Figure 1 and Figure 2As shown, in this way, when in the on state, a large number of electrons are accumulated at the groove oxygen boundary to form an electron accumulation layer, which can reduce the specific on-resistance of the device, and at the same time can flatten the potential and the electric field peak at the edge of the gate 80, thereby avoiding premature breakdown of the device. The present application adopts a step gate structure (i.e., the second structure 82 is arranged in a step-like shape along the first direction a) to increase the thickness of the epitaxial layer 20 of the device relative to the prior art, which can solve the contradiction between the breakdown voltage and the on-resistance, and achieve the improvement of the breakdown performance of the device while reducing the on-resistance.

[0038] The present application does not impose any specific limitation on the number of steps of the second structure 82 , and it may be one step, or two, three or even more steps.

[0039] In summary, the VDMOS device provided in the present application includes a substrate 10, an epitaxial layer 20 arranged on the substrate 10, a P-well region 30 arranged in the epitaxial layer 20 and flush with the upper surface of the epitaxial layer 20, a first doped region 40 and a second doped region 50 arranged in the P-well region 30 and flush with the upper surface of the P-well region 30, a source 60 located on the epitaxial layer 20 and connected to the first doped region 40 and the second doped region 50 respectively, a drain 70 located on the side of the substrate 10 away from the epitaxial layer 20, and a gate 80; the first doped region 40 and the second doped region 50 are arranged side by side; the gate 80 includes a first structure 81 arranged on the epitaxial layer 20 and a second structure 82 arranged in the epitaxial layer 20, the first structure 81 and the second structure 82 are connected, and the second structure 82 is arranged in a stepped manner along a first direction a, and the first direction a is the arrangement direction of the substrate 10 and the epitaxial layer 20. The present application arranges the second structure 82 located in the epitaxial layer 20 to be arranged in a stepped manner along the first direction a. Thus, compared with the prior art which increases the thickness of the epitaxial layer 20 of the device in order to improve the breakdown performance, the present application can solve the contradiction between the breakdown voltage and the on-resistance, thereby achieving the goal of reducing the on-resistance while improving the breakdown performance of the device.

[0040] Optionally, the second structure 82 includes at least two substructures 821 connected in sequence along the first direction a, and the widths of the at least two substructures 821 gradually decrease along the direction from the epitaxial layer 20 to the substrate 10. It should be noted that at least two substructures 821 are required to form a step in the second structure 82.

[0041] The widths of the at least two substructures 821 gradually decrease along the direction from the epitaxial layer 20 to the substrate 10. That is, along the direction from the epitaxial layer 20 to the substrate 10 (i.e. Figure 1 The width of the substructures 821 is the width of the substructures 821. Figure 1 The horizontal dimension of the orientation.

[0042] Optionally, the epitaxial layer 20 includes at least two ion-doped regions arranged along the first direction a, and two adjacent ion-doped regions are connected to each other. That is, the epitaxial layer 20 is divided into at least two ion-doped regions along the first direction a. Figure 2 Of course, the present application does not limit the specific number of the ion-doped regions, which may be two, three or four.

[0043] In addition, in order to further improve the device performance, the device can improve the device breakdown performance while reducing the on-resistance. Optionally, the doping dose of at least two ion doping regions gradually decreases along the direction from the epitaxial layer 20 to the substrate 10 .

[0044] That is to say, in this embodiment, the doping doses of the multiple ion-doped regions of the epitaxial layer 20 gradually decrease along the direction from the epitaxial layer 20 to the substrate 10. That is, the doping doses of the multiple ion-doped regions of the epitaxial layer 20 gradually decrease from top to bottom. In this way, the overall doping dose of the ion-doped region located above any two adjacent ion-doped regions is greater than the overall doping dose of the ion-doped region located below.

[0045] Furthermore, the ion doping concentration in each ion doping region gradually increases along the direction from the epitaxial layer 20 to the substrate 10. That is, in a single ion doping region, the ion doping concentration gradually increases from top to bottom.

[0046] The present application utilizes the equivalent concentration distribution theory and, through multiple epitaxial growths of different doping concentrations, makes the doping concentration inside the epitaxial layer 20 present a step change, which will advantageously regulate the electric field within the epitaxial layer 20, making the electric field within the epitaxial layer 20 present multiple "peaks and valleys", effectively flattening the electric potential; in addition, combined with the above-mentioned groove gate and step gate structures, this will further flatten the electric potential, flatten the electric field peaks at the edge of the gate 80, and avoid premature breakdown of the device.

[0047] In addition, it should be noted that for N-type VDMOS, the epitaxial layer 20 needs to be doped with donor-type impurities, and the donor impurities that can be doped include phosphorus, arsenic, antimony, bismuth, etc.; for P-type VDMOS, the epitaxial layer 20 needs to be doped with acceptor-type impurities, and the acceptor impurities that can be doped include boron, aluminum, gallium, indium, etc.

[0048] like Figure 2 As shown, optionally, the at least two ion doping regions include a first ion doping region 21 and a second ion doping region 22 arranged along the first direction a, the first ion doping region 21 is located on the side of the second ion doping region 22 away from the substrate 10, and the first ion doping region 21 and the second structure 82 are arranged correspondingly to the substructure 821 close to the substrate 10. That is, Figure 2 Taking the above aspect as an example, the first ion doping region 21 is located above the second ion doping region 22 .

[0049] Optionally, the doping concentration distribution of the first ion doping region 21 satisfies the following formula:

[0050]

[0051] Among them, N FAD (x) is the doping concentration, ε s is the dielectric constant of silicon, E x is the electric field strength, x is the distance from the first position to the surface of the first ion doped region 21 away from the substrate 10, q is the electron charge, t αFP is the effect of the field plate structure on the equivalent thickness of the area it covers, t αFP =t / (α) 0.5 ,α is the field plate factor, α=t / (ε si / ε fox )t fox +1,t fox is the field oxide thickness, t s is the thickness of the substrate, ε si is the dielectric constant of silicon, ε fox is the dielectric constant of the field oxide layer.

[0052] Optionally, the doping concentration distribution of the second ion doping region 22 satisfies the following formula:

[0053]

[0054] Among them, N FAD (x) is the doping concentration, ε s is the dielectric constant of silicon, E x is the electric field strength, x is the distance from the first position to the surface of the first ion doping region 21 away from the substrate 10, L FP is the length of the first ion doped region 21 along the first direction a, q is the electron charge, t is the effective characteristic thickness, V is the potential at the edge of the field plate, and the field plate is the substructure 821 of the second structure 82 close to the substrate 10.

[0055] It should be noted that the field plate adaptive doping technology proposed for doping the epitaxial layer 20 in the present application is based on the graded junction theory and the equivalent concentration profile (ECP) theory, and fully considers the complex coupling effect in the epitaxial layer 20. The above formula satisfied by the doping concentration of the first ion doping region 21 and the second ion doping region 22 can be obtained through the following derivation process:

[0056] For a complex lateral power device, the overall equivalent concentration distribution (N) can be obtained by combining the increments of the ECP components caused by each effect. eff(x)). In particular, under reverse bias conditions, the surface electric field and potential can be easily obtained by the one-dimensional Poisson equation, namely:

[0057]

[0058] where q is the electron charge, ε s is the dielectric constant of silicon, N eff (x) is the doping concentration of the equivalent one-dimensional virtual junction. eff (x) represents the overall influence of drift region doping curve and FP effect on device breakdown characteristics, which can be further written as:

[0059] N eff (x) = N FAD (x)+ΔN eff-FP (x)

[0060] Among them, N FAD (x) is the doping concentration N eff-FP (x) represents the ECP increase caused by the gate electrode field plate effect.

[0061] (2) can be further rewritten to obtain:

[0062]

[0063] Among them, N d is the doping concentration of the drift region under the drain 70 region, x is the distance from the first position in the second ion doping region 22 to the surface of the first ion doping region 21 away from the substrate 10 (wherein the first position is any position in the first ion doping region 21 or the second ion doping region 22), Nv=ε s V / qt s 2 represents the influence of the potential at the drift region at the edge of the field plate on the ECP of the second ion doping region 22, where the potential V is the potential at the drift region at the edge of the field plate, and t s is the thickness of the silicon layer (i.e., substrate 10). d is the sum of the lengths of the first ion-doped region 21 and the second ion-doped region 22 along the first direction a, η FP1 is the two-dimensional coupling coefficient enhanced by the field plate effect in the cover area below the field plate, η FP1 =X ver (α·V d ) / t s ,X ver is the length of the depletion region below the field plate, V d is the drain potential, α = t s / (ε si / ε fox )t fox+1 is the field plate factor (indicating the influence of FP on the two-dimensional coupling effect), ε si is the dielectric constant of silicon, ε fox is the dielectric constant of the field oxide layer.

[0064] Furthermore, according to the ECP theory, the drift region obtains an ideal "rectangular" electric field distribution under the condition of N eff(x) =0, thus, the field plate adaptive doping distribution proposed in this application satisfies the following formula:

[0065]

[0066] Please refer to Figure 1 and Figure 2 Optionally, a field oxide layer 91 and a gate oxide layer 92 located on the field oxide layer 91 are also provided in the epitaxial layer 20; the field oxide layer 91 is provided at the periphery of the field plate, the field plate is a substructure 821 of the second structure 82 close to the substrate 10, and the gate oxide layer 92 is provided at the periphery of the remaining substructures 821.

[0067] The field plate adaptive doping technology proposed in the present application fully considers the multi-dimensional coupling effect in the device and the doping distribution under the condition of uniform electric field distribution of the epitaxial layer 20, wherein the multi-dimensional coupling effect includes field plate effect and RESURF effect. Since the field plate effect will enhance the depletion of carriers in the epitaxial layer 20, and the field plate effect is inversely proportional to the thickness of the field oxide layer 91. Therefore, the thinner the field oxide layer 91, the stronger the field plate effect, the higher the concentration of carriers that can be doped in the epitaxial layer 20, and the device's specific on-resistance will be reduced. Similarly, the field plate adaptive doping metering proposed in the present application is also in an inversely proportional relationship with the thickness of the field oxide layer 91. In order to achieve the optimization of the device's specific on-resistance, in the present application, optionally, the thickness of the above-mentioned gate oxide layer 92 is less than the thickness of the field oxide layer 91.

[0068] The thickness of the gate oxide layer 92 may be between 0.03 μm and 0.08 μm, and the thickness of the field oxide layer 91 may be between 0.05 μm and 0.15 μm. The thinner field oxide layer 91 can effectively improve the doping dosage of the field plate adaptive doping and optimize the conduction characteristics of the device.

[0069] The above description is only an optional embodiment of the utility model and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

[0070] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present utility model will not further describe various possible combinations.

Claims

1. A VDMOS device, characterized in that: The invention comprises a substrate, an epitaxial layer arranged on the substrate, a P-well region arranged in the epitaxial layer and flush with the upper surface of the epitaxial layer, a first doping region and a second doping region arranged in the P-well region and flush with the upper surface of the P-well region, a source electrode located on the epitaxial layer and connected to the first doping region and the second doping region respectively, a drain electrode located on a side of the substrate away from the epitaxial layer, and a gate electrode; the first doping region and the second doping region are arranged side by side; The gate includes a first structure disposed on the epitaxial layer and a second structure disposed in the epitaxial layer, the first structure and the second structure are connected, and the second structure is arranged in a stepped manner along a first direction, and the first direction is an arrangement direction of the substrate and the epitaxial layer.

2. The VDMOS device according to claim 1, characterized in that: The second structure includes at least two substructures connected in sequence along the first direction, and the widths of the at least two substructures gradually decrease along the direction from the epitaxial layer to the substrate.

3. The VDMOS device according to claim 2, characterized in that: The epitaxial layer includes at least two ion-doped regions arranged along the first direction, and two adjacent ion-doped regions are connected to each other.

4. The VDMOS device according to claim 3, characterized in that: The doping doses of the at least two ion doping regions gradually decrease along the direction from the epitaxial layer toward the substrate.

5. The VDMOS device according to claim 3, characterized in that: The ion doping concentration in each of the ion doping regions gradually increases along the direction from the epitaxial layer toward the substrate.

6. The VDMOS device according to any one of claims 3 to 5, characterized in that: The at least two ion doping regions include a first ion doping region and a second ion doping region arranged along the first direction, the first ion doping region is located on a side of the second ion doping region away from the substrate, and the first ion doping region and the second structure are arranged corresponding to the substructure close to the substrate.

7. The VDMOS device according to claim 6, characterized in that: The doping concentration distribution of the first ion doping region satisfies the following formula: Among them, the N FAD (x) is the doping concentration, the ε s is the dielectric constant of silicon, the E x is the electric field strength, x is the distance from the first position to the surface of the first ion-doped region away from the substrate, q is the electron charge, and t αFP is the effect of the field plate structure on the equivalent thickness of the area it covers, t αFP =t / (α) 0.5 ,α is the field plate factor, α=t s / (ε si / ε fox )t fox +1,t fox is the field oxide thickness, t s is the thickness of the substrate, ε si is the dielectric constant of silicon, ε fox is the dielectric constant of the field oxide layer.

8. The VDMOS device according to claim 6, characterized in that: The doping concentration distribution of the second ion doping region satisfies the following formula: Among them, the N FAD (x) is the doping concentration, the ε s is the dielectric constant of silicon, the E x is the electric field strength, x is the distance from the first position to the surface of the first ion-doped region away from the substrate, and L FP is the length of the first ion-doped region along the first direction, q is the electron charge, t is the effective characteristic thickness, V is the potential at the edge of the field plate, and the field plate is the substructure of the second structure close to the substrate.

9. The VDMOS device according to claim 2, characterized in that: A field oxide layer and a gate oxide layer on the field oxide layer are also provided in the epitaxial layer; the field oxide layer is provided at the periphery of the field plate, the field plate is the substructure of the second structure close to the substrate, and the gate oxide layer is provided at the periphery of the remaining substructures.

10. The VDMOS device according to claim 9, characterized in that: The thickness of the gate oxide layer is smaller than the thickness of the field oxide layer.

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