Power semiconductor device

Abstract

The utility model discloses a power semiconductor device. The power semiconductor device includes: a high voltage unit configured to output a high voltage; a low voltage unit configured to output a low voltage; the capacitor is electrically connected with the high-voltage unit and provides power for the high-voltage unit during the period of outputting the high voltage; and a switching unit which is electrically connected to the high voltage unit and the capacitor, and which connects the capacitor and a driving power supply in order to charge the capacitor during the period in which the low voltage is output. The high-voltage unit is used for preventing the high-voltage unit and the driving power supply from being electrically connected with each other during the period of outputting the high voltage; and the resistor unit is electrically connected between the switch unit and the high voltage unit, and reduces the high voltage to a voltage lower than the breakdown voltage of the switch unit during the period of outputting the high voltage.

Description

Technical Field

[0001] The embodiments of the utility model relate to a power semiconductor device, and more particularly, to a power semiconductor device including a bootstrap circuit, such as a high voltage integrated circuit (HVIC) device. Background Art

[0002] Generally speaking, a power semiconductor device may include a high voltage portion and a low voltage portion. In addition, a bootstrap circuit may be used to ensure stable operation of the high voltage portion. The bootstrap circuit may include a capacitor connected to the high voltage portion to provide power.

[0003] The bootstrap circuit may include a diode, which connects the capacitor to the driving voltage to charge the capacitor during the period when the low voltage unit outputs a low voltage, and prevents the driving power supply from being electrically connected to the high voltage unit during the period when the high voltage unit outputs a high voltage. However, in the case where the high voltage is directly loaded on the diode, the diode may be damaged, and therefore, a separate transistor may be provided between the high voltage unit and the diode to prevent the high voltage from being loaded on the diode.

[0004] When the separate transistor is used, the size of the power semiconductor device may increase. At the same time, the distance electrons move during charging of the capacitor may increase due to the separate transistor, which may result in a decrease in the current flowing to the capacitor. Utility Model Content

[0005] An object of the embodiments of the present invention is to provide a further improved power semiconductor device for solving the above-mentioned problems.

[0006] In order to achieve the above-mentioned purpose, a power semiconductor device according to one aspect of the present invention may include: a high voltage unit, configured to output a high voltage; a low voltage unit, configured to output a low voltage; a capacitor, electrically connected to the high voltage unit, to provide power to the high voltage unit during the period of outputting the high voltage; a switch unit, electrically connected to the high voltage unit and the capacitor, to connect the capacitor to a driving power supply in order to charge the capacitor during the period of outputting the low voltage, and to prevent the high voltage unit and the driving power supply from being electrically connected to each other during the period of outputting the high voltage; and a resistance unit, electrically connected between the switch unit and the high voltage unit, to reduce the high voltage to a voltage lower than the breakdown voltage of the switch unit during the period of outputting the high voltage.

[0007] According to some embodiments of the present invention, the resistance unit may include: an N-type impurity diffusion region formed in the substrate to electrically connect the switch unit and the high voltage unit.

[0008] According to some embodiments of the present invention, the resistor unit may further include: a field oxide layer formed on the substrate.

[0009] According to some embodiments of the present invention, the resistor unit may further include: a P-type impurity diffusion region formed between the N-type impurity diffusion region and the long oxide layer.

[0010] According to some embodiments of the present invention, the resistance unit may further include: a first electrode layer formed on the field oxide layer in a manner adjacent to the switching unit and electrically connected to the ground terminal; and a second electrode layer formed on the field oxide layer in a manner adjacent to the high voltage unit and electrically connected to the high voltage unit.

[0011] According to some embodiments of the present invention, the resistance unit may further include: a first contact region formed on one side of the N-type impurity diffusion region and electrically connected to the switch unit; and a second contact region formed on the other side of the N-type impurity diffusion region and electrically connected to the high voltage unit.

[0012] According to some embodiments of the present invention, the resistor unit may further include: an N-type buried layer formed at the lower side of the second contact region, for dispersing the electric field formed by the high voltage when the high voltage is loaded to the second contact region.

[0013] According to some embodiments of the present invention, the resistor unit may further include: a field oxide layer formed on a substrate; and a resistor layer formed on the field oxide layer.

[0014] According to some embodiments of the present invention, the resistance layer may be composed of polysilicon doped with N-type impurities.

[0015] In order to achieve the above-mentioned purpose, a power semiconductor device according to another aspect of the present invention may include: a high voltage unit, configured to output a high voltage; a low voltage unit, configured to output a low voltage; a capacitor, electrically connected to the high voltage unit, to provide power to the high voltage unit during the period of outputting the high voltage; a bipolar junction transistor, electrically connected to the high voltage unit and the capacitor, to connect the capacitor to a driving power supply in order to charge the capacitor during the period of outputting the low voltage, and to prevent the high voltage unit and the driving power supply from being electrically connected to each other during the period of outputting the high voltage; and a resistance unit, electrically connected between the bipolar junction transistor and the high voltage unit, to reduce the high voltage to a voltage lower than the breakdown voltage of the bipolar junction transistor during the period of outputting the high voltage.

[0016] According to some embodiments of the utility model, the bipolar junction transistor may include: an N-type emitter region formed on the substrate; a P-type base region formed on the substrate; and an N-type collector region formed on the substrate; the P-type base region and the N-type collector region may be electrically connected to the driving power supply, and the N-type emitter region may be electrically connected to the resistance unit.

[0017] According to some embodiments of the present invention, the bipolar junction transistor may further include: a P-type well region formed in the substrate; the N-type emitter region and the P-type base region may be formed on the P-type well region.

[0018] According to some embodiments of the present invention, the bipolar junction transistor may further include: an N-type buried layer formed in the substrate; and the P-type well region may be formed on the N-type buried layer.

[0019] According to some embodiments of the present invention, the P-type base region may be in a ring shape surrounding the N-type emitter region, and the N-type collector region may be in a ring shape surrounding the P-type base region.

[0020] In order to achieve the above-mentioned purpose, a power semiconductor device according to another aspect of the present invention may include: a high voltage unit, configured to output a high voltage; a low voltage unit, configured to output a low voltage; a capacitor, electrically connected to the high voltage unit, to provide power to the high voltage unit during the period of outputting the high voltage; a diode, electrically connected to the high voltage unit and the capacitor, to connect the capacitor to a driving power supply in order to charge the capacitor during the period of outputting the low voltage, and to prevent the high voltage unit and the driving power supply from being electrically connected to each other during the period of outputting the high voltage; and a resistance unit, electrically connected between the diode and the high voltage unit, to reduce the high voltage to a voltage lower than the breakdown voltage of the diode during the period of outputting the high voltage.

[0021] According to some embodiments of the utility model, the diode may include: a field oxide layer formed on a substrate; an anode layer formed on the field oxide layer; and a cathode layer formed on the field oxide layer; the anode layer may be electrically connected to the driving power supply, and the cathode layer may be electrically connected to the resistance unit.

[0022] According to some embodiments of the present invention, the anode layer may be composed of polysilicon doped with P-type impurities, and the cathode layer may be composed of polysilicon doped with N-type impurities.

[0023] The effects of the utility model are as follows.

[0024] According to the embodiment of the utility model described above, it is not necessary to use a separate transistor to prevent the high voltage from being loaded from the high voltage unit to the switch unit, so the size of the power semiconductor device can be reduced. In addition, compared with the prior art, the electron movement distance can be reduced, and the resistance of the N-type impurity diffusion region can be reduced, so the amount of current flowing from the driving power supply to the capacitor can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is an equivalent circuit diagram for describing a power semiconductor device according to an embodiment of the present utility model.

[0026] Figure 2 It is used for Figure 1 A schematic plan view illustrating the power semiconductor device shown in FIG.

[0027] Figure 3 It is used for Figure 2 A schematic cross-sectional view illustrating the switch unit and the resistance unit shown in FIG.

[0028] Figure 4 It is used for Figure 3 A schematic cross-sectional view illustrating another example of the resistor unit shown in FIG.

[0029] Figure 5 It is used for Figure 3 A schematic cross-sectional view illustrating another example of the resistor unit shown in FIG.

[0030] Figures 6 to 8 It is used for Figure 3 A schematic cross-sectional view illustrating another example of the switch unit shown in FIG.

[0031] Explanation of symbols

[0032] 10: power semiconductor device, 20: level shift region, 30: high voltage unit, 40: low voltage unit, 50: first device separation region, 60: second device separation region, 70: third device separation region, 100: switch unit, 102: substrate, 110: bipolar junction transistor, 112: N-type emitter region, 114: P-type base region, 116: N-type collector region, 118: P-type well region, 120: first N-type buried layer, 130: diode, 132: field oxide layer, 134: anode layer, 136: cathode layer, 200: resistor unit, 210: N-type impurity diffusion region, 212: first N-type contact region, 214: second N-type contact region, 220: field oxide layer, 230: second N-type buried layer, 240: first electrode layer, 242: second electrode layer, 250: P-type impurity diffusion region, 260: resistor layer. DETAILED DESCRIPTION

[0033] Next, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the composition of the present invention is not limited to the embodiments described in the following content, but can be implemented in a variety of different forms. The embodiments provided in the following content are not only to enable the complete implementation of the present invention, but also to fully convey the scope of the present invention to skilled practitioners in the technical field to which the present invention belongs.

[0034] In the case of describing in an embodiment of the present invention in a manner that one element is configured or connected to another element, the element may be directly configured or connected to the other element, or other elements may be interposed between the elements. In contrast, in the case of describing in a manner that one element is directly configured or connected to another element, there will be no other elements between the elements. In order to describe various items such as various elements, compositions, regions, layers and / or parts, terms such as first, second and third may be used, but the items are not limited by the terms.

[0035] The special terms used in the embodiments of the present invention are only used to illustrate specific embodiments and are not intended to limit the present invention. In addition, unless otherwise specified, the meanings of all terms, including descriptions and scientific terms, are the same as those understood by practitioners with general knowledge of the technical field to which the present invention belongs. The commonly used terms defined in dictionaries should be interpreted as having the same meaning as in the context of the relevant technology and the description of the present invention, and should not be interpreted as overly idealized, exaggerated or intuitive meanings unless otherwise clearly specified.

[0036] Next, embodiments of the present invention will be described with reference to schematic illustrations of ideal embodiments of the present invention. Therefore, it is fully anticipated that the shapes shown in the illustrations may vary, such as changes in manufacturing methods and / or tolerances. Therefore, embodiments of the present invention are not limited to the specific shapes of the areas illustrated by the illustrations, but include deviations in shape, and the elements illustrated in the drawings are generally schematic and are not intended to illustrate the exact shapes of the elements or to limit the scope of the present invention.

[0037] Figure 1 is an equivalent circuit diagram for describing a power semiconductor device according to an embodiment of the present utility model, and Figure 2 It is used for Figure 1 A schematic plan view illustrating the power semiconductor device shown in FIG.

[0038] See also Figure 1 as well as Figure 2 According to an embodiment of the present invention, a power semiconductor device 10 may include a high voltage unit 30, a low voltage unit 40, a capacitor C, a switch unit 100, and a resistor unit 200. The high voltage unit 30 may include a high voltage driving circuit 32 and a first power transistor T1, and the low voltage unit 40 may include a low voltage driving circuit 42 and a second power transistor T2.

[0039] The capacitor C may be connected in parallel to a power supply terminal V for providing power to the high voltage drive circuit 32. B 、V S The output terminal H of the high voltage drive circuit 32 O The low voltage output terminal L of the low voltage driving circuit 42 may be connected to the gate of the first power transistor T1, and the first power transistor T1 may be connected in parallel with the first diode D1. OThe first power transistor T1 may be connected to the gate of the second power transistor T2, and the second power transistor T2 may be connected in parallel with the second diode D2. The source of the first power transistor T1 may be connected to the high voltage HV, the first power transistor T1 and the second power transistor T2 may be connected in series, and the drain of the second power transistor T2 may be linked to the ground terminal GND.

[0040] The low voltage driving circuit 42 can be configured to input a low voltage through the low voltage input terminal L in The input signal is sent to the low voltage output terminal L O The low voltage driving circuit 42 can output a low voltage control signal to control the second power transistor T2. The low voltage driving circuit 42 can connect the low voltage to the driving power supply V CC The potential difference between the driving voltage receives power and works.

[0041] The high voltage driving circuit 32 may provide a high voltage output terminal H in response to a signal provided from the level shifting circuit 22. O The high voltage drive circuit 32 can output a high voltage control signal to control the first power transistor T1. The high voltage drive circuit 32 can be connected to a terminal V having the same potential as the output terminal OUT. S With terminal V B The capacitor C between the two terminals receives power and operates. The level shift circuit 22 can convert the high voltage input terminal H in The input signal is provided to the high voltage driving circuit 32. According to the state of the pulse width modulation (PWM) signal output from the output terminal OUT, the reference voltage of the high voltage driving circuit 32 may be a high voltage HV or a low voltage, such as a ground voltage.

[0042] The power semiconductor device 10 can be used as a power supply from a high voltage input terminal H in And the low voltage input terminal L in Specifically, when the low voltage driving circuit 42 outputs a high voltage HV or a low voltage, such as a ground voltage, to the output terminal OUT in response to the input signal, O When the second power transistor T2 is turned on, the output terminal OUT can output a low voltage, such as a ground voltage. At this time, the second diode D2 can prevent reverse voltage. At the same time, in order to prevent high voltage and low voltage from being loaded to the output terminal OUT at the same time, the high voltage driving circuit 32 can turn off the first power transistor T1. That is, the ground voltage loaded to the output terminal OUT and the voltage from the driving power supply V CC In addition, the driving power supply VCC A current may be provided to the capacitor C through the switch unit 100 and the resistance unit 200 , so that the capacitor C is charged with a driving voltage of approximately 100 Å.

[0043] When the low voltage driving circuit 42 outputs a shutdown signal and the high voltage driving circuit 32 outputs a high voltage output terminal H O When a start signal is provided to the first power transistor T1 to turn on the first power transistor T1, the output terminal OUT can output a high voltage HV. At this time, the first diode D1 can prevent reverse voltage. At the same time, the high voltage HV can be loaded to the terminal V S , and the high voltage HV and the charging voltage of the capacitor C can be loaded to the terminal V B .

[0044] According to an embodiment of the present invention, the switch unit 100 may include a bipolar junction transistor or a diode. In particular, when the high voltage unit 30 outputs the high voltage, the driving voltage may be loaded to the node a, and the high voltage HV and the charging voltage of the capacitor C may be loaded to the node b. As a result, the reverse voltage will be loaded to the switch unit 100, thereby preventing the high voltage unit 30 from being in contact with the driving power supply V CC are electrically connected to each other.

[0045] However, since the potential difference between the node a and the node b is as high as the high voltage HV, the switch unit 100 may be broken down. In order to prevent the above phenomenon, a resistance unit 200 may be configured between the switch unit 100 and the high voltage unit 30. The resistance unit 200 may reduce the high voltage HV to a voltage lower than the breakdown voltage of the switch unit 100 during the period of outputting the high voltage HV, thereby preventing the switch unit 100 from being damaged by the reverse voltage.

[0046] See also Figure 2 , the power semiconductor device 10 can be formed on a substrate, such as a semiconductor wafer. Specifically, the low voltage unit 40 can be formed in a manner of surrounding the high voltage unit 30, and a first device separation area 50 and a second device separation area 60 can be formed between the high voltage unit 30 and the low voltage unit 40. In addition, a level shift area 20 equipped with the level shift circuit 22 can be formed between the high voltage unit 30 and the low voltage unit 40. In addition, the switch unit 100 and the resistance unit 200 can be formed between the high voltage unit 30 and the low voltage unit 40. At this time, the resistance unit 200 can be formed between the switch unit 100 and the high voltage unit 30.

[0047] Figure 3 It is used for Figure 2 A schematic cross-sectional view illustrating the switch unit and the resistance unit shown in FIG.

[0048] See also Figure 3 The switch unit 100 may include an NPN-type bipolar junction transistor 110. For example, the bipolar junction transistor 110 may include: an N-type emitter region 112 formed on a substrate 102; a P-type base region 114 formed on the substrate 102; and an N-type collector region 106 formed on the substrate 102. As an example, the substrate 102 may include: a P-type bulk silicon substrate 104; and an N-type epitaxial layer 106 formed on the bulk silicon substrate 104; the N-type emitter region 112, the P-type base region 114, and the N-type collector region 116 may be formed on the upper portion of the N-type epitaxial layer 106.

[0049] The bipolar junction transistor 110 may include: a P-type well region 118 formed in the substrate 102; in the case described above, the N-type emitter region 112 and the P-type base region 114 may be formed on the P-type well region 118. In addition, a first N-type buried layer 120 may be formed in the substrate 102, and the P-type well region 118 may be formed on the first N-type buried layer 120. In the case described above, the first N-type buried layer 120 may be used to reduce the leakage current of the bipolar junction transistor 110.

[0050] Although not shown, the P-type base region 114 may be in a form surrounding the N-type emitter region 112, and the N-type collector region 116 may be in a form surrounding the P-type base region 114. A field oxide layer may be formed between the N-type emitter region 112, the P-type base region 114, and the N-type collector region 116, thereby electrically isolating them from each other.

[0051] The first device separation region 50 may be formed between the low voltage unit 40 and the bipolar junction transistor 110. The first device separation region 50 may include: a first P-type buried layer 52 formed in the substrate 102; a first P-type contact region 54 formed on the substrate 102; and a first P-type impurity diffusion region 56 formed between the first P-type buried layer 52 and the first P-type contact region 54.

[0052] A third device separation region 70 may be formed between the bipolar junction transistor 110 and the resistor unit 200. The third device separation region 70 may include: a third P-type buried layer 72 formed in the substrate 102; a third P-type contact region 74 formed on the substrate 102; and a third P-type impurity diffusion region 76 formed between the third P-type buried layer 72 and the third P-type contact region 74.

[0053] The first device separation region 50 and the third device separation region 70 may be in a ring shape surrounding the bipolar junction transistor 110. In particular, the first N-type buried layer 120, the first P-type buried layer 52, and the third P-type buried layer 72 may be formed between the bulk silicon substrate 104 and the N-type epitaxial layer 106, and the first P-type buried layer 52 and the third P-type buried layer 72 may be formed in a manner of surrounding the first N-type buried layer 120.

[0054] The P-type base region 114 and the N-type collector region 116 can be connected to the driving power source V by means of metal wiring and contact plugs. CC The N-type emitter region 112 can be electrically connected to the resistor unit 200 by means of metal wiring and contact plugs. During the period when the low voltage is output from the low voltage unit 40, current can flow from the P-type base region 114 and the N-type collector region 116 to the N-type emitter region 112, and the current can charge the capacitor C through the resistor unit 200. According to an embodiment of the utility model, an N-type well region 122 can be formed in the substrate 102 in a form surrounding the P-type well region 118. In the above case, the N-type collector region 116 can be formed on the N-type well region 122, thereby reducing the internal resistance of the bipolar junction transistor 110.

[0055] The resistor unit 200 may include: an N-type impurity diffusion region 210 formed in the substrate 102. For example, the N-type impurity diffusion region 210 may be formed on the upper portion of the N-type epitaxial layer 106. In addition, the resistor unit 200 may include: a field oxide layer 220 formed on the substrate. For example, the field oxide layer 220 may be formed on the N-type impurity diffusion region 210. In particular, in the case where the low voltage unit 40 outputs the low voltage, since the forward voltage will be loaded to the bipolar junction transistor 110 and the resistor unit 200, the resistance of the N-type impurity diffusion region 210 can be reduced, and in the case where the high voltage unit 30 outputs the high voltage, since the reverse voltage will be loaded to the bipolar junction transistor 110 and the resistor unit 200, the resistance of the N-type impurity diffusion region 210 can be increased.

[0056] The resistor unit 200 may include: a first N-type contact region 212 formed on one side of the N-type impurity diffusion region 210; and a second N-type contact region 214 formed on the other side of the N-type impurity diffusion region 210. Meanwhile, a first N-type well region 216 may be formed between the first N-type contact region 212 and the N-type impurity diffusion region 210, and a second N-type well region 218 may be formed between the second N-type contact region 214 and the N-type impurity diffusion region 210.

[0057] The first N-type contact region 212 and the second N-type contact region 214 may have a higher impurity concentration than the first N-type well region 216 and the second N-type well region 218. The first N-type contact region 212 may be electrically connected to the switch unit 100 through metal wiring and contact plugs, and the second N-type contact region 214 may be electrically connected to the high voltage unit 30 and the capacitor C through metal wiring and contact plugs.

[0058] The N-type impurity diffusion region 210 may have a lower impurity concentration than the first N-type well region 216 and the second N-type well region 218. In particular, the impurity concentration of the N-type impurity diffusion region 210 may be appropriately adjusted so as to reduce the high voltage to a voltage lower than the breakdown voltage of the switch unit 100 during the period of outputting the high voltage. Specifically, the N-type impurity diffusion region 210 may reduce the high voltage to a voltage lower than the breakdown voltage of the switch unit 100 but higher than the driving voltage. As a result, even if a reverse voltage is applied to the switch unit 100 during the period of applying the high voltage, the switch unit 100 may be prevented from being damaged because the reverse voltage is lower than the breakdown voltage of the switch unit 100.

[0059] A second device separation region 60 may be formed between the high voltage unit 30 and the resistance unit 200. The second device separation region 60 may include: a second P-type buried layer 62 formed in the substrate 102; a second P-type contact region 64 formed on the substrate 102; and a second P-type impurity diffusion region 66 formed between the second P-type buried layer 62 and the second P-type contact region 64.

[0060] A second N-type buried layer 230 for dispersing an electric field formed by the high voltage when the high voltage is applied from the high voltage unit 30 to the second N-type contact region 214 may be formed in the substrate 102. For example, the second N-type buried layer 230 may be formed at the lower side of the second N-type contact region 214 and between the bulk silicon substrate 104 and the N-type epitaxial layer 106.

[0061] A first electrode layer 240 may be formed on the field oxide layer 220 in a manner adjacent to the switch unit 100, and a second electrode layer 242 may be formed in a manner adjacent to the high voltage unit 30. The first electrode layer 240 may be electrically connected to a ground terminal GND, and the second electrode layer 242 may be electrically connected to the high voltage unit 30. For example, the first electrode layer 240 and the second electrode layer 242 may be formed of polysilicon doped with N-type impurities.

[0062] Figure 4 It is used for Figure 3 A schematic cross-sectional view illustrating another example of the resistor unit shown in FIG.

[0063] See also Figure 4 , the resistor unit 200 may include: a P-type impurity diffusion region 250 formed on the N-type impurity diffusion region 210. That is, the P-type impurity diffusion region 250 may be formed between the N-type impurity diffusion region 210 and the field oxide layer 220. In the above case, a depletion layer may be formed between the N-type impurity diffusion region 210 and the P-type impurity diffusion region 250. In particular, during the period when the high voltage unit 30 outputs the high voltage, the depletion layer may be expanded by means of the high voltage loaded to the second N-type contact region 214, thereby increasing the resistance of the resistor unit 200. At the same time, the depletion layer may be formed more uniformly by means of the first electrode layer 240 and the second electrode layer 242.

[0064] Figure 5 It is used for Figure 3 A schematic cross-sectional view illustrating another example of the resistor unit shown in FIG.

[0065] See also Figure 5 The resistor unit 200 may include a resistor layer 260 formed on the field oxide layer 220. One end of the resistor layer 260 may be electrically connected to the switch unit 100, and the other end of the resistor layer 260 may be electrically connected to the high voltage unit 30 and the capacitor C. For example, the resistor layer 260 may be composed of polysilicon doped with N-type impurities, and the impurity concentration of the resistor layer 260 may be appropriately adjusted so as to reduce the high voltage to a voltage lower than the breakdown voltage of the switch unit during the period of outputting the high voltage.

[0066] Figures 6 to 8 It is used for Figure 3 A schematic cross-sectional view illustrating another example of the switch unit shown in FIG.

[0067] See also Figures 6 to 8 The switch unit 100 may include a diode 130 formed on the substrate 102. The diode 130 may include a field oxide layer 132 formed on the substrate 102; an anode layer 134 formed on the field oxide layer 132; and a cathode layer 136 formed on the field oxide layer 132. For example, the anode layer 134 may be composed of polysilicon doped with P-type impurities, and the cathode layer 136 may be composed of polysilicon doped with N-type impurities.

[0068] The anode layer 134 can be connected to the driving power supply V CC The cathode layer 136 can be electrically connected to the resistor unit 200. For example, the cathode layer 136 is Figure 6 as well as Figure 7 As shown, the cathode layer 136 may be electrically connected to the first N-type contact region 212 of the resistor unit 200. As another example, the cathode layer 136 may be electrically connected to the first N-type contact region 212 of the resistor unit 200. Figure 8 As shown, it can be electrically connected to one side end of the resistance layer 260 of the resistance unit 200.

[0069] According to the embodiments of the present invention described above, there is no need to use a separate transistor to prevent the high voltage from being loaded from the high voltage unit 30 to the switch unit 100, so the size of the power semiconductor device 10 can be reduced. In addition, compared with the prior art, the electron moving distance can be reduced, and the resistance of the N-type impurity diffusion region 210 can be reduced, so the power supply voltage V CC The amount of current flowing to the capacitor C.

[0070] In the above content, the preferred embodiments of the present invention are described with reference to each other, but skilled practitioners in the relevant technical field should understand that the present invention can be modified and deformed in various ways without departing from the scope of the idea and purpose of the present invention as recorded in the attached claims.

Claims

1. A power semiconductor device, characterized in that: include: The high voltage unit is configured to output a high voltage; The low voltage unit is configured to output a low voltage; a capacitor, electrically connected to the high voltage unit, and providing power to the high voltage unit during a period of outputting the high voltage; a switch unit, electrically connected to the high voltage unit and the capacitor, for connecting the capacitor to a driving power source in order to charge the capacitor during the period of outputting the low voltage, and for preventing the high voltage unit and the driving power source from being electrically connected to each other during the period of outputting the high voltage; and The resistor unit is electrically connected between the switch unit and the high voltage unit, and reduces the high voltage to a voltage lower than a breakdown voltage of the switch unit during a period of outputting the high voltage.

2. The power semiconductor device according to claim 1, characterized in that: The resistance unit comprises: An N-type impurity diffusion region is formed in the substrate to electrically connect the switch unit and the high voltage unit.

3. The power semiconductor device according to claim 2, characterized in that: The switch unit comprises: Bipolar junction transistor or diode.

4. The power semiconductor device according to claim 2, characterized in that: The resistor unit further includes: A field oxide layer is formed on the substrate.

5. The power semiconductor device according to claim 4, characterized in that: The resistance unit comprises: A P-type impurity diffusion region is formed between the N-type impurity diffusion region and the field oxide layer.

6. The power semiconductor device according to claim 5, characterized in that: The switch unit comprises: Bipolar junction transistor or diode.

7. The power semiconductor device according to claim 4, characterized in that: The resistor unit further includes: a first electrode layer, formed on the field oxide layer in a manner adjacent to the switch unit and electrically connected to a ground terminal; and The second electrode layer is formed on the field oxide layer in a manner adjacent to the high voltage unit and is electrically connected to the high voltage unit.

8. The power semiconductor device according to claim 2, characterized in that: The resistor unit further includes: a first contact region, formed on one side of the N-type impurity diffusion region and electrically connected to the switch unit; and The second contact region is formed on the other side of the N-type impurity diffusion region and is electrically connected to the high voltage unit.

9. The power semiconductor device according to claim 8, characterized in that: The resistor unit further includes: An N-type buried layer is formed at a lower side of the second contact region, and is used to disperse an electric field formed by the high voltage when the high voltage is applied to the second contact region.

10. The power semiconductor device according to claim 1, characterized in that: The resistance unit comprises: a field oxide layer formed on a substrate; and A resistance layer is formed on the field oxide layer.

11. The power semiconductor device according to claim 10, characterized in that: The resistance layer, Made of polysilicon doped with N-type impurities.

12. The power semiconductor device according to claim 10, characterized in that: The switch unit comprises: Bipolar junction transistor or diode.

13. A power semiconductor device, characterized in that: include: The high voltage unit is configured to output a high voltage; The low voltage unit is configured to output a low voltage; a capacitor, electrically connected to the high voltage unit, and providing power to the high voltage unit during a period of outputting the high voltage; a bipolar junction transistor, electrically connected to the high voltage unit and the capacitor, connected between the capacitor and a driving power source in order to charge the capacitor during the period of outputting the low voltage, and used to prevent the high voltage unit and the driving power source from being electrically connected to each other during the period of outputting the high voltage; and The resistor unit is electrically connected between the bipolar junction transistor and the high voltage unit, and reduces the high voltage to a voltage lower than a breakdown voltage of the bipolar junction transistor during a period of outputting the high voltage.

14. The power semiconductor device according to claim 13, characterized in that: The bipolar junction transistor comprises: An N-type emitter region is formed on the substrate; A P-type base region is formed on the substrate; and An N-type collector region is formed on the substrate; The P-type base region and the N-type collector region are electrically connected to the driving power source, The N-type emitter region is electrically connected to the resistor unit.

15. The power semiconductor device according to claim 14, characterized in that: The bipolar junction transistor further comprises: A P-type well region is formed in the substrate; The N-type emitter region and the P-type base region are formed on the P-type well region.

16. The power semiconductor device according to claim 15, characterized in that: The bipolar junction transistor further comprises: An N-type buried layer is formed in the substrate; The P-type well region is formed on the N-type buried layer.

17. The power semiconductor device according to claim 14, characterized in that: The P-type base region is in a ring shape surrounding the N-type emitter region. The N-type collector region is in a ring shape surrounding the P-type base region.

18. A power semiconductor device, characterized in that: include: The high voltage unit is configured to output a high voltage; The low voltage unit is configured to output a low voltage; a capacitor, electrically connected to the high voltage unit, and providing power to the high voltage unit during a period of outputting the high voltage; a diode electrically connected to the high voltage unit and the capacitor, connected between the capacitor and a driving power source in order to charge the capacitor during the period of outputting the low voltage, and used to prevent the high voltage unit and the driving power source from being electrically connected to each other during the period of outputting the high voltage; and The resistor unit is electrically connected between the diode and the high voltage unit, and reduces the high voltage to a voltage lower than a breakdown voltage of the diode during a period of outputting the high voltage.

19. The power semiconductor device according to claim 18, characterized in that: The diode comprises: A field oxide layer is formed on the substrate; an anode layer formed on the field oxide layer; and a cathode layer formed on the field oxide layer; The anode layer is electrically connected to the driving power source, The cathode layer is electrically connected to the resistor unit.

20. The power semiconductor device according to claim 19, characterized in that: The anode layer is composed of polysilicon doped with P-type impurities. The cathode layer is made of polysilicon doped with N-type impurities.

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