Array substrate and display device

Abstract

The utility model discloses an array substrate and a display device. The array substrate further comprises a substrate, a data line, a data connection electrode and a first transistor, and the data line, the data connection electrode and the first transistor are all located in a display area. The first transistor comprises a first active layer, the first active layer is located on the side, away from the substrate, of the data line, and a part of the data connection electrode is located on the side, away from the substrate, of the first active layer; the array substrate further comprises a through hole, and the orthographic projection of the through hole in the plane where the substrate is located is located in the orthographic projection of at least one data line in the plane where the substrate is located. The hole wall of the through hole and part of the side wall of the first active layer are shared, and only part of the side wall of the first active layer is exposed out of the through hole; at least part of the data connection electrode is located in the through hole and connected with part of the side wall and the data line, and the pixel density can be improved.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid Crystal Display (LCD) is a common type of display. LCD uses two polarized materials with a liquid crystal solution (liquid crystal) between them. When voltage is applied to the two polarized materials, the liquid crystal will deflect. By controlling the applied voltage, the degree of liquid crystal deflection can be adjusted. Currently, liquid crystal displays (LCD) are developing towards the goal of being light, thin, short and small. Utility Model Content

[0003] The embodiments of the utility model provide an array substrate and a display device, which can solve the problems of low pixel density of existing display devices.

[0004] On the one hand, an embodiment of the utility model provides an array substrate, comprising a display area and a frame area located at least on one side of the display area; the array substrate further comprises a substrate, at least one data line located on the substrate, at least one data connection electrode located on the substrate, and at least one first transistor located on the substrate, and the at least one data line, the at least one data connection electrode, and the at least one first transistor are all located in the display area; the first transistor comprises a first active layer, and the first active layer is located on a side of the data line away from the substrate, and a portion of the data connection electrode is located on a side of the first active layer away from the substrate;

[0005] The array substrate further comprises at least one through hole, the orthographic projection of the at least one through hole on the plane where the substrate is located is located within the orthographic projection of the at least one data line on the plane where the substrate is located; the hole wall of the at least one through hole is shared with a portion of the side wall of the first active layer, and the through hole only exposes the portion of the side wall of the first active layer; wherein at least a portion of the data connection electrode is located within the through hole and is connected to both the portion of the side wall and the data line.

[0006] In some exemplary embodiments, the at least one first transistor further includes a first gate and an auxiliary gate; the first gate is located on a side of the first active layer away from the substrate, and the auxiliary gate is located on a side of the first active layer close to the substrate; wherein the material of the auxiliary gate is a transparent conductive material.

[0007] In some exemplary embodiments, the auxiliary gate has a first size in the orthographic projection of the plane where the substrate is located, and the first size is greater than or equal to 4 microns; wherein the direction of the first size is perpendicular to the extension direction of the orthographic projection of the first active layer in the plane where the substrate is located.

[0008] In some exemplary embodiments, the first active layer includes a first region, a first channel region and a second region which are connected to each other, and the first region and the second region are respectively located on opposite sides of the first channel region; wherein the orthographic projection of the first channel region on the plane where the substrate is located is located within the orthographic projection of the auxiliary gate on the plane where the substrate is located.

[0009] In some exemplary embodiments, the orthographic projection of the first channel region on the plane where the substrate is located has a third size, and the third size is smaller than the first size; wherein the direction of the third size is perpendicular to the extension direction of the orthographic projection of the first active layer on the plane where the substrate is located.

[0010] In some exemplary embodiments, the third dimension is 70% to 80% of the first dimension.

[0011] In some exemplary embodiments, the at least one first transistor also includes a first gate, which is located on a side of the first active layer away from the substrate; the first active layer includes a first region, a first channel region and a second region that are connected to each other, and the first region and the second region are respectively located on opposite sides of the first channel region; wherein the orthographic projection of the first gate on the plane where the substrate is located is located within the orthographic projection of the first channel region on the plane where the substrate is located.

[0012] In some exemplary embodiments, the orthographic projection of the first channel region on the plane where the substrate is located has a third size, and the orthographic projection of the first gate on the plane where the substrate is located has a fourth size; wherein the fourth size is smaller than the third size; wherein the direction of the third size and the direction of the fourth size are both perpendicular to the extension direction of the orthographic projection of the first active layer on the plane where the substrate is located.

[0013] In some exemplary embodiments, the fourth dimension is 60% to 70% of the third dimension.

[0014] In some exemplary embodiments, the array substrate also includes at least one insulating layer, and a portion of the at least one insulating layer is located between the first gate and the first active layer, and a portion of the at least one insulating layer is in contact with the first gate; the portion of the at least one insulating layer includes a first region and a second region, and the orthographic projection of the first gate on the plane where the substrate is located is located within the orthographic projection of the first region on the plane where the substrate is located; wherein the first region has a first surface away from the substrate, the second region has a second surface away from the substrate, and the first surface is farther away from the substrate than the second surface.

[0015] In some exemplary embodiments, along a thickness direction of the array substrate, a distance between the first surface and the second surface is 25% to 40% of a maximum thickness of a portion of the at least one insulating layer.

[0016] In some exemplary embodiments, the array substrate further includes a color filter layer, and the color filter layer is located on a side of the first transistor away from the substrate.

[0017] In some exemplary embodiments, the array substrate also includes at least one second transistor, at least one first connection line and at least one second connection line, and the at least one second transistor, the at least one first connection line and the at least one second connection line are all located in the border area; wherein the first connection line and the second connection line are both connected to the second transistor; the first connection line and the second connection line are located in the same conductive layer as the data connection electrode; or, the first connection line and the second connection line are located in the same conductive layer as the data line; or, the first connection line and the second connection line are located in the conductive layer on the side of the data connection electrode away from the substrate.

[0018] In some exemplary embodiments, the at least one second transistor includes a second active layer and a second gate; the second active layer and the second gate are both located between the data line and the substrate; or, the second active layer and the second gate are both located between the data line and the first active layer.

[0019] On the other hand, an embodiment of the present invention provides a display device, comprising the array substrate described in any one of the above embodiments.

[0020] Other features and advantages of the utility model will be described in the following description, and partly become apparent from the description, or understood by implementing the utility model. Other advantages of the utility model can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide an understanding of the technical solution of the utility model and constitute a part of the specification. Together with the embodiments of the utility model, they are used to explain the technical solution of the utility model and do not constitute a limitation on the technical solution of the utility model.

[0022] Figure 1 is a partial cross-sectional schematic diagram of a display device;

[0023] Figure 2 is a partial cross-sectional schematic diagram of an array substrate;

[0024] Figure 3 is a partial top view schematic diagram of an array substrate;

[0025] Figure 4 This is a schematic front view of an array substrate according to an embodiment of the utility model;

[0026] Figure 5 It is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the utility model;

[0027] Fig. 6A It is a partial cross-sectional schematic diagram of an array substrate after forming a first conductive layer pattern in an embodiment of the utility model;

[0028] Figure 6B It is a partial cross-sectional schematic diagram of an array substrate after forming a second semiconductor layer pattern in one embodiment of the utility model;

[0029] Figure 6C It is a partial cross-sectional schematic diagram of an array substrate after forming a second conductive layer pattern in one embodiment of the utility model;

[0030] Fig.6D It is a partial cross-sectional schematic diagram of an array substrate after forming a first semiconductor layer pattern in one embodiment of the utility model;

[0031] Fig. 6E It is a partial cross-sectional schematic diagram of an array substrate after an initial pattern of a fourth insulating layer is formed on the array substrate according to an embodiment of the utility model;

[0032] Fig. 6F It is a partial cross-sectional schematic diagram of an array substrate after an initial pattern of a third conductive layer is formed in an embodiment of the utility model;

[0033] Figure 6G This is a schematic diagram of a first active layer of an array substrate after being conductively converted according to an embodiment of the utility model;

[0034] Figure 6H It is a partial cross-sectional schematic diagram of an array substrate after a third conductive layer pattern is formed on the array substrate according to an embodiment of the utility model;

[0035] Fig.6IIt is a partial cross-sectional schematic diagram of an array substrate after a sixth insulating layer pattern is formed on the array substrate according to an embodiment of the utility model;

[0036] Figure 6J It is a partial cross-sectional schematic diagram of an array substrate after a seventh insulating layer pattern is formed on the array substrate according to an embodiment of the utility model;

[0037] Figure 6K It is a partial cross-sectional schematic diagram of an array substrate after a fifth conductive layer pattern is formed on the array substrate according to an embodiment of the utility model;

[0038] Figure 6L It is a partial cross-sectional schematic diagram of an array substrate after a sixth conductive layer pattern is formed on the array substrate according to an embodiment of the utility model;

[0039] Figure 6M It is a partial cross-sectional schematic diagram of an array substrate after forming a spacer column pattern according to an embodiment of the utility model;

[0040] Figure 7 It is a partial cross-sectional schematic diagram of an array substrate of another embodiment of the utility model;

[0041] Figure 8 A partial cross-sectional schematic diagram of an array substrate according to another embodiment of the utility model;

[0042] Fig. 9A It is a partial cross-sectional schematic diagram of an array substrate after forming an initial pattern of a fourth insulating layer according to another embodiment of the utility model;

[0043] Fig. 9B This is a partial cross-sectional schematic diagram of an array substrate after a third conductive layer pattern is formed in another embodiment of the utility model;

[0044] Fig. 9C It is a partial cross-sectional schematic diagram of an array substrate after forming an initial pattern of a fifth insulating layer according to another embodiment of the utility model;

[0045] Fig.9D This is a partial cross-sectional schematic diagram of an array substrate after a seventh conductive layer pattern is formed according to another embodiment of the utility model;

[0046] Fig.9E It is a partial cross-sectional schematic diagram of an array substrate after forming a spacer column pattern according to another embodiment of the utility model;

[0047] Fig.10 This is a partial cross-sectional schematic diagram of an array substrate according to yet another embodiment of the utility model;

[0048] Fig.11 It is a partial cross-sectional schematic diagram of an array substrate of another embodiment of the utility model;

[0049] Fig.12 A partial cross-sectional schematic diagram of an array substrate according to another embodiment of the utility model;

[0050] Fig.13 This is a partial cross-sectional schematic diagram of an array substrate integrated with a color filter layer according to an embodiment of the utility model;

[0051] Fig.14 It is a partial cross-sectional schematic diagram of an array substrate integrated with a color filter layer according to another embodiment of the utility model;

[0052] Fig.15 This is a partial cross-sectional schematic diagram of an array substrate integrated with a color filter layer according to another embodiment of the utility model;

[0053] Fig.16 The present invention is a partial cross-sectional schematic diagram of an array substrate integrated with a color filter layer in yet another embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical scheme and advantages of the utility model clearer, the embodiments of the utility model will be described in detail in conjunction with the accompanying drawings below. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the utility model. Therefore, the utility model should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the utility model and the features in the embodiments can be combined with each other arbitrarily.

[0055] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present invention is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present invention is not limited to the shapes or values ​​shown in the drawings.

[0056] The ordinal numbers such as "first", "second", "third" and the like in the present invention are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present invention includes two and more than two.

[0057] In the present utility model, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0058] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in the present invention can be understood according to the circumstances.

[0059] In the present invention, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present invention, the channel region refers to a region where current mainly flows.

[0060] In the present invention, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present invention, the "source electrode" and the "drain electrode" may be interchanged.

[0061] In the present utility model, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0062] In the present invention, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle may be greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle may be greater than 85° and less than 95°.

[0063] In the present invention, "film" and "layer" can be interchanged. For example, "conductive layer" can be replaced by "conductive film" in some cases. Similarly, "insulating film" can be replaced by "insulating layer" in some cases.

[0064] The term "approximately" in the present invention means that the limits are not strictly defined and the numerical value is allowed to be within the range of process and measurement errors.

[0065] In recent years, the application fields of virtual reality (VR) technology and augmented reality (AR) technology have been increasingly diversified, and the market demand for VR products and AR products has grown rapidly. The display panel is one of the core hardware of VR products and AR products. VR products and AR products need to restore real scenes. Therefore, VR products and AR products have higher and higher requirements for the pixel density (Pixels Per Inch, PPI) of the display panel. Generally, VR products and AR products require the pixel density of the display panel to be higher than 1500PPI. The higher the PPI requirement for the display panel, the smaller the area occupied by a single sub-pixel. As the size of a single sub-pixel decreases, the opening area of ​​the sub-pixel also decreases, which leads to a decrease in the aperture ratio of the display panel and reduces the brightness of the display panel, thereby restricting the improvement and application of the display performance of AR products and VR products.

[0066] Figure 1 FIG. 1 is a partial cross-sectional schematic diagram of a display device. Figure 1 As shown, the display device may include an array substrate 100 and an opposing substrate 200 disposed opposite to each other, and a liquid crystal layer 300 located between the array substrate 100 and the opposing substrate 200. The opposing substrate 200 may include a base substrate 201 and a black matrix 202 and a color filter layer 203 disposed on the base substrate 201.

[0067] In the manufacturing process of the display device, it is usually necessary to perform a cell-aligning operation on the array substrate 100 and the counter substrate 200. Due to the limitation of the cell-aligning operation precision, the size D2 of the black matrix 202 is required to be larger than the size D1 of the uncontrollable area of ​​the liquid crystal layer 300 in design to prevent light leakage. However, increasing the size of the black matrix 202 will result in a decrease in the aperture ratio of the display device.

[0068] Typically, the array substrate 100 includes a plurality of sub-pixel regions, and one sub-pixel region may correspond to one sub-pixel region. The sub-pixel region may include an opening region and a non-opening region surrounding the opening region. The non-opening region may be an area blocked by the black matrix 202 of the opposing substrate 200 of the array substrate 100, and the opening region may be an area not blocked by the black matrix 202 of the opposing substrate 200. The array substrate 100 includes a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers include a plurality of conductive wires, and the plurality of insulating layers are provided with a plurality of vias for realizing electrical connection of the conductive wires. The plurality of conductive wires and the plurality of vias are arranged in the non-opening region as much as possible, and reducing the size of the conductive wires can reduce the size of the black matrix, which helps to improve the aperture ratio. However, in the actual production of the product, the size of the conductive wire is limited by the production equipment and process capabilities. As the size of the conductive wire approaches the production limit of the equipment, the aperture ratio cannot be further improved.

[0069] Figure 2 is a partial cross-sectional schematic diagram of an array substrate, Figure 3 FIG. 1 is a partial top view schematic diagram of an array substrate. Figure 2 , Figure 3 As shown, an array substrate 100 can improve the display brightness of a display device by improving the transmittance of an opening area, and the array substrate 100 may include a connecting lead 101, a gate 102, and an auxiliary gate 103. The material of the auxiliary gate 103 is set to be a transparent conductive material to improve the transmittance of the opening area, and the size of the gate 102 is reduced to improve the transmittance of the opening area.

[0070] However, the array substrate 100 has the following problems: (1) There is a minimum distance a between the connecting lead 101 and the auxiliary gate 103, which cannot meet the electrical requirements, resulting in a short circuit between the connecting lead 101 and the auxiliary gate 103. (2) There is a minimum distance b between the via D and the auxiliary gate 103, which cannot meet the electrical requirements, resulting in a short circuit between the auxiliary gate 103 and the connecting electrode 104. (3) There is a minimum distance c between the via D and the gate 102, which cannot meet the electrical requirements, resulting in a short circuit between the gate 102 and the connecting electrode 104.

[0071] Therefore, an embodiment of the utility model provides an array substrate, comprising a display area and a frame area located at least on one side of the display area; the array substrate further comprises a substrate, at least one data line located on the substrate, at least one data connection electrode located on the substrate, and at least one first transistor located on the substrate, and the at least one data line, the at least one data connection electrode, and the at least one first transistor are all located in the display area; the first transistor comprises a first active layer, and the first active layer is located on a side of the data line away from the substrate, and a portion of the data connection electrode is located on a side of the first active layer away from the substrate;

[0072] The array substrate further comprises at least one through hole, the orthographic projection of the at least one through hole on the plane where the substrate is located is located within the orthographic projection of the at least one data line on the plane where the substrate is located; the hole wall of the at least one through hole is shared with a portion of the side wall of the first active layer, and the through hole only exposes the portion of the side wall of the first active layer; wherein at least a portion of the data connection electrode is located within the through hole and is connected to both the portion of the side wall and the data line.

[0073] In the embodiment of the utility model, by arranging the data line between the first transistor and the substrate and designing the position of the through hole, the size of the through hole can be reduced while ensuring the connection reliability, which is beneficial to improving the pixel density of the array substrate.

[0074] Figure 4 FIG. 1 is a schematic front view of an array substrate according to an embodiment of the present utility model. Figure 4 As shown, the array substrate may include a display area AA and a frame area BB located on at least one side of the display area AA. The frame area BB may include a first frame area B1 located on one side of the display area AA and a second frame area B2 located on the remaining sides of the display area AA. For example, the first frame area B1 may include a lower frame of the array substrate, and the second frame area B2 may include an upper frame, a left frame, and a right frame of the array substrate. In the embodiment of the utility model, the frame area may also be referred to as a non-display area.

[0075] In an exemplary embodiment, if Figure 4As shown, the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect, for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers, for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL close to the substrate.

[0076] In an exemplary embodiment, if Figure 4 As shown, a plurality of data lines DL and a plurality of gate lines GL may cross to form a plurality of sub-pixel regions. The region defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel region. A sub-pixel may be correspondingly arranged in the sub-pixel region. The sub-pixel region may include an opening region and a non-opening region surrounding the opening region. The non-opening region may be a region blocked by the black matrix of the opposing substrate of the array substrate, and the opening region may be a region not blocked by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL may both be located in the non-opening region. The array substrate of the embodiment of the utility model may be used to realize a display function, and the opening region of each sub-pixel region may be configured to display. The non-opening region may surround the opening region and not display. However, the embodiment of the utility model is not limited to this. In some examples, the array substrate may be used to realize other functions.

[0077] In an exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged in sequence in the order of the blue sub-pixel, the red sub-pixel, and the green sub-pixel. Figure 4 As shown, at least one sub-pixel may include: a pixel electrode 10 and a common electrode ( Figure 4Not shown), and the pixel electrode 10 of the sub-pixel and the common electrode may partially overlap in the positive projection of the substrate. For example, the common electrode of multiple sub-pixels in the display area AA may be an integrated structure. For example, the common electrode may be located on the side of the pixel electrode 10 away from the substrate. The sub-pixel may also include a first transistor 21. The first transistor 21 may be adjacent to the intersection of the data line DL and the gate line GL. The first transistor 21 may include a first gate, a first pole, and a second pole. The first gate may be electrically connected to the gate line GL, the first pole of the first transistor 21 may be electrically connected to the data line DL, and the second pole may be electrically connected to the pixel electrode 10 of a sub-pixel. The first transistor 21 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0078] In an exemplary embodiment, the second frame area B2 may include at least a gate drive circuit (e.g., including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to a plurality of gate lines GL in the display area AA. The gate drive circuit may also include a second transistor. The structure of the second transistor located in the second frame area B2 may be the same as or different from the structure of the first transistor located in the display area AA.

[0079] Figure 5 FIG. 1 is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present utility model. Figure 5 As shown, the array substrate may include a substrate 20, a plurality of conductive layers located on the substrate 20, a plurality of insulating layers located on the substrate 20, and a plurality of semiconductor layers located on the substrate 20. The plurality of conductive layers may include a first conductive layer to a sixth conductive layer, the plurality of insulating layers may include a first insulating layer to an eighth insulating layer, and the plurality of semiconductor layers may include a first semiconductor layer and a second semiconductor layer.

[0080] In a plane perpendicular to the plane where the substrate 20 is located, in a direction away from the substrate 20, the array substrate may include a first conductive layer, a first insulating layer 1, a second semiconductor layer, a second insulating layer 2, a second conductive layer, a third insulating layer 3, a first semiconductor layer, a fourth insulating layer 4, a third conductive layer, a fifth insulating layer 5, a sixth insulating layer 6, a fourth conductive layer, a seventh insulating layer 7, a fifth conductive layer, a sixth conductive layer and an eighth insulating layer 8 which are stacked in sequence. In the embodiment of the utility model, the first insulating layer 1 may also be referred to as a buffer layer, the second insulating layer 2 may also be referred to as a first gate insulating layer (GI1), the third insulating layer 3 may also be referred to as a first interlayer insulating layer (ILD1), the fourth insulating layer 4 may also be referred to as a second gate insulating layer (GI2), the fifth insulating layer 5 may also be referred to as a second interlayer insulating layer (ILD2), the sixth insulating layer 6 may also be referred to as a third interlayer insulating layer (ILD3), the seventh insulating layer 7 may also be referred to as a planar (PLN) layer, and the eighth insulating layer 8 may also be referred to as a passivation (PVX) layer.

[0081] The first conductive layer may include at least one data line DL, and the at least one data line DL is located within the display area AA. Designing the data line DL close to the substrate 20 can increase the distance between the data line DL and other signal lines, for example, the distance between the data line DL and the first gate 15 can be increased, for example, the distance between the data line DL and the common electrode 30 can be increased, the parasitic capacitance generated between the two signal lines can be reduced or avoided, and the charging efficiency can be improved.

[0082] The second conductive layer may include at least one auxiliary gate 13 and at least one second gate 16, and at least one auxiliary gate 13 is located within the display area AA, and at least one second gate 16 is located within the second frame area B2. The third conductive layer may include at least one data connection electrode 14, and at least one data connection electrode 14 is located within the display area AA, and the first active layer 11 of the first transistor 21 may be connected to the data line DL via the data connection electrode 14, and the first active layer 11 is located in the first semiconductor layer. The third conductive layer may include at least one gate line GL and at least one first gate 15, and at least one gate line GL and at least one first gate 15 are located within the display area AA. For example, the gate line GL and the first gate 15 may be an integrated structure connected to each other. In the embodiment of the utility model, the auxiliary gate 13 and the first gate 15 are respectively located on both sides of the first active layer 11, so that the first transistor 21 forms a dual-gate structure. In the embodiment of the utility model, the auxiliary gate can also be called the bottom gate of the first transistor, and the first gate can also be called the top gate of the first transistor. The material of the auxiliary gate can be a transparent conductive material, and the material of the first gate can be a metal conductive material, which can not only improve the transmittance of light, but also improve the performance stability of the transistor.

[0083] The third conductive layer may further include at least one first connection line 17 and at least one second connection line 18, and at least one first connection line 17 and at least one second connection line 18 are both located within the second frame area B2. The first connection line 17 and the second connection line 18 are both connected to the second active layer 12 of the second transistor 22, and the second active layer 12 is located in the second semiconductor layer. The fourth conductive layer may include at least one first connection electrode 31, and the fifth conductive layer may include at least one second connection electrode 32, and the first connection electrode 31 and the second connection electrode 32 are both located within the display area AA and connected. The first connection electrode 31 is connected to the first active layer 11 of the first transistor 21, and the second connection electrode 32 is connected to the pixel electrode 10 located in the sixth conductive layer, and the pixel electrode 10 is located within the display area AA. In an exemplary embodiment, the array substrate may further include a light shielding portion CM, and the light shielding portion CM is located on the side of the eighth insulating layer 8 away from the substrate 20. For example, the material of the light shielding portion CM may include a metal material, and for example, the metal material may include chromium or molybdenum. The light shielding portion CM can be used to avoid light crosstalk between two adjacent sub-pixels, thereby improving the display quality of the display device.

[0084] In an exemplary embodiment, the array substrate may further include isolation columns PS, and the isolation columns PS may be arranged in groups corresponding to the light shielding portions CM. The isolation columns PS may be located on a side of the light shielding portion CM away from the substrate 20, and the orthographic projection of the isolation columns PS on the plane where the substrate 20 is located may be located within the orthographic projection of the light shielding portion CM on the plane where the substrate 20 is located. During the cell alignment operation of the array substrate and the counter substrate, the isolation columns may be used for positioning during the cell alignment operation.

[0085] In an exemplary embodiment, the first active layer 11 may include a top wall 11a and a bottom wall 11c that are arranged opposite to each other, and the top wall 11a is farther away from the substrate 20 than the bottom wall 11c. The first active layer 11 may also include a side wall 11b, and the side wall 11b is located between the top wall 11a and the bottom wall 11c, and the top wall 11a and the bottom wall 11c are connected via the side wall 11b. The array substrate may also include at least one through hole K, and the through hole K is arranged in a group corresponding to the first transistor 21, and the through hole K is used to realize the connection between the data connection electrode 14 and the first transistor 21 and the data line DL. The orthographic projection of at least one through hole K in the plane where the substrate 20 is located is located within the orthographic projection of at least one data line DL in the plane where the substrate is located. The hole wall of at least one through hole K is shared with a part of the side wall of the first active layer 11, and the through hole K only exposes a part of the side wall of the first active layer 11, and at least a part of the data connection electrode 14 is located in the through hole K and is connected to a part of the side wall and the data line DL. In the embodiment of the utility model, by setting the through hole close to the side wall of the first active layer, the distance between the data connection electrode and the first gate can be increased, and the distance between the data connection electrode and the auxiliary gate can be increased, so that the short circuit between the data connection electrode and the first gate and the short circuit between the data connection electrode and the auxiliary gate can be avoided, and the reliability of the electrical connection of the array substrate can be improved.

[0086] The following is an exemplary description of the preparation process of the array substrate. The "patterning process" mentioned in the utility model includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited by the utility model. "Thin film" refers to a layer of thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the array substrate. In an exemplary embodiment of the present invention, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0087] The preparation process of the array substrate may include the following steps:

[0088] (01) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: depositing a first conductive film on one side of the substrate 20, and patterning the first conductive film through a patterning process so that the first conductive film forms a first conductive layer pattern located on one side of the substrate 20. The first conductive layer may include at least one data line GL, such as Fig. 6A shown.

[0089] In an exemplary embodiment, the substrate 20 may be a transparent substrate. For example, the substrate 20 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the embodiments of the utility model are not limited thereto. The substrate 20 may be a single layer or a composite layer structure. For example, the substrate 20 may be a composite layer structure of a rigid substrate and a flexible substrate.

[0090] In an exemplary embodiment, the material of the first conductive layer may include a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. Alternatively, it may be an alloy material of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb) or molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti or Mo / Nb / Cu or MoNiTi / Cu or MoNb / Cu / MoNiTi or MoNiTi / Cu / MoNiTi, etc.

[0091] In an exemplary embodiment, the data line GL can be designed with non-uniform line widths. For example, the portion where the data line GL is connected to the first transistor can be widened, which can improve the reliability of the connection between the data line and the first transistor and improve the rationality of the wiring as a whole.

[0092] (02) Forming a second semiconductor layer pattern. Forming the second semiconductor layer pattern may include: depositing a first insulating film 1-1 and a second semiconductor film in sequence on one side of the substrate 20, and patterning the second semiconductor film through a patterning process so that the second semiconductor film forms a second semiconductor layer pattern located on a side of the first insulating film 1-1 away from the substrate 20, such as Figure 6B The second semiconductor layer may include a second active layer 12 of at least one second transistor 22 .

[0093] In an exemplary embodiment, the material of the second semiconductor film may include one or more of indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), indium gallium zinc Y oxide (IGZYO, Y represents doped tin), etc. In an example, the material of the second semiconductor film may include various materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc. The array substrate provided in the embodiment of the utility model is suitable for transistors manufactured based on oxide technology, silicon technology and organic technology.

[0094] In an exemplary embodiment, the material of the first insulating film may include an inorganic material. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x ) and the like. The first insulating film may be a single layer or a multi-layer or a composite layer structure. For example, the first insulating film may include two film layers.

[0095] (03) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a second insulating film 2-1 and a second conductive film on one side of the substrate 20, and patterning the second conductive film through a patterning process so that the second conductive film forms a second conductive layer pattern located on a side of the second insulating film 2-1 away from the substrate 20. The second conductive layer may include at least one second gate 16 and at least one auxiliary gate 13, such as Figure 6C shown.

[0096] In an exemplary embodiment, the material of the second conductive film may be a transparent conductive oxide material, and the transparent conductive oxide material may include indium tin oxide (ITO) or indium zinc oxide (IZO), etc. For example, the second conductive layer may be a single-layer structure, or a multi-layer composite structure, such as ITO / Al / ITO, etc.

[0097] In some possible exemplary embodiments, the second gate 16 and the auxiliary gate 13 are both located in the second conductive layer, but the material of the second gate 16 is different from that of the auxiliary gate 13. The material of the auxiliary gate 13 may be a transparent conductive oxide material. The material of the second gate 16 may include a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. Alternatively, it may be an alloy material of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc.

[0098] In an exemplary embodiment, the material of the second insulating film may be the same as or different from the material of the first insulating film.

[0099] In an exemplary embodiment, forming the second conductive layer pattern may further include conducting the second active layer 12 so that portions of the second active layer 12 form a third region 12-3 and a fourth region 12-4, respectively. The third region 12-3 may be used as a first electrode of the second transistor 22, and the fourth region 12-4 may be used as a second electrode of the second transistor 22. The region of the second active layer 12 other than the third region 12-3 and the fourth region 12-4 becomes a second channel region 12-2.

[0100] In an exemplary embodiment, in the plane where the substrate 20 is located, the orthographic projection of the auxiliary gate 13 has a first size L1. The larger L1 is, the more conducive it is to the stability of the first transistor, and the auxiliary gate is not prone to defects such as peeling. The first size L1 can be equal to 4 microns, or greater than 4 microns, etc. For example, the first size L1 can be 5 microns, or 6 microns, etc. In the embodiment of the utility model, the direction of the first size L1 is perpendicular to the extension direction of the orthographic projection of the first active layer formed subsequently on the plane where the substrate is located.

[0101] (04) Forming a first semiconductor layer pattern. Forming the first semiconductor layer pattern may include: depositing a third insulating film 3-1 and a first semiconductor film in sequence on one side of the substrate 20, and patterning the first semiconductor film through a patterning process so that the first semiconductor film forms a first semiconductor layer pattern located on a side of the third insulating film 3-1 away from the substrate 20. The first semiconductor layer may include at least one first active layer 11, such as Fig.6D shown.

[0102] The orthographic projection of the first active layer 11 on the plane where the substrate 20 is located may include the orthographic projection of the auxiliary gate 13 on the plane where the substrate 20 is located, and the orthographic projection area of ​​the first active layer 11 on the plane where the substrate 20 is located is larger than the orthographic projection area of ​​the auxiliary gate 13 on the plane where the substrate 20 is located.

[0103] In an exemplary embodiment, the material of the first semiconductor thin film and the material of the second semiconductor thin film may be the same as or different from each other.

[0104] (05) Forming a fourth insulating layer initial pattern. Forming the fourth insulating layer initial pattern may include: depositing a fourth insulating film on one side of the substrate 20, patterning the fourth insulating film through a patterning process to form a fourth insulating layer initial pattern 4-1, and making the first insulating film 1-1 form a first insulating layer 1, making the third insulating film 3-1 form a third insulating layer 3, and making the second insulating film 2-1 form a second insulating layer 2, such as Fig. 6EThe array substrate may include a plurality of via holes, and the plurality of via holes may include at least a first via hole K1, a second via hole K2, and a third via hole K3. In the embodiment of the utility model, the third via hole K3 is a through hole for connecting the data connection electrode with the data line and the first active layer.

[0105] The second insulating film, the third insulating film and the fourth insulating film within the first via hole K1 are all etched away, exposing a portion of the surface of the third region 12-3, and the first via hole K1 is configured so that a first connecting line formed subsequently can be connected to the third region 12-3 through the via hole.

[0106] The second insulating film, the third insulating film and the fourth insulating film within the second via hole K2 are all etched away, exposing a portion of the surface of the fourth region 12-4, and the second via hole K2 is configured so that a second connecting line formed subsequently can be connected to the fourth region 12-4 through the via hole.

[0107] The first insulating film, the second insulating film, the third insulating film and the fourth insulating film within the third via hole K3 are all etched away, exposing part of the surface of the data line DL, and the third via hole K3 is configured so that the subsequently formed data connection electrode can be connected to the data line DL through the via hole.

[0108] In an exemplary embodiment, the orthographic projection of the third via hole K3 on the plane where the substrate 20 is located partially overlaps with the orthographic projection of the data line DL on the plane where the substrate 20 is located and the orthographic projection of the first active layer 11 on the plane where the substrate 20 is located. The third via hole K3 exposes part of the first active layer 11, so that the data connection electrode formed subsequently can be connected to the first active layer 11 through the via hole, thereby realizing the connection between the first active layer and the data line.

[0109] In an exemplary embodiment, the orthographic projection of the third via K3 on the plane where the substrate 20 is located is located within the orthographic projection of the data line DL on the plane where the substrate 20 is located, and the edge of the orthographic projection of the third via K3 on the plane where the substrate 20 is located partially overlaps with the edge of the orthographic projection of the first active layer 11 on the plane where the substrate 20 is located, which can reduce the size of the third via hole and is beneficial to improving the opening ratio of the array substrate.

[0110] In an exemplary embodiment, the material of the fourth insulating film may be the same as or different from the material of the first insulating film.

[0111] (06) Forming an initial pattern of the third conductive layer. Forming the initial pattern of the third conductive layer may include: sequentially forming a third conductive film and a photoresist layer on one side of the substrate 20, exposing the photoresist layer to ultraviolet light using a mask to form a photoresist pattern PR, and then performing an etching process to form the initial pattern of the third conductive layer on the third conductive film, such as Fig. 6F As shown, for example, the etching process may be dry etching.

[0112] The third conductive layer preliminary pattern may include at least one first connection line 17 , at least one second connection line 18 , at least one data connection electrode 14 , and at least one conductive structure 19 .

[0113] The orthographic projection of the first connecting line 17 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the first via K1 on the plane where the substrate 20 is located. For example, the orthographic projection of the first connecting line 17 on the plane where the substrate 20 is located includes the orthographic projection of the first via K1 on the plane where the substrate 20 is located. A portion of the first connecting line 17 is located within the first via K1 and is connected to the third area 12-3.

[0114] The orthographic projection of the second connection line 18 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the second via K2 on the plane where the substrate 20 is located. For example, the orthographic projection of the second connection line 18 on the plane where the substrate 20 is located includes the orthographic projection of the second via K2 on the plane where the substrate 20 is located. A portion of the second connection line 18 is located within the second via K2 and is connected to the fourth area 12-4.

[0115] The orthographic projection of the data connection electrode 14 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the third via hole K3 on the plane where the substrate 20 is located. For example, the orthographic projection of the data connection electrode 14 on the plane where the substrate 20 is located includes the orthographic projection of the third via hole K3 on the plane where the substrate 20 is located. Part of the data connection electrode 14 is located in the third via hole K3 and is connected to the data line DL and the first active layer 11.

[0116] The orthographic projection of the conductive structure 19 on the plane where the substrate 20 is located is located within the orthographic projection of the first active layer 11 on the plane where the substrate 20 is located, and the orthographic projection of the conductive structure 19 on the plane where the substrate 20 is located is located within the orthographic projection of the auxiliary gate 13 on the plane where the substrate 20 is located. The conductive structure 19 is configured to form a gate line and a first gate through subsequent processes.

[0117] In an exemplary embodiment, in the plane where the substrate 20 is located, the conductive structure 19 has a second size L2 in the orthographic projection, and the second size L2 is smaller than the first size L1. In the embodiment of the utility model, the direction of the second size L2 is perpendicular to the extension direction of the orthographic projection of the first active layer in the plane where the substrate is located. For example, the second size L2 can be 70% to 80% of the first size L1, for example, the second size L2 can be 75% of the first size L1, for example, the first size L1 can be 4 microns, and the second size L2 can be 3 microns.

[0118] In an exemplary embodiment, the material of the third conductive film may be the same as or different from the material of the first conductive film.

[0119] In an exemplary embodiment, the fourth insulating layer initial pattern 4-1 may include a first region 4a and a second region 4b. The orthographic projection of the first region 4a on the plane where the substrate 20 is located overlaps with the orthographic projection of the photoresist pattern PR on the plane where the substrate 20 is located, and the orthographic projection of the second region 4b on the plane where the substrate 20 is located does not overlap with the orthographic projection of the photoresist pattern PR on the plane where the substrate 20 is located. The surface of the first region 4a away from the substrate 20 is the first surface, and the surface of the second region 4b away from the substrate 20 is the second surface. The first surface is farther away from the substrate 20 than the second surface. During the etching process, the third conductive film can be over-etched to ensure the quality of forming the initial pattern of the third conductive layer, and short circuits can be avoided. Over-etching causes the thickness of the initial pattern of the fourth insulating layer to be inconsistent.

[0120] In an exemplary embodiment, along the thickness direction of the array substrate, the distance between the first surface and the second surface may be 100 angstroms to 500 angstroms.

[0121] In an exemplary embodiment, along the thickness direction of the array substrate, the distance between the first surface and the second surface is 25% to 40% of the maximum thickness of the fourth insulating layer initial pattern 4 - 1 .

[0122] In an exemplary embodiment, the thickness of the fourth insulating layer preliminary pattern 4 - 1 may range from 250 angstroms to 2000 angstroms. The over-etched thickness may be 25% to 40% of the thickness of the fourth insulating layer preliminary pattern.

[0123] In an exemplary embodiment, the glue material of the photoresist layer may include a photosensitive resin, an additive, a solvent, and the like.

[0124] (07) Conducting the first active layer. Conducting the first active layer may include: conducting the first active layer 11 so that a portion of the first active layer 11 forms a first region 11-1 and a second region 11-2, such as Figure 6G The first region 11-1 can be used as a first electrode of the first transistor 21, and the second region 11-2 can be used as a second electrode of the first transistor 21. The region of the first active layer 11 other than the first region 11-1 and the second region 11-2 becomes a first channel region 11-3.

[0125] The orthographic projection of the first channel region 11 - 3 on the plane where the substrate 20 is located is located within the orthographic projection of the auxiliary gate 13 on the plane where the substrate 20 is located, and the orthographic projection of the first channel region 11 - 3 on the plane where the substrate 20 is located is located within the orthographic projection of the conductive structure 19 on the plane where the substrate 20 is located.

[0126] In an exemplary embodiment, in the plane where the substrate 20 is located, the orthographic projection of the first channel region 11-3 has a third size L3, and the third size L3 may be equal to the second size L2. The direction of the third size L3 is perpendicular to the extension direction of the orthographic projection of the first active layer in the plane where the substrate is located.

[0127] In an exemplary embodiment, the third size L3 may be 70% to 80% of the first size L1 . For example, the third size L3 is 75% of the first size L1 .

[0128] (08) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: etching the substrate 20 formed with the aforementioned structure, for example, wet etching may be used to form at least one gate line GL and at least one first gate 15 in the conductive structure 19, and removing the photoresist pattern, such as Figure 6H The wet etching has little effect on the thickness of the fourth insulating layer initial pattern 4-1.

[0129] In an exemplary embodiment, in the plane where the substrate 20 is located, the orthographic projection of the first gate 15 has a fourth dimension L4, and the fourth dimension L4 may be smaller than the third dimension L3. In the embodiment of the utility model, the direction of the fourth dimension L4 is perpendicular to the extension direction of the orthographic projection of the first active layer in the plane where the substrate is located.

[0130] In an exemplary embodiment, the orthographic projection of the first gate 15 on the plane where the substrate 20 is located can be located within the orthographic projection of the first channel region 11-3 on the plane where the substrate 20 is located, and the orthographic projection area of ​​the first gate 15 on the plane where the substrate 20 is located is smaller than the orthographic projection area of ​​the first channel region 11-3 on the plane where the substrate 20 is located. Reducing the size of the first gate can avoid problems such as short circuits with subsequently formed pixel electrodes, and can improve the reliability of the array substrate.

[0131] In an exemplary embodiment, the fourth dimension L4 may be 60% to 70% of the third dimension L3. For example, the fourth dimension L4 may be 67% of the third dimension L3. For example, the third dimension L3 may be 3 microns, and the fourth dimension L4 may be 2 microns.

[0132] (09) Forming a sixth insulating layer pattern. Forming the sixth insulating layer pattern may include: depositing a fifth insulating film and a sixth insulating film in sequence on one side of the substrate 20, using a patterning process to form a fourth insulating layer 4 from the initial pattern of the fourth insulating layer, forming a fifth insulating layer 5 located on a side of the fourth insulating layer 4 away from the substrate 20, and forming a sixth insulating layer 6 located on a side of the fifth insulating layer 5 away from the substrate 20, such as Fig.6I shown.

[0133] The array substrate may include a plurality of via holes, and the plurality of via holes may include at least one fourth via hole K4. The sixth insulating film, the fifth insulating film and the fourth insulating film located within the fourth via hole K4 are all etched away, and a portion of the surface of the second region 11-2 is exposed. The fourth via hole K4 is configured so that a first connecting electrode formed subsequently can be connected to the second region via the via hole, thereby realizing the connection between the first connecting electrode and the first active layer.

[0134] In an exemplary embodiment, the material of the fifth insulating film and the material of the sixth insulating film may be the same as or different from the material of the first insulating film.

[0135] (10) Forming a seventh insulating layer pattern. Forming the seventh insulating layer pattern may include: depositing a fourth conductive film on one side of the substrate 20, and patterning the fourth conductive film through a patterning process so that the fourth conductive film forms a fourth conductive layer pattern. Subsequently, depositing a seventh insulating film on one side of the substrate 20, and patterning the seventh insulating film through a patterning process so that the seventh insulating film forms a seventh insulating layer 7, such as Figure 6J shown.

[0136] The fourth conductive layer pattern may include at least one first connection electrode 31, and the orthographic projection of the first connection electrode 31 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the fourth via K4 on the plane where the substrate 20 is located. By way of example, the orthographic projection of the first connection electrode 31 on the plane where the substrate 20 is located includes the orthographic projection of the fourth via K4 on the plane where the substrate 20 is located, and at least a portion of the first connection electrode 31 is located within the fourth via K4 and connected to the second area 11-2.

[0137] The array substrate may include a plurality of via holes, which may include at least one fifth via hole K5, wherein the seventh insulating film within the fifth via hole K5 is etched away and a portion of the first connecting electrode 31 is exposed, and the fifth via hole K5 is configured such that a second connecting electrode formed subsequently can be connected to the first connecting electrode 31 via the via hole.

[0138] In an exemplary embodiment, the material of the fourth conductive film may be a transparent conductive oxide material, and the transparent conductive oxide material may include indium tin oxide (ITO) or indium zinc oxide (IZO), etc. For example, the fourth conductive layer may be a single-layer structure, or a multi-layer composite structure, such as ITO / Al / ITO, etc.

[0139] (11) Forming a fifth conductive layer pattern. Forming the fifth conductive layer pattern may include: depositing a fifth conductive film on one side of the substrate 20, and patterning the fifth conductive film through a patterning process so that the fifth conductive film forms a fifth conductive layer pattern, such as Figure 6K shown.

[0140] The fifth conductive layer pattern may include at least one second connection electrode 32, the orthographic projection of the second connection electrode 32 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the fifth via K5 on the plane where the substrate 20 is located. For example, the orthographic projection of the second connection electrode 32 on the plane where the substrate 20 is located includes the orthographic projection of the fifth via K5 on the plane where the substrate 20 is located. Part of the second connection electrode 32 is located within the fifth via K5 and is connected to the first connection electrode 31.

[0141] In an exemplary embodiment, the second connection electrode 32 forms a groove 33a in the fifth via hole K5, so that the second connection electrode 32 has a relatively uniform thickness in the fifth via hole K5, which can ensure the quality of the second connection electrode and the reliability of the electrical connection. The groove 33a is configured to accommodate a subsequently formed filling layer.

[0142] In an exemplary embodiment, the material of the fifth conductive film may be a transparent conductive oxide material, and the transparent conductive oxide material may include indium tin oxide (ITO) or indium zinc oxide (IZO), etc. For example, the fifth conductive layer may be a single-layer structure, or a multi-layer composite structure, such as ITO / Al / ITO, etc.

[0143] (12) Forming a sixth conductive layer pattern. Forming the sixth conductive layer pattern may include: depositing an insulating film on one side of the substrate 20, wherein the insulating film is located within the groove 33a to form a fill layer 33, such as Figure 6L The surface of the second connection electrode 32 away from the substrate 20 is substantially flush with the surface of the filling layer 33 away from the substrate 20, so that the pixel electrode formed in the subsequent process has a flat surface and can obtain an electric field that meets the performance requirements together with the common electrode.

[0144] Subsequently, a sixth conductive film is deposited on one side of the substrate 20, and the sixth conductive film is patterned by a patterning process so that the sixth conductive film forms a sixth conductive layer pattern, such as: Figure 6L As shown. The sixth conductive layer may include at least one pixel electrode 10. The orthographic projection of the pixel electrode 10 on the plane where the substrate 20 is located may include the orthographic projection of the fill layer 33 on the plane where the substrate 20 is located. The pixel electrode 10 is connected to the second connection electrode 32, the second connection electrode 32 is connected to the first connection electrode 31, and the first connection electrode 31 is connected to the second area 11-2 of the first active layer 11, thereby realizing the connection between the pixel electrode 10 and the second area 11-2 of the first active layer 11. In the embodiment of the utility model, the connection between the pixel electrode and the first active layer is realized by setting the first connection electrode and the second connection electrode. Compared with setting one connection electrode, the height of a single connection electrode can be reduced, the process complexity can be reduced, and the reliability of the electrical connection can be ensured.

[0145] In an exemplary embodiment, the material of the sixth conductive film may be the same as or different from the material of the fifth conductive film.

[0146] (13) Forming an isolation column pattern. Forming the isolation column pattern may include: depositing an eighth insulating film on one side of the substrate 20 to form an eighth insulating layer 8, such as Figure 6M As shown. The orthographic projection of the eighth insulating layer 8 on the plane where the substrate 20 is located may include the orthographic projections of the second connecting electrode 32 and the pixel electrode 10 on the plane where the substrate 20 is located. The surface of the eighth insulating layer 8 away from the substrate 20 may be a plane, which may flatten the film layer drop caused by the second connecting electrode 32 and the pixel electrode 10, avoid adverse effects on subsequent components, and ensure product reliability.

[0147] Subsequently, a light shielding portion CM and a common electrode 30 are formed on a side of the eighth insulating layer 8 away from the substrate 20. The orthographic projection of the common electrode 30 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the pixel electrode 10 on the plane where the substrate 20 is located. The orthographic projection of the light shielding portion CM on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the gate line GL on the plane where the substrate 20 is located. For example, the orthographic projection of the light shielding portion CM on the plane where the substrate 20 is located may include the orthographic projection of the gate line GL on the plane where the substrate 20 is located, which can reduce the area occupied by the wiring, and can reduce the size of the black matrix in the opposing substrate, which is beneficial to improving the aperture ratio of the array substrate.

[0148] Subsequently, an isolation column PS is formed on a side of the light shielding portion CM away from the substrate 20 , and the orthographic projection of the isolation column PS on the plane where the substrate 20 is located may be located within the orthographic projection of the light shielding portion CM on the plane where the substrate 20 is located.

[0149] In one exemplary embodiment, the material of the isolation column PS may include an inorganic material. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x ) and the like. The material of the isolation column PS may include an organic material. For example, the organic material may be any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc. The isolation column PS may be a single layer, a multi-layer, or a composite layer structure.

[0150] Figure 7 FIG. 1 is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present invention. Figure 7As shown, the array substrate may include a substrate 20, a plurality of conductive layers located on the substrate 20, a plurality of insulating layers located on the substrate 20, and a plurality of semiconductor layers located on the substrate 20. The plurality of conductive layers may include a first conductive layer to a sixth conductive layer, the plurality of insulating layers may include a first insulating layer to an eighth insulating layer, and the plurality of semiconductor layers may include a first semiconductor layer and a second semiconductor layer. Figure 7 The structure of the array substrate shown is Figure 5 The main difference of the structure of the array substrate shown is that the first transistor 21 is not provided with an auxiliary gate. The other structures of the array substrate can refer to the introduction of the above-mentioned embodiment and will not be elaborated here.

[0151] Figure 8 FIG. 1 is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present utility model. Figure 8 As shown, the array substrate may include a substrate 20, a plurality of conductive layers located on the substrate 20, a plurality of insulating layers located on the substrate 20, and a plurality of semiconductor layers located on the substrate 20. The plurality of conductive layers may include a first conductive layer to a seventh conductive layer, the plurality of insulating layers may include a first insulating layer to an eighth insulating layer, and the plurality of semiconductor layers may include a first semiconductor layer and a second semiconductor layer.

[0152] Part of the seventh conductive layer is located between the fifth insulating layer 5 and the sixth insulating layer 6, and the seventh conductive layer is located in the second border region B2. The seventh conductive layer may include at least one first connecting line 17 and at least one second connecting line 18. For other structures of the array substrate, please refer to Figure 5 The description of the illustrated embodiment will not be repeated here.

[0153] The method for preparing the array substrate may include:

[0154] (01) A first conductive layer pattern, a second semiconductor layer pattern, a second conductive layer pattern and a first semiconductor layer pattern are sequentially formed on one side of the substrate 20 , and the description of the above embodiments may be referred to.

[0155] (02) Forming a fourth insulating layer initial pattern. Forming the fourth insulating layer initial pattern may include: depositing a fourth insulating film on one side of the substrate 20, patterning the fourth insulating film through a patterning process to form a fourth insulating layer initial pattern 4-1 and making the first insulating film 1-1 form a first insulating layer 1, such as Fig. 9A The array substrate may include a plurality of via holes, and the plurality of via holes may include at least a sixth via hole K6.

[0156] The first insulating film, the second insulating film, the third insulating film and the fourth insulating film located in the sixth via hole K6 are all etched away, and a portion of the surface of the data line DL is exposed, and the sixth via hole K6 is configured so that the subsequently formed data connection electrode can be connected to the data line DL via the via hole. In the embodiment of the utility model, the sixth via hole K6 is a through hole that realizes the connection between the data connection electrode and the data line and the first active layer.

[0157] (03) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 20, and patterning the third conductive film through a patterning process to form a third conductive layer pattern, such as Fig. 9B As shown, the third conductive layer may include at least one gate line GL, at least one first gate electrode 15, and at least one data connection electrode 14. The orthographic projection of the data connection electrode 14 on the plane where the substrate 20 is located is at least partially overlapped with the orthographic projection of the sixth via hole K6 on the plane where the substrate 20 is located. For example, the orthographic projection of the data connection electrode 14 on the plane where the substrate 20 is located may include the orthographic projection of the sixth via hole K6 on the plane where the substrate 20 is located. Part of the data connection electrode 14 may be located within the sixth via hole K6 and connected to the data line DL.

[0158] The formation of the third conductive layer pattern may further include conducting the first active layer 11. The first active layer 11 is conducted so that parts of the first active layer 11 form a first region 11-1 and a second region 11-2 respectively. The first region 11-1 may be used as a first electrode of the first transistor 21, and the second region 11-2 may be used as a second electrode of the first transistor 21. The region of the first active layer 11 other than the first region 11-1 and the second region 11-2 becomes a first channel region 11-3. Part of the process of forming the third conductive layer pattern may refer to the foregoing embodiment for the process of conducting the first active layer 11. Fig. 6F , Figure 6G as well as Figure 6H Description.

[0159] (04) Forming a fifth insulating layer initial pattern. Forming the fifth insulating layer initial pattern may include: depositing a fifth insulating film on one side of the substrate 20, patterning the fifth insulating film through a patterning process so that the fifth insulating film forms a fifth insulating layer initial pattern 5-1, and the third insulating film 3-1 forms the third insulating layer 3 and the second insulating film 2-1 forms the second insulating layer 2, such as Fig. 9C As shown, the array substrate may include a plurality of via holes, and the plurality of via holes may include at least one seventh via hole K7 and at least one eighth via hole K8, and both the seventh via hole K7 and the eighth via hole K8 are located in the second frame area B2.

[0160] The fifth insulating film, the fourth insulating film, the third insulating film and the second insulating film in the seventh via hole K7 are all etched away, and a portion of the surface of the third region 12-3 of the second active layer 12 is exposed. The seventh via hole K7 is configured so that the first connecting line formed subsequently can be connected to the second active layer through the via hole.

[0161] The fifth insulating film, the fourth insulating film, the third insulating film and the second insulating film in the eighth via hole K8 are all etched away, and a portion of the surface of the fourth region 12-4 of the second active layer 12 is exposed. The eighth via hole K8 is configured so that the second connecting line formed subsequently can be connected to the second active layer through the via hole.

[0162] (05) Forming a seventh conductive layer pattern. Forming the seventh conductive layer pattern may include: depositing a seventh conductive film on one side of the substrate 20, and patterning the seventh conductive film through a patterning process so that the seventh conductive film forms a seventh conductive layer pattern, such as Fig.9D The seventh conductive layer pattern may include at least one first connection line 17 and at least one second connection line 18, and both the first connection line 17 and the second connection line 18 are located in the second frame area B2.

[0163] The orthographic projection of the first connecting line 17 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the seventh via K7 on the plane where the substrate 20 is located. For example, the orthographic projection of the first connecting line 17 on the plane where the substrate 20 is located may include the orthographic projection of the seventh via K7 on the plane where the substrate 20 is located. A portion of the first connecting line 17 is located within the seventh via K7 and is connected to the third area 12-3. The orthographic projection of the second connecting line 18 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the eighth via K8 on the plane where the substrate 20 is located. For example, the orthographic projection of the second connecting line 18 on the plane where the substrate 20 is located may include the orthographic projection of the eighth via K8 on the plane where the substrate 20 is located. A portion of the second connecting line 18 is located within the eighth via K8 and is connected to the fourth area 12-4.

[0164] (06) On the substrate 20 having the aforementioned structure, a sixth insulating layer 6, a fourth conductive layer, a seventh insulating layer 7, a fifth conductive layer, a fill layer 33, a sixth conductive layer, an eighth insulating layer 8, a common electrode 30, a light shielding portion CM and an isolation column PS are sequentially formed. Fig.9E The fourth conductive layer may include at least one first connection electrode 31, the fifth conductive layer may include at least one second connection electrode 32, and the sixth conductive layer may include at least one pixel electrode 10. The structure of the array substrate may refer to the description of the above embodiment, which will not be elaborated here.

[0165] Fig.10 FIG. 1 is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present utility model. Fig.10 As shown, the array substrate may include a substrate 20, a plurality of conductive layers located on the substrate 20, a plurality of insulating layers located on the substrate 20, and a plurality of semiconductor layers located on the substrate 20. The plurality of conductive layers may include a first conductive layer to a seventh conductive layer, the plurality of insulating layers may include a first insulating layer to an eighth insulating layer, and the plurality of semiconductor layers may include a first semiconductor layer and a second semiconductor layer. Fig.10 The array substrate structure shown is Figure 8 The main difference between the array substrate structure shown is that the first transistor 21 is not provided with an auxiliary gate. For other structures, reference may be made to the description of the aforementioned embodiment.

[0166] Fig.11 FIG. 1 is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present invention. Fig.11 As shown, the second transistor 22 may be located between the first conductive layer and the substrate 20. The second transistor 22 may include a second active layer 12 and a second gate 16, and the second active layer 12 is closer to the substrate 20 than the second gate 16. The array substrate may also include at least one first connecting line 17 and at least one second connecting line 18, and at least one first connecting line 17 and at least one second connecting line 18 are both located within the second border area B2. The first connecting line 17 and the second connecting line 18 are both connected to the second active layer 12. The first connecting line 17 and the second connecting line 18 may both be located in the first conductive layer. In an embodiment of the utility model, the second active layer is disposed on a side of the first conductive layer close to the substrate, which can reduce the depth of the through hole K, reduce the excessive etching caused to the fourth insulating layer, and is conducive to improving the performance of the second active layer.

[0167] Fig.12 FIG. 1 is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present utility model. Fig.12As shown, the second transistor 22 may be located between the first conductive layer and the substrate 20. The second transistor 22 may include a second active layer 12 and a second gate 16, and the second active layer 12 is closer to the substrate 20 than the second gate 16. The array substrate may also include at least one first connection line 17 and at least one second connection line 18, and the at least one first connection line 17 and the at least one second connection line 18 are both located within the second border area B2. The first connection line 17 and the second connection line 18 are both connected to the second active layer 12. The first connection line 17 and the second connection line 18 may be located in the same conductive layer, and a portion of the first connection line 17 and a portion of the second connection line 18 are located on a side of the first conductive layer away from the substrate 20. In an embodiment of the utility model, the second active layer is arranged on the side of the first conductive layer close to the substrate, which can reduce the depth of the through hole K and reduce the excessive etching of the fourth insulating layer. The via hole connecting the first connecting line, the second connecting line and the second active layer is prepared after the connection between the data connecting electrode and the data line is completed. This can prevent the process of preparing the data connecting electrode and the first gate from causing adverse effects on the second active layer through the via hole connecting the first connecting line, the second connecting line and the second active layer, thereby helping to improve the performance of the second transistor.

[0168] Fig.13 This is a partial cross-sectional schematic diagram of an array substrate integrated color filter layer according to an embodiment of the utility model. Fig.13 As shown, the array substrate may include a substrate 20, a plurality of conductive layers located on the substrate 20, a plurality of insulating layers located on the substrate 20, and a plurality of semiconductor layers located on the substrate 20. The plurality of conductive layers may include a first conductive layer to a sixth conductive layer, the plurality of insulating layers may include a first insulating layer to an eighth insulating layer, and the plurality of semiconductor layers may include a first semiconductor layer and a second semiconductor layer.

[0169] In a plane perpendicular to the plane where the substrate 20 is located, in a direction away from the substrate 20, the array substrate may include a first conductive layer, a first insulating layer 1, a second semiconductor layer, a second insulating layer 2, a second conductive layer, a third insulating layer 3, a first semiconductor layer, a fourth insulating layer 4, a third conductive layer, a fifth insulating layer 5, a sixth insulating layer 6, a fourth conductive layer, a seventh insulating layer 7, a fifth conductive layer, a sixth conductive layer and an eighth insulating layer 8 which are stacked in sequence.

[0170] The array substrate may further include a color filter layer 40, and the color filter layer 40 may be located between the sixth insulating layer 6 and the seventh insulating layer 7. For example, the first connecting electrode 31 and the color filter layer 40 may be a same-layer structure. In an embodiment of the utility model, the "same-layer structure" refers to the same layer located in the array substrate. In an embodiment of the utility model, the color filter layer is arranged in the array substrate, which can reduce the thickness of the opposing substrate, thereby reducing the thickness of the display device, and is conducive to the thin and light design of the display product. Furthermore, by arranging the color filter layer in the array substrate, it is necessary to arrange the black matrix in the array substrate, which is conducive to reducing the size of the black matrix, can improve the transmittance of the display product, and is conducive to improving the display brightness of the display product and reducing power consumption.

[0171] For other structures of the array substrate, please refer to the above Figure 5 The description of the array substrate structure will not be elaborated here.

[0172] Fig.14 This is a partial cross-sectional schematic diagram of an array substrate integrated with a color filter layer according to another embodiment of the utility model. Fig.14 As shown, the array substrate structure is Fig.13 The main difference of the array substrate structure shown is that the auxiliary gate is not provided in the first transistor 21. The array substrate may further include a color filter layer 40, which may be located between the sixth insulating layer 6 and the seventh insulating layer 7. For example, the first connection electrode 31 and the color filter layer 40 may be in the same layer structure.

[0173] Fig.15 FIG. 1 is a partial cross-sectional schematic diagram of an array substrate integrated with a color filter layer according to another embodiment of the present utility model. Fig.15 As shown, the array substrate may include a substrate 20, a plurality of conductive layers located on the substrate 20, a plurality of insulating layers located on the substrate 20, and a plurality of semiconductor layers located on the substrate 20. The plurality of conductive layers may include a first conductive layer to a seventh conductive layer, the plurality of insulating layers may include a first insulating layer to an eighth insulating layer, and the plurality of semiconductor layers may include a first semiconductor layer and a second semiconductor layer. A portion of the seventh conductive layer is located between the fifth insulating layer 5 and the sixth insulating layer 6, and the seventh conductive layer is located in the second border area B2. The seventh conductive layer may include at least one first connecting line 17 and at least one second connecting line 18. The array substrate may further include a color filter layer 40, and the color filter layer 40 may be located between the sixth insulating layer 6 and the seventh insulating layer 7. For example, the first connecting electrode 31 and the color filter layer 40 may be a same-layer structure.

[0174] Fig.16 This is a partial cross-sectional schematic diagram of an array substrate integrated with a color filter layer according to another embodiment of the utility model. Fig.16 As shown, the structure of the array substrate is Fig.15The main difference between the structures of the array substrate shown is that the first transistor 21 is not provided with an auxiliary gate.

[0175] In the embodiment of the utility model, the structure of the display area, the structure of the second frame area and the color filter layer can be arbitrarily combined. For example, the color filter layer can be combined with Fig.11 or Fig.12 The structures shown are combined.

[0176] The preparation process of the array substrate provided by the embodiment of the utility model is compatible with the existing preparation process, and the process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0177] The embodiment of the utility model further provides a display device. The display device includes the array substrate described in any of the above embodiments. The display device can be: a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. The embodiment of the utility model is not limited to this.

[0178] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely exemplary and not restrictive. Therefore, the present invention is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of implementation without departing from the scope of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate further comprises a display area and a frame area located at least on one side of the display area; the array substrate further comprises a substrate, at least one data line located on the substrate, at least one data connection electrode located on the substrate, and at least one first transistor located on the substrate, and the at least one data line, the at least one data connection electrode, and the at least one first transistor are all located in the display area; the first transistor comprises a first active layer, and the first active layer is located on a side of the data line away from the substrate, and a portion of the data connection electrode is located on a side of the first active layer away from the substrate; The array substrate further comprises at least one through hole, the orthographic projection of the at least one through hole on the plane where the substrate is located is located within the orthographic projection of the at least one data line on the plane where the substrate is located; the hole wall of the at least one through hole is shared with a portion of the side wall of the first active layer, and the through hole only exposes the portion of the side wall of the first active layer; wherein at least a portion of the data connection electrode is located within the through hole and is connected to both the portion of the side wall and the data line.

2. The array substrate according to claim 1, characterized in that: The at least one first transistor also includes a first gate and an auxiliary gate; the first gate is located on a side of the first active layer away from the substrate, and the auxiliary gate is located on a side of the first active layer close to the substrate; wherein the material of the auxiliary gate is a transparent conductive material.

3. The array substrate according to claim 2, characterized in that: The auxiliary gate has a first size in its orthographic projection on the plane where the substrate is located, and the first size is greater than or equal to 4 microns; wherein the direction of the first size is perpendicular to the extension direction of the orthographic projection of the first active layer on the plane where the substrate is located.

4. The array substrate according to claim 3, characterized in that: The first active layer includes a first region, a first channel region and a second region which are connected to each other, and the first region and the second region are respectively located on two opposite sides of the first channel region; The orthographic projection of the first channel region on the plane where the substrate is located is located within the orthographic projection of the auxiliary gate on the plane where the substrate is located.

5. The array substrate according to claim 4, characterized in that: The orthographic projection of the first channel region on the plane where the substrate is located has a third size, and the third size is smaller than the first size; wherein the direction of the third size is perpendicular to the extension direction of the orthographic projection of the first active layer on the plane where the substrate is located.

6. The array substrate according to claim 5, characterized in that: The third dimension is 70% to 80% of the first dimension.

7. The array substrate according to claim 1, wherein: The at least one first transistor further comprises a first gate, wherein the first gate is located on a side of the first active layer away from the substrate; The first active layer includes a first region, a first channel region and a second region which are connected to each other, and the first region and the second region are respectively located on two opposite sides of the first channel region; The orthographic projection of the first gate on the plane where the substrate is located is located within the orthographic projection of the first channel region on the plane where the substrate is located.

8. The array substrate according to claim 7, characterized in that: The orthographic projection of the first channel region on the plane where the substrate is located has a third size, and the orthographic projection of the first gate on the plane where the substrate is located has a fourth size; wherein the fourth size is smaller than the third size; wherein the direction where the third size is located and the direction where the fourth size is located are both perpendicular to the extension direction of the orthographic projection of the first active layer on the plane where the substrate is located.

9. The array substrate according to claim 8, characterized in that: The fourth dimension is 60% to 70% of the third dimension.

10. The array substrate according to claim 7, wherein: The array substrate further includes at least one insulating layer, and a portion of the at least one insulating layer is located between the first gate and the first active layer, and a portion of the at least one insulating layer is in contact with the first gate; The portion of the at least one insulating layer includes a first region and a second region, and an orthographic projection of the first gate on the plane where the substrate is located is located within an orthographic projection of the first region on the plane where the substrate is located; The first region has a first surface away from the substrate, the second region has a second surface away from the substrate, and the first surface is farther away from the substrate than the second surface.

11. The array substrate according to claim 10, characterized in that: Along the thickness direction of the array substrate, a distance between the first surface and the second surface is 25% to 40% of a maximum thickness of a portion of the at least one insulating layer.

12. The array substrate according to any one of claims 1 to 11, characterized in that: The array substrate further includes a color filter layer, and the color filter layer is located on a side of the first transistor away from the substrate.

13. The array substrate according to any one of claims 1 to 11, characterized in that: The array substrate further includes at least one second transistor, at least one first connection line and at least one second connection line, and the at least one second transistor, the at least one first connection line and the at least one second connection line are all located in the frame area; Among them, the first connecting line and the second connecting line are both connected to the second transistor; the first connecting line and the second connecting line are located in the same conductive layer as the data connecting electrode; or, the first connecting line and the second connecting line are located in the same conductive layer as the data line; or, the first connecting line and the second connecting line are located in the conductive layer on the side of the data connecting electrode away from the substrate.

14. The array substrate according to claim 13, characterized in that: The at least one second transistor includes a second active layer and a second gate; the second active layer and the second gate are both located between the data line and the substrate; or the second active layer and the second gate are both located between the data line and the first active layer.

15. A display device, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 14.

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