Bandgap reference circuit, system on chip, chip and electronic device

Abstract

The present application discloses a bandgap reference circuit, a system on chip and a chip. The bandgap reference circuit includes a reference acquisition unit, an isolation buffer unit and an operation output unit; the operation output unit is connected to the isolation buffer unit; the isolation buffer unit is connected to the reference acquisition unit; the operation output unit is connected to the reference acquisition unit. The present application can set an isolation buffer unit between the operation output unit and the reference acquisition unit, and the isolation buffer unit can reduce the circuit noise of the reference acquisition unit, thereby improving the accuracy of the circuit output reference voltage. The present application can be widely used in the field of integrated circuit technology.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a bandgap reference circuit, a system on chip, a chip, and an electronic device. Background Art

[0002] In the related art, the bandgap reference circuit generally uses the direct output of the operational amplifier inside the circuit as the reference voltage output. This bandgap reference circuit has poor circuit anti-noise performance, and the circuit reference voltage is prone to deviation due to noise interference. Therefore, there are still technical problems that need to be solved in the related art. Utility Model Content

[0003] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of an embodiment of the present application is to provide a bandgap reference circuit, a system on chip, and a chip, which can reduce the noise of the circuit output reference voltage.

[0005] In order to achieve the above-mentioned technical objectives, the technical solution adopted by the embodiments of the present application includes: a bandgap reference circuit, including a reference acquisition unit, an isolation buffer unit and an operation output unit; the operation output unit is connected to the isolation buffer unit; the isolation buffer unit is connected to the reference acquisition unit; the operation output unit is connected to the reference acquisition unit.

[0006] In addition, a bandgap reference circuit according to the above embodiment of the utility model may also have the following additional technical features:

[0007] Furthermore, in an embodiment of the present application, the operational output unit includes an operational amplifier and a transistor sub-circuit; the input end of the operational amplifier is connected to the transistor sub-circuit; and the output end of the operational amplifier serves as the output end of the operational output unit.

[0008] Further, in an embodiment of the present application, the transistor subcircuit includes a first triode, a second triode, a first resistor, a second resistor and a third resistor; the collector of the second triode and one end of the third resistor are connected to the inverting input terminal of the operational amplifier, and the emitter of the second triode and the base of the second triode are grounded; the collector of the first triode is connected to one end of the first resistor, and the emitter of the first triode and the base of the first triode are grounded; the other end of the first resistor and one end of the second resistor are connected to the non-inverting input terminal of the operational amplifier; the other end of the second resistor and the other end of the third resistor are connected to the first power supply.

[0009] Furthermore, in an embodiment of the present application, the isolation buffer unit includes a first MOS tube, a second MOS tube and a power module; the gate of the first MOS tube is connected, and the source of the first MOS tube is connected to the drain of the second MOS tube; the source of the first MOS tube is connected to the power module; the gate of the second MOS tube serves as the input end of the isolation buffer unit and is connected to the operation output unit; the source of the second MOS tube is connected to the first power supply; the drain of the first MOS tube serves as the output end of the isolation buffer unit and is connected to the reference acquisition unit.

[0010] Furthermore, in an embodiment of the present application, the power supply module includes a voltage source or a power supply sub-circuit.

[0011] Furthermore, in an embodiment of the present application, the power subcircuit includes a current source, a first capacitor, a third MOS tube and a fourth MOS tube; the drain of the third MOS tube, the gate of the third MOS tube, and one end of the current source are connected to one end of the first capacitor; the gate of the fourth MOS tube and the drain of the fourth MOS tube are connected to the source of the third MOS tube; and the source of the fourth MOS tube is connected to the first power supply.

[0012] Furthermore, in the embodiment of the present application, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all P-channel MOS tubes.

[0013] On the other hand, an embodiment of the present application further provides a system on chip, comprising a bandgap reference circuit and a peripheral circuit as described in any of the above items.

[0014] On the other hand, an embodiment of the present application further provides a chip, comprising the system on chip described above.

[0015] On the other hand, an embodiment of the present application further provides an electronic device, comprising the chip described above.

[0016] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0017] The present application can set an isolation buffer unit between the operation output unit and the reference acquisition unit, so that the output of the operation output unit is not used as a direct output reference voltage, but the output of the operation output unit is converted into a reference voltage after passing through the isolation buffer unit and the reference acquisition unit. The present application can reduce the influence of noise in the circuit on the output reference voltage through the isolation buffer unit, thereby improving the accuracy of the circuit output reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a circuit structure diagram of a bandgap reference circuit in the related art;

[0019] Figure 2 A schematic diagram of the module structure of a bandgap reference circuit in a specific embodiment of the utility model;

[0020] Figure 3 This is a schematic diagram of the circuit structure of a calculation output unit in a specific embodiment of the utility model;

[0021] Figure 4 It is a structural schematic diagram of a bandgap reference circuit in a specific embodiment of the utility model;

[0022] Figure 5 It is a structural schematic diagram of a bandgap reference circuit in another specific embodiment of the utility model;

[0023] Figure 6 It is a structural schematic diagram of a bandgap reference circuit in another specific embodiment of the utility model;

[0024] Figure 7 The figure is a schematic diagram of the circuit structure of a peripheral circuit in a specific embodiment of the utility model. DETAILED DESCRIPTION

[0025] The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings to illustrate the principles and processes of the bandgap reference circuit, system on chip, chip and electronic device in the embodiments of the present invention.

[0026] First, the architecture and principle of the bandgap reference structure of the related art are explained:

[0027] Reference Figure 1 , Figure 1 This is a triode reference structure of the related technology. This structure is to connect a voltage regulator circuit to each of the two input terminals of a negative feedback operational amplifier. The two voltage regulator circuits are connected in parallel. The total voltage of their parallel connection is used as the required reference voltage and is connected to the output terminal of the operational amplifier for output. Its working principle is as follows:

[0028] First, output V REF for:

[0029] V REF =V BE2 +V R3 (1)

[0030] in:

[0031]

[0032] Combining formula (1) and (2), we can get:

[0033]

[0034] The expression of K is:

[0035]

[0036] In the above formula, k is the Boltzmann constant, q is the electron charge, T is the absolute temperature, and A is the emitter area. The voltage Vbe2 between the base and emitter of transistor Q2 has a negative temperature coefficient, which is about -2.2mV / ℃ at room temperature. When K=17.2, it can just offset the negative temperature coefficient of Vbe2 and achieve zero temperature coefficient.

[0037] In the above circuit, the op amp can directly output the reference signal V REF To the external circuit, this causes the circuit to have poor anti-noise performance, such as the operational amplifier noise, resistor noise and resistor noise in the circuit will directly affect the accuracy of the reference voltage VREF directly input by the operational amplifier. At the same time, the external circuit also requires higher power consumption to reduce a certain amount of noise, which leads to a larger power consumption of the external circuit. Therefore, there are still technical problems that need to be solved in the related art.

[0038] In view of the technical defects existing in the related art, the present application provides a bandgap reference circuit. Figure 2 The bandgap reference circuit may include a reference acquisition unit 1, an isolation buffer unit 2 and an operation output unit 3; the operation output unit 3 may be connected to the isolation buffer unit 2; the isolation buffer unit 2 may be connected to the reference acquisition unit 1; the operation output unit 3 may be connected to the reference acquisition unit 1.

[0039] In this embodiment, an isolation buffer unit may be provided between the operation output unit and the reference acquisition unit. In this embodiment, the output of the operation output unit may not be directly used as the reference voltage output by the bandgap reference circuit, but the output of the output unit may be converted into a voltage after passing through the isolation buffer unit and the reference acquisition unit as the reference voltage output by the bandgap reference circuit. Through the isolation buffer unit, the present application may reduce the noise doped in the output reference voltage, thereby improving the accuracy of the circuit output reference voltage.

[0040] Further, in some feasible embodiments of the present application, referring to Figure 3 The operation output unit 3 may include an operation amplifier 31 and a transistor subcircuit 32. The input end of the operation amplifier 31 may be connected to the transistor subcircuit 32. The output end of the operation amplifier 31 serves as the output end of the operation output unit 3.

[0041] Further, in some feasible embodiments of the present application, the transistor subcircuit 32 may include a first triode Q1, a second triode Q2, a first resistor R1, a second resistor R2, and a third resistor R3. The collector of the second triode Q2 and one end of the third resistor R3 may be connected to the inverting input terminal of the operational amplifier 31, and the emitter of the second triode Q2 and the base of the second triode Q2 are grounded. The collector of the first triode Q1 may be connected to one end of the first resistor R1, and the emitter of the first triode Q1 and the base of the first triode Q1 are grounded. The other end of the first resistor R1 and one end of the second resistor R2 may be connected to the non-inverting input terminal of the operational amplifier 31. The other end of the second resistor R2 and the other end of the third resistor R3 may be connected to the first power supply VDD.

[0042] Furthermore, in some feasible embodiments of the present application, the first transistor Q1 and the second transistor Q2 are both PNP transistors.

[0043] Further, in some feasible embodiments of the present application, referring to Figure 4 , the isolation buffer unit may include a first MOS transistor PM10, a second MOS transistor PM11, and a power module V101. The gate of the first MOS transistor PM10 is connected, and the source of the first MOS transistor PM10 may be connected to the drain of the second MOS transistor PM11. The source of the first MOS transistor PM10 may be connected to the power module V101. The gate of the second MOS transistor PM11 serves as the input end of the isolation buffer unit 2 and may be connected to the operation output unit 3. The source of the second MOS transistor PM11 may be connected to the first power supply VDD. The drain of the first MOS transistor PM10 serves as the output end of the isolation buffer unit 2 and may be connected to the reference acquisition unit 1.

[0044] Further, in some feasible embodiments of the present application, referring to Figure 4 The power module V101 may include a voltage source or a power sub-circuit. Specifically, when the power module is a voltage source, one end of the voltage source may be connected to the source of the first MOS transistor PM10, and the other end of the voltage source may be grounded.

[0045] Further, in some feasible embodiments of the present application, referring to Figure 5The power subcircuit may include a current source Is, a first capacitor C1, a third MOS transistor PM13, and a fourth MOS transistor PM17; the drain of the third MOS transistor PM13, the gate of the third MOS transistor PM13, and one end of the current source Is may be connected to one end of the first capacitor C1; the gate of the fourth MOS transistor PM17 and the drain of the fourth MOS transistor PM17 may be connected to the source of the third MOS transistor PM13; the source of the fourth MOS transistor PM17 may be connected to the first power supply VDD. The PM10 transistor undergoes further gate voltage stabilization and filtering, which is implemented using capacitors C1, PM17, and PM13, and I1 is a current source that provides current to PM13 and PM17.

[0046] Furthermore, in some feasible embodiments of the present application, the first MOS transistor PM10 , the second MOS transistor PM11 , the third MOS transistor PM13 , and the fourth MOS transistor PM17 are all P-channel MOS transistors.

[0047] Further, in some feasible embodiments of the present application, the reference acquisition unit 1 may include a fourth resistor R4, one end of the fourth resistor R4 may be connected to the isolation buffer unit 2; the other end of the fourth resistor R4 may be connected to the operation output unit 3; the voltage at one end of the fourth resistor R4 is used as the output voltage V of the reference acquisition unit REF .

[0048] Reference Figure 6 , the principle of the bandgap reference circuit of the present application is specifically as follows:

[0049] Figure 6 The output of the circuit V REF for:

[0050] V REF =V Be2 +V R4

[0051] Assuming that the current gain of the isolation buffer unit is M times, we have:

[0052]

[0053] It can be concluded that:

[0054]

[0055] The expression of K is:

[0056]

[0057] K is the Boltzmann constant, q is the electron charge, T is the absolute temperature, and A is the emitter area of ​​the transistor. The base of the transistor Q2 can have a negative temperature coefficient with the voltage drop Vbe2 of the emitter, which is about -2.2mV / ℃ at room temperature. When K=17.2, it can offset the negative temperature coefficient of Vbe2 and achieve a zero temperature coefficient.

[0058] In summary, this embodiment can still ensure zero temperature coefficient in the circuit after adding two MOS transistors PM11 and PM10 to realize isolation structure. And this embodiment can isolate the noise of the circuit through two compositive source and compositive gate MOS transistors PM11 and PM10. This application can reduce V REF The op amp noise, resistor noise and resistor noise mixed in the reference voltage V REF accuracy.

[0059] In addition, the present application also provides a system on chip, which may include any of the foregoing bandgap reference circuits and peripheral circuits.

[0060] Specifically, refer to Figure 7 , the peripheral circuit may include a second operational amplifier I19, a third operational amplifier I20, and an analog-to-digital converter. The non-inverting input terminal of the second operational amplifier I19 and the non-inverting input terminal of the third operational amplifier I20 may be connected to the output voltage VREF of any of the above-mentioned bandgap reference voltages, the inverting input terminal of the second operational amplifier I19 may be connected to the output terminal of the second operational amplifier I19, and after being connected, it may be connected to one input terminal of the analog-to-digital converter. The inverting input terminal of the third operational amplifier I20 may be connected to the output terminal of the third operational amplifier I20, and after being connected, it may be connected to another input terminal of the analog-to-digital converter.

[0061] In an analog-to-digital converter, the reference voltage V REF It is a crucial parameter. The reference voltage determines the accuracy and dynamic range of the analog-to-digital converter conversion. The reference voltage is the reference level used by the analog-to-digital converter to quantize the analog signal. The reference voltage provides a stable reference for the analog-to-digital converter to convert the input analog signal into a digital signal. A high-precision reference voltage can improve the conversion accuracy of the analog-to-digital converter and reduce errors. The stability of the reference voltage has a direct impact on the performance of the analog-to-digital converter, so a stable reference voltage with a low temperature coefficient (TC) and a low voltage coefficient (VC) is usually required.

[0062] It should be noted that the contents of the above-mentioned bandgap reference circuit embodiment are all applicable to the present system-on-chip embodiment. The functions specifically implemented by the present system-on-chip embodiment are the same as those of the above-mentioned bandgap reference circuit embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned bandgap reference circuit embodiment.

[0063] In addition, the present application also provides a chip. The chip may include one or more systems on chip.

[0064] In addition, the present application also provides an electronic device. The electronic device may include one or more chips.

[0065] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the term "switch" should be understood in a broad sense, for example, it can be a transformation or a conversion; for ordinary technicians in this field, the specific meaning of the above terms in the present invention can be understood according to specific circumstances.

[0066] In the description of this specification, the description of the reference term means that the specific structure or feature described in conjunction with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0067] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0068] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A bandgap reference circuit, characterized in that: include: A reference acquisition unit, an isolation buffer unit, and an operation output unit; The operation output unit is connected to the isolation buffer unit; The isolation buffer unit is connected to the reference acquisition unit; and the operation output unit is connected to the reference acquisition unit.

2. The bandgap reference circuit according to claim 1, characterized in that: The operational output unit includes an operational amplifier and a transistor sub-circuit; the input end of the operational amplifier is connected to the transistor sub-circuit; the output end of the operational amplifier serves as the output end of the operational output unit; the transistor sub-circuit includes a first triode, a second triode, a first resistor, a second resistor and a third resistor; the collector of the second triode and one end of the third resistor are connected to the inverting input end of the operational amplifier, and the emitter of the second triode and the base of the second triode are grounded; the collector of the first triode is connected to one end of the first resistor, and the emitter of the first triode and the base of the first triode are grounded; the other end of the first resistor and one end of the second resistor are connected to the non-inverting input end of the operational amplifier; the other end of the second resistor and the other end of the third resistor are connected to a first power supply.

3. The bandgap reference circuit according to claim 1, characterized in that: The isolation buffer unit includes a first MOS tube, a second MOS tube and a power module; the gate of the first MOS tube is connected, and the source of the first MOS tube is connected to the drain of the second MOS tube; the source of the first MOS tube is connected to the power module; the gate of the second MOS tube serves as the input end of the isolation buffer unit and is connected to the operation output unit; the source of the second MOS tube is connected to the first power supply; the drain of the first MOS tube serves as the output end of the isolation buffer unit and is connected to the reference acquisition unit.

4. The bandgap reference circuit according to claim 3, characterized in that: The power module includes a voltage source or a power subcircuit.

5. The bandgap reference circuit according to claim 4, characterized in that: The power subcircuit includes a current source, a first capacitor, a third MOS tube and a fourth MOS tube; the drain of the third MOS tube, the gate of the third MOS tube, and one end of the current source are connected to one end of the first capacitor; the gate of the fourth MOS tube and the drain of the fourth MOS tube are connected to the source of the third MOS tube; the source of the fourth MOS tube is connected to the first power supply.

6. The bandgap reference circuit according to claim 5, characterized in that: The first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all P-channel MOS transistors.

7. The bandgap reference circuit according to claim 1, characterized in that: The reference acquisition unit includes a fourth resistor, one end of which is connected to the isolation buffer unit; the other end of the fourth resistor is connected to the operation output unit; and the voltage at one end of the fourth resistor serves as the output voltage of the reference acquisition unit.

8. A system on chip, characterized in that: It comprises the bandgap reference circuit and peripheral circuits as described in any one of claims 1 to 7.

9. A chip, characterized in that: Comprising the system on chip as claimed in claim 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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