Semiconductor device and electrical system

Abstract

The utility model relates to a semiconductor device and an electrical system. Disclosed is a semiconductor device comprising: a semiconductor substrate comprising at least one power semiconductor device; the insulating diaphragm is arranged on the semiconductor substrate and is provided with at least one first opening penetrating through the insulating diaphragm, and the at least one first opening enables the corresponding first part of the semiconductor substrate to be exposed; at least one electrically conductive attachment member filled in a corresponding one of the at least one first opening; and a metal diaphragm disposed on the insulating diaphragm and the at least one attachment member, where the at least one attachment member joins and electrically connects a respective portion of the metal diaphragm with a respective first portion of the semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an electrical system including the semiconductor device. Background Art

[0002] Die Top System (DTS) has received increasing attention. DTS provides a thick metal film (eg, copper foil) on the top of the die to improve the strength of the top surface of the die, thereby achieving a thick interconnect solution.

[0003] The inventors of the present application have discovered that the relevant products and processes have some defects, such as high production costs, complex processes, high storage conditions, inherent material defects and low device yield (for example, low output per hour (UPH)).

[0004] The DTS technology of the prior art is a solution at the tube core level. In a typical DTS solution of the prior art, a sintering paste is first applied on a mounting substrate (e.g., a copper-clad substrate) and pre-dried. Then the tube core is picked up and placed in an appropriate position on the mounting substrate so that the sintering paste is between the two. Afterwards, a sintering process is performed to bond the tube core and the mounting substrate using the sintering paste. In addition, a sintering paste is pre-coated on the surface of the prefabricated half-cut copper diaphragm opposite to the chip (tube core). The pre-coating process requires a solid binder (tacking agent) to help the sintering paste maintain its shape during processing, or to provide temporary bonding before the final formation of the attachment material formed by the sintering paste. Afterwards, pre-drying of the sintering paste and thermal activation of the binder (to activate the binder in the sintering paste) are performed. Then the copper diaphragm unit is picked up from the half-cut copper diaphragm and placed on the tube core on the side opposite to the mounting substrate. Afterwards, pressure sintering is performed to bond the copper diaphragm to the tube core. The wires or tapes can then be bonded to the copper diaphragm and molded.

[0005] In the DTS solution of the prior art, two sintering steps and two pick and place steps are required, and a binder and activation of the binder are required, which makes the process complicated and the yield is low.

[0006] On the other hand, the pre-applied sintering paste is unstable, and pre-dried paste particles may fall off during the pick-and-place process. In addition, during the sintering process, the binder evaporates and disappears, leaving a large void. If a liquid adhesive is used, it will lead to a further reduction in UPH. In addition, the device prepared in this way is sensitive to temperature, humidity and vacuum, and thus has high requirements for storage conditions. In addition, the thickness of the metal diaphragm used in the DTS solution of the prior art is fixed, which limits the flexibility of the design.

[0007] Therefore, there is a need in the art for improved semiconductor devices and methods of making the same. Utility Model Content

[0008] In view of the above problems, the utility model disclosed herein is proposed to at least solve one or more of the above problems.

[0009] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate, comprising at least one power semiconductor device; an insulating diaphragm on the semiconductor substrate, having at least one first opening passing through the insulating diaphragm, the at least one first opening exposing a corresponding first portion of the semiconductor substrate; at least one conductive attachment component filled in a corresponding first opening of the at least one first opening; and a metal diaphragm, disposed on the insulating diaphragm and the at least one attachment component, wherein the at least one attachment component joins and electrically connects a corresponding portion of the metal diaphragm with a corresponding first portion of the semiconductor substrate.

[0010] In some embodiments, the insulating film further includes at least one second opening, wherein the at least one second opening exposes a corresponding second portion of the semiconductor substrate, and the metal film does not overlap with the at least one second opening.

[0011] In some embodiments, the at least one first opening exposes at least a portion of a corresponding current terminal of a corresponding semiconductor device, and the at least one second opening exposes at least a portion of a control terminal of the corresponding semiconductor device.

[0012] In some embodiments, the semiconductor substrate includes a chip, the at least one power semiconductor device includes a plurality of power semiconductor devices arranged in an array, and the insulating membrane includes a plurality of first openings, each of which exposes a metallization layer of a corresponding power semiconductor device among the plurality of power semiconductor devices.

[0013] In some embodiments, the semiconductor substrate includes a tube core separated from a chip, wherein the insulating film and the metal film are basically absent on the lateral sides of the semiconductor substrate, and wherein at least one side of the insulating film, the corresponding side of the metal film, and the corresponding side of the semiconductor substrate are basically flush.

[0014] In some embodiments, the insulating film is formed of an organic material, and wherein the metal film includes one or more layers of metal material.

[0015] In some embodiments, the attachment component is obtained by subjecting the applied attachment material to a bonding process, wherein the bonding process comprises at least one of the following: sintering, firing, annealing, transient liquid phase welding, and curing.

[0016] In some embodiments, the attachment material includes one of the following: sintering paste, pre-sintering sheet, solder, transient liquid phase soldering material, and conductive glue.

[0017] In some embodiments, the semiconductor device is a power MOS transistor, and the at least one first opening exposes at least a portion of a corresponding source or drain terminal of the corresponding semiconductor device, and the at least one second opening exposes at least a portion of a gate terminal of the corresponding semiconductor device.

[0018] In some embodiments, the semiconductor device further includes: at least one first conductive line coupled to a corresponding current terminal of the corresponding semiconductor device; and at least one second conductive line coupled to a corresponding control terminal of the corresponding semiconductor device.

[0019] In some embodiments, the semiconductor device further comprises: a mounting base including a die attach portion and a lead, wherein the semiconductor substrate is attached to the die attach portion, the at least one first wire is coupled to the lead, and the at least one first wire comprises a copper wire.

[0020] According to one aspect of the present disclosure, an electrical system is further provided, comprising the semiconductor device according to any embodiment.

[0021] According to another aspect of the present disclosure, a method for preparing a semiconductor device is provided, comprising: providing an attachment structure, the attachment structure comprising: an insulating diaphragm having at least one first opening passing through the insulating diaphragm, the at least one first opening; a metal diaphragm attached to the insulating diaphragm, the metal diaphragm comprising a portion overlapping with the at least one first opening of the insulating diaphragm; and an attachment material filled in a corresponding first opening in the at least one first opening and in contact with the metal diaphragm, the attachment material comprising a conductive material; attaching the attachment structure to a semiconductor wafer comprising at least one semiconductor device, so that the insulating diaphragm is in contact with the semiconductor wafer, the at least one first opening is aligned with the corresponding first portion of the semiconductor substrate, and the attachment material is in contact with the corresponding first portion of the semiconductor substrate; and performing a bonding process so that the attachment material forms an attachment component to bond and electrically connect the corresponding portion of the metal diaphragm to the corresponding first portion of the semiconductor substrate through the attachment component.

[0022] In some embodiments, providing an attachment structure includes: attaching the metal diaphragm to the first surface of the insulating diaphragm; filling the at least one first opening of the insulating diaphragm with an attachment material from the side of a second surface of the insulating diaphragm opposite to the first surface, wherein the attachment material filled in the at least one first opening is in contact with the metal diaphragm.

[0023] In some embodiments, the method further comprises: performing dicing after the bonding process to form separated semiconductor devices.

[0024] In some embodiments, the insulating film further includes at least one second opening, wherein the at least one second opening exposes a corresponding second portion of the semiconductor substrate, and the metal film does not overlap with the at least one second opening.

[0025] In some embodiments, the insulating film and the metal film are basically absent on the lateral sides of the semiconductor substrate of the semiconductor device, and wherein at least one side of the portion of the insulating film included in the separated semiconductor device, the corresponding side of the portion of the metal film included, and the corresponding side of the semiconductor substrate included are basically flush.

[0026] In some embodiments, the at least one semiconductor device comprises a power semiconductor device, the at least one first opening exposes at least a portion of a corresponding current terminal of the corresponding semiconductor device, and the at least one second opening exposes at least a portion of a control terminal of the corresponding semiconductor device.

[0027] In some embodiments, the insulating film is formed of an organic material, and wherein the metal film includes one or more layers of metal material.

[0028] In some embodiments, the bonding process includes at least one of: sintering, firing, annealing, transient liquid phase welding, and or curing.

[0029] In some embodiments, the attachment material includes one of the following: sintering paste, pre-sintering sheet, solder, transient liquid phase welding material and conductive glue.

[0030] In some embodiments, the method also includes: picking up the separated semiconductor device and placing it on a mounting substrate; attaching the separated semiconductor device to the mounting substrate; bonding at least one first wire to a corresponding current terminal of the corresponding semiconductor device; and bonding at least one second wire to a corresponding control terminal of the corresponding semiconductor device.

[0031] According to aspects and embodiments of the present disclosure, the processability and UPH of the device are improved. Harsh storage conditions are no longer required, greatly reducing the cost of delivery. In addition, according to aspects and embodiments of the present disclosure, there is no need to use solid adhesives, thereby greatly reducing or avoiding the defects caused by them, and improving the reliability and service life of the device.

[0032] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0034] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0035] Figure 1 shows a schematic top view of an apparatus according to some embodiments of the present disclosure;

[0036] Figure 2 Shows Figure 1 A schematic cross-sectional view of the device shown;

[0037] Figure 3A shows a schematic top view of an insulating membrane of a device according to some embodiments of the present disclosure;

[0038] Figure 3B shows a schematic top view of a portion of an apparatus according to some embodiments of the present disclosure;

[0039] Figure 3C shows a schematic top view of a portion of an apparatus according to some embodiments of the present disclosure;

[0040] Figure 3D shows a schematic top view of a portion of an apparatus according to some embodiments of the present disclosure;

[0041] Figure 4 shows a schematic perspective view of a device in the process of being prepared according to some embodiments of the present disclosure;

[0042] Figure 5A shows a schematic top view of an insulating film according to some embodiments of the present disclosure, Figure 5B An enlarged view of a portion of an insulating diaphragm is shown;

[0043] Figure 6 shows a schematic top view of an insulating film according to some embodiments of the present disclosure;

[0044] Fig. 7A and 7BSchematic cross-sectional views of insulating films according to other embodiments of the present disclosure are respectively shown;

[0045] Figure 8 shows a schematic top view of a metal diaphragm according to some embodiments of the present disclosure;

[0046] Fig. 9 A schematic top view showing a metal diaphragm after being attached to an insulating diaphragm according to some embodiments of the present disclosure;

[0047] Fig.10 A schematic top view showing a side of the insulating film away from the metal film after the metal film is attached to the insulating film according to some embodiments of the present disclosure;

[0048] Fig.11A A schematic top view showing a side of the insulating film away from the metal film after the metal film is attached to the insulating film according to some embodiments of the present disclosure;

[0049] Fig. 11B A schematic top view showing a side of the insulating film away from the metal film after the metal film is attached to the insulating film according to other embodiments of the present disclosure;

[0050] Fig.12 A schematic top view showing an attachment structure including a metal film and an insulating film attached thereto being attached to a wafer according to some embodiments of the present disclosure;

[0051] Fig.13 A schematic flow chart showing a method for preparing a device according to some embodiments of the present disclosure is shown;

[0052] Fig.14 schematic perspective views showing devices according to some embodiments of the present disclosure and devices of comparative examples; and

[0053] Fig.15 A schematic cross-sectional view of an apparatus according to some embodiments of the present disclosure is shown.

[0054] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0055] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed utility model is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. DETAILED DESCRIPTION

[0056] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure. In addition, techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered part of the authorized specification.

[0057] It should be understood that the following description of at least one exemplary embodiment is merely illustrative and does not constitute any limitation on the present disclosure and its application or use. It should also be understood that any implementation described exemplarily herein does not necessarily mean that it is preferred or advantageous over other implementations. The present disclosure is not limited by any stated or implied theory given in the above technical field, background technology, utility model content or specific implementation.

[0058] In addition, certain terms may also be used in the following description for reference purposes only and are not intended to be limiting. For example, the words "first", "second" and other such numerical words referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0059] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0060] Figure 1 shows a schematic top view of an apparatus according to some embodiments of the present disclosure; Figure 2 Shown along Figure 1 A schematic cross-sectional view of the device shown along line A-A'. Figure 1 and 2 As shown, the semiconductor device 20 includes a semiconductor substrate 101 and an attachment structure 200 on the semiconductor substrate 101. As shown in the figure, the attachment structure 200 may include: an insulating film 211, an attachment member 221 and a metal film 231.

[0061] The semiconductor substrate 101 may include at least one power semiconductor device (not shown). A conductive structure for electrical connection to the outside may be formed on or in the surface of the semiconductor substrate, such as a metallization layer, which may be the uppermost metallization layer of the semiconductor substrate and may include one or more portions 103 and 105, each of which may be used as a terminal (including a pad or an electrode) for the power semiconductor device. Although in the figure, the surface of the substrate 101 is shown to be substantially in the same plane, and the metallization portions 103 and 105 are embedded in an insulating film (e.g., a passivation film) 111, it should be understood that the present disclosure is not limited thereto.

[0062] The insulating film 211 is disposed on the semiconductor substrate 101. Preferably, the insulating film 211 is formed of an organic material (for example, but not limited to, polyetherimide (PEI) or polyimide (PI), etc.). Figure 3A 2 shows a schematic top view of an insulating membrane of a device according to some embodiments of the present disclosure. The insulating membrane 211 has at least one first opening (two openings 217 and 219 are shown in the figure) penetrating the insulating membrane. Figure 1 The openings 217 and 219 are schematically shown in dashed boxes. In some embodiments, the thickness of the insulating film can range from 20 microns to 150 microns, for example, 20, 50, 100, 150.

[0063] The at least one first opening 217, 219 exposes a corresponding first portion of the semiconductor substrate (eg, see Figure 3C In some embodiments, the power semiconductor device may be a power metal oxide semiconductor (MOS) field effect transistor (FET), and the openings 217, 219 may, for example, allow the current terminal (eg, source terminal) 105 of the power MOS FET to be exposed. Figure 2 ) is exposed. Although power MOS FET is used as an example for explanation here, it should be understood that the present disclosure is not limited thereto, but can be used for a variety of power devices. In addition, although the term terminal is used for explanation here, it should be understood that it can also include, or can be, or can be replaced by: a terminal, a pad, a metallization layer, etc.

[0064] like Figure 2As shown, the conductive attachment part 221 is filled in the corresponding first opening (here, 217) in the at least one first opening. The metal diaphragm (also referred to as a metal foil) 231 is disposed on the insulating diaphragm 211 and the at least one attachment part 221. In some embodiments, preferably, the metal diaphragm completely covers the at least one attachment part 221 to provide a reliable electrical connection and physical connection. The attachment part 221 joins (and thereby electrically connects) the corresponding portion of the metal diaphragm 231 with the corresponding first portion of the semiconductor substrate 101. The metal diaphragm may include one or more layers of metal or metal alloy material. In some embodiments, the metal diaphragm may include, for example but not limited to, copper (Cu), silver (Ag), gold (Au), aluminum (Al), an alloy containing one or more of the above materials, or any other suitable metal material, etc. In some embodiments, the metal diaphragm may further include an additional coating, which may include, for example but not limited to, one or more of the following materials: silver, gold, nickel (Ni), an alloy containing one or more of the above materials (e.g., Ni-Ag, Ni-Pd-Au, or Ni-Au), or any other suitable metal material, etc. In some embodiments, the thickness of the metal diaphragm may range, for example, from 35 microns to 250 microns, such as 35 microns, 50 microns, 100 microns, 150 microns, 200 microns, or 250 microns.

[0065] In some embodiments, the attachment component is obtained by processing an attachment material. As an example, the attachment material may include solder, sintering paste (eg, silver sintering paste), preformed sintering sheet, or conductive glue (eg, silver glue).

[0066] For example, after the sintering paste is filled into the opening in the insulating film, it may be necessary to preheat (predry) it; after the attachment structure containing the preheated (predried) sintering paste is attached to the substrate, sintering, welding or curing is performed to bond the metal diaphragm 231 to the substrate (more precisely, to the metal layer (terminal) on the substrate).

[0067] For example, for a preformed sintered sheet, after attaching the attachment structure including the sintered sheet to the substrate, a sintering process may be directly performed to achieve bonding between the metal diaphragm 231 and the substrate.

[0068] A transient liquid phase welding material (for example, a gold (Au)-tin (Sn) alloy or an alloy containing one or more of nickel (Ni), tin (Sn) and copper (Cu), which can be in sheet or paste form) can also be used as an attachment material to achieve the bonding of the metal diaphragm 231 to the substrate through a transient liquid phase welding process.

[0069] For example, for solder, after the solder is dispersed into the opening in the insulating film, the attachment structure is attached to the substrate; then reflow soldering can be performed to achieve bonding between the metal film 231 and the substrate. For another example, for conductive glue, after the conductive glue is dispersed into the opening in the insulating film, the attachment structure is attached to the substrate; then heating or curing treatment can be performed to achieve bonding between the metal film 231 and the substrate.

[0070] Preferably, the insulating film 211 is configured so that, when no attachment component is formed or when the material used to form the attachment component needs further processing to provide a stable bond, the insulating film 211 itself can also provide a certain degree of adhesive force to firmly bond the substrate and the metal film. For example, for the insulating film, a material that has or has been processed to have a certain degree of adhesion can be selected. In some embodiments, the insulating film 211 can be formed of an organic material such as polyetherimide (PEI) or polyimide (PI); however, the present disclosure is not limited to this. The insulating film can be heat-treated so that it is in a semi-cured state, for example, so that it has a certain degree of adhesion and can maintain its basic shape. The metal film can be attached (or bonded) to the insulating film when the insulating film is in a semi-solid state. Similarly, the attachment structure can also be bonded to the substrate (the insulating film is in contact with the substrate) when the insulating film is in a semi-solid state. It should be understood that the above examples are merely illustrative and not restrictive. For example, in other embodiments, a binder or adhesion promoter may be applied to one or both sides of the insulating film to enhance its adhesion. In some embodiments, temporary adhesion or positioning support may be provided by adsorption of a smooth surface, or by hydrogen bonds or dangling bonds between surfaces, or by an external holding device. Therefore, there is no particular limitation on the material forming the insulating film, as long as it can withstand the temperature during the process and provide a certain degree of adhesion.

[0071] In some embodiments, the insulating film 211 further includes at least one through-going second opening 215, such as Figure 1 and 2 As shown. For example, the second opening 215 may expose the corresponding second portion of the semiconductor substrate. For example, the second opening 215 may expose the control terminal (e.g., gate terminal) 103 of the power MOSFET. As shown in the figure, the metal film 231 is configured to not overlap with the second opening 215. Figure 1 In the embodiment, the opening 215 also exposes other terminals 241 and the insulating layer 111 (eg, passivation layer) on the upper portion of the substrate.

[0072] exist Figure 1 and 2In the example shown, the semiconductor substrate is a die separated from a wafer (e.g., by dicing). In this case, the material of the insulating film and the material of the metal film are substantially absent on the lateral sides of the semiconductor substrate. At least one side of the insulating film, the corresponding side of the metal film, and the corresponding side of the semiconductor substrate are substantially flush.

[0073] Figure 3B Schematic top view of a substrate portion of a device according to some embodiments of the present disclosure is shown. Figure 3B As shown, the substrate 101 includes an insulating layer 111 (e.g., a passivation layer formed of silicon dioxide or other insulating materials) on its upper portion. The insulating layer 111 has openings to expose the terminals. Here, taking MOSFET as an example, a gate terminal 103, a source terminal (or a drain terminal) 105 and 107 are shown. Other one or more auxiliary terminals 241 are also shown, which can provide connections to a back gate or a drift region, etc. In some embodiments, the gate terminal 103 may include a trench gate structure 109, such as Figure 3B It should be understood that, according to different implementations, the trench gate structure 109 may also be covered by the passivation layer 111 .

[0074] Figure 3C A schematic top view of a portion of an apparatus according to some embodiments of the present disclosure is shown. Here, Figure 3A The insulating film 211 shown is arranged on Figure 3B on the substrate shown; or, Figure 1 and 2 The metal film 231 and the attachment member 221 shown in FIG. 2 are removed. The openings 215, 217, and 219 in the insulating film 211 expose corresponding portions (including corresponding terminals) on the substrate.

[0075] Figure 3D Schematic top view of a portion of an apparatus according to some embodiments of the present disclosure is shown. Figure 3C On the basis of, the attachment member or the attachment material 221 is formed in the first openings 217 and 219 in the insulating film 211; or, Figure 1 and 2 The metal diaphragm 231 in the device is removed.

[0076] Figure 4 Schematic perspective view of a wafer-level fabrication process of a device according to some embodiments of the present disclosure is shown. Figure 4 As shown, a wafer 403 is loaded on a wafer carrier (e.g., a carrier ring) 401. The wafer 403 includes an insulating film 501 and a metal film (e.g., a copper foil) attached to the insulating film 501, and an attachment material ( Figure 4An attachment structure (not shown) is attached (bonded) to the wafer 403. The wafer 403 may include a plurality of power semiconductor devices arranged in an array.

[0077] Figure 5A shows a schematic top view of an insulating film according to some embodiments of the present disclosure, Figure 5B An enlarged view of a portion of the insulating diaphragm is shown. Figure 5A As shown, the insulating film 501 includes a plurality of units 505. The units 505 may be, for example, Figure 1-3A The insulating film 211 shown corresponds to one of the plurality of power semiconductor devices. The insulating film 211 for the die can be formed by cutting the insulating film 501 (which will be described later). Figure 5B An enlarged view of a portion of the insulating film 501 is shown. The openings 215, 217, and 219 in each cell 505 in the insulating film may expose a terminal (eg, a metal layer) of a semiconductor device in a corresponding semiconductor substrate.

[0078] Figure 6 A schematic top view of an insulating film according to some embodiments of the present disclosure is shown. Fig. 7A and 7B Schematic cross-sectional views of insulating films according to other embodiments of the present disclosure are respectively shown. In this example, additional coatings 507 and 509 are provided on the upper and lower surfaces of the insulating film 501. In some embodiments, the coatings 507 and 509 may be formed of a material different from that of the insulating film 501 and may be configured to be easily removed or peeled off from the insulating film 501, such as Figure 7B shown.

[0079] Figure 8 A schematic top view of a metal diaphragm according to some embodiments of the present disclosure is shown. In some embodiments, the metal diaphragm 601 can be formed of copper, for example, integrally formed of copper. The metal diaphragm 601 can include a frame 801 of a peripheral portion and a cross-structure 803 corresponding to an array of power devices (and corresponding units of the insulating diaphragm 501).

[0080] Fig. 9 FIG. 5 shows a schematic top view of a metal film attached to an insulating film according to some embodiments of the present disclosure. In some embodiments, the coating 507 (eg, Figure 7B ), the metal diaphragm 601 is attached to the side of the insulating diaphragm 501, as shown Fig. 9 In some embodiments, the metal film may be attached to the insulating film 501, for example, by a pick-and-place device.

[0081] Here, the cross structure 803 of the metal film 601 covers or overlaps with a corresponding row of cells 505 of the insulating film 501 and does not overlap with the openings 215 of the row of cells, that is, the openings 215 of the row of cells are exposed. Fig.10 A schematic top view of a metal diaphragm according to some embodiments of the present disclosure is shown, after the metal diaphragm is attached to the insulating diaphragm, from a side of the insulating diaphragm away from the metal diaphragm, that is, Fig. 9 The structure shown is a view from the other side after being turned over. Fig.10 As shown, the corresponding parts of the metal film 601 are exposed through the openings 217 and 219 of each unit of the insulating film 501. Fig.10 In FIG. 6 , the obscured portion of the metal film 601 under the insulating film is also shown in a semi-transparent manner. Fig.10 In the example shown, the cover film 507 on this side of the insulating film 601 is not removed.

[0082] Fig.11A FIG. 2 shows a schematic top view of a metal diaphragm according to some embodiments of the present disclosure after the metal diaphragm is attached to the insulating diaphragm from a side of the insulating diaphragm away from the metal diaphragm. Fig.11A As shown, in Fig.10 On the basis of the structure shown, an attachment material 521 is applied from the side of the insulating diaphragm 501 opposite to the metal diaphragm 601 to fill the corresponding openings 217 and 219 to form an attachment part (for example, attachment part 221). The attachment material includes a conductive material. In some embodiments, a sintering paste (also referred to as a sintering slurry) can be sprayed into the corresponding openings using a high-precision printing method; thereby reducing the probability of sintering paste overflow. It is also possible to apply a preformed sintering sheet or apply solder, conductive glue, etc. to the openings 217 and 219 as an attachment material. Here, in Fig.11A In the example shown, the coating 507 on this side of the insulating film 601 is not removed. Later, in some embodiments, the coating 507 may be removed, such as Fig. 11B In some other embodiments, the coating 507 may also be retained. In the case where the coating 507 is retained, the coating is regarded as a part of the insulating film.

[0083] Depending on the material used for the attachment component, the attachment material may be subjected to some optional treatments, such as pre-treatments such as pre-heating, pre-drying, pre-sintering, semi-curing, and the like.

[0084] For example, in some cases, certain coatings may also be applied to the substrate and / or the metal diaphragm; in this case, these coatings may be considered as part of the substrate and / or the metal diaphragm. For another example, a process involving a thermal process will naturally involve a cooling process. In the present disclosure, in order not to obscure the gist of the present disclosure, certain conventional processes or components are not described in detail, but the focus is on explaining the relevant aspects, components or processing techniques that the present disclosure is concerned with. Therefore, those skilled in the art will easily understand that the aspects or embodiments of the present disclosure do not exclude the existence of other processes or components that the present disclosure is not concerned with.

[0085] Thereafter, an attachment structure including the insulating film, the metal film, and the applied attachment material is attached to a wafer. Fig.12 FIG. 2 shows a schematic top view of an attachment structure according to some embodiments of the present disclosure being attached (bonded) to a wafer. Figure 4 and 12 As shown, the attachment material 521 and the side of the insulating film opposite to the metal film 601 are attached to the wafer, so that the attachment member 521 and the insulating film are in contact with the wafer. As mentioned above, the insulating film 501 itself can have a certain adhesion, and the metal film 601 and the wafer are held in place.

[0086] Afterwards, depending on the different attachment materials used and the different materials of the insulating film used, corresponding treatments may be performed, which are referred to as bonding treatments herein. For example, sintering or transient diffusion soldering treatments, reflow soldering treatments, baking annealing treatments, or curing treatments, etc. may be performed so that the attachment materials are firmly bonded to the metal film and the terminals (metal layers) on the wafer, etc., thereby also firmly bonding the wafer.

[0087] Fig.13 FIG. 1 is a schematic flow chart of a method 1300 for preparing a device according to some embodiments of the present disclosure. Fig.13 As shown, in step S1301, an attachment structure is provided. The attachment structure may be the attachment structure as described above. For example, the attachment structure may include: an insulating diaphragm having at least one first opening passing through the insulating diaphragm, the at least one first opening corresponding to a corresponding first portion of the semiconductor substrate. The attachment structure also includes: a metal diaphragm attached to the insulating diaphragm, the metal diaphragm including a portion overlapping with the at least one first opening of the insulating diaphragm. The attachment structure also includes: an attachment material filled in a corresponding first opening in the at least one first opening and in contact with the metal diaphragm. The attachment material includes a conductive material.

[0088] In some embodiments, providing an attachment structure may include: in step S1303, attaching a metal diaphragm to a first surface of an insulating diaphragm; and in step S1305, filling at least one first opening of the insulating diaphragm with an attachment material from a second surface of the insulating diaphragm opposite to the first surface, wherein the attachment material filled in the at least one first opening is in contact with the metal diaphragm.

[0089] The method further includes, at step S1307, attaching the attachment structure to a semiconductor wafer. The semiconductor wafer includes at least one power semiconductor device. This step causes the insulating diaphragm to contact the semiconductor wafer, the at least one first opening to correspond to the corresponding first portion of the semiconductor substrate, and the attachment material to contact the corresponding first portion of the semiconductor substrate.

[0090] In some embodiments, optionally, the method further includes, in step S1309, performing a bonding process. The process causes the attachment material to form an attachment component so as to attach and electrically connect the corresponding portion of the metal diaphragm to the corresponding first portion of the semiconductor substrate through the attachment component. The bonding process may include, for example, at least one of the following: sintering, baking, annealing or curing. Thus, the attachment material filled in the insulating diaphragm can be cured, sintered or melted, so that the metal diaphragm is attached to the semiconductor substrate (more accurately, to the metallization layer (including electrodes, terminals or pads, etc.) on the semiconductor substrate) through the attachment component. Although not described in detail here, it will be easily understood by those skilled in the art that the attachment material that has undergone the bonding process will cool to room temperature.

[0091] Then, in step S13011, cutting is performed to form a tube core, such as Figure 1 and 2 The device or die 20 shown. For example, the cutting step can be performed by sawing or laser cutting, etc. Note that the device or die 20 of the present disclosure includes a substrate and an attachment structure 200 thereon, that is, an insulating film, a metal film and an attachment component formed thereon.

[0092] Then, in step S1313, the cut tube die is bonded to the mounting substrate. For example, the cut tube die can be picked up and placed on the mounting substrate (on which an attachment material, such as sintering paste, may be formed). Then, a bonding process (such as sintering process) is performed to bond the tube die to the mounting substrate. In step S1315, the corresponding wire is bonded to the metal film and the exposed terminal (such as the gate terminal 103 or other terminal 241), such as Fig.14 shown.

[0093] Thereafter, at step S1317 , a molding process may be performed to encapsulate the die, at least a portion of the mounting substrate, and the conductive wires, etc., with a molding compound.

[0094] Fig.14 Schematic perspective views of devices according to some embodiments of the present disclosure and devices of comparative examples are shown. Fig.14 A prior art die 921 and a device (die) 923 prepared according to an embodiment of the present disclosure are shown.

[0095] Both dies 921 and 923 are mounted on a mounting substrate 900. The substrate 900 may have an insulating layer 903 and metal layers 901 and 905 above and below the insulating layer. The bottom terminals (metallization layers) of both dies 921 and 923 are bonded and electrically coupled to a die attach portion 913 in the metal layer 901 on the substrate 900. Fig.15 A schematic cross-sectional view is shown of a device 923 mounted to a mounting substrate and bonded with a wire 933 according to some embodiments of the present disclosure.

[0096] For the prior art die 921, aluminum wire 931 is attached to its current terminal (e.g., source). For the die 923 according to the present disclosure, copper wire 933 with a larger diameter can be used to bond the metal film (e.g., metal film 231) of the die 923 and the lead 915.

[0097] Since the metallization layer (e.g., electrode, terminal or pad) prepared on the semiconductor substrate in the tube core 921 of the prior art is often thin, such as a few microns (e.g., 2 microns (μm)), it may not be able to withstand the copper wire bonding process, causing defects. According to an embodiment of the present disclosure, the metal diaphragm is attached to the tube core through an insulating diaphragm and an attachment component, and the wire is attached to the metal diaphragm on the tube core, so that a wire with a larger diameter or greater hardness (e.g., a copper wire) is used, thereby improving the performance and reliability of the device. In addition, due to the presence of the insulating layers 211 and 501, the impact of the copper wire bonding process on the tube core is reduced, further improving the reliability. It should also be noted that although in the example shown, an independent wire is shown as an example, the present disclosure is not limited to this. For example, in the context of this article, the term wire also covers various forms, including a single wire and a wire strip containing multiple wires side by side.

[0098] According to one aspect of the present disclosure, there is also provided an electrical system comprising any semiconductor device as disclosed herein or as is obvious from the present disclosure.

[0099] According to an embodiment of the present disclosure, a novel wafer-level system-on-chip (DTS) package and a method for preparing the same are provided. According to the inventor's calculation, compared with the DTS solution of the prior art, the embodiment of the present disclosure can shorten the preparation process to about one-third to one-quarter, thereby greatly improving production efficiency.

[0100] In addition, according to the embodiments of the present disclosure, by providing an insulating film, the distance and electrical isolation between the metal film and the semiconductor substrate are increased, and the dielectric strength is increased, thereby preventing unwanted discharge or creepage between the substrate and the metal film connected to the source.

[0101] By providing an insulating diaphragm, adhesion can also be provided to keep the die and the metal diaphragm in place before utilizing an attachment component (or attachment material) to provide a secure attachment between the die and the metal diaphragm (e.g., Cu foil), thereby reducing or eliminating the relative displacement between the two and simplifying the process.

[0102] According to aspects and embodiments of the present disclosure, the processability and UPH of the device are improved, and harsh storage conditions are no longer required, greatly reducing the cost of delivery.

[0103] Furthermore, by providing an insulating film, mechanical strength can be provided and deformation of the attaching material before sintering / reflow can be prevented.

[0104] In addition, by providing an insulating film, various stresses or strains can be absorbed during the processing (for example, during heating treatment or pressure bonding treatment or welding wire process), such as warping, deformation or other strains caused by differences in thermal expansion coefficient (CTE) or externally applied pressure.

[0105] According to the embodiments of the present disclosure, the use of a tacking agent is avoided, thereby avoiding the void problem existing in the prior art, thereby increasing the reliability and life of the device.

[0106] According to the embodiment of the present disclosure, by using an insulating film and filling the attaching member (or attaching material) in the opening in the insulating film, the thickness of the attaching material is increased, and the reliability of the attaching is improved.

[0107] Although the embodiments are described herein using power MOS FET as an example, those skilled in the art will readily appreciate that the present disclosure is not limited thereto, but can be applied to a variety of power devices, such as, but not limited to, thyristors, power diodes, as long as they have electrodes or terminals that need to withstand large currents and / or large voltages, the principles and teachings of the present disclosure can be used.

[0108] Those skilled in the art will appreciate that the boundaries between the operations (or steps) described in the above-described embodiments are merely illustrative. Multiple operations can be combined into a single operation, which can be distributed in additional operations, and the operations can be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, variations, and replacements are equally possible. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0109] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate comprising at least one power semiconductor device; An insulating film on the semiconductor substrate has at least one first opening penetrating the insulating film, wherein the at least one first opening exposes a corresponding first portion of the semiconductor substrate; at least one conductive attachment member filled in a corresponding first opening of the at least one first opening; as well as a metal diaphragm disposed on the insulating diaphragm and the at least one attachment member, The at least one attachment member bonds and electrically connects a corresponding portion of the metal diaphragm to a corresponding first portion of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein: in, The insulating film further comprises at least one second opening, wherein the at least one second opening exposes a corresponding second portion of the semiconductor substrate. The metal diaphragm does not overlap with the at least one second opening.

3. The semiconductor device according to claim 2, wherein: in, The at least one first opening exposes at least a portion of a corresponding current terminal of a corresponding semiconductor device, and the at least one second opening exposes at least a portion of a control terminal of the corresponding semiconductor device.

4. The semiconductor device according to claim 1, wherein: in, The semiconductor substrate comprises a wafer, The at least one power semiconductor device comprises a plurality of power semiconductor devices arranged in an array, The insulating film includes a plurality of first openings, and the plurality of first openings respectively expose metallization layers of corresponding power semiconductor devices among the plurality of power semiconductor devices.

5. The semiconductor device according to claim 1, wherein: in, The semiconductor substrate includes dies separated from a wafer, wherein the insulating film and the metal film are substantially absent on the lateral sides of the semiconductor substrate, and Wherein, at least one side surface of the insulating diaphragm, the corresponding side surface of the metal diaphragm and the corresponding side surface of the semiconductor substrate are substantially flush.

6. The semiconductor device according to claim 1, wherein: in, The insulating film is formed of an organic material, and The metal diaphragm includes one or more layers of metal material.

7. The semiconductor device according to claim 1, wherein: in, The attachment member is obtained by bonding the applied attachment material. The joining process includes at least one of the following: Sintering, firing, annealing, transient liquid phase welding and solidification.

8. The semiconductor device according to claim 7, wherein: in, The attachment material includes one of the following: Sintering pastes, pre-sintered sheets, solders, transient liquid phase soldering materials, and conductive adhesives.

9. The semiconductor device according to claim 3, wherein: in, The semiconductor device is a power MOS transistor, the at least one first opening exposes at least a portion of a corresponding source or drain terminal of the corresponding semiconductor device, and the at least one second opening exposes at least a portion of a gate terminal of the corresponding semiconductor device.

10. The semiconductor device according to claim 3, wherein: Also includes: at least one first conductive line coupled to a corresponding current terminal of the corresponding semiconductor device; as well as At least one second conductive line is coupled to a corresponding control terminal of the corresponding semiconductor device.

11. The semiconductor device according to claim 10, wherein: Also includes: a mounting substrate including a die attach portion and leads, wherein the semiconductor substrate is attached to the die attach portion, The at least one first conductive line is coupled to the lead, and The at least one first conductive line comprises a copper conductive line.

12. An electrical system, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 11.

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