Stacked transistor

Abstract

In one embodiment, a stacked transistor includes a lower semiconductor nanostructure, an isolation structure, an upper semiconductor nanostructure, and a gate dielectric. A lower semiconductor nanostructure is over the substrate. The isolation structure is on the lower semiconductor nanostructure. The upper semiconductor nanostructure is on the isolation structure. The gate dielectric respectively surrounds the isolation structure, the lower semiconductor nanostructure, and the upper semiconductor nanostructure.

Description

Technical Field

[0001] The present disclosure relates to a stacked transistor. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and patterning the various material layers using lithography techniques to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size is reduced, other problems arise that need to be solved. Utility Model Content

[0004] In some embodiments disclosed herein, a stacked transistor includes a lower semiconductor nanostructure, an isolation structure, an upper semiconductor nanostructure, and a gate dielectric. The lower semiconductor nanostructure is located above a substrate. The isolation structure is located on the lower semiconductor nanostructure. The upper semiconductor nanostructure is located on the isolation structure. The gate dielectric surrounds the isolation structure, the lower semiconductor nanostructure, and the upper semiconductor nanostructure, respectively.

[0005] In some embodiments disclosed herein, a stacked transistor includes a lower semiconductor nanostructure, a middle semiconductor nanostructure, and an upper semiconductor nanostructure. The lower semiconductor nanostructure is located above a substrate and includes a plurality of lower gate structure layers located above the substrate and a plurality of lower nanostructure layers alternately disposed with the lower gate structure layers and located above the substrate. The middle semiconductor nanostructure is located on the lower semiconductor nanostructure and includes an isolation structure. The upper semiconductor nanostructure is located on the middle semiconductor nanostructure and includes a plurality of upper gate structure layers located on the middle semiconductor nanostructure and a plurality of upper nanostructure layers alternately disposed with the upper gate structure layers and located above the middle semiconductor nanostructure.

[0006] In some embodiments of the present disclosure, a stacked transistor includes a first semiconductor nanostructure located above a substrate, a first gate electrode located around the first semiconductor nanostructure, an isolation structure located on the first gate electrode, a second semiconductor nanostructure located on the isolation structure, and a second gate electrode located around the second semiconductor nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In practice, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An exemplary schematic diagram of a stacked transistor (eg, a complementary field-effect transistor (CFET)) according to some embodiments is depicted in a three-dimensional view; and

[0009] Figures 2 to 12B is a diagram of a CFET at an intermediate stage in the fabrication process according to some embodiments.

[0010]

Explanation of symbols

[0011] 50:Substrate

[0012] 52: Multi-layer stacking

[0013] 54: Virtual Layer

[0014] 54A: First virtual layer

[0015] 54B: Second virtual layer

[0016] 56: Semiconductor layer

[0017] 56U: Upper semiconductor layer

[0018] 56L: Lower semiconductor layer

[0019] 62: Fins

[0020] 64,66: Nanostructures

[0021] 64A: First Virtual Nanostructure

[0022] 64B: Second virtual nanostructure

[0023] 66U: Upper semiconductor nanostructure

[0024] 66L: Lower semiconductor nanostructure

[0025] 66M: Intermediate Semiconductor Nanostructures

[0026] 70: Quarantine

[0027] 72: Virtual dielectric layer

[0028] 74: Virtual gate layer

[0029] 76: Mask layer

[0030] 82: Virtual Dielectric

[0031] 84: Virtual Gate

[0032] 86:Mask

[0033] 90: Gate spacer

[0034] 94: Source / drain groove

[0035] 96A: Sidewall depression

[0036] 96B: Open

[0037] 98:Internal spacer

[0038] 100: Isolation structure

[0039] 108: Source / drain region

[0040] 108U: Upper epitaxial source / drain region

[0041] 108L: Lower epitaxial source / drain region

[0042] 112: first contact etching stop layer / first CESL

[0043] 114: first interlayer dielectric / first ILD

[0044] 122: Second CESL

[0045] 124: Second ILD

[0046] 132: Gate dielectric

[0047] 134: Gate electrode

[0048] 134U: Upper gate electrode

[0049] 134L: Lower gate electrode

[0050] 142:Metal-Semiconductor Alloy Area

[0051] 144: Source / drain contact

[0052] 152: Etch stop layer / ESL

[0053] 154: Third ILD

[0054] 156: Gate contact

[0055] 158: Source / drain vias

[0056] AA',BB': section line DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these specific examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0058] Additionally, for ease of description, spatially relative terms (e.g., "underlying," "beneath," "lower," "overlying," "upper," and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the accompanying figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0059] According to various embodiments, a complementary field-effect transistor (CFET) is formed. The CFET includes a lower nanostructure-FET and an upper nanostructure-FET. An isolation structure (also referred to as a nanostructure isolation material) is formed between the lower nanostructure-FET and the upper nanostructure-FET. First, the isolation structure can be formed by forming a virtual nanostructure in a multilayer stack, and then, after subsequent processing of the multilayer stack, at least partially replacing the virtual nanostructure with the isolation structure. In some embodiments, the virtual nanostructure is formed of doped silicon, and therefore, the risk of defects in the multilayer stack can be effectively reduced, while providing good etching selectivity and insulation properties. Accordingly, the performance of the device can be improved and the ease of manufacturing of the CFET can be completed.

[0060] Figure 1 An exemplary schematic diagram of a stacked transistor (CFET) is depicted in accordance with some embodiments. Figure 1 It is a three-dimensional view, and some features of the CFET are omitted for clarity.

[0061] The CFET includes a plurality of vertically stacked nanostructure FETs (e.g., nanowire FETs, nanosheet FETs, multi-bridge channel (MBC) FETs, nanobelt FETs, or gate-all-around (GAA) FETs, etc.). For example, the CFET may include a lower nanostructure-FET of a first device type (e.g., n-type / p-type) and an upper nanostructure-FET of a second device type (e.g., p-type / n-type), and the second device type is opposite to the first device type. Specifically, the CFET may include a lower PMOS transistor and an upper NMOS transistor, or the CFET may include a lower NMOS transistor and an upper PMOS transistor. Each nanostructure-FET includes a semiconductor nanostructure 66 (including a lower semiconductor nanostructure 66L and an upper semiconductor nanostructure 66U), wherein the semiconductor nanostructure 66 serves as a channel region of the nanostructure-FET. The semiconductor nanostructure 66 may be a nanosheet or a nanowire, etc. The lower semiconductor nanostructure 66L is configured on the lower nanostructure-FET, and the upper semiconductor nanostructure 66U is configured on the upper nanostructure-FET. Channel isolation material (in Figure 1 Not clearly shown, please refer to FIG. 12A to FIG. 12B ) may be configured to separate and electrically isolate the upper semiconductor nanostructure 66U from the lower semiconductor nanostructure 66L.

[0062] The gate dielectric 132 is disposed along the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 66. The gate electrode 134 (including the lower gate electrode 134L and the upper gate electrode 134U) is located above the gate dielectric 132 and surrounds the semiconductor nanostructure 66. The source / drain region 108 (including the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U) is disposed on opposite sides of the gate dielectric 132 and the gate electrode 134. The source / drain region 108 may refer to a source or a drain individually or collectively depending on the context. An isolation component may be formed to separate a desired one of the source / drain regions 108 and / or a desired one of the gate electrodes 134. For example, the lower gate electrode 134L may be selectively separated from the upper gate electrode 134U. Alternatively, the lower gate electrode 134L may be coupled to the upper gate electrode 134U. In addition, the upper epitaxial source / drain region 108U may be formed by one or more dielectric layers ( Figure 1 Not clearly shown, please refer to FIG. 12A to FIG. 12B ) is separated from the lower epitaxial source / drain region 108L. The isolation components located between the channel region, the gate and the source / drain region can be configured in a vertically stacked transistor and increase the device density. Due to the vertical stacking nature of the CFET, the schematic diagram can also be called a stacked transistor or a folded transistor.

[0063] Figure 1 Reference cross-sectional lines used in the following figures are also shown. Cross-sectional line AA' is parallel to the longitudinal axis of the semiconductor nanostructure 66 of the CFET and is along the direction of current flow, for example, between the source / drain regions 108 of the CFET. Cross-sectional line BB' is perpendicular to cross-sectional line AA' and is along the longitudinal axis of the gate electrode 134 of the CFET. For clarity, the following figures will refer to these reference cross-sectional lines.

[0064] Figures 2 to 12B is a diagram of an intermediate stage in the fabrication process of a CFET according to some embodiments. Figure 2 , Figure 3 and Figure 4 Draws the Figure 1 Similar 3D view. Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig. 12A Plotted along a path similar to Figure 1 Cross-sectional view along the section line AA'. Fig. 12B Plotted along a path similar to Figure 1 Cross-sectional view along the section line BB'.

[0065] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 50 may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally speaking, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0066] A multilayer stack 52 is formed over the substrate 50. The multilayer stack 52 includes alternating dummy layers 54 (including a first dummy layer 54A and a second dummy layer 54B) and semiconductor layers 56 (including a lower semiconductor layer 56L and an upper semiconductor layer 56U). A subset of the lower semiconductor layer 56L and the first dummy layer 54A is disposed below the second dummy layer 54B. The upper semiconductor layer 56U and another subset of the first dummy layer 54A are disposed above the second dummy layer 54B. As described in more detail below, the dummy layer 54 is removed and the semiconductor layer 56 is patterned to form a channel region of the CFET. Specifically, the lower semiconductor layer 56L is patterned to form a channel region of the lower nanostructure-FET of the CFET, and the upper semiconductor layer 56U is patterned to form a channel region of the upper nanostructure-FET of the CFET.

[0067] The multilayer stack 52 is illustrated as including a specific number of dummy layers 54 and a specific number of semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of dummy layers 54 and semiconductor layers 56. Each layer of the multilayer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE) and deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0068] The first virtual layer 54A is formed of a first semiconductor material, and the second virtual layer 54B is formed of a second semiconductor material. The first semiconductor material and the second semiconductor material can be selected from candidate semiconductor materials of the substrate 50. The semiconductor materials of the first virtual layer 54A and the second virtual layer 54B will be described in more detail later. The first and second semiconductor materials have high etching selectivity to each other. Therefore, in the subsequent process, the material of the second virtual layer 54B can be removed at a faster rate than the material of the first virtual layer 54A.

[0069] The semiconductor layer 56 (including the lower semiconductor layer 56L and the upper semiconductor layer 56U) is formed of one or more semiconductor materials. The semiconductor material can be selected from the candidate semiconductor material of the substrate 50. The lower semiconductor layer 56L and the upper semiconductor layer 56U can be formed of the same semiconductor material, or can be formed of different semiconductor materials. In some embodiments, the lower semiconductor layer 56L and the upper semiconductor layer 56U are both formed of semiconductor materials suitable for p-type devices and n-type devices (e.g., silicon). In some embodiments, the lower semiconductor layer 56L is formed of a semiconductor material suitable for a p-type device (e.g., germanium or silicon-germanium), and the upper semiconductor layer 56U is formed of a semiconductor material suitable for an n-type device (silicon or carbon-doped silicon). The semiconductor material of the semiconductor layer 56 will be described in more detail later. The semiconductor material of the semiconductor layer 56 has a high etching selectivity relative to the semiconductor material of the virtual layer 54. Therefore, in subsequent processes, the material of the virtual layer 54 can be removed at a faster rate than the material of the semiconductor layer 56.

[0070] Some layers of the multilayer stack 52 may be thicker than other layers of the multilayer stack 52. The thickness of the second virtual layer 54B may be different from (e.g., greater than or less than) the thickness of the first virtual layer 54A. In some embodiments, the second virtual layer 54B has a small thickness, such as a smaller thickness than each first virtual layer 54A. Forming the second virtual layer 54B to a smaller thickness may allow the second virtual layer 54B to be more easily removed in a subsequent process. In other embodiments, the second virtual layer 54B has a large thickness, such as a larger thickness than each first virtual layer 54A. Forming the second virtual layer 54B to a large thickness may increase the isolation effect between the subsequently formed channel regions. In some embodiments, the thickness of the first virtual layer 54A is between 3nm and 10nm, while the thickness of the second virtual layer 54B is between 1nm and 4nm, and the second virtual layer 54B is 40% to 90% thinner than the first virtual layer 54A. A thickness of the second virtual layer 54B less than 1nm or greater than 4nm may result in over-etching or under-etching during removal of the second virtual layer 54B in a subsequent process, respectively. In addition, the thickness of each semiconductor layer 56 may be different from (e.g., greater than or less than) the thickness of each first dummy layer 54A and / or second dummy layer 54B. In some embodiments, the second dummy layer 54B may be thicker than each semiconductor layer 56. In other embodiments, each semiconductor layer 56 may be thicker than each dummy layer 54.

[0071] In some embodiments, the first virtual layer 54A is formed of silicon-germanium, while the second virtual layer 54B is formed of doped silicon, and the semiconductor layer 56 is formed of silicon. In this process step, the silicon of the semiconductor layer 56 can be undoped or lightly doped. In some embodiments, the second virtual layer 54B is formed of silicon doped with n-type impurities or p-type impurities. The n-type impurity can be phosphorus or arsenic, etc. The p-type impurity can be boron, etc. Using doped silicon as the second virtual layer 54B makes the second virtual layer 54B have a high etching selectivity relative to the first virtual layer 54A and the semiconductor layer 56. For example, the second virtual layer 54B can be at least partially replaced with an isolation structure. As part of the replacement process, the second virtual layer 54B can be removed using an etchant that is selective to the dopant of the second virtual layer 54B. Therefore, the second virtual layer 54B can be removed at a faster rate than the first virtual layer 54A and the semiconductor layer 56. Using doped silicon as the second virtual layer 54B can be superior to other semiconductor materials (for example, having a high germanium concentration). Semiconductor materials with high germanium concentrations have low critical thickness, so when grown to a large thickness, there may be a high risk of defects. In addition, using doped silicon as the second dummy layer 54B can reduce the lattice mismatch of the lower semiconductor layer 56L (the lower semiconductor layer 56L is grown with the second dummy layer 54B). Therefore, forming the second dummy layer 54B doped with silicon can allow the second dummy layer 54B to grow to a large thickness while still maintaining etching selectivity and reducing the risk of defects.

[0072] exist Figure 3In the embodiment of the present invention, a fin 62 is formed in the substrate 50, and nanostructures 64, 66 (including a first virtual nanostructure 64A, a second virtual nanostructure 64B, a lower semiconductor nanostructure 66L, an intermediate semiconductor nanostructure 66M, and an upper semiconductor nanostructure 66U) are formed in the multilayer stack 52. In some embodiments, the nanostructures 64, 66 and the fin 62 can be formed in the multilayer stack 52 and the substrate 50 by etching grooves in the multilayer stack 52 and the substrate 50, respectively. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic. The nanostructures 64 and 66 formed by etching the multilayer stack 52 may be defined by the first virtual layer 54A to define the first virtual nanostructure 64A, by the second virtual layer 54B to define the second virtual nanostructure 64B, by a portion of the lower semiconductor layer 56L to define the lower semiconductor nanostructure 66L, by a portion of the upper semiconductor layer 56U to define the upper semiconductor nanostructure 66U, and by a portion of the lower semiconductor layer 56L and a portion of the upper semiconductor layer 56U to define the middle semiconductor nanostructure 66M. The first virtual nanostructure 64A and the second virtual nanostructure 64B may be collectively referred to as virtual nanostructures 64. The lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U may be collectively referred to as semiconductor nanostructures 66.

[0073] As described in more detail below, one of the nanostructures 64, 66 will be removed to form the channel region of the CFET. Specifically, the lower semiconductor nanostructure 66L serves as the channel region of the lower nanostructure-FET of the CFET. In addition, the upper semiconductor nanostructure 66U serves as the channel region of the upper nanostructure-FET of the CFET.

[0074] The intermediate semiconductor nanostructure 66M is a semiconductor nanostructure 66 that is directly above / below (e.g., in contact with) the second dummy nanostructure 64B. Depending on the height of the source / drain regions to be formed later, the intermediate semiconductor nanostructure 66M may or may not be adjacent to any source / drain regions and may or may not serve as a functional channel region of the CFET. The second dummy nanostructure 64B will subsequently be replaced by an isolation structure. The isolation structure and the intermediate semiconductor nanostructure 66M may define the boundaries of the lower nanostructure-FET and the upper nanostructure-FET.

[0075] The fins 62 and nanostructures 64, 66 may be patterned by any suitable method. For example, the fins 62 and nanostructures 64, 66 may be patterned using one or more lithography processes, including double patterning or multi-patterning processes. In general, double patterning or multi-patterning processes combine lithography processes with self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch smaller than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Next, the sacrificial layer is removed, and the remaining spacers may then be used to pattern the fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may remain on the nanostructures 64, 66.

[0076] Although each fin 62 and each nanostructure 64, 66 are depicted as having a constant width, in other embodiments, the fin 62 and / or the nanostructure 64, 66 may have tapered sidewalls such that the width of each fin 62 and / or the width of each nanostructure 64, 66 continuously increases toward the substrate 50. In such embodiments, each nanostructure 64, 66 may have different widths and be trapezoidal in shape.

[0077] In addition, an isolation region 70 is formed above the substrate 50 and between adjacent semiconductor fins 62. The isolation region 70 may include a liner and a filling material above the liner. The liner and the filling material may include a dielectric material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof. The formation of the isolation region 70 may include depositing a dielectric material and performing a planarization process (e.g., a chemical mechanism polish (CMP) process or a mechanical polishing process, etc.) to remove excess portions of the dielectric material (e.g., portions above the nanostructures 64 and 66). The deposition process may include ALD, high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or a combination thereof. In some embodiments, the isolation region 70 including silicon oxide is formed by an FCVD process and an annealing process. Then, the dielectric material is recessed to define the isolation region 70. The dielectric material may be recessed so that upper portions of the semiconductor fins 62 and nanostructures 64 , 66 extend above the isolation regions 70 .

[0078] The processes described above are only one example of how the fin 62 and the nanostructures 64, 66 may be formed. In some embodiments, the fin 62 and / or the nanostructures 64, 66 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 62 and / or the nanostructure 64, 66. The epitaxial structure may include the aforementioned alternating semiconductor materials, such as the first semiconductor material, the second semiconductor material, and doped silicon of the second virtual nanostructure 64B. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be in-situ doped during growth, and even though in-situ doping and implantation doping may be operated together, in-situ doping may prevent previous and / or subsequent implants from mixing with each other.

[0079] In addition, appropriate wells (not shown separately) may be formed in the semiconductor nanostructure 66. For example, n-type impurity implantation and / or p-type impurity implantation may be performed, or the semiconductor material may be in-situ doped during growth. The n-type impurity may be at a concentration between 10 17 atom / cm 3 Up to 10 19 atom / cm 3 Phosphorus, arsenic or antimony, etc. The p-type impurity can be a concentration between 10 17 atom / cm 3 Up to 10 19 atom / cm 3 The well in the lower semiconductor nanostructure 66L has a conductivity type opposite to that of the lower source / drain region to be formed later, and the lower source / drain region to be formed later is adjacent to the lower semiconductor nanostructure 66L. The well in the upper semiconductor nanostructure 66U has a conductivity type opposite to that of the upper source / drain region to be formed later, and the upper source / drain region to be formed later is formed adjacent to the upper semiconductor nanostructure 66U.

[0080] When the semiconductor nanostructure 66 is doped, the semiconductor nanostructure 66 may have a lower dopant concentration than the first dummy nanostructure 64A. In some embodiments, the first dummy nanostructure 64A has a dopant concentration greater than 10 20 atom / cm 3 The dopant concentration of the semiconductor nanostructure 66 is between 10 17 atom / cm 3 Up to 10 19 atom / cm 3Therefore, the desired etching selectivity between the materials of the first virtual nanostructure 64A, the second virtual nanostructure 64B, and the semiconductor nanostructure 66 can still be achieved. Therefore, as described in more detail later, the first virtual nanostructure 64A can be removed at a faster rate than the second virtual nanostructure 64B and the semiconductor nanostructure 66.

[0081] exist Figure 4 In the embodiment, a dummy dielectric layer 72 is formed on the fin 62 and / or the nanostructures 64, 66. The dummy dielectric layer 72 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 74 is formed on the dummy dielectric layer 72, and a mask layer 76 is formed on the dummy gate layer 74. The dummy gate layer 74 may be deposited on the dummy dielectric layer 72 and then planarized, such as by CMP planarization. The mask layer 76 may be deposited on the dummy gate layer 74. The dummy gate layer 74 may be a conductive or non-conductive material, and may be selected from a combination including amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 74 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other deposition techniques to deposit the selected material. The dummy gate layer 74 may be formed of other materials having high etch selectivity to insulating materials. The mask layer 76 may include, for example, silicon nitride or silicon oxynitride, etc. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 70, such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the isolation region 70. In another embodiment, the dummy dielectric layer 72 only covers the fins 62 and / or the nanostructures 64, 66.

[0082] exist Figure 5 In the embodiment of the present invention, the mask layer 76 can be patterned using acceptable lithography and etching techniques to form a mask 86. Then, the pattern of the mask 86 can be transferred to the virtual gate layer 74 and the virtual dielectric layer 72 to form a virtual gate 84 and a virtual dielectric 82. The virtual gate 84 will cover the channel area corresponding to the nanostructures 64 and 66. The pattern of the mask 86 can be used to physically separate each virtual gate 84 from an adjacent virtual gate 84. The virtual gate 84 can also have a length direction that is substantially perpendicular to the length direction of each fin 62. Optionally, the mask 86 can be removed after patterning, for example by any acceptable etching technique.

[0083] exist Figure 6In the embodiment of the present invention, gate spacers 90 are formed above nanostructures 64, 66 and on exposed sidewalls of mask 86 (if present), dummy gate 84 and dummy dielectric 82. Gate spacers 90 can be formed by conformally forming one or more dielectric materials and then etching the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride or silicon carbon nitride oxide, etc., and the dielectric material may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Other dielectric materials may also be formed by any acceptable process. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, may be performed to pattern the dielectric material. The etching may be anisotropic. During etching, part of the dielectric material will remain on the sidewalls of dummy gate 84 (forming gate spacers 90). In some embodiments, during etching, part of the dielectric material may also remain on the sidewalls of fin 62 and / or nanostructure 64, 66.

[0084] Further, implantation of a lightly doped source / drain (LDD) region (not shown separately) may be performed. LDD implantation may be performed before forming the gate spacer 90. Appropriate types of impurities may be implanted into the nanostructures 64, 66 and implanted to a desired depth. The LDD region may have the same conductivity type as the source / drain region subsequently formed adjacent to the semiconductor nanostructure 66. In addition, the conductivity type of the LDD region in the lower semiconductor nanostructure 66L may be opposite to the conductivity type of the LDD region in the upper semiconductor nanostructure 66U. In some embodiments, the lower semiconductor nanostructure 66L has a p-type LDD region, while the upper semiconductor nanostructure 66U has an n-type LDD region. In some embodiments, the lower semiconductor nanostructure 66L has an n-type LDD region, while the upper semiconductor nanostructure 66U has a p-type LDD region. The n-type impurity may be any of the aforementioned n-type impurities, and the p-type impurity may be any of the aforementioned p-type impurities. The impurity concentration of the lightly doped source / drain region may be between 10 17 atom / cm 3 Up to 10 20 atom / cm 3 Annealing can be used to repair damage caused by implantation and activate implanted impurities. In some embodiments, the growth material of nanostructures 64, 66 can be in-situ doped during growth, even if in-situ doping and implantation doping can be operated together, in-situ doping can avoid mixing of previous and / or subsequent implants.

[0085] It should be noted that the above discloses a general process for forming spacers and LDD regions, and other processes and sequences may also be used. For example, fewer or more spacers may be used, a different sequence of steps may be used, more spacers may be formed and removed, etc.

[0086] Source / drain recesses 94 are formed in the fins 62, the nanostructures 64, 66, and the substrate 50. Subsequently, epitaxial source / drain regions are formed in the source / drain recesses 94. The source / drain recesses 94 may extend through the nanostructures 64, 66 and into the substrate 50. The fins 62 may be etched so that the bottom surface of the source / drain recesses 94 is disposed above, below, or flush with the top surface of the isolation region 70. In the example shown, the top surface of the isolation region 70 is located above the bottom surface of the source / drain recesses 94. The source / drain recesses 94 may be formed by etching the fins 62, the nanostructures 64, 66, and the substrate 50 by an anisotropic etching process, such as RIE or NBE. During the etching process to form the source / drain recesses 94, the gate spacers 90 and the dummy gate 84 may shield portions of the fins 62, the nanostructures 64, 66, and the substrate 50. A single etching process or multiple etching processes may be used to etch each nanostructure 64, 66 and / or fin 62. A timed etching process may be used to stop etching the source / drain recesses 94 after the source / drain recesses 94 reach a desired depth.

[0087] exist Figure 7 In the embodiment, the sidewall of the first dummy nanostructure 64A exposed by the source / drain recess 94 is recessed to form a sidewall recess 96A. In addition, the second dummy nanostructure 64B is removed to form an opening 96B between the lower semiconductor nanostructure 66L (commonly) and the upper semiconductor nanostructure 66U (commonly). Subsequently, the sidewall recess 96A is filled with a spacer. The opening 96B is then filled with an isolation structure.

[0088] The sidewall recess 96A may be formed by recessing the sidewalls of the first virtual nanostructure 64A using any acceptable etching process. The etching is selective to the first virtual nanostructure 64A (e.g., by selectively etching the material of the first virtual nanostructure 64A at a faster rate than etching the material of the semiconductor nanostructure 66). The etching may be isotropic. Although the sidewalls of the first virtual nanostructure 64A are depicted as straight after etching, the sidewalls may be concave or convex.

[0089] The opening 96B can be formed by removing the second dummy nanostructure 64B using any acceptable etching process. The etching process is selective to the second dummy nanostructure 64B (e.g., selectively etches the material of the second dummy nanostructure 64B at a faster rate than the material of the semiconductor nanostructure 66). The etching can be isotropic. The dummy gate 84 can attach and support the upper semiconductor nanostructure 66U so that the upper semiconductor nanostructure 66U does not collapse after the opening 96B is formed.

[0090] In some embodiments, the same etching process is used to recess the sidewall of the first virtual nanostructure 64A and remove the second virtual nanostructure 64B. For example, the second virtual nanostructure 64B can be completely removed without completely removing the first virtual nanostructure 64A, and the first virtual nanostructure 64A can be recessed without significantly recessing the semiconductor nanostructure 66. The etching process is selective between the materials of the first virtual nanostructure 64A, the second virtual nanostructure 64B, and the semiconductor nanostructure 66. Specifically, the etching process selectively etches the material of the first virtual nanostructure 64A at a faster rate than the material of the semiconductor nanostructure 66, and also selectively etches the second virtual nanostructure 64B at a faster rate than the material of the first virtual nanostructure 64A. Therefore, the etching rate of the first virtual nanostructure 64A is less than the etching rate of the second virtual nanostructure 64B, and is greater than the etching rate of the semiconductor nanostructure 66. In some embodiments, the first dummy nanostructure 64A is formed of silicon germanium, the second dummy nanostructure 64B is formed of doped silicon having a high doping concentration, and the semiconductor nanostructure 66 is formed of doped silicon having a low doping concentration, and the etching process is dry etching using chlorine gas (with or without plasma). The etching process etches the doped silicon having a high dopant concentration at a faster rate than etching the doped silicon having a low dopant concentration.

[0091] The middle semiconductor nanostructure 66M is exposed through the opening 96B. In some embodiments, the etching process thins the middle semiconductor nanostructure 66M. Therefore, the thickness of the middle semiconductor nanostructure 66M can be different from (e.g., less than) the thickness of the lower semiconductor nanostructure 66L and the thickness of the upper semiconductor nanostructure 66U. In some embodiments, after the etching process, the middle semiconductor nanostructure 66M is 0% to 20% thinner than the lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U.

[0092] exist Figure 8In the embodiment, an inner spacer 98 is formed in the sidewall recess 96A and on the sidewalls of the remaining portion of the first virtual nanostructure 64A. As described in more detail below, the source / drain region will be subsequently formed in the source / drain groove 94, and the first virtual nanostructure 64A will be replaced by a corresponding gate structure. The inner spacer 98 serves as an isolation component between the subsequently formed source / drain region and the subsequently formed gate structure. In addition, the inner spacer 98 can be used to prevent the subsequently formed source / drain region from being damaged by a subsequent etching process (e.g., an etching process for forming a gate structure). In addition, an isolation structure 100 is formed in the opening 96B and between the intermediate semiconductor nanostructures 66M. The isolation structure 100 and the intermediate semiconductor nanostructure 66M define the boundaries of the lower nanostructure-FET and the upper nanostructure-FET.

[0093] The inner spacer 98 and the isolation structure 100 can be formed by conformally forming an insulating material in the source / drain groove 94, the sidewall recess 96A and the opening 96B and then etching the insulating material. The insulating material can be a carbon-containing dielectric material, such as silicon oxycarbonitride, silicon oxycarbon or silicon oxynitride. Other low dielectric constant (low-k) materials with a k value less than about 3.5 can also be used. The insulating material can be formed by a deposition process such as ALD or CVD. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etching such as RIE, NBE, etc. During etching, part of the insulating material will remain in the sidewall recess 96A (forming the inner spacer 98), and part of the insulating material will remain in the opening 96B (forming the isolation structure 100).

[0094] Although the outer sidewalls of the inner spacers 98 and the isolation structures 100 are depicted as being flush with the sidewalls of the semiconductor nanostructures 66, the outer sidewalls of the inner spacers 98 and the isolation structures 100 may extend beyond the sidewalls or be recessed from the sidewalls. Thus, the inner spacers 98 and the isolation structures 100 of the semiconductor nanostructures 66 may partially fill, completely fill, or overfill the sidewall recesses 96A and the openings 96B, respectively. Furthermore, although the sidewalls of the inner spacers 98 and the isolation structures 100 are depicted as being straight, the sidewalls of the inner spacers 98 and the isolation structures 100 may be concave or convex.

[0095] Isolation structure 100 has a similar size to second dummy nanostructure 64B replaced by isolation structure 100. Therefore, isolation structure 100 may have a large thickness, such as a greater thickness than semiconductor nanostructure 66 and first dummy nanostructure 64A, or isolation structure 100 may have a small thickness, such as a smaller thickness than semiconductor nanostructure 66 and first dummy nanostructure 64A. In some embodiments, isolation structure 100 is 60% to 90% thinner than semiconductor nanostructure 66, and isolation structure 100 is 40% to 90% thinner than first dummy nanostructure 64A.

[0096] exist Fig. 9 In the embodiment of the present invention, a lower epitaxial source / drain region 108L and an upper epitaxial source / drain region 108U are formed in the source / drain recess 94. A first contact etch stop layer (CESL) 112 and / or a first inter-layer dielectric (ILD) 114 may also be formed in the source / drain recess 94. The first ILD 114 is located between the upper epitaxial source / drain region 108U and the lower epitaxial source / drain region 108L. The lower epitaxial source / drain region 108L is used for the lower nanostructure-FET of the CFET, and the upper epitaxial source / drain region 108U is used for the upper nanostructure-FET of the CFET. Therefore, the first ILD 114 serves as an isolation region to prevent the lower and upper nanostructure-FETs from shorting. Additionally, a second CESL 122 and / or a second ILD 124 may be formed on the upper epitaxial source / drain region 108U.

[0097] The lower epitaxial source / drain region 108L contacts the lower semiconductor nanostructure 66L, but does not contact the upper semiconductor nanostructure 66U. In some embodiments, the lower epitaxial source / drain region 108L applies stress in the corresponding channel region of the lower semiconductor nanostructure 66L, thereby improving performance. The lower epitaxial source / drain region 108L is formed in the source / drain groove 94 so that each stack of the lower semiconductor nanostructure 66L is disposed between its adjacent pair of lower epitaxial source / drain regions 108L. In some embodiments, the inner spacer 98 is used to separate the lower epitaxial source / drain region 108L from the first dummy nanostructure 64A, and the first dummy nanostructure 64A will be replaced by a gate structure in a subsequent process.

[0098] The lower epitaxial source / drain region 108L is epitaxially grown in the lower portion of the source / drain recess 94. For example, the lower epitaxial source / drain region 108L can be laterally grown from the exposed sidewalls of the lower semiconductor nanostructure 66L. During the epitaxial growth of the lower epitaxial source / drain region 108L, the middle semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U can be shielded to prevent undesired epitaxial growth on the middle semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U. After growing the lower epitaxial source / drain region 108L, the shield on the middle semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U can be removed. The lower epitaxial source / drain region 108L has a conductivity type suitable for the device type of the lower nanostructure-FET. In some embodiments, the lower epitaxial source / drain region 108L is an n-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon, the lower epitaxial source / drain region 108L may include a material that applies tensile strain to the lower semiconductor nanostructure 66L, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, or silicon arsenide. In some embodiments, the lower epitaxial source / drain region 108L is a p-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon-germanium, the lower epitaxial source / drain region 108L may include a material that applies compressive strain to the lower semiconductor nanostructure 66L, such as silicon-germanium, boron-doped silicon-germanium, boron-doped silicon, germanium, or germanium-tin. The lower epitaxial source / drain region 108L may have a surface protruding from the corresponding upper surface of the lower semiconductor nanostructure 66L, and may have a facet.

[0099] The lower epitaxial source / drain region 108L may be implanted with dopants to form a source / drain region, similar to the process used to form the lightly doped source / drain region and the subsequent annealing described above. The source / drain region may have a thickness between 10 19 atom / cm 3 Up to 10 21 atom / cm 3 The n-type and / or p-type impurities used in the source / drain regions may be any of the impurities described above. In some embodiments, the lower epitaxial source / drain region 108L is in-situ doped during growth.

[0100] Due to the epitaxial process of forming the lower epitaxial source / drain regions 108L, the upper surfaces of the lower epitaxial source / drain regions 108L have facets that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, adjacent lower epitaxial source / drain regions 108L remain separated after the epitaxial process is completed. In other embodiments, these facets may cause adjacent lower epitaxial source / drain regions 108L of the same nanostructure-FET to merge.

[0101] The first ILD 114 is formed over the lower epitaxial source / drain region 108L. The first ILD 114 may be formed of a dielectric material that may be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), or undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process may also be used.

[0102] The first CESL 112 may be formed between the first ILD 114 and the lower epitaxial source / drain region 108L. The first CESL 112 may be formed of a dielectric material having a high etch selectivity relative to the dielectric material of the first ILD 114, such as silicon nitride, silicon oxide, or silicon oxynitride, and the dielectric material may be formed by any suitable deposition process, such as CVD or ALD.

[0103] The first CESL 112 and / or the first ILD 114 are formed by depositing a material for forming the first CESL 112 and a material for the first ILD 114 and then performing an etch-back process. In some embodiments, the first ILD 114 is etched first without etching the first CESL 112 so that the first CESL 112 remains. Then, an anisotropic etching process is performed to remove a portion of the first CESL 112 that is higher than the first ILD 114. After the recess is generated, the sidewall of the upper semiconductor nanostructure 66U is exposed.

[0104] The upper epitaxial source / drain region 108U contacts the upper semiconductor nanostructure 66U but not the lower semiconductor nanostructure 66L. In some embodiments, the upper epitaxial source / drain region 108U applies stress in the corresponding channel region of the upper semiconductor nanostructure 66U, thereby improving performance. The upper epitaxial source / drain region 108U is formed in the source / drain groove 94 so that each stack of the upper semiconductor nanostructure 66U is disposed between corresponding adjacent pairs of upper epitaxial source / drain regions 108U. In some embodiments, the inner spacer 98 is used to separate the upper epitaxial source / drain region 108U from the first dummy nanostructure 64A, and the first dummy nanostructure 64A will be replaced by a gate structure in a subsequent process.

[0105] The upper epitaxial source / drain region 108U is epitaxially grown in the upper portion of the source / drain recess 94. For example, the upper epitaxial source / drain region 108U can be laterally grown from the exposed sidewalls of the upper semiconductor nanostructure 66U. The upper epitaxial source / drain region 108U has a conductivity type suitable for the device type of the upper nanostructure-FET. The conductivity type of the upper epitaxial source / drain region 108U can be opposite to the conductivity type of the lower epitaxial source / drain region 108L. In other words, the upper epitaxial source / drain region 108U can be doped opposite to the lower epitaxial source / drain region 108L. In some embodiments, the upper epitaxial source / drain region 108U is an n-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon, the upper epitaxial source / drain region 108U may include a material that applies tensile strain to the upper semiconductor nanostructure 66U, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, or silicon arsenide. In some embodiments, the upper epitaxial source / drain region 108U is a p-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon-germanium, the upper epitaxial source / drain region 108U may include a material that applies compressive strain to the upper semiconductor nanostructure 66U, such as silicon-germanium, boron-doped silicon-germanium, boron-doped silicon, germanium, or germanium-tin. The upper epitaxial source / drain region 108U may have a surface protruding from the corresponding upper surface of the upper semiconductor nanostructure 66U, and may have a facet.

[0106] The upper epitaxial source / drain region 108U may be implanted with dopants to form a source / drain region, similar to the process used to form the lightly doped source / drain region and the subsequent annealing described above. The source / drain region may have a thickness between 10 19 atom / cm 3 Up to 10 21 atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities described above. In some embodiments, the upper epitaxial source / drain regions 108U are in-situ doped during growth.

[0107] Due to the epitaxial process of forming the upper epitaxial source / drain regions 108U, the upper surfaces of the upper epitaxial source / drain regions 108U have facets that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, adjacent upper epitaxial source / drain regions 108U remain separated after the epitaxial process is completed. In other embodiments, these facets may cause adjacent upper epitaxial source / drain regions 108U of the same nanostructure-FET to merge.

[0108] The second ILD 124 is deposited over the upper epitaxial source / drain region 108U. The second ILD 124 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process may also be used.

[0109] The second CESL 122 may be formed between the second ILD 124 and the upper epitaxial source / drain region 108U. The second CESL 122 may be formed of a dielectric material having a high etching selectivity relative to the dielectric material of the second ILD 124, such as silicon nitride, silicon oxide, or silicon oxynitride, etc. The dielectric material may be formed by any suitable deposition process, such as CVD or ALD, etc.

[0110] The second CESL 122 and / or the second ILD 124 may be formed by depositing a material for forming the second CESL 122 and depositing a material for forming the second ILD 124. Then, a removal process is performed to make the top surface of the second CESL 122 flush with the top surface of the gate spacer 90 and the mask 86 (if present) or the dummy gate 84. In some embodiments, a planarization process may be used, such as a chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. The planarization process may also remove the mask 86 on the dummy gate 84 and the gate spacer 90 along a portion of the sidewall of the mask 86. After the planarization process, the second ILD 124, the gate spacer 90, and the mask (if present) or the dummy gate 84 are substantially coplanar (within process variations). Accordingly, the top surface of the mask 86 (if present) or the dummy gate 84 is exposed through the second ILD 124. In the embodiment shown, the mask 86 remains after the removal process. In other embodiments, the mask 86 is removed such that the top surface of the dummy gate 84 is exposed through the second ILD 124 .

[0111] exist Fig.10In one or more etching steps, the dummy gate 84 is removed so that a recess is formed between the gate spacers 90. Also, a portion of the dummy dielectric 82 in the recess is removed. In some embodiments, the dummy gate 84 and the dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, which selectively etches the material of the dummy gate 84 at a faster rate than etching the material of the second ILD 124, the isolation structure 100, the inner spacer 98, and the gate spacer 90. Each recess between the gate spacers 90 exposes and / or covers a portion of the nanostructures 64, 66, and the nanostructures 64, 66 serve as a channel region in the resulting device. The nanostructures 64, 66 that serve as a portion of the channel region are disposed between adjacent pairs of lower epitaxial source / drain regions 108L or between adjacent pairs of upper epitaxial source / drain regions 108U. During the removal, when etching the dummy gate 84, the dummy dielectric 82 may be used as an etch stop layer. Then, after removing the dummy gate 84 , the dummy dielectric 82 is removed.

[0112] Next, the remaining portion of the first dummy nanostructure 64A is removed to form an opening in the region between the semiconductor nanostructures 66. The remaining portion of the first dummy nanostructure 64A may be selectively etched at a faster rate than the material of the semiconductor nanostructure 66, the inner spacer 98, and the isolation structure 100. The etching may be isotropic. For example, when the first dummy nanostructure 64A is formed of silicon-germanium, the semiconductor nanostructure 66 is formed of silicon, the inner spacer 98 is formed of silicon oxycarbonitride, and the isolation structure 100 is formed of silicon oxycarbonitride, the etching process may be using tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH 4 In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portion of the semiconductor nanostructure 66 and to expand the openings between the semiconductor nanostructures 66.

[0113] Next, a gate dielectric 132 and a gate electrode 134 (including a lower gate electrode 134L and an upper gate electrode 134U) are formed to replace the gate. Each pair of gate dielectrics 132 and gate electrodes 134 (including an upper gate electrode 134U and / or a lower gate electrode 134L) may be collectively referred to as a "gate structure". Each gate structure extends along at least three sides (e.g., top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 66. The gate structure may also extend along the sidewalls and / or top surface of the semiconductor fin 62.

[0114] The gate dielectric 132 includes one or more layers of gate dielectric layers, and the gate dielectric 132 is disposed around the lower semiconductor nanostructure 66L, the upper semiconductor nanostructure 66U, and the isolation structure 100. Specifically, the gate dielectric 132 is disposed on the top surface of the fin 62; on the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 66; and on the sidewalls of the gate spacer 90. The gate dielectric 132 surrounds all (e.g., four) sides of the semiconductor nanostructure 66. The gate dielectric 132 may be formed of an oxide, such as silicon oxide or a metal oxide, a silicate (metal silicate), a combination thereof, or multiple layers thereof, etc. Additionally or alternatively, the gate dielectric 132 may be formed of a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as a metal oxide or silicate composed of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and a combination thereof. The dielectric material of the gate dielectric 132 may be formed by molecular-beam deposition (MBD), ALD, or PECVD. Although a single layer of the gate dielectric 132 is shown, the gate dielectric 132 may include any number of interfacial layers and any number of main layers. For example, the gate dielectric 132 may include an interfacial layer and a covering high-k dielectric layer.

[0115] The lower gate electrode 134L includes one or more gate electrode layers, and the lower gate electrode 134L is disposed above the gate dielectric 132 and around the lower semiconductor nanostructure 66L. The lower gate electrode 134L is disposed in the lower portion of the recess between the gate spacers 90 and in the opening between the lower semiconductor nanostructures 66L. The lower gate electrode 134L may be formed of a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multiple layers thereof. Although a single-layer gate electrode 134 is depicted, the lower gate electrode 134L may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials.

[0116] The lower gate electrode 134L is formed of a material suitable for the device type of the lower nanostructure-FET. For example, the lower gate electrode 134L may include a work function adjustment layer formed of one or more layers of a work function adjustment metal suitable for the device type of the lower nanostructure-FET. In some embodiments, the lower gate electrode 134L includes an n-type work function adjustment layer and may be formed of an n-type work function adjustment metal, such as titanium aluminum, titanium aluminum carbide, aluminum tantalum, tantalum carbide, or a combination thereof. In some embodiments, the lower gate electrode 134L includes a p-type work function adjustment layer and may be formed of a p-type work function adjustment metal such as titanium nitride, tantalum nitride, or a combination thereof. Additionally or optionally, the lower gate electrode 134L may include a dipole inducing element suitable for the device type of the lower nanostructure-FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0117] The upper gate electrode 134U includes one or more gate electrode layers, and the upper gate electrode 134U is disposed above the gate dielectric 132 and around the upper semiconductor nanostructure 66U. The upper gate electrode 134U is disposed in the upper portion of the recess between the gate spacers 90 and in the opening between the upper semiconductor nanostructures 66U. The upper gate electrode 134U may be formed of a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multiple layers thereof. Although a single-layer gate electrode 134 is depicted, the upper gate electrode 134U may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials.

[0118] The upper gate electrode 134U is formed of a material suitable for the device type of the upper nanostructure-FET. For example, the upper gate electrode 134U may include a work function adjustment layer formed of one or more layers of a work function adjustment metal suitable for the device type of the upper nanostructure-FET. In some embodiments, the upper gate electrode 134U includes an n-type work function adjustment layer and may be formed of an n-type work function adjustment metal, such as titanium aluminum, titanium aluminum carbide, aluminum tantalum, tantalum carbide, or a combination thereof. In some embodiments, the upper gate electrode 134U includes a p-type work function adjustment layer and may be formed of a p-type work function adjustment metal such as titanium nitride, tantalum nitride, or a combination thereof. The work function adjustment metal of the upper gate electrode 134U is different from the work function adjustment metal of the lower gate electrode 134L. Additionally or optionally, the upper gate electrode 134U may include a dipole inducing element suitable for the device type of the upper nanostructure-FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof. The dipole-inducing element of the upper gate electrode 134U may be different from the dipole-inducing element of the lower gate electrode 134L.

[0119] In some embodiments, an isolation layer (not shown separately) is formed between the lower gate electrode 134L and the upper gate electrode 134U. The isolation layer is configured to serve as an isolation component between the lower gate electrode 134L and the upper gate electrode 134U. The isolation layer can be formed of a dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, or a combination thereof, and may be formed by a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Other dielectric materials formed by any acceptable process may also be used. In an embodiment in which an isolation layer is formed, the isolation layer and the isolation structure 100 jointly isolate the upper gate electrode 134U from the lower gate electrode 134L. Therefore, the upper nanostructure-FET can be isolated from the lower nanostructure-FET by the combination of the isolation structure 100 and the isolation layer. In some embodiments in which the isolation layer is omitted, the upper nanostructure-FET can be coupled to the lower nanostructure-FET. When the isolation layer is omitted, the lower gate electrode 134L may be physically and electrically coupled to the upper gate electrode 134U.

[0120] As one example of forming a gate structure, one or more layers of gate dielectric layers may be deposited in the grooves between the gate spacers 90 and the openings between the semiconductor nanostructures 66. The gate dielectric layer may also be deposited on the top surface of the second ILD 124 and the gate spacers 90. Then, one or more layers of lower gate electrode layers may be deposited on the gate dielectric layer, in the remaining portion of the grooves between the second ILD 124 and the gate spacers 90, and in the openings between the semiconductor nanostructures 66. Then, the lower gate electrode layer may be recessed. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, may be performed to recess the lower gate electrode layer. The etching may be isotropic, such as an etch-back process, where the etching removes the lower gate electrode layer from the upper portion of the grooves between the gate spacers 90, so that the lower gate electrode layer remains in the opening and is located between the lower semiconductor nanostructures 66L. In an embodiment of forming an isolation layer, the isolation material is conformally formed on the lower gate electrode layer and then recessed. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, may be performed to recess the isolation material. Then, one or more upper gate electrode layers may be deposited on the isolation material (if present) or the lower gate electrode layer, in the remaining portion of the recess between the gate spacers 90, and in the opening between the upper semiconductor nanostructures 66U. A removal process is performed to remove excess portions of the upper gate electrode layer, which are located above the top surface of the gate spacers 90 and the second ILD 124, so that the upper gate electrode layer remains in the opening between the upper semiconductor nanostructures 66U. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof, may be used. After the removal process, portions of the gate dielectric layer remain in the recesses between the gate spacers 90 and the openings between the semiconductor nanostructures 66 (thereby forming a gate dielectric layer 132). After the removal process, a portion of the lower gate electrode layer remains in the lower portion of the recesses between the gate spacers 90 and in the openings between the lower semiconductor nanostructures 66L (forming the lower gate electrode 134L). After the removal process, a portion of the upper gate electrode layer remains in the upper portion of the recesses between the gate spacers 90 and in the openings between the upper semiconductor nanostructures 66U (forming the upper gate electrode 134U). After the planarization process is used, the top surfaces of the gate spacers 90, the second ILD 124, the gate dielectric 132, and the upper gate electrode 134U are coplanar (within process variations).

[0121] exist Fig.11, source / drain contacts 144 are formed through the second ILD 124 to electrically couple to the upper epitaxial source / drain region 108U and / or the lower epitaxial source / drain region 108L. As one example of forming the source / drain contacts 144, openings for the source / drain contacts 144 are formed through the second ILD 124 and the second CESL 122. The openings may be formed using acceptable lithography and etching techniques. In the illustrated embodiment, the openings are formed by a self-aligned contact (SAC) process. A liner (not shown separately) (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, or tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, or nickel, etc. A removal process may be performed to remove the conductive material from the gate spacer 90, the second ILD 124 (see Fig.10 ) and the top surface of the upper gate electrode 134U are removed of excess material. The remaining liner and conductive material form source / drain contacts 144 in the opening. In some embodiments, a planarization process is used, such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. After the planarization process, the gate spacer 90, the second ILD 124 (see FIG. Fig.10 ), the top surfaces of the upper gate electrode 134U and the source / drain contacts 144 are substantially coplanar (within process variations).

[0122] Optionally, a metal-semiconductor alloy region 142 is formed at the interface between the source / drain region 108 and the source / drain contact 144. The metal-semiconductor alloy region 142 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanide region formed of both a metal silicide and a metal germanide. The metal-semiconductor alloy region 142 may be formed before the material of the source / drain contact 144 is formed by depositing a metal in the opening where the source / drain contact 144 is to be formed and then performing a thermal annealing process. The metal may be any metal that can react with the semiconductor material of the source / drain region 108 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, or PVD. After the thermal annealing process, a cleaning process such as a wet clean may be performed to remove any remaining metal from the openings where the source / drain contacts 144 are to be formed (e.g., from the surface of the metal-semiconductor alloy region 142). Then, the source / drain contacts 144 may be formed on the metal-semiconductor alloy region 142.

[0123] exist FIG. 12A to FIG. 12B In the embodiment, the third ILD 154 is deposited over the gate spacer 90, the second ILD 124, the upper gate electrode 134U, and the source / drain contacts 144. In some embodiments, the third ILD 154 is formed by a flowable film by a flowable CVD method, and then the flowable film is cured. In some embodiments, the third ILD 154 is formed of a dielectric material such as PSG, BSG, BPSG, or USG, and the third ILD 154 can be deposited by any suitable method such as CVD or PECVD.

[0124] In some embodiments, an etch stop layer (ESL) 152 is formed between the third ILD 154 and the gate spacer 90, the second ILD 124, the upper gate electrode 134U, and the source / drain contacts 144. The ESL 152 may include a dielectric material having a high etching selectivity relative to the dielectric material of the third ILD 154, such as silicon nitride, silicon oxide, or silicon oxynitride.

[0125] The gate contact 156 and the source / drain via 158 are formed through the third ILD 154 to electrically couple to the upper gate electrode 134U and the source / drain contact 144, respectively. As an example of forming the gate contact 156 and the source / drain via 158, the third ILD 154 and the ESL 152 are passed through to form an opening that will become the gate contact 156 and the source / drain via 158. Acceptable lithography and etching techniques can be used to form the opening. A liner (not shown separately) (such as a diffusion barrier layer or an adhesion layer, etc.) and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, or tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, or nickel, etc. A planarization process such as CMP can be performed to remove excess material from the top surface of the third ILD 154. The remaining liner and conductive material form a gate contact 156 and a source / drain via 158 in the opening. The gate contact 156 and the source / drain via 158 can be formed in different processes, or can be formed in the same process. Although the gate contact 156 and the source / drain via 158 are illustrated as being formed in the same cross-section, it should be understood that each gate contact 156 and each source / drain via 158 can be formed in a different cross-section, so that shorting of the contacts can be avoided.

[0126] The active devices shown are collectively referred to as the device layer. In some embodiments, contacts to the lower gate electrode 134L and the lower epitaxial source / drain regions 108L may be formed through the back side of the device layer (eg, the side opposite the source / drain contacts 144).

[0127] The embodiments of the present disclosure can achieve the following advantages. The isolation structure 100 helps to isolate the upper gate electrode 134U from the lower gate electrode 134L. The isolation structure 100 is formed by growing the second dummy nanostructure 64B, and then the isolation structure 100 is at least partially replaced by the isolation structure 100 to form the isolation structure 100, so as to achieve isolation between semiconductor nanostructures. The formation of the second dummy nanostructure 64B doped with silicon can advantageously reduce the risk of defects in the multilayer stack 52 during epitaxial growth.

[0128] In one embodiment, a method of forming a stacked transistor includes: patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure, wherein the dummy nanostructure is disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure, and the dummy nanostructure includes doped silicon; forming an opening between the lower semiconductor nanostructure and the upper semiconductor nanostructure by etching the silicon-doped dummy nanostructure; forming an isolation structure in the opening; and depositing a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure. In some embodiments, the method further includes: forming a lower gate electrode on the gate dielectric and around the lower semiconductor nanostructure; and forming an upper gate electrode on the gate dielectric and around the upper semiconductor nanostructure. In some embodiments of the method, the lower gate electrode includes a p-type work function adjustment layer, and the upper gate electrode includes an n-type work function adjustment layer. In some embodiments, the method further includes: forming a lower inner spacer and an upper inner spacer, wherein the lower inner spacer is adjacent to the lower semiconductor nanostructure and the upper inner spacer is adjacent to the upper semiconductor nanostructure; growing a lower source / drain region adjacent to the lower inner spacer; and growing an upper source / drain region adjacent to the upper inner spacer. In some embodiments of the method, the conductivity type of the upper source / drain region is opposite to the conductivity type of the lower source / drain region. In some embodiments of the method, the lower inner spacer, the upper inner spacer, and the isolation structure are formed of the same dielectric material. In some embodiments of the method, the doped silicon of the virtual nanostructure is etched by dry etching using chlorine gas. In some embodiments of the method, the virtual nanostructure has a first thickness, the lower semiconductor nanostructure and the upper semiconductor nanostructure have a second thickness, respectively, and the first thickness is greater than the second thickness. In some embodiments of the method, the virtual nanostructure has a first thickness, the lower semiconductor nanostructure and the upper semiconductor nanostructure have a second thickness, respectively, and the first thickness is less than the second thickness.

[0129] In one embodiment, a method of forming a stacked transistor includes: patterning a first virtual nanostructure, a second virtual nanostructure, and a semiconductor nanostructure, wherein the first virtual nanostructure includes a first semiconductor material, the second virtual nanostructure includes a second semiconductor material, the semiconductor nanostructure includes a third semiconductor material, and the third semiconductor material has a lower dopant concentration than the second semiconductor material; recessing the sidewall of the first virtual nanostructure to form a sidewall recess; removing the second virtual nanostructure to form an opening, wherein the sidewall of the first virtual nanostructure is recessed and the second virtual nanostructure is removed by using the same etching process, the same etching process selectively etches the second semiconductor material at a faster rate than etching the first semiconductor material, and the same etching process selectively etches the first semiconductor material at a faster rate than etching the third semiconductor material; and, forming an inner spacer and an isolation structure in the sidewall recess and the opening, respectively. In some embodiments of the method, the first semiconductor material is silicon-germanium, the second semiconductor material is doped silicon, and the third semiconductor material is doped silicon. In some embodiments of the method, the same etching process includes dry etching using chlorine gas. In some embodiments of the method, the second semiconductor material is doped with an n-type dopant. In some embodiments of the method, the second semiconductor material is doped with a p-type dopant. In some embodiments of the method, the thickness of the second virtual nanostructure is greater than the thickness of the first virtual nanostructure. In some embodiments of the method, the thickness of the second virtual nanostructure is less than the thickness of the first virtual nanostructure.

[0130] In one embodiment, a method for forming a stacked transistor includes: patterning a first semiconductor nanostructure, a second semiconductor nanostructure, and a dummy nanostructure, wherein the dummy nanostructure is disposed between the first semiconductor nanostructure and the second semiconductor nanostructure, the dummy nanostructure includes silicon doped to a first dopant concentration, the first semiconductor nanostructure and the second semiconductor nanostructure each include silicon doped to a second dopant concentration, and the first dopant concentration is greater than the second dopant concentration; etching the dummy nanostructure by an etching process to form an opening, and the etching process selectively etches the silicon doped to the first dopant concentration at a faster rate than etching the silicon doped to the second dopant concentration; and forming an isolation structure in the opening. In some embodiments, the method further includes: growing a first source / drain region adjacent to the first semiconductor nanostructure; depositing an interlayer dielectric on the first source / drain region; and growing a second source / drain region on the interlayer dielectric and adjacent to the second semiconductor nanostructure. In some embodiments, the method further includes: forming a first gate electrode around the first semiconductor nanostructure; and forming a second gate electrode around the second semiconductor nanostructure. In some embodiments of the method, the etching process includes dry etching using chlorine gas.

[0131] In some embodiments, a stacked transistor includes a lower semiconductor nanostructure, an isolation structure, an upper semiconductor nanostructure, and a gate dielectric. The lower semiconductor nanostructure is located above a substrate. The isolation structure is located on the lower semiconductor nanostructure. The upper semiconductor nanostructure is located on the isolation structure. The gate dielectric surrounds the isolation structure, the lower semiconductor nanostructure, and the upper semiconductor nanostructure, respectively. In some embodiments, the stacked transistor further includes a lower gate electrode located on the gate dielectric and surrounding the lower semiconductor nanostructure and an upper gate electrode located on the lower gate electrode and surrounding the upper semiconductor nanostructure. In some embodiments, the stacked transistor further includes a lower inner spacer adjacent to the lower semiconductor nanostructure and an upper inner spacer adjacent to the upper semiconductor nanostructure. In some embodiments, the stacked transistor further includes a lower source / drain region adjacent to the lower semiconductor nanostructure and an upper source / drain region adjacent to the upper semiconductor nanostructure. In some embodiments, an interlayer dielectric layer is included between the lower source / drain region and the upper source / drain region. In some embodiments, the thickness of the isolation structure is less than the thickness of the lower semiconductor nanostructure.

[0132] In some embodiments, a stacked electrocrystalline includes a lower semiconductor nanostructure, a middle semiconductor nanostructure, and an upper semiconductor nanostructure. The lower semiconductor nanostructure is located above a substrate and includes a plurality of lower gate structure layers located above the substrate and a plurality of lower nanostructure layers alternately arranged with the lower gate structure layers and located above the substrate. The middle semiconductor nanostructure is located on the lower semiconductor nanostructure and includes an isolation structure. The upper semiconductor nanostructure is located on the middle semiconductor nanostructure and includes a plurality of upper gate structure layers located on the middle semiconductor nanostructure and a plurality of upper nanostructure layers alternately arranged with the upper gate structure layers and located above the middle semiconductor nanostructure. In some embodiments, the thickness of the upper gate structure layer is different from the thickness of the lower gate structure layer.

[0133] In some embodiments, a stacked transistor includes a first semiconductor nanostructure located above a substrate, a first gate electrode located around the first semiconductor nanostructure, an isolation structure located on the first gate electrode, a second semiconductor nanostructure located on the isolation structure, and a second gate electrode located around the second semiconductor nanostructure. In some embodiments, the stacked transistor further includes a first source / drain region adjacent to the first semiconductor nanostructure, an interlayer dielectric located on the first source / drain region, and a second source / drain region adjacent to the second semiconductor nanostructure and located on the interlayer dielectric.

[0134] The present disclosure summarizes various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A stacked transistor, characterized in that: include: a lower semiconductor nanostructure disposed above a substrate; an isolation structure disposed on the lower semiconductor nanostructure; an upper semiconductor nanostructure located on the isolation structure; and A gate dielectric surrounds the isolation structure, the lower semiconductor nanostructure and the upper semiconductor nanostructure respectively.

2. The stacked transistor according to claim 1, wherein: Further including: a lower gate electrode disposed on the gate dielectric and surrounding the lower semiconductor nanostructure; as well as An upper gate electrode is located on the lower gate electrode and surrounds the upper semiconductor nanostructure.

3. The stacked transistor according to claim 1, wherein: Further including: a lower inner spacer adjacent to the lower semiconductor nanostructure; as well as An upper inner spacer is adjacent to the upper semiconductor nanostructure.

4. The stacked transistor according to claim 3, wherein: Further including: a lower source / drain region adjacent to the lower semiconductor nanostructure; as well as An upper source / drain region is adjacent to the upper semiconductor nanostructure.

5. The stacked transistor according to claim 4, wherein: An interlayer dielectric layer is included between the lower source / drain region and the upper source / drain region.

6. The stacked transistor according to claim 1, wherein: The thickness of the isolation structure is smaller than the thickness of the lower semiconductor nanostructure.

7. A stacked transistor, characterized in that: include: A lower semiconductor nanostructure is disposed above a substrate and includes: A plurality of lower gate structure layers are located above the substrate; and A plurality of lower nanostructure layers, arranged alternately with the plurality of lower gate structure layers and located above the substrate; a middle semiconductor nanostructure located on the lower semiconductor nanostructure, wherein the middle semiconductor nanostructure includes an isolation structure; and An upper semiconductor nanostructure, located on the middle semiconductor nanostructure, and comprising: A plurality of upper gate structure layers are located on the middle semiconductor nanostructure; and A plurality of upper nanostructure layers are alternately arranged with the plurality of upper gate structure layers and are located above the middle semiconductor nanostructure.

8. The stacked transistor according to claim 7, wherein: The thickness of each upper gate structure layer is different from the thickness of each lower gate structure layer.

9. A stacked transistor, characterized in that: include: a first semiconductor nanostructure located above a substrate; a first gate electrode, located around the first semiconductor nanostructure; an isolation structure located on the first gate electrode; a second semiconductor nanostructure located on the isolation structure; and A second gate electrode is located around the second semiconductor nanostructure.

10. The stacked transistor according to claim 9, wherein: Further including: a first source / drain region adjacent to the first semiconductor nanostructure; an interlayer dielectric disposed on the first source / drain region; as well as A second source / drain region is adjacent to the second semiconductor nanostructure and is located on the interlayer dielectric.

Images