Display device

Abstract

A display device includes: a substrate including a first light-emitting area, a second light-emitting area and a third light-emitting area and a light-blocking area located between the first light-emitting area, the second light-emitting area and the third light-emitting area; a first light-emitting layer, which is arranged in the first light-emitting area on the substrate and emits light of a first color; a second light-emitting layer, which is arranged in the second light-emitting area on the substrate, includes an upper surface having a curved shape in a cross section, and emits light of a second color different from the first color; a third light-emitting layer, which is arranged in the third light-emitting area on the substrate and emits light of a third color different from the first color and the second color; and a reflection control layer, which is arranged on the first light-emitting layer, the second light-emitting layer and the third light-emitting layer.

Description

Technical Field

[0001] Embodiments generally provide display devices. More specifically, embodiments relate to display devices that provide visual information. Background Art

[0002] As information technology develops, the importance of display devices as a communication medium between users and information becomes increasingly prominent. Therefore, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices is increasing.

[0003] Meanwhile, since the display device includes wires and electrodes including metal, external light incident on the display device may be reflected from the wires and electrodes. In order to prevent the reflection of external light, the display device generally includes a polarizer. However, the polarizer may prevent the reflection of external light, but the light efficiency of the display device may be reduced due to the polarizer. Utility Model Content

[0004] The embodiment provides a display device with improved display quality.

[0005] According to an embodiment of the present disclosure, a display device includes: a substrate, the substrate including a first light-emitting area, a second light-emitting area and a third light-emitting area and a light-blocking area located between the first light-emitting area, the second light-emitting area and the third light-emitting area; a first light-emitting layer, which is arranged in the first light-emitting area on the substrate and emits light of a first color; a second light-emitting layer, which is arranged in the second light-emitting area on the substrate, includes an upper surface having a curved shape in a cross-section, and the second light-emitting layer emits light of a second color different from the first color; a third light-emitting layer, which is arranged in the third light-emitting area on the substrate, and the third light-emitting layer emits light of a third color different from the first color and the second color; and a reflection control layer, which is arranged on the first light-emitting layer, the second light-emitting layer and the third light-emitting layer.

[0006] In an embodiment, an edge of the upper surface of the second light emitting layer may be inclined with respect to a main upper surface of the substrate.

[0007] In an embodiment, the upper surface of the second light emitting layer may have a concave shape or a convex shape in a cross section.

[0008] In an embodiment, each of the first light emitting layer and the third light emitting layer may have a substantially flat upper surface.

[0009] In an embodiment, the display device may further include: a first pixel electrode disposed between the substrate and the first light-emitting layer in the first light-emitting region; a second pixel electrode disposed between the substrate and the second light-emitting layer in the second light-emitting region; and a third pixel electrode disposed between the substrate and the third light-emitting layer in the third light-emitting region. The second pixel electrode may have an upper surface having a curved shape in the cross section.

[0010] In an embodiment, the display device may further include a via insulating layer disposed between the substrate and the first pixel electrode, the second pixel electrode, and the third pixel electrode. In the second light emitting region, the via insulating layer may include a protruding portion protruding toward the second pixel electrode at an upper surface of the via insulating layer.

[0011] In an embodiment, the display device may further include a via insulating layer disposed between the substrate and the first pixel electrode, the second pixel electrode and the third pixel electrode. In the second light emitting region, the via insulating layer may include a recessed portion recessed toward the substrate at an upper surface of the via insulating layer.

[0012] In an embodiment, the display device may further include: a first transistor electrically connected to the first pixel electrode and including a first active pattern, a first gate electrode, a first source electrode, and a first drain electrode; a second transistor electrically connected to the second pixel electrode and including a second active pattern, a second gate electrode, a second source electrode, and a second drain electrode; and a third transistor electrically connected to the third pixel electrode and including a third active pattern, a third gate electrode, a third source electrode, and a third drain electrode.

[0013] In an embodiment, when the second source electrode and the second drain electrode at least partially overlap with the second light-emitting layer in a plan view, the thickness of each of the second source electrode and the second drain electrode may be different from the thickness of each of the first source electrode, the first drain electrode, the third source electrode, and the third drain electrode.

[0014] In an embodiment, when the second gate electrode at least partially overlaps the second light emitting layer in a plan view, the thickness of the second gate electrode may be different from the thickness of each of the first gate electrode and the third gate electrode.

[0015] In an embodiment, when the second active pattern at least partially overlaps the second light emitting layer in a plan view, a thickness of the second active pattern may be different from a thickness of each of the first active pattern and the third active pattern.

[0016] In an embodiment, the first color may be red, the second color may be green, and the third color may be blue.

[0017] In an embodiment, the reflection control layer may include an inorganic material or an organic material containing at least one selected from the group consisting of a dye and a pigment.

[0018] In an embodiment, the display device may further include an anti-reflection inorganic layer disposed on the first light emitting layer, the second light emitting layer, and the third light emitting layer and including an inorganic material.

[0019] In an embodiment, the display device may further include an encapsulation layer, which is arranged on the first light-emitting layer, the second light-emitting layer and the third light-emitting layer and includes: a first inorganic encapsulation layer, including a first sublayer, a second sublayer, a third sublayer and a fourth sublayer arranged in sequence; an organic encapsulation layer, which is arranged on the first inorganic encapsulation layer; and a second inorganic encapsulation layer, which is arranged on the organic encapsulation layer.

[0020] In an embodiment, the first sublayer may include silicon nitride, each of the second sublayer, the third sublayer, and the fourth sublayer may include silicon oxynitride, and the second inorganic encapsulating layer may include silicon oxynitride.

[0021] In an embodiment, the display device may further include a light blocking layer disposed in the light blocking area on the substrate and covered by the reflection control layer.

[0022] According to an embodiment of the present disclosure, a display device includes: a substrate, including a first light-emitting area, a second light-emitting area and a third light-emitting area and a light-blocking area located between the first light-emitting area, the second light-emitting area and the third light-emitting area; a first light-emitting layer, which is arranged in the first light-emitting area on the substrate, includes a substantially flat upper surface and emits red light; a second light-emitting layer, which is arranged in the second light-emitting area on the substrate, includes an upper surface having a curved shape in a cross section and emits green light; a third light-emitting layer, which is arranged in the third light-emitting area on the substrate, includes a substantially flat upper surface and emits blue light; an encapsulation layer, which is arranged on the first light-emitting layer, the second light-emitting layer and the third light-emitting layer; a touch sensing layer, which is arranged on the encapsulation layer and includes a first touch electrode and a second touch electrode connected to the first touch electrode; and a reflection control layer, which is arranged on the touch sensing layer.

[0023] In an embodiment, an edge of the upper surface of the second light emitting layer may be inclined with respect to a main upper surface of the substrate.

[0024] In an embodiment, the upper surface of the second light emitting layer may have a concave shape or a convex shape in the cross section.

[0025] In the display device according to the embodiment, the upper surface of the second light-emitting layer emitting green light may have a curved shape in cross section, and the upper surface of each of the first light-emitting layer emitting red light and the third light-emitting layer emitting blue light may be substantially flat. Therefore, the amount of light emitted at a low angle from the second light-emitting layer can be increased, and the color of the image displayed in the display area can be prevented from being reddish. In this case, the display quality of the display device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is along Figure 1 FIG. 1 is a cross-sectional view of a display device according to an embodiment of the present disclosure, taken along line II′.

[0029] Figure 3 It is used to illustrate Figure 2 Cross-sectional view of the encapsulation layer.

[0030] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 It is used to illustrate the use of manufacturing Figure 2 A cross-sectional view of a method for displaying a device.

[0031] Fig.10 is a cross-sectional view showing a display device according to another embodiment of the present disclosure.

[0032] Fig.11 is a cross-sectional view showing a display device according to still another embodiment of the present disclosure.

[0033] Fig.12 is a cross-sectional view showing a display device according to still another embodiment of the present disclosure.

[0034] Fig.13 is a cross-sectional view showing a display device according to still another embodiment of the present disclosure.

[0035] Fig.14 is a cross-sectional view showing a display device according to still another embodiment of the present disclosure.

[0036] Fig.15 is a cross-sectional view showing a display device according to still another embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] It will be understood that when an element is referred to as being "on" another element, the element can be directly on the other element or intervening elements may exist between them. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements between them.

[0038] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, areas, layers and / or parts, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Thus, without departing from the teachings herein, the "first element", "first component", "first area", "first layer" or "first part" discussed below may be named "second element", "second component", "second area", "second layer" or "second part".

[0039] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be restrictive. Unless the context clearly indicates otherwise, as used herein, the singular forms "one", "one (kind / person)", "the (said)" and "at least one (kind / person)" do not represent a limitation on quantity, and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". "At least one (kind / person)" is not interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It will be further understood that when used in this specification, the term "comprises and / or comprising" or "includes and / or including" specifies the presence of stated features, regions, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or their groups.

[0040] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially flat" may mean within one or more standard deviations or within ±20%, ±10%, or ±5% of the preferred flatness.

[0041] Hereinafter, a display device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0042] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure. As used herein, a "plan view" is a view in a thickness direction of a substrate.

[0043] refer to Figure 1 , the display device 100 according to the embodiment may include a display area DA and a non-display area NDA. The display area DA may be an area capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The non-display area NDA may be an area where an image is not displayed. The non-display area NDA may be located around the display area DA. In an embodiment, for example, the non-display area NDA may surround the entire display area DA.

[0044] The display area DA may include a plurality of light emitting areas and a light blocking area BA. Each of the light emitting areas may refer to an area where light emitted from a light emitting element is emitted to the outside of the display device 100. When the light emitting area emits light, the display area DA may display an image. For example, the light emitting areas may be arranged in a matrix form along a first direction DR1 and a second direction DR2 crossing the first direction DR1.

[0045] The light emitting area may include a first light emitting area EA1, a second light emitting area EA2, and a third light emitting area EA3. In an embodiment, for example, the first light emitting area EA1 may emit a first light, the second light emitting area EA2 may emit a second light, and the third light emitting area EA3 may emit a third light. In an embodiment, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, for example, the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be combined to emit yellow light, cyan light, and magenta light.

[0046] The first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may emit four or more colors of light. For example, the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be combined to further emit at least one of yellow light, cyan light, and magenta light in addition to red light, green light, and blue light. In addition, the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be combined to further emit white light.

[0047] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a triangular plane shape, a quadrilateral plane shape, a circular plane shape, an elliptical plane shape, etc. In an embodiment, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a rectangular plane shape. However, the embodiments of the present disclosure are not limited thereto, and in another embodiment, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a different plane shape.

[0048] The light blocking area BA may be located between the first, second and third light emitting areas EA1, EA2 and EA3. For example, in a plan view, the light blocking area BA may surround the first, second and third light emitting areas EA1, EA2 and EA3. The light blocking area BA may not emit light.

[0049] The non-display area NDA may include a pad area PDA. The pad area PDA may be spaced apart from one side of the display area DA. In an embodiment, for example, the pad area PDA may have a shape extending in the first direction DR1.

[0050] A plurality of lines may be provided in the non-display area NDA, and a plurality of pad electrodes PDE may be provided in the pad area PDA. These lines may electrically connect the pad electrodes PDE to the light emitting area. For example, these lines may include data signal lines, scan signal lines, light emitting control signal lines, or power supply voltage lines, etc.

[0051] The pad electrodes PDE may be disposed to be spaced apart from each other in the first direction DR1. In an embodiment, for example, each of the pad electrodes PDE may include metal, alloy, metal nitride, conductive metal oxide, or transparent conductive material, etc. These may be used alone or in combination with each other.

[0052] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. For example, the first direction DR1 may be perpendicular to the second direction DR2.

[0053] Figure 2 It is along Figure 1 FIG. 1 is a cross-sectional view of a display device according to an embodiment of the present disclosure, taken along line II′. Figure 3 It is used to illustrate Figure 2 Cross-sectional view of the encapsulation layer.

[0054] refer to Figure 2 and Figure 3 According to an embodiment of the present disclosure, the display device 100 may include a substrate SUB1, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1, a second transistor TR2, and a third transistor TR3, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a first light emitting element LED1, a second light emitting element LED2, and a third light emitting element LED3, a capping layer CL, a first low-reflective inorganic layer LAL1, a second low-reflective inorganic layer LAL2, and a third low-reflective inorganic layer LAL3, an encapsulation layer ENC, a touch sensing layer TCL, a light blocking layer BL, and a reflection control layer RCL.

[0055] Here, the first transistor TR1 may include a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1, the second transistor TR2 may include a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2, and the third transistor TR3 may include a third active pattern ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0056] In addition, the first light-emitting element LED1 may include a first pixel electrode PE1, a first light-emitting layer EML1 and a first common electrode CE1, the second light-emitting element LED2 may include a second pixel electrode PE2, a second light-emitting layer EML2 and a second common electrode CE2, and the third light-emitting element LED3 may include a third pixel electrode PE3, a third light-emitting layer EML3 and a third common electrode CE3.

[0057] As described above, the display device 100 may include the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, and the light blocking area BA. Since the display device 100 includes the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, and the light blocking area BA, a component included in the display device 100 (e.g., the substrate SUB1) may also include the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, and the light blocking area BA.

[0058] The substrate SUB1 may include a transparent material or an opaque material. The substrate SUB1 may be made of a transparent resin substrate. Examples of transparent resin substrates may include polyimide substrates, etc. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, and a second organic layer. Alternatively, the substrate SUB1 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine (F) doped quartz substrate, a soda-lime (or soda-lime) glass substrate, or a non-alkali glass substrate, etc. These may be used alone or in combination with each other.

[0059] The buffer layer BUF may be disposed on the substrate SUB1. The buffer layer BUF may prevent metal atoms or impurities from diffusing from the substrate SUB1 into the first transistor TR1, the second transistor TR2, and the third transistor TR3. In addition, when the surface of the substrate SUB1 is uneven, the buffer layer BUF may improve the flatness of the surface of the substrate SUB1. In an embodiment, for example, the buffer layer BUF may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. These may be used alone or in combination with each other.

[0060] First, second, and third active patterns ACT1, ACT2, and ACT3 may be disposed on the buffer layer BUF. Each of the first, second, and third active patterns ACT1, ACT2, and ACT3 may include a metal oxide semiconductor, an inorganic semiconductor (eg, amorphous silicon, polysilicon), or an organic semiconductor.

[0061] Each of the first, second, and third active patterns ACT1, ACT2, and ACT3 may include a source region, a drain region, and a channel region therebetween. The first, second, and third active patterns ACT1, ACT2, and ACT3 may be formed by the same process and include the same material.

[0062] Metal oxide semiconductors may include binary compounds (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), or magnesium (Mg). x ), ternary compounds (AB x C y ) or quaternary compounds (AB x C y D z ) etc. In an embodiment, for example, the metal oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x), indium gallium oxide ("IGO"), indium zinc oxide ("IZO"), indium tin oxide ("ITO"), indium zinc tin oxide ("IZTO"), or indium gallium zinc oxide ("IGZO"), etc. These may be used alone or in combination with one another.

[0063] The gate insulating layer GI may be disposed on the buffer layer BUF. The gate insulating layer GI may fully cover the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3, and may have a substantially flat upper surface without generating steps around the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3. Alternatively, the gate insulating layer GI may cover the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3, and may be disposed along the contour of each of the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 to have a uniform thickness. In an embodiment, for example, the gate insulating layer GI may include a material such as silicon oxide (SiO x ), Silicon Nitride (SiN x ), Silicon Carbide (SiC x ), silicon oxynitride (SiO x N y ) or silicon oxycarbide (SiO x C y ) etc. These may be used alone or in combination with each other.

[0064] The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be disposed on the gate insulating layer GI. The first gate electrode GE1 may overlap the channel region of the first active pattern ACT1, the second gate electrode GE2 may overlap the channel region of the second active pattern ACT2, and the third gate electrode GE3 may overlap the channel region of the third active pattern ACT3.

[0065] Each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. Examples of the metal may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). Examples of the conductive metal oxide may include indium tin oxide or indium zinc oxide. In addition, examples of the metal nitride may include aluminum nitride (AlN x ), tungsten nitride (WN x ) or chromium nitride (CrN x ) etc. These may be used alone or in combination with each other.

[0066] The first gate electrode GE1 , the second gate electrode GE2 , and the third gate electrode GE3 may be formed by the same process and include the same material.

[0067] The interlayer insulating layer ILD may be disposed on the gate insulating layer GI. The interlayer insulating layer ILD may fully cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 and may have a substantially flat upper surface without generating steps around the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. Optionally, the interlayer insulating layer ILD may cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 and may be disposed along the contour of each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 to have a uniform thickness. In an embodiment, for example, the interlayer insulating layer ILD may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide. These may be used alone or in combination with each other.

[0068] The first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 may be disposed on the interlayer insulating layer ILD. The first source electrode SE1 may be connected to the source region of the first active pattern ACT1 through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD. The second source electrode SE2 may be connected to the source region of the second active pattern ACT2 through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD. The third source electrode SE3 may be connected to the source region of the third active pattern ACT3 through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD.

[0069] The first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 may be disposed on the interlayer insulating layer ILD. The first drain electrode DE1 may be connected to the drain region of the first active pattern ACT1 through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD. The second drain electrode DE2 may be connected to the drain region of the second active pattern ACT2 through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD. The third drain electrode DE3 may be connected to the drain region of the third active pattern ACT3 through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD.

[0070] In an embodiment, for example, each of the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. These may be used alone or in combination with each other. The first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 may be formed by the same process as the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 and may include the same material.

[0071] Therefore, a first transistor TR1 including a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1 may be disposed on a substrate SUB1. A second transistor TR2 including a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2 may be disposed on the substrate SUB1. A third transistor TR3 including a third active pattern ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3 may be disposed on the substrate SUB1.

[0072] The via insulating layer VIA may be disposed on the interlayer insulating layer ILD. The via insulating layer VIA may fully cover the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 and the first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3. The via insulating layer VIA may include an organic material. In an embodiment, for example, the via insulating layer VIA may include a phenolic resin, a polyacrylate resin, a polyimide resin, a polyamide resin, a siloxane resin, or an epoxy resin, etc. These may be used alone or in combination with each other.

[0073] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be disposed on the via insulating layer VIA. The first pixel electrode PE1 may overlap the first light emitting region EA1, the second pixel electrode PE2 may overlap the second light emitting region EA2, and the third pixel electrode PE3 may overlap the third light emitting region EA3. The first pixel electrode PE1 may be connected to the first drain electrode DE1 through a contact hole penetrating the via insulating layer VIA, the second pixel electrode PE2 may be connected to the second drain electrode DE2 through a contact hole penetrating the via insulating layer VIA, and the third pixel electrode PE3 may be connected to the third drain electrode DE3 through a contact hole penetrating the via insulating layer VIA.

[0074] In an embodiment, for example, each of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide or a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, each of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a stacked structure including ITO / Ag / ITO. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may be formed by the same process and include the same material. For example, each of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may be used as an anode.

[0075] The pixel defining layer PDL may be disposed on the via insulating layer VIA. The pixel defining layer PDL may overlap the light blocking area BA. The pixel defining layer PDL may cover an edge of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. In addition, a pixel opening exposing at least a portion of an upper surface of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be defined in the pixel defining layer PDL.

[0076] In an embodiment, for example, the pixel defining layer PDL may include an inorganic material and / or an organic material. In an embodiment, the pixel defining layer PDL may include an organic material such as an epoxy resin or a silicone resin. These may be used alone or in combination with each other. In another embodiment, the pixel defining layer PDL may include an inorganic material and / or an organic material containing a black light blocking material.

[0077] In an embodiment, in the second light emitting area EA2 , the pixel defining layer PDL may include a protruding portion contacting the second pixel electrode PE2 and protruding toward the center of the pixel opening.

[0078] The first light emitting layer EML1 may be disposed on the first pixel electrode PE1, the second light emitting layer EML2 may be disposed on the second pixel electrode PE2, and the third light emitting layer EML3 may be disposed on the third pixel electrode PE3. In an embodiment, for example, each of the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may include an organic light emitting material that emits light of a predetermined color.

[0079] The first light emitting layer EML1 may include an organic light emitting material that emits light L1 of a first color, the second light emitting layer EML2 may include an organic light emitting material that emits light L2 of a second color, and the third light emitting layer EML3 may include an organic light emitting material that emits light L3 of a third color. In an embodiment, for example, the first color may be red, the second color may be green, and the third color may be blue. However, embodiments of the present disclosure are not limited thereto.

[0080] In an embodiment, the second light emitting layer EML2 may include an upper surface US_E having a curved shape in a cross section. Specifically, an edge of the upper surface US_E of the second light emitting layer EML2 may be inclined relative to the main upper surface of the substrate SUB1. That is, the angle between the tangent at the edge of the upper surface US_E and the main upper surface of the substrate SUB1 is greater than 0 degrees (°) and less than 90°. In this case, each of the first light emitting layer EML1 and the third light emitting layer EML3 may have a substantially flat upper surface in a cross section.

[0081] Since the second light emitting layer EML2 includes the upper surface US_E having a curved shape in a cross section, the amount of light emitted from the second light emitting layer EML2 at a low angle (e.g., about +30 degrees and / or about -30 degrees relative to the upper surface of the substrate SUB1) can be increased. Therefore, the side brightness ratio of the second light emitting area EA2 can be increased. In this case, the light displayed in the display area DA (see FIG. 1 ) from a low angle is prevented from being Figure 1 Here, low angle means viewing angle.

[0082] In an embodiment, for example, the upper surface US_E of the second light emitting layer EML2 may have a concave curved shape in a cross section. Alternatively, the upper surface US_E of the second light emitting layer EML2 may have a convex curved shape in a cross section. However, the embodiments of the present disclosure are not limited thereto. Alternatively, the upper surface US_E of the second light emitting layer EML2 may include a flat portion located at the center and substantially flat, and an inclined portion located at the edge and extending from the flat portion to have a predetermined slope.

[0083] The first common electrode CE1 may be disposed on the first light emitting layer EML1 and the pixel defining layer PDL, the second common electrode CE2 may be disposed on the second light emitting layer EML2 and the pixel defining layer PDL, and the third common electrode CE3 may be disposed on the third light emitting layer EML3 and the pixel defining layer PDL. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be formed integrally. In an embodiment, for example, each of the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. These may be used alone or in combination with each other. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be used as a cathode.

[0084] Therefore, the first light emitting element LED1 including the first pixel electrode PE1, the first light emitting layer EML1 and the first common electrode CE1 may be disposed in the first light emitting area EA1 on the substrate SUB1. The second light emitting element LED2 including the second pixel electrode PE2, the second light emitting layer EML2 and the second common electrode CE2 may be disposed in the second light emitting area EA2 on the substrate SUB1. The third light emitting element LED3 including the third pixel electrode PE3, the third light emitting layer EML3 and the third common electrode CE3 may be disposed in the third light emitting area EA3 on the substrate SUB1.

[0085] The first light emitting element LED1 may be electrically connected to the first transistor TR1 , the second light emitting element LED2 may be electrically connected to the second transistor TR2 , and the third light emitting element LED3 may be electrically connected to the third transistor TR3 .

[0086] The capping layer CL may be disposed on the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3. The capping layer CL may be disposed on the entirety of the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3. The capping layer CL may be used to protect the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3. In an embodiment, for example, the capping layer CL may include an organic material and / or an inorganic material.

[0087] The first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may be disposed on the capping layer CL. The first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may absorb external light. In addition, the first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may cause destructive interference between external light reflected from the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 and external light reflected from the first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3. Therefore, the first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may reduce the external light reflectivity of the display device 100 by reducing or blocking light traveling toward the outside of the display device 100. The low-reflection inorganic layers LAL1 , LAL2 , and LAL3 may be referred to as “anti-reflection inorganic layers”.

[0088] The first low-reflection inorganic layer LAL1 may overlap the first light emitting area EA1, the second low-reflection inorganic layer LAL2 may overlap the second light emitting area EA2, and the third low-reflection inorganic layer LAL3 may overlap the third light emitting area EA3. Optionally, the first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may be integrally formed and disposed as a whole in the display area DA.

[0089] Each of the first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may include an inorganic material. In an embodiment, for example, each of the first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may include an inorganic material such as a metal, a silicon compound, or a metal oxide.

[0090] Examples of metals may include silver (Ag), aluminum (Al), magnesium (Mg), chromium (Cr), titanium (Ti), nickel (Ni), gold (Au), tantalum (Ta), copper (Cu), calcium (Ca), cobalt (Co), iron (Fe), molybdenum (Mo), tungsten (W), platinum (Pt), or ytterbium (Yb). Examples of silicon compounds may include silicon oxide (SiO 2 ) or silicon nitride (SiN x ) etc. Examples of metal oxides may include titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O3 ), zinc oxide (ZnO x , which can be ZnO or ZnO 2 ), yttrium oxide (Y 2 O 3 ), beryllium oxide (BeO), magnesium oxide (MgO), lead oxide (PbO 2 ) or tungsten oxide (WO 3 ) and the like. These may be used alone or in combination with each other. Optionally, each of the first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may include a material such as lithium fluoride (LiF), calcium fluoride (CaF 2 ), magnesium fluoride (MgF 2 ) or cadmium sulfide (CdS) and the like. These may be used alone or in combination with one another.

[0091] The encapsulation layer ENC may be disposed on the capping layer CL and the first, second, and third low-reflection inorganic layers LAL1, LAL2, and LAL3. The encapsulation layer ENC may prevent impurities, moisture, and the like from penetrating from the outside into the first, second, and third light-emitting elements LED1, LED2, and LED3. The encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0092] In an embodiment, for example, the encapsulation layer ENC may include a first inorganic encapsulation layer ENC1 , an organic encapsulation layer ENC2 disposed on the first inorganic encapsulation layer ENC1 , and a second inorganic encapsulation layer ENC3 disposed on the organic encapsulation layer ENC2 .

[0093] In an embodiment, the first inorganic encapsulation layer ENC1 may have a multi-layer structure including a first sublayer SL1, a second sublayer SL2 disposed on the first sublayer SL, a third sublayer SL3 disposed on the second sublayer SL2, and a fourth sublayer SL4 disposed on the third sublayer SL3. In an embodiment, for example, the first sublayer SL1 may include silicon nitride, the second sublayer SL2 may include silicon oxynitride, the third sublayer SL3 may include silicon oxynitride, and the fourth sublayer SL4 may include silicon oxynitride.

[0094] In an embodiment, for example, the organic encapsulation layer ENC2 may include a cured polymer such as polyacrylate, and the second inorganic encapsulation layer ENC3 may include a silicon compound such as silicon oxynitride.

[0095] Since the encapsulation layer ENC includes the first inorganic encapsulation layer ENC1 , the organic encapsulation layer ENC2 , and the second inorganic encapsulation layer ENC3 , and the first inorganic encapsulation layer ENC1 has a multi-layer structure including four sub-layers, light efficiency of the display device 100 may be improved.

[0096] The touch sensing layer TCL may be disposed on the encapsulation layer ENC. The touch sensing layer TCL may be used as an input unit of the display device 100. The touch sensing layer TCL may include a first touch insulating layer TIL1, a second touch insulating layer TIL2, a first touch electrode TE1, a second touch electrode TE2, and a protective layer PL.

[0097] The first touch insulating layer TIL1 may be disposed on the encapsulation layer ENC. The first touch insulating layer TIL1 may include an inorganic material or an organic material. In an embodiment, for example, the first touch insulating layer TIL1 may include an inorganic material such as silicon oxide or silicon nitride. These may be used alone or in combination with each other.

[0098] The first touch electrode TE1 may be disposed on the first touch insulating layer TIL1. The first touch electrode TE1 may overlap the light blocking area BA. In an embodiment, for example, the first touch electrode TE1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. These may be used alone or in combination with each other.

[0099] The second touch insulating layer TIL2 may be disposed on the first touch insulating layer TIL1 and the first touch electrode TE1. The second touch insulating layer TIL2 may fully cover the first touch electrode TE1. The second touch insulating layer TIL2 may include an inorganic material or an organic material. In an embodiment, for example, the second touch insulating layer TIL2 may include an inorganic material such as silicon oxide or silicon nitride. These may be used alone or in combination with each other.

[0100] The second touch electrode TE2 may be disposed on the second touch insulating layer TIL2. The second touch electrode TE2 may overlap the light blocking area BA. The second touch electrode TE2 may be connected to the first touch electrode TE1 through a contact hole penetrating the second touch insulating layer TIL2. In an embodiment, for example, the second touch electrode TE2 may include carbon nanotubes ("CNTs"), transparent conductive oxides, indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), graphene, silver nanowires (AgNW), copper (Cu) or chromium (Cr), etc. These may be used alone or in combination with each other.

[0101] The first touch electrode TE1 and the second touch electrode TE2 may include the same material. Alternatively, the first touch electrode TE1 and the second touch electrode TE2 may include different materials.

[0102] The protective layer PL may be disposed on the second touch insulating layer TIL2 and the second touch electrode TE2. The protective layer PL may fully cover the second touch electrode TE2. The protective layer PL may protect the first touch electrode TE1 and the second touch electrode TE2. The protective layer PL may include an inorganic material or an organic material. In an embodiment, for example, the protective layer PL may include an inorganic material such as silicon oxide or silicon nitride. These may be used alone or in combination with each other.

[0103] The light blocking layer BL may be disposed on the protective layer PL. The light blocking layer BL may overlap the light blocking area BA. The light blocking layer BL may block light incident to the light blocking layer BL. Therefore, the light blocking layer BL may prevent color mixing between the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. An opening overlapping each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be defined in the light blocking layer BL. In an embodiment, for example, the light blocking layer BL may include an inorganic material and / or an organic material containing a black pigment or a black dye, etc.

[0104] The reflection control layer RCL may be disposed on the protective layer PL. The reflection control layer RCL may cover the light blocking layer BL. Since the display device 100 includes the reflection control layer RCL, the display device 100 may not include a polarizer. That is, the reflection control layer RCL may replace the function of the polarizer. In other words, the reflection control layer RCL may selectively absorb external light reflected from the inside of the display device 100 according to the wavelength, thereby preventing the light efficiency of the display device 100 from being deteriorated.

[0105] In an embodiment, the reflection control layer RCL may include an inorganic material or an organic material containing a dye, a pigment, or a combination thereof.

[0106] In an embodiment, for example, the maximum absorption wavelength of the reflection control layer RCL may include a wavelength range of about 530 nm to about 600 nm. That is, the reflection control layer RCL may absorb light having a wavelength outside the wavelength range of red light, green light, or blue light emitted from the first light emitting element LED1, the second light emitting element LED2, and the third light emitting element LED3.

[0107] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 It is used to illustrate the use of manufacturing Figure 2 A cross-sectional view of a method for displaying a device.

[0108] refer to Figure 4A buffer layer BUF, a first active pattern ACT1, a second active pattern ACT2, and a third active pattern ACT3, a gate insulating layer GI, a first gate electrode GE1, a second gate electrode GE2, and a third gate electrode GE3, an interlayer insulating layer ILD, a first source electrode SE1, a second source electrode SE2, and a third source electrode SE3, a first drain electrode DE1, a second drain electrode DE2, and a third drain electrode DE3, and a via insulating layer VIA can be sequentially formed on a substrate SUB1.

[0109] refer to Figure 5 The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be formed on the via insulating layer VIA. The first pixel electrode PE1 may be formed in the first emission area EA1, the second pixel electrode PE2 may be formed in the second emission area EA2, and the third pixel electrode PE3 may be formed in the third emission area EA3.

[0110] The pixel defining layer PDL may be formed on the via insulating layer VIA. The pixel defining layer PDL may be formed in the light blocking area BA. A pixel opening exposing at least a portion of the upper surface of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be formed in the pixel defining layer PDL. In an embodiment, in the second light emitting area EA2, a protruding portion PP_P contacting the second pixel electrode PE2 and protruding toward the pixel opening may be formed in the pixel defining layer PDL.

[0111] refer to Figure 6 , the first light emitting layer EML1 may be formed on the first pixel electrode PE1, the second light emitting layer EML2 may be formed on the second pixel electrode PE2, and the third pixel electrode PE3 may be formed on the third light emitting layer EML3. Specifically, the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may be formed in the pixel opening. In this case, the upper surface US_E of the second light emitting layer EML2 may be formed by the protruding portion PP_P of the pixel defining layer PDL (see Figure 5 ) is formed in a curved shape (eg, a convex shape) in a cross section. In an embodiment, for example, each of the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may be formed using an organic light emitting material that emits predetermined light.

[0112] refer to Figure 7The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be formed on the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 and the pixel defining layer PDL. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be integrally formed and may be formed on the entire surface of the display area DA.

[0113] The capping layer CL may be formed on the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3. In an embodiment, for example, the capping layer CL may be formed using an organic material and / or an inorganic material.

[0114] The first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may be formed on the capping layer CL. Specifically, the first low-reflection inorganic layer LAL1 may be formed in the first light-emitting area EA1, the second low-reflection inorganic layer LAL2 may be formed in the second light-emitting area EA2, and the third low-reflection inorganic layer LAL3 may be formed in the third light-emitting area EA3. In an embodiment, for example, each of the first low-reflection inorganic layer LAL1, the second low-reflection inorganic layer LAL2, and the third low-reflection inorganic layer LAL3 may be formed of a metal, a silicon compound, a metal oxide, or the like.

[0115] refer to Figure 8 The encapsulation layer ENC may be formed on the capping layer CL and the first, second, and third low-reflective inorganic layers LAL1, LAL2, and LAL3. In an embodiment, for example, the encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0116] The first touch insulating layer TIL1 may be formed on the encapsulation layer ENC. In an embodiment, for example, the first touch insulating layer TIL1 may be formed using an inorganic material. The first touch electrode TE1 may be formed on the first touch insulating layer TIL1.

[0117] The second touch insulating layer TIL2 may be formed on the first touch insulating layer TIL1 and the first touch electrode TE1. In an embodiment, for example, the second touch insulating layer TIL2 may be formed using an inorganic material.

[0118] The second touch electrode TE2 may be formed on the second touch insulating layer TIL2. The second touch electrode TE2 may be connected to the first touch electrode TE1 through a contact hole formed by removing a portion of the second touch insulating layer TIL2.

[0119] The protection layer PL may be formed on the second touch insulating layer TIL2 and the second touch electrode TE2. In an embodiment, for example, the protection layer PL may be formed using an inorganic material.

[0120] refer to Fig. 9 The light blocking layer BL may be formed in the light blocking area BA on the protection layer PL. In embodiments, for example, the light blocking layer BL may be formed using an inorganic material and / or an organic material containing a light blocking material such as a black pigment or a black dye.

[0121] Return to reference Figure 2 The reflection control layer RCL may be formed on the touch sensing layer TCL. The reflection control layer RCL may cover the light blocking layer BL. In an embodiment, for example, the reflection control layer RCL may be formed using an inorganic material or an organic material containing a dye, a pigment, or a combination thereof.

[0122] Therefore, it is possible to produce Figure 2 The display device 100 is shown in FIG.

[0123] Fig.10 is a cross-sectional view showing a display device according to another embodiment of the present disclosure.

[0124] refer to Fig.10 According to another embodiment of the present disclosure, a display device 101 may include a substrate SUB1, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1, a second transistor TR2, and a third transistor TR3, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a first light emitting element LED1, a second light emitting element LED2, and a third light emitting element LED3, a capping layer CL, a first low-reflection inorganic layer LAL1, a second low-reflection inorganic layer LAL2, and a third low-reflection inorganic layer LAL3, an encapsulation layer ENC, a touch sensing layer TCL, a light blocking layer BL, and a reflection control layer RCL. However, in addition to the second pixel electrode PE2, reference is made to Fig.10 The display device 101 described can be used with reference Figure 2 The display device 100 described is substantially the same or similar. In the following, redundant descriptions are omitted or simplified.

[0125] In an embodiment, the second pixel electrode PE2 may include an upper surface US_P having a curved shape in a cross-section. In detail, an edge of the upper surface US_P of the second pixel electrode PE2 may be inclined with respect to the substrate SUB1.

[0126] In an embodiment, for example, the upper surface US_P of the second pixel electrode PE2 may have a convex curved shape in a cross section. Alternatively, the upper surface US_P of the second pixel electrode PE2 may have a concave curved shape in a cross section. However, the embodiments of the present disclosure are not limited thereto. Alternatively, the upper surface US_P of the second pixel electrode PE2 may include a flat portion located at the center and substantially flat and an inclined portion located at the edge and extending from the flat portion to have a predetermined slope.

[0127] That is, since the second pixel electrode PE2 includes the upper surface US_P having a curved shape, the second light emitting layer EML2 may have a curved shape. In other words, the second light emitting layer EML2 may be disposed along the contour of the upper surface US_P of the second pixel electrode PE2.

[0128] Fig.11 is a cross-sectional view showing a display device according to still another embodiment of the present disclosure.

[0129] refer to Fig.11 According to another embodiment of the present disclosure, the display device 102 may include a substrate SUB1, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1, a second transistor TR2, and a third transistor TR3, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a first light emitting element LED1, a second light emitting element LED2, and a third light emitting element LED3, a capping layer CL, a first low-reflection inorganic layer LAL1, a second low-reflection inorganic layer LAL2, and a third low-reflection inorganic layer LAL3, an encapsulation layer ENC, a touch sensing layer TCL, a light blocking layer BL, and a reflection control layer RCL. However, except for the via insulating layer VIA, reference is made to Fig.11 The display device 102 described can be used with reference Fig.10 The display devices 101 described are substantially the same or similar. In the following, redundant descriptions are omitted or simplified.

[0130] In the second light emitting area EA2, a portion of the via insulating layer VIA may protrude or be recessed. In an embodiment, in the second light emitting area EA2, the via insulating layer VIA may include a protruding portion PP protruding toward the second pixel electrode PE2 at the upper surface of the via insulating layer VIA. For example, the upper surface of the protruding portion PP may have a convex curved shape in a cross section. Alternatively, the upper surface of the protruding portion PP may include a flat portion located at the center and substantially flat and an inclined portion located at the edge and extending from the flat portion to have a predetermined slope.

[0131] That is, since the via insulating layer VIA includes the protruding portion PP overlapping the second light emitting area EA2, each of the second pixel electrode PE2 and the second light emitting layer EML2 may have a curved shape (e.g., a convex shape). In other words, each of the second pixel electrode PE2 and the second light emitting layer EML2 may be disposed along the contour of the protruding portion PP of the via insulating layer VIA.

[0132] Fig.12 is a cross-sectional view showing a display device according to still another embodiment of the present disclosure.

[0133] refer to Fig.12 According to another embodiment of the present disclosure, the display device 103 may include a substrate SUB1, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1, a second transistor TR2, and a third transistor TR3, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a first light emitting element LED1, a second light emitting element LED2, and a third light emitting element LED3, a capping layer CL, a first low-reflection inorganic layer LAL1, a second low-reflection inorganic layer LAL2, and a third low-reflection inorganic layer LAL3, an encapsulation layer ENC, a touch sensing layer TCL, a light blocking layer BL, and a reflection control layer RCL. However, in addition to the via insulating layer VIA, the second pixel electrode PE2, and the second light emitting layer EML2, refer to Fig.12 The display device 103 described can be used with reference Fig.11 The display devices 102 described are substantially the same or similar. In the following, redundant descriptions are omitted or simplified.

[0134] In the second light emitting area EA2, a portion of the via insulation layer VIA may be recessed. In an embodiment, in the second light emitting area EA2, the via insulation layer VIA may include a recessed portion DP recessed toward the substrate SUB1 at an upper surface of the via insulation layer VIA. For example, the upper surface of the recessed portion DP may have a concave curved shape in a cross section. Alternatively, the upper surface of the recessed portion DP may include a flat portion located at the center and substantially flat and an inclined portion located at the edge and extending from the flat portion to have a predetermined slope.

[0135] That is, since the via insulating layer VIA includes the recessed portion DP overlapping the second light emitting area EA2, each of the second pixel electrode PE2 and the second light emitting layer EML2 may have a curved shape (e.g., a concave shape) in a cross section. In other words, each of the second pixel electrode PE2 and the second light emitting layer EML2 may be disposed along the contour of the recessed portion DP of the via insulating layer VIA.

[0136] Fig.13is a cross-sectional view showing a display device according to still another embodiment of the present disclosure.

[0137] refer to Fig.13 According to another embodiment of the present disclosure, the display device 104 may include a substrate SUB1, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1, a second transistor TR2, and a third transistor TR3, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a first light emitting element LED1, a second light emitting element LED2, and a third light emitting element LED3, a capping layer CL, a first low-reflection inorganic layer LAL1, a second low-reflection inorganic layer LAL2, and a third low-reflection inorganic layer LAL3, an encapsulation layer ENC, a touch sensing layer TCL, a light blocking layer BL, and a reflection control layer RCL. However, in addition to the second source electrode SE2 and the second drain electrode DE2, reference is made to Fig.13 The display device 104 described can be used with reference Fig.11 The display devices 102 described are substantially the same or similar. In the following, redundant descriptions are omitted or simplified.

[0138] In an embodiment, when the second source electrode SE2 and the second drain electrode DE2 at least partially overlap with the second light-emitting layer EML2 in a plan view, the thickness of each of the second source electrode SE2 and the second drain electrode DE2 may be different from the thickness of each of the first source electrode SE1, the first drain electrode DE1, the third source electrode SE3 and the third drain electrode DE3.

[0139] In an embodiment, for example, the thickness of each of the second source electrode SE2 and the second drain electrode DE2 may be thicker than the thickness of each of the first source electrode SE1, the first drain electrode DE1, the third source electrode SE3, and the third drain electrode DE3. In this case, the via insulating layer VIA may include a protruding portion PP overlapping the second light emitting area EA2, and each of the second pixel electrode PE2 and the second light emitting layer EML2 may have a convex shape in cross section.

[0140] Alternatively, the thickness of each of the second source electrode SE2 and the second drain electrode DE2 may be thinner than the thickness of each of the first source electrode SE1, the first drain electrode DE1, the third source electrode SE3, and the third drain electrode DE3. In this case, the via insulating layer VIA may include a recessed portion (e.g., Fig.12 A recessed portion DP) is formed, and each of the second pixel electrode PE2 and the second light emitting layer EML2 may have a concave shape in a cross-section.

[0141] Fig.14is a cross-sectional view showing a display device according to still another embodiment of the present disclosure.

[0142] refer to Fig.14 According to another embodiment of the present disclosure, the display device 105 may include a substrate SUB1, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1, a second transistor TR2, and a third transistor TR3, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a first light emitting element LED1, a second light emitting element LED2, and a third light emitting element LED3, a capping layer CL, a first low-reflection inorganic layer LAL1, a second low-reflection inorganic layer LAL2, and a third low-reflection inorganic layer LAL3, an encapsulation layer ENC, a touch sensing layer TCL, a light blocking layer BL, and a reflection control layer RCL. However, except for the second gate electrode GE2, reference is made to Fig.14 The display device 105 described can be used with reference Fig.11 The display devices 102 described are substantially the same or similar. In the following, redundant descriptions are omitted or simplified.

[0143] In an embodiment, when the second gate electrode GE2 at least partially overlaps the second light emitting layer EML2 in a plan view, the thickness of the second gate electrode GE2 may be different from the thickness of each of the first gate electrode GE1 and the third gate electrode GE3 .

[0144] In an embodiment, for example, the thickness of the second gate electrode GE2 may be thicker than the thickness of each of the first gate electrode GE1 and the third gate electrode GE3. In this case, the via insulating layer VIA may include a protruding portion overlapping the second light emitting area EA2, and each of the second pixel electrode PE2 and the second light emitting layer EML2 may have a convex shape in cross section.

[0145] Alternatively, the thickness of the second gate electrode GE2 may be thinner than the thickness of each of the first gate electrode GE1 and the third gate electrode GE3. In this case, the via insulating layer VIA may include a recessed portion (eg, Fig.12 A recessed portion DP) is formed, and each of the second pixel electrode PE2 and the second light emitting layer EML2 may have a concave shape in a cross-section.

[0146] Fig.15 is a cross-sectional view showing a display device according to still another embodiment of the present disclosure.

[0147] refer to Fig.15According to another embodiment of the present disclosure, the display device 106 may include a substrate SUB1, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1, a second transistor TR2, and a third transistor TR3, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, a first light emitting element LED1, a second light emitting element LED2, and a third light emitting element LED3, a capping layer CL, a first low-reflective inorganic layer LAL1, a second low-reflective inorganic layer LAL2, and a third low-reflective inorganic layer LAL3, an encapsulation layer ENC, a touch sensing layer TCL, a light blocking layer BL, and a reflection control layer RCL. However, in addition to the second active pattern ACT2, the reference Fig.15 The display device 106 described can be used with reference to Fig.11 The display devices 102 described are substantially the same or similar. In the following, redundant descriptions are omitted or simplified.

[0148] In an embodiment, when the second active pattern ACT2 at least partially overlaps the second light emitting layer EML2 in a plan view, the thickness of the second active pattern ACT2 may be different from the thickness of each of the first and third light emitting layers EML1 and EML3 .

[0149] In an embodiment, for example, the thickness of the second active pattern ACT2 may be thicker than the thickness of each of the first active pattern ACT1 and the third active pattern ACT3. In this case, the via insulating layer VIA may include a protruding portion PP overlapping the second light emitting area EA2, and each of the second pixel electrode PE2 and the second light emitting layer EML2 may have a convex shape in cross section.

[0150] Alternatively, the thickness of the second active pattern ACT2 may be thinner than each of the first active pattern ACT1 and the third active pattern ACT3. In this case, the via insulating layer VIA may include a recessed portion (eg, Fig.12 The recessed portion DP) and each of the second pixel electrode PE2 and the second light emitting layer EML2 may have a concave shape in a cross-section.

[0151] Reference again Figure 2 , Figure 3 and Figures 10 to 15 In the display devices 100, 101, 102, 103, 104, 105, and 106 according to the embodiments, the upper surface US_E of the second light emitting layer EML2 emitting green light may have a curved shape in cross section, and the upper surface of each of the first light emitting layer EML1 emitting red light and the third light emitting layer EML3 emitting blue light may be substantially flat. Therefore, the amount of light emitted from the second light emitting layer EML2 at a low angle may be increased, and the light emitted from the second light emitting layer EML2 at a low angle may be prevented from being reflected in the display area DA (see Figure 1 ) has a reddish color. In this case, the display quality of the display devices 100, 101, 102, 103, 104, 105, and 106 can be effectively improved.

[0152] The present disclosure may be applied to various display devices. For example, the present disclosure may be applied to various display devices such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for display or information transmission, and medical display devices.

[0153] The above is an illustration of the embodiments and should not be construed as limiting the embodiments. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined in the claims. Therefore, it should be understood that the above is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, characterized in that: The display device comprises: A substrate including a first light emitting region, a second light emitting region, and a third light emitting region and a light blocking region located between the first light emitting region, the second light emitting region, and the third light emitting region; a first light-emitting layer, disposed on the substrate in the first light-emitting region and emitting light of a first color; a second light emitting layer disposed in the second light emitting region on the substrate, including an upper surface having a curved shape in cross section, and emitting light of a second color different from the first color; a third light emitting layer disposed in the third light emitting region on the substrate, and emitting light of a third color different from the first color and the second color; and The reflection control layer is arranged on the first light-emitting layer, the second light-emitting layer and the third light-emitting layer.

2. The display device according to claim 1, characterized in that An edge of the upper surface of the second light emitting layer is inclined relative to a main upper surface of the substrate.

3. The display device according to claim 1, characterized in that In the cross section, the upper surface of the second light emitting layer has a concave shape or a convex shape.

4. The display device according to claim 1, characterized in that Each of the first light emitting layer and the third light emitting layer has a flat upper surface.

5. The display device according to claim 1, characterized in that The display device further comprises: a first pixel electrode, disposed between the substrate and the first light-emitting layer in the first light-emitting region; a second pixel electrode disposed between the substrate and the second light-emitting layer in the second light-emitting region; and A third pixel electrode is arranged between the substrate and the third light-emitting layer in the third light-emitting region. The second pixel electrode has an upper surface having a curved shape in the cross section.

6. The display device according to claim 5, characterized in that: The display device further comprises: a via insulating layer, disposed between the substrate and the first pixel electrode, the second pixel electrode and the third pixel electrode, Wherein, in the second light emitting region, the via insulation layer includes a protruding portion protruding toward the second pixel electrode at an upper surface of the via insulation.

7. The display device according to claim 5, characterized in that: The display device further comprises: a via insulating layer, disposed between the substrate and the first pixel electrode, the second pixel electrode and the third pixel electrode, Wherein, in the second light emitting region, the via insulating layer includes a concave portion at an upper surface of the via insulating layer that is concave toward the substrate.

8. The display device according to claim 5, characterized in that The display device further comprises: a first transistor electrically connected to the first pixel electrode and including a first active pattern, a first gate electrode, a first source electrode, and a first drain electrode; a second transistor electrically connected to the second pixel electrode and including a second active pattern, a second gate electrode, a second source electrode, and a second drain electrode; and a third transistor electrically connected to the third pixel electrode and including a third active pattern, a third gate electrode, a third source electrode, and a third drain electrode, Wherein, when the second source electrode and the second drain electrode at least partially overlap with the second light-emitting layer in a plan view, the thickness of each of the second source electrode and the second drain electrode is different from the thickness of each of the first source electrode, the first drain electrode, the third source electrode and the third drain electrode.

9. The display device according to claim 5, characterized in that: The display device further comprises: a first transistor electrically connected to the first pixel electrode and including a first active pattern, a first gate electrode, a first source electrode, and a first drain electrode; a second transistor electrically connected to the second pixel electrode and including a second active pattern, a second gate electrode, a second source electrode, and a second drain electrode; and a third transistor electrically connected to the third pixel electrode and including a third active pattern, a third gate electrode, a third source electrode, and a third drain electrode, Wherein, when the second gate electrode at least partially overlaps with the second light emitting layer in a plan view, the thickness of the second gate electrode is different from the thickness of each of the first gate electrode and the third gate electrode.

10. The display device according to claim 5, characterized in that: The display device further comprises: a first transistor electrically connected to the first pixel electrode and including a first active pattern, a first gate electrode, a first source electrode, and a first drain electrode; a second transistor electrically connected to the second pixel electrode and including a second active pattern, a second gate electrode, a second source electrode, and a second drain electrode; and a third transistor electrically connected to the third pixel electrode and including a third active pattern, a third gate electrode, a third source electrode, and a third drain electrode, Wherein, when the second active pattern at least partially overlaps the second light emitting layer in a plan view, a thickness of the second active pattern is different from a thickness of each of the first active pattern and the third active pattern.

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