Display device

Abstract

A display device includes a substrate including an emitter region and a non-emitter region. The light emitting layer is disposed on the pixel electrode and within the first opening. A common electrode is disposed on the light emitting layer in contact with the first bank layer within the second opening. An encapsulation layer is disposed on the common electrode and the second bank layer. The protruding tip of the second bank layer includes a side surface of the second bank layer. The packaging layer comprises an inorganic layer covering the common electrode. The protruding tip and the fluidizing layer are disposed on the inorganic layer. The fluidization layer includes a first portion disposed on the common electrode and a second portion disposed on the second bank layer. The first portion and the second portion are spaced apart from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0082298 filed in the Korean Intellectual Property Office on June 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device including a fluidizing layer. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices, such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device, such as a liquid crystal display (LCD) device, a field emission display device, or an organic light emitting diode (OLED) display device. In such a flat panel display device, because each of the multiple pixels of the display panel includes a light emitting element that can emit light by itself, the light emitting display device can display an image without a backlight unit that provides light to the display panel. Utility Model Content

[0005] A display device includes a substrate, the substrate including an emission region and a non-emission region. A first pixel electrode is disposed on the emission region of the substrate. A pixel defining layer is disposed on the non-emission region of the substrate, the pixel defining layer overlaps the first pixel electrode, and the pixel defining layer defines a first opening. A first bank layer is disposed on the pixel defining layer and defines a second opening overlapping the first opening. A second bank layer is disposed on the first bank layer and includes a protruding tip toward the first opening. A first light emitting layer is disposed on the first pixel electrode and disposed within the first opening. A first common electrode is disposed on the first light emitting layer and contacts the first bank layer within the second opening. A first encapsulation layer is disposed on the first common electrode and the second bank layer. The protruding tip of the second bank layer includes a side surface of the second bank layer that protrudes toward the first opening to a greater extent than a side surface of the first bank layer. The first encapsulation layer includes a first inorganic layer that completely covers the protruding tip of the first common electrode and the second bank layer. A first fluidizing layer is disposed on the first inorganic layer. The first fluidizing layer includes a first portion disposed on the first common electrode and a second portion disposed on the second bank layer. The first portion and the second portion are spaced apart from each other.

[0006] The first fluidizing layer may overlap the protruding tips of the second bank layer.

[0007] The first portion may completely cover a portion of the first inorganic layer overlapping the first opening.

[0008] The display device may further include a first electrode pattern, the first electrode pattern surrounding the first opening on the second bank layer and may also include the same material as the first common electrode. In a portion of the first common electrode and the first electrode pattern overlapping the protruding tip of the second bank layer, the first common electrode and the first electrode pattern may be spaced apart from each other with a space interposed between the first common electrode and the first electrode pattern.

[0009] The first portion may be disposed in the space between the first common electrode and the first electrode pattern.

[0010] The second portion may overlap the first electrode pattern outside the first opening.

[0011] The first inorganic layer and the first fluidizing layer may include different materials.

[0012] The first fluidization layer may include silicon oxynitride (SiON), silicon nitride (SiN), or silicon oxycarbide (SiOC).

[0013] The first encapsulation layer may further include a second inorganic layer completely covering the first fluidizing layer and a portion of the first inorganic layer overlapping the second opening.

[0014] The display device may further include an organic encapsulation layer disposed on the first encapsulation layer. On the side surface of the second bank layer, one surface of the second inorganic layer may be in contact with the first inorganic layer.

[0015] The other surface of the second inorganic layer may be in contact with the organic encapsulating layer on the side surface of the second bank layer.

[0016] The first inorganic layer may include a first inclined surface in a portion thereof overlapping with an outer portion of the second opening. The first fluidized layer may include a second inclined surface in a portion thereof overlapping with the outer portion of the second opening, and the second inorganic layer may include a third inclined surface in a portion of the second inorganic layer overlapping with the outer portion of the second opening.

[0017] The first inclined surface, the second inclined surface, and the third inclined surface may be aligned with each other, and the first inclined surface, the second inclined surface, and the third inclined surface may be in contact with the organic encapsulating layer.

[0018] The first encapsulation layer may further include a second fluidizing layer disposed on the second inorganic layer to overlap the first opening, and a third inorganic layer completely covering the second fluidizing layer.

[0019] The first encapsulation layer may further include a third fluidization layer disposed on the third inorganic layer to overlap the first opening, and a fourth inorganic layer that may completely cover the third fluidization layer.

[0020] A display device includes a substrate, the substrate including an emission region and a non-emission region. A first pixel electrode is disposed on the emission region of the substrate. A pixel defining layer is disposed on the non-emission region of the substrate, the pixel defining layer overlaps the first pixel electrode, and the pixel defining layer defines a first opening. A first bank layer is disposed on the pixel defining layer and defines a second opening overlapping the first opening. A second bank layer is disposed on the first bank layer and includes a protruding tip toward the first opening. A first light emitting layer is disposed on the first pixel electrode and disposed within the first opening. A first common electrode is disposed on the first light emitting layer and contacts the first bank layer within the second opening. A first encapsulation layer is disposed on the first common electrode and the second bank layer. The first encapsulation layer includes: a first inorganic layer, completely covering the protruding tip of the first common electrode and the second bank layer within the second opening; a second inorganic layer, disposed on the first inorganic layer; and a first fluidization layer, disposed between the first inorganic layer and the second inorganic layer within the first opening. The first inorganic layer and the second inorganic layer contact each other in a portion of the first inorganic layer and the second inorganic layer overlapping the outside of the second opening.

[0021] The first encapsulation layer may further include a second fluidizing layer disposed on the second inorganic layer to overlap the first opening, and a third inorganic layer completely covering the second fluidizing layer.

[0022] The first encapsulation layer may further include a third fluidizing layer disposed on the third inorganic layer to overlap the first opening, and a fourth inorganic layer completely covering the third fluidizing layer.

[0023] A display device includes a substrate, the substrate including an emission region and a non-emission region. A light emitting element is disposed on the emission region of the substrate. A first embankment structure is disposed on the non-emission region of the substrate. A second embankment structure is spaced apart from the first embankment structure, and a separation region is disposed between the second embankment structure and the first embankment structure. A first inorganic layer covers the first embankment structure and the second embankment structure. A first fluidizing layer is disposed on the first inorganic layer. A second inorganic layer is disposed on the first fluidizing layer. Each of the first embankment structure and the second embankment structure includes a first surface disposed toward the substrate and a second surface opposite to the first surface. The width of the second surface of the first embankment structure is greater than the width of the first surface of the first embankment structure. The width of the second surface of the second embankment structure is greater than the width of the first surface of the second embankment structure. The first fluidizing layer is completely surrounded by the first inorganic layer and the second inorganic layer in a portion of the first fluidizing layer overlapping the separation region between the first embankment structure and the second embankment structure.

[0024] The first fluidizing layer may include a first portion disposed in the separation region between the first and second bank structures and a second portion disposed on the first and second bank structures. The first and second portions of the first fluidizing layer are spaced apart from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0026] Figure 1 is a schematic perspective view of an electronic device according to an embodiment of the present disclosure;

[0027] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment of the present disclosure;

[0028] Figure 3 Observed from the side Figure 2 A cross-sectional view of a display device;

[0029] Figure 4 is a plan view showing a display layer of a display device according to an embodiment of the present disclosure;

[0030] Figure 5 is a plan view showing the arrangement of emission areas in a first display area of ​​a display device according to an embodiment of the present disclosure;

[0031] Figure 6 and Figure 7 It is along Figure 5 A cross-sectional view of the display device taken along line X1-X1';

[0032] Figure 8 yes Figure 6 An enlarged cross-sectional view of a first emission region;

[0033] Fig. 9 yes Figure 8 An enlarged cross-sectional view of area "T";

[0034] Fig.10 yes Figure 6 An enlarged cross-sectional view of area "P";

[0035] Fig.11 According to the embodiment of the present disclosure Figure 6 An enlarged cross-sectional view of a first emission region;

[0036] Fig.12 According to the embodiment of the present disclosure Figure 6 An enlarged cross-sectional view of a first emission region;

[0037] Fig.13 According to the embodiment of the present disclosure Figure 6 An enlarged cross-sectional view of a first emission region;

[0038] Fig.14 According to the embodiment of the present disclosure Figure 6 An enlarged cross-sectional view of a first emission region;

[0039] Fig.15 According to the embodiment of the present disclosure Figure 6 An enlarged cross-sectional view of a first emission region;

[0040] Fig.16 is a cross-sectional view of a structure including a recessed portion between adjacent bank structures according to an embodiment of the present disclosure; and

[0041] Fig.17 is a cross-sectional view of a structure including a recessed portion between adjacent bank structures according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] Embodiments of the present invention will now be described more fully below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Throughout the specification and the accompanying drawings, the same reference numerals may indicate the same components. In the accompanying drawings, various thicknesses, lengths and angles are shown, and although the arrangements shown do represent embodiments of the present invention, it should be understood that within the spirit and scope of the present invention, modifications of various thicknesses, lengths and angles are possible, and the present invention need not be limited to the specific thicknesses, lengths and angles shown.

[0043] It will also be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements.

[0044] It will be understood that although the terms "first", "second", or "third", etc. may be used herein to describe various elements, these elements are not necessarily limited by these terms. These terms are used to distinguish one element from another element, or to facilitate its description and illustration. For example, when discussing a "first element" in the specification, it may be named as a "second element" or a "third element", and without departing from the spirit and scope of the present invention, the "second element" and the "third element" may be named in a similar manner.

[0045] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0046] Figure 1 is a schematic perspective view of an electronic device 1 according to an embodiment of the present disclosure.

[0047] refer to Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 may refer to all electronic devices that provide a display screen. For example, a television, a laptop computer, a computer monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and a video camera that provide a display screen may be included in the electronic device 1.

[0048] The electronic device 1 may include a display device 10 (see Figure 2 ). Examples of display devices may include inorganic light emitting diode display devices, organic light emitting display devices, quantum dot light emitting display devices, plasma display devices, and field emission display devices, etc. Hereinafter, a case where an organic light emitting diode display device is applied as an example of a display device will be described by way of example, but the present disclosure is not necessarily limited thereto, and the same technical spirit may be applied to other display devices if applicable.

[0049] The shape of the electronic device 1 may be variously modified. For example, the electronic device 1 may have a shape such as a rectangular shape with a width greater than a length, a rectangular shape with a length greater than a width, a square shape, a rectangular shape with rounded corners (vertices), other polygonal shapes, or a circular shape in a plan view. The shape of the display area DA of the electronic device 1 may also be similar to the overall shape of the electronic device 1. Figure 1 , the electronic device 1 having a rectangular shape having a greater length in the second direction Y in a plan view has been illustrated.

[0050] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where an image may be displayed, and the non-display area NDA is an area where an image is not displayed. The display area DA may also be referred to as an active area / valid area, and the non-display area NDA may also be referred to as a non-active area / invalid area. The display area DA may substantially occupy the center of the electronic device 1.

[0051] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 may be areas in which components for adding various functions to the electronic device 1 are disposed, and may correspond to component areas.

[0052] Figure 2 FIG. 1 is a diagram showing an electronic device 1 (see FIG. 1 ) according to an embodiment of the present disclosure. Figure 1 ) is a perspective view of the display device 10 in FIG.

[0053] refer to Figure 2 , the electronic device 1 according to an embodiment of the present disclosure may include a display device 10. The display device 10 may provide an image displayed by the electronic device 1. In a plan view, the display device 10 may have a shape similar to that of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangular shape having short sides in a first direction X and long sides in a second direction Y in a plan view. The corner at the intersection of the short side in the first direction X and the long side in the second direction Y may be rounded with a specific curvature, but the utility model is not necessarily limited thereto, and the corner may also be a right angle. The shape of the display device 10 in a plan view is not necessarily limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0054] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0055] The display panel 100 may include a main area MA and a sub area SBA.

[0056] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. In addition, the display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3.

[0057] The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element. For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not necessarily limited thereto.

[0058] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver supplying a gate signal to a gate line, and a fan-out line connecting the display driver 200 and the display area DA to each other.

[0059] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, and curled to a significant degree without breaking or otherwise being damaged. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (e.g., the third direction Z). The sub-area SBA may include a display driver 200 and a pad component connected to the circuit board 300. In an embodiment of the present disclosure, the sub-area SBA may be omitted, and the display driver 200 and the pad component may be disposed in the non-display area NDA.

[0060] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may provide a source voltage to a power line and supply a gate control signal to a gate driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner. As an example, the display driver 200 may be disposed in a sub-area SBA and may overlap with the main area MA in a thickness direction by bending of the sub-area SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0061] The circuit board 300 may be attached to the pad part of the display panel 100 by using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pad part of the display panel 100. The circuit board 300 may be a printed circuit board such as a flexible printed circuit board or a flexible film such as a chip on film.

[0062] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit and sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may determine whether an input has occurred based on the amount of change in capacitance between the plurality of touch electrodes and calculate the input coordinates. The touch driver 400 may be formed as an integrated circuit (IC).

[0063] Figure 3 Observed from the side Figure 2 1 is a cross-sectional view of a display device 10 .

[0064] refer to Figure 3 , the display panel 100 may include a display layer DPL, a touch sensing layer 180 and a color filter layer 190. The display layer DPL may include a substrate 110, a thin film transistor layer 130, a light emitting element layer 150 and a thin film encapsulation layer 170.

[0065] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, and curled to a significant degree without breaking or otherwise suffering damage. As an example, the substrate 110 may include a polymer resin such as polyimide (PI), but is not necessarily limited thereto. As another example, the substrate 110 may include a glass material or a metal.

[0066] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer 130 may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line to each other, and a lead connecting the display driver 200 and the pad component to each other. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0067] The thin film transistor layer 130 may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, gate line, data line, and power line of each of the plurality of pixels of the thin film transistor layer 130 may be disposed in the display area DA. The gate control line and fan-out line of the thin film transistor layer 130 may be disposed in the non-display area NDA. The lead line of the thin film transistor layer 130 may be disposed in the sub-area SBA.

[0068] The light emitting element layer 150 may be disposed on the thin film transistor layer 130. The light emitting element layer 150 may include a plurality of light emitting elements and a pixel defining layer defining pixels, each light emitting element including a first electrode, a second electrode and a light emitting layer to emit light. The plurality of light emitting elements of the light emitting element layer 150 may be disposed in the display area DA.

[0069] In an embodiment of the present disclosure, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer 130 and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light-emitting layer to emit light.

[0070] In an embodiment of the present disclosure, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0071] The thin film encapsulation layer 170 may cover the upper surface and the side surface of the light emitting element layer 150 and may protect the light emitting element layer 150. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer 150.

[0072] The touch sensing layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensing layer 180 may include a plurality of touch electrodes for sensing a user's touch in a capacitive manner, and touch lines connecting the plurality of touch electrodes and the touch driver 400. For example, the touch sensing layer 180 may sense a user's touch in a mutual capacitance manner or a self-capacitance manner.

[0073] In an embodiment of the present disclosure, the touch sensing layer 180 may be disposed on a separate substrate disposed on the display layer DPL. In this case, the substrate supporting the touch sensing layer 180 may be a base member encapsulating the display layer DPL.

[0074] A plurality of touch electrodes of the touch sensing layer 180 may be disposed in a touch sensor area overlapping the display area DA, and a touch line of the touch sensing layer 180 may be disposed in a touch peripheral area overlapping the non-display area NDA.

[0075] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may emit or receive light in an infrared band, an ultraviolet band, and a visible light band. For example, the optical device 500 may be an optical sensor that senses light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, or an image sensor.

[0076] The color filter layer 190 may be disposed on the thin film encapsulation layer 170 to overlap with the emission region. The color filter layer 190 may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the plurality of color filters may selectively allow light of a specific wavelength to pass through the color filter and block or absorb light of other wavelengths. The color filter layer 190 may absorb some of the light introduced from outside the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer 190 may prevent color distortion caused by external light reflection.

[0077] Since the color filter layer 190 may be directly disposed on the thin film encapsulation layer 170, the display device 10 may not require a separate substrate for the color filter layer 190. Therefore, the thickness of the display device 10 may be relatively small.

[0078] Figure 4 is a plan view showing a display layer DPL of the display device 10 according to an embodiment of the present disclosure.

[0079] refer to Figure 4 , a plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL may be disposed in a display area DA of a display layer DPL. Each of the plurality of pixels PX may be defined as a minimum unit that emits light.

[0080] The plurality of gate lines GL may supply the plurality of pixels PX with gate signals received from the gate driver 210. The plurality of gate lines GL may extend in a first direction X, and may be spaced apart from each other in a second direction Y crossing the first direction X.

[0081] The plurality of data lines DL may supply the plurality of pixels PX with data voltages received from the display driver 200. The plurality of data lines DL may extend in the second direction Y, and may be spaced apart from each other in the first direction X.

[0082] The plurality of power lines VL may supply a source voltage received from the display driver 200 to the plurality of pixels PX. Here, the source voltage may be a driving voltage, an initialization voltage, a reference voltage, and / or a low potential voltage. The plurality of power lines VL may extend in the second direction Y and may be spaced apart from each other in the first direction X.

[0083] The gate driver 210, the fan-out lines FOL, and the gate control lines GCL may be disposed in the non-display area NDA of the display layer DPL. The gate driver 210 may generate a plurality of gate signals based on the gate control signal and may sequentially supply the plurality of gate signals to the plurality of gate lines GL according to a set order.

[0084] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0085] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply the gate driver 210 with a gate control signal received from the display driver 200.

[0086] The sub-area SBA may include the display driver 200 and the pad area DPA.

[0087] The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 may supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be supplied to a plurality of pixels PX, and the brightness of the plurality of pixels PX may be controlled. The display driver 200 may supply gate control signals to the gate driver 210 through the gate control lines GCL.

[0088] The pad area DPA may be disposed at an edge of the sub-area SBA. The pad area DPA may be electrically connected to the circuit board 300 (see FIG. 1 ) using a material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP). Figure 3 ).

[0089] The pad area DPA may include a plurality of display pads DP. The plurality of display pads DP may be connected to a graphics system through the circuit board 300. The plurality of display pads DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0090] Figure 5 is a plan view showing the arrangement of emission areas EA1 , EA2 , and EA3 in the first display area DA1 of the display device 10 according to an embodiment of the present disclosure.

[0091] refer to Figure 5 The display device 10 may include a display area DA (see Figure 1 ) in multiple emission areas EA1, EA2 and EA3. Figure 5The display area shown in FIG. 1 is the first display area DA1, and the plurality of emission areas EA1, EA2, and EA3 may be disposed in the first display area DA1. However, the plurality of emission areas EA1, EA2, and EA3 may also be disposed in the second display area DA2 of the display area DA (see FIG. 1 ). Figure 1 ) and the third display area DA3 (see Figure 1 )middle.

[0092] The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The plurality of emission areas EA1, EA2, and EA3 may emit red light, green light, or blue light, respectively, and the colors of the light emitted from the respective emission areas EA1, EA2, and EA3 may be selected according to the configuration of the light emitting element layer 150 (see FIG. 1 ) to be described later. Figure 6 ) at the light emitting elements ED1, ED2 and ED3 (see Figure 6 ) types. In an embodiment of the present disclosure, the first emission area EA1 may emit a first light as red light, the second emission area EA2 may emit a second light as green light, and the third emission area EA3 may emit a third light as blue light. However, the present disclosure is not necessarily limited thereto.

[0093] Multiple emission areas EA1, EA2 and EA3 can be Type (e.g. diamond Type) setting, where It is a series of sub-pixel matrix schemes used in electronic device displays produced by SAMSUNG. For example, the first emission area EA1 and the third emission area EA3 can be spaced apart from each other in the first direction X and the second direction Y, and can be alternately arranged in the first direction X and the second direction Y. In the arrangement of the emission areas EA1, EA2 and EA3, the first emission area EA1 and the third emission area EA3 can be alternately arranged in the first direction X in the first row R1 and the third row R3. The first emission area EA1 and the third emission area EA3 can be alternately arranged in the second direction Y in the first column C1 and the third column C3.

[0094] The second emission area EA2 may be spaced apart from other adjacent second emission areas EA2 in the first direction X and the second direction Y, and may be spaced apart from the adjacent first emission area EA1 and the third emission area EA3 in the fourth direction DR4 or the fifth direction DR5. A plurality of second emission areas EA2 may be repeatedly disposed along the first direction X and the second direction Y, and the second emission area EA2 and the first emission area EA1 or the second emission area EA2 and the third emission area EA3 may be alternately disposed along the fourth direction DR4 or the fifth direction DR5. In the arrangement of the emission areas EA1, EA2, and EA3, the second emission area EA2 may be repeatedly disposed in the first direction X in the second row R2 and the fourth row R4, and the second emission area EA2 may be repeatedly disposed in the second direction Y in the second column C2 and the fourth column C4.

[0095] The plurality of emission areas EA1, EA2, and EA3 may be defined by a plurality of first openings OP1 and a plurality of second openings OP2 formed by an inorganic pixel defining layer 151 (see FIG. 1 ) of a light emitting element layer 150 to be described later. Figure 6 ) and dike structure 160 (see Figure 6 )form.

[0096] Figure 6 and Figure 7 It is along Figure 5 1 is a cross-sectional view of the display device 10 taken along line X1 - X1 ′.

[0097] Figure 6 is a partial cross-sectional view of the display device 10 , and shows cross sections of the substrate 110 , the thin film transistor layer 130 , the light emitting element layer 150 , the thin film encapsulation layer 170 , the touch sensing layer 180 , and the color filter layer 190 .

[0098] like Figure 6 As shown in , the display layer DPL may include a substrate 110 , a thin film transistor layer 130 , a light emitting element layer 150 , and a thin film encapsulation layer 170 .

[0099] The substrate 110 may be the same as that mentioned above. Figure 3 The substrates described are essentially the same.

[0100] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may include a first buffer layer 111, a bottom metal layer BML, a second buffer layer 113, a thin film transistor TFT, a gate insulating layer 131, a first interlayer insulating layer 133, a capacitor electrode CPE, a second interlayer insulating layer 135, a first connection electrode CNE1, a first passivation layer 137, a second connection electrode CNE2, and a second passivation layer 139.

[0101] The first buffer layer 111 may be disposed on the substrate 110. The first buffer layer 111 may include an inorganic film capable of preventing penetration of air or moisture. For example, the first buffer layer 111 may include a plurality of inorganic films alternately stacked.

[0102] The bottom metal layer BML may be disposed on the first buffer layer 111. For example, the bottom metal layer BML may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0103] The second buffer layer 113 may cover the first buffer layer 111 and the bottom metal layer BML. The second buffer layer 113 may include an inorganic film capable of preventing penetration of air or moisture. For example, the second buffer layer 113 may include a plurality of inorganic films alternately stacked.

[0104] The thin film transistor TFT may be disposed on the second buffer layer 113 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0105] The semiconductor layer ACT may be disposed on the second buffer layer 113. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in the thickness direction, and may be insulated from the gate electrode GE by the gate insulating layer 131. The semiconductor material in a portion of the semiconductor layer ACT may become a conductor to form a source electrode SE and a drain electrode DE.

[0106] The gate electrode GE may be disposed on the gate insulating layer 131. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer 131 interposed therebetween.

[0107] The gate insulating layer 131 may be disposed on the semiconductor layer ACT. For example, the gate insulating layer 131 may cover the semiconductor layer ACT and the second buffer layer 113 and may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer 131 may include a contact hole through which the first connection electrode CNE1 passes.

[0108] The first interlayer insulating layer 133 may cover the gate electrode GE and the gate insulating layer 131. The first interlayer insulating layer 133 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer 133 may be connected to the contact hole of the gate insulating layer 131 and the contact hole of the second interlayer insulating layer 135.

[0109] The capacitor electrode CPE may be disposed on the first interlayer insulating layer 133. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitance (ie, function as a capacitor).

[0110] The second interlayer insulating layer 135 may cover the capacitor electrode CPE and the first interlayer insulating layer 133. The second interlayer insulating layer 135 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer 135 may be connected to the contact hole of the first interlayer insulating layer 133 and the contact hole of the gate insulating layer 131.

[0111] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer 135. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer 135, the first interlayer insulating layer 133, and the gate insulating layer 131 to contact the drain electrode DE of the thin film transistor TFT.

[0112] The first passivation layer 137 may cover the first connection electrode CNE1 and the second interlayer insulating layer 135. The first passivation layer 137 may protect the thin film transistor TFT. The first passivation layer 137 may include a contact hole through which the second connection electrode CNE2 passes.

[0113] The second connection electrode CNE2 may be disposed on the first passivation layer 137. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 to each other. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer 137 to contact the first connection electrode CNE1.

[0114] The second passivation layer 139 may cover the second connection electrode CNE2 and the first passivation layer 137. The second passivation layer 139 may include a contact hole through which the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 pass.

[0115] The light emitting element layer 150 may be disposed on the thin film transistor layer 130. The light emitting element layer 150 may include light emitting elements ED1, ED2, and ED3, an inorganic pixel defining layer 151, and a plurality of embankment structures 160. The light emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, respectively. The plurality of emission areas EA1, EA2, and EA3 described above may be defined by a first opening OP1 and a second opening OP2, the first opening OP1 being defined by the inorganic pixel defining layer 151 of the light emitting element layer 150, and the second opening OP2 being defined by the embankment structure 160.

[0116] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 disposed in a first emission area EA1, a second light emitting element ED2 disposed in a second emission area EA2, and a third light emitting element ED3 disposed in a third emission area EA3.

[0117] The light-emitting elements ED1, ED2 and ED3 may include pixel electrodes AE1, AE2 and AE3, light-emitting layers EL1, EL2 and EL3, and common electrodes CE1, CE2 and CE3, respectively. The light-emitting elements ED1, ED2 and ED3 arranged in different emission areas EA1, EA2 and EA3 may emit light of different colors according to the materials of the light-emitting layers EL1, EL2 and EL3. For example, the first light-emitting element ED1 arranged in the first emission area EA1 may emit red light as the light of the first color, the second light-emitting element ED2 arranged in the second emission area EA2 may emit green light as the light of the second color, and the third light-emitting element ED3 arranged in the third emission area EA3 may emit blue light as the light of the third color. The multiple emission areas EA1, EA2 and EA3 constituting one pixel may include light-emitting elements ED1, ED2 and ED3 that emit light of different colors to present a white grayscale.

[0118] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer 139. The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2.

[0119] The pixel electrodes AE1, AE2 and AE3 may be respectively arranged in a plurality of emission areas EA1, EA2 and EA3. The pixel electrodes AE1, AE2 and AE3 may include a first pixel electrode AE1 arranged in a first emission area EA1, a second pixel electrode AE2 arranged in a second emission area EA2 and a third pixel electrode AE3 arranged in a third emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3 may be spaced apart from each other on the second passivation layer 139, respectively. The pixel electrodes AE1, AE2 and AE3 may be respectively arranged in different emission areas EA1, EA2 and EA3 to respectively constitute light-emitting elements ED1, ED2 and ED3 emitting light of different colors. In an embodiment of the present disclosure, the pixel electrodes AE1, AE2 and AE3 may have a stacked film structure in which a film made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In 2 O 3 ) and a layer made of a reflective material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture / compound thereof. The layer made of the material having a high work function may be disposed at a layer above the layer made of the reflective material to be disposed close to the light emitting layers EL1, EL2, and EL3. As an example, the pixel electrodes AE1, AE2, and AE3 may have ITO / Mg, ITO / MgF 2 , ITO / Ag and ITO / Ag / ITO multilayer structures, but are not necessarily limited thereto.

[0120] The display device 10 may include an inorganic pixel defining layer 151 disposed on the second passivation layer 139 and the pixel electrodes AE1, AE2, and AE3. The inorganic pixel defining layer 151 may define a plurality of first openings OP1 forming emission areas EA1, EA2, and EA3. The inorganic pixel defining layer 151 may be completely disposed on the second passivation layer 139, but may expose portions of the upper surfaces of the pixel electrodes AE1, AE2, and AE3 while partially overlapping the pixel electrodes AE1, AE2, and AE3. For example, the inorganic pixel defining layer 151 may expose the pixel electrodes AE1, AE2, and AE3 in portions thereof overlapping with the first opening OP1, and the light emitting layers EL1, EL2, and EL3 may be directly disposed on the electrodes AE1, AE2, and AE3, respectively, in portions of the inorganic pixel defining layer 151 overlapping with the first opening OP1.

[0121] The inorganic pixel defining layer 151 may include an inorganic insulating material. As an example, the inorganic pixel defining layer 151 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0122] The embankment structure 160 may be disposed on the inorganic pixel defining layer 151. The embankment structure 160 may define a plurality of second openings OP2 forming emission areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3 of the display device 10 may overlap with the second openings OP2 of the embankment structure 160. The embankment structure 160 may include a first embankment layer 161 and a second embankment layer 163 including different metals and structures. The embankment structure 160 will be described in detail later.

[0123] The light-emitting layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3, respectively. The light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers made of organic materials and may be formed on the pixel electrodes AE1, AE2, and AE3, respectively, by a deposition process. When the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layers EL1, EL2, and EL3, respectively, through the hole transport layer and the electron transport layer, and may be recombined with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0124] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are respectively arranged in different emission areas EA1, EA2, and EA3. The first light-emitting layer EL1 may be arranged on the first pixel electrode AE1 in the first emission area EA1, the second light-emitting layer EL2 may be arranged on the second pixel electrode AE2 in the second emission area EA2, and the third light-emitting layer EL3 may be arranged on the third pixel electrode AE3 in the third emission area EA3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be light-emitting layers of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, respectively. The first light-emitting layer EL1 may be a light-emitting layer that emits red light as the first color of light, the second light-emitting layer EL2 may be a light-emitting layer that emits green light as the second color of light, and the third light-emitting layer EL3 may be a light-emitting layer that emits blue light as the third color of light.

[0125] In some embodiments, portions of the light-emitting layers EL1, EL2, and EL3 may be disposed between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151. For example, the inorganic pixel defining layer 151 may be disposed on the pixel electrodes AE1, AE2, and AE3, but may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The deposition process of the light-emitting layers EL1, EL2, and EL3 may be performed so that the materials of the light-emitting layers EL1, EL2, and EL3 are deposited in a direction inclined relative to the upper surface of the substrate 110, rather than in a direction perpendicular to the upper surface of the substrate 110. Therefore, portions of the light-emitting layers EL1, EL2, and EL3 may be disposed between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151. The deposition process of the light-emitting layers EL1, EL2, and EL3 will be described in detail later.

[0126] In the manufacturing process of the display device 10, a temporary protective layer may be provided between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3, and then the temporary protective layer may be partially removed. Therefore, the lower surface of the inorganic pixel defining layer 151 may be spaced apart from the pixel electrodes AE1, AE2, and AE3 in the area where the temporary protective layer is partially removed. The unremoved portion of the temporary protective layer may be retained as a residual pattern 157 in the area between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3. Therefore, the area between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3 may be filled with a portion of the residual pattern 157 and the light-emitting layers EL1, EL2, and EL3.

[0127] Common electrodes CE1, CE2 and CE3 may be disposed on the light emitting layers EL1, EL2 and EL3, respectively. Common electrodes CE1, CE2 and CE3 may include a transparent conductive material to emit light generated from the light emitting layers EL1, EL2 and EL3. Common electrodes CE1, CE2 and CE3 may receive a common voltage or a low potential voltage. When pixel electrodes AE1, AE2 and AE3 receive a voltage corresponding to a data voltage and common electrodes CE1, CE2 and CE3 receive a low potential voltage, a potential difference is formed between pixel electrodes AE1, AE2 and AE3 and common electrodes CE1, CE2 and CE3, so that the light emitting layers EL1, EL2 and EL3 may emit light. In an embodiment of the present disclosure, common electrodes CE1, CE2 and CE3 may include a material such as Li, Ca, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, Ba or compounds thereof (e.g., BaF 2) or a mixture (e.g., a mixture of Ag and Mg, etc.), or a layer made of a material with a small work function such as a multilayer structure of LiF / Ca, LiF / Al. The common electrodes CE1, CE2, and CE3 may further include a transparent metal oxide layer disposed on the layer made of the material with a small work function.

[0128] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 disposed in different emission areas EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light emitting layer EL1 in the first emission area EA1, the second common electrode CE2 may be disposed on the second light emitting layer EL2 in the second emission area EA2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3 in the third emission area EA3. The common electrodes CE1, CE2, and CE3 disposed in the different emission areas EA1, EA2, and EA3 are not directly connected to each other, but may be electrically connected to each other through the first bank layer 161 of the bank structure 160.

[0129] The covering layer 159 may be disposed on the common electrodes CE1, CE2, and CE3. The covering layer 159 may include an inorganic insulating material and covers the light emitting elements ED1, ED2, and ED3 and a pattern disposed on the embankment structure 160. The covering layer 159 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air, and prevent the pattern disposed on the embankment structure 160 from being peeled off during the manufacturing process of the display device 10. In an embodiment of the present disclosure, the covering layer 159 may include aluminum oxide (Al 2 O 3 ), titanium oxide (Ti 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (Si 2 N 2 O).

[0130] like Figure 6 As shown in FIG. 1 , the cover layer 159 may partially expose the common electrodes CE1, CE2, and CE3 in portions of the common electrodes CE1, CE2, and CE3 that overlap with the second opening OP2. This may be due to poor step coverage in the manufacturing process of forming the cover layer 159 and the common electrodes CE1, CE2, and CE3. However, the present disclosure is not necessarily limited thereto, and as Figure 7As shown in FIG. 1 , the cover layer 159 may cover the entire common electrodes CE1 , CE2 , and CE3 in portions of the common electrodes CE1 , CE2 , and CE3 overlapping the second opening OP2 .

[0131] The thin film encapsulation layer 170 may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure 160, and may cover the plurality of light emitting elements ED1, ED2, and ED3 and the embankment structure 160. The thin film encapsulation layer 170 may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer 150. The thin film encapsulation layer 170 may include at least one organic film to protect the light emitting element layer 150 from foreign substances such as dust.

[0132] The thin film encapsulation layer 170 may include a first thin film encapsulation layer 171, a second thin film encapsulation layer 173, and a third thin film encapsulation layer 175, which are sequentially stacked. The first thin film encapsulation layer 171 and the third thin film encapsulation layer 175 may be inorganic encapsulation layers, and the second thin film encapsulation layer 173 disposed between the first thin film encapsulation layer 171 and the third thin film encapsulation layer 175 may be an organic encapsulation layer.

[0133] In some embodiments, the first thin film encapsulation layer 171 may have a structure in which a barrier layer and a fluidization layer are alternately stacked. For example, the first thin film encapsulation layer 171 of the display device 10 may have a structure in which a first inorganic layer B11, a first fluidization layer S1, and a second inorganic layer B12 are sequentially stacked. The uppermost layer disposed at the uppermost portion of the first thin film encapsulation layer 171 may be a barrier layer that prevents moisture penetration.

[0134] The first thin film encapsulation layer 171 may include a first encapsulation layer 171-1, a second encapsulation layer 171-2, and a third encapsulation layer 171-3 corresponding to different emission areas EA1, EA2, and EA3, respectively. As an example, the first encapsulation layer 171-1 may overlap with the first emission area EA1, the second encapsulation layer 171-2 may overlap with the second emission area EA2, and the third encapsulation layer 171-3 may overlap with the third emission area EA3. The first encapsulation layer 171-1, the second encapsulation layer 171-2, and the third encapsulation layer 171-3 may be considered to be disposed at the same layer, but because they are formed in different processes in the manufacturing process, they may be spaced apart from each other. The first encapsulation layer 171-1, the second encapsulation layer 171-2, and the third encapsulation layer 171-3 may be directly disposed on the cover layer 159 within the first opening OP1, and may be directly disposed on the cover patterns 159-1, 159-2, and 159-3 within the second opening OP2, respectively.

[0135] The second thin film encapsulation layer 173 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, polyethylene, and siloxane resin, etc. For example, the second thin film encapsulation layer 173 may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The second thin film encapsulation layer 173 may be formed by curing a monomer or applying a polymer.

[0136] The third thin film encapsulation layer 175 may include one or more inorganic insulating materials. The inorganic insulating material may include aluminum oxide (Al 2 O 3 ), titanium oxide (Ti 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (Si 2 N 2 O).

[0137] The touch sensing layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensing layer 180 may include a touch buffer layer 181, a touch insulating layer 183, a touch electrode TE, and a touch protection layer 185.

[0138] The touch buffer layer 181 may be disposed on the thin film encapsulation layer 170. The touch buffer layer 181 may have an insulating function and an optical function. The touch buffer layer 181 may include at least one inorganic film. Alternatively, the touch buffer layer 181 may be omitted.

[0139] A connection electrode that electrically connects the touch electrodes TE to each other may be disposed on the touch buffer layer 181 .

[0140] The connecting electrode can be formed as a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or indium tin oxide (ITO), or formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0141] The touch insulating layer 183 may cover the touch buffer layer 181. The touch insulating layer 183 may have an insulating function and an optical function. For example, the touch insulating layer 183 may be an inorganic layer including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0142] Some of the touch electrodes TE may be disposed on the touch insulating layer 183. Each of the touch electrodes TE may not overlap with the plurality of emission areas EA1, EA2, and EA3. Each of the touch electrodes TE may be formed as a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0143] The touch protection layer 185 may cover the touch electrode TE and the touch insulating layer 183 . The touch protection layer 185 may have an insulating function and an optical function. The touch protection layer 185 may be made of the materials exemplified in the touch insulating layer 183 .

[0144] The light blocking layer BM may be disposed on the touch sensing layer 180 . The light blocking layer BM may overlap the inorganic pixel defining layer 151 and the bank structure 160 .

[0145] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the present disclosure is not necessarily limited thereto. The light blocking layer BM may prevent color mixing caused by the transmission of visible light between the multiple emission areas EA1, EA2, and EA3 to improve the color gamut of the display device 10.

[0146] The color filter layer 190 may be disposed on each of the touch protection layer 185 and the light blocking layer BM to overlap the emission areas EA1 , EA2 , and EA3 .

[0147] The color filter layer 190 may include a first color filter 191, a second color filter 192, and a third color filter 193 corresponding to different emission areas EA1, EA2, and EA3, respectively. The plurality of color filters 191, 193, and 195 may include a colorant such as a dye or a pigment that absorbs light of a wavelength band other than light of a specific wavelength band, and may correspond to the color of light emitted from the emission areas EA1, EA2, and EA3. For example, the first color filter 191 may be a red color filter that overlaps with the first emission area EA1 and allows only the first light, which is red light, to be transmitted through. The second color filter 193 may be a green color filter that overlaps with the second emission area EA2 and allows only the second light, which is green light, to be transmitted through, and the third color filter 195 may be a blue color filter that overlaps with the third emission area EA3 and allows only the third light, which is blue light, to be transmitted through.

[0148] exist Figure 61 has shown a structure in which a plurality of color filters 191, 193, and 195 are spaced apart from other adjacent color filters 191, 193, and 195 on the light blocking layer BM, but the present disclosure is not necessarily limited thereto. For example, a plurality of color filters 191, 193, and 195 may partially overlap with other adjacent color filters 191, 193, and 195. Different color filters 191, 193, and 195 may overlap with each other on the light blocking layer BM, which is an area that does not overlap with the emission areas EA1, EA2, and EA3.

[0149] An overcoat layer OC may be disposed on the color filter layer 190 and the light blocking layer BM to planarize the upper ends of the plurality of color filters 191, 193, and 195. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0150] Figure 8 yes Figure 6 FIG. 1 is an enlarged cross-sectional view of the first emission area EA1. Fig. 9 yes Figure 8 An enlarged cross-sectional view of area "T".

[0151] refer to Figure 8 , the first bank layer 161 included in the bank structure 160 may be disposed on the inorganic pixel defining layer 151. The first bank layer 161 may include a first surface 161a in contact with the inorganic pixel defining layer 151 and a side surface 161c disposed toward the first opening OP1. The first surface 161a of the first bank layer 161 may be disposed to simultaneously cover a curvature of the inorganic pixel defining layer 151.

[0152] The side surface 161c of the first bank layer 161 may be inclined between the first direction X (e.g., the X-axis direction) and the third direction Z (e.g., the Z-axis direction). The bank structure 160 may be formed by a deposition process and an etching process instead of a mask process, and the first bank layer 161 may be formed by a wet etching process. Therefore, compared to the inorganic pixel defining layer 151, the side surface 161c of the first bank layer 161 may be recessed in the first direction X (e.g., the X-axis direction) to be arranged in the shape of an inclined surface inclined in the first direction X (e.g., the X-axis direction) based on the third direction Z (e.g., the Z-axis direction).

[0153] The first bank layer 161 may include a metal having high conductivity. As an example, the first bank layer 161 may include aluminum (Al) having high conductivity. Therefore, the first bank layer 161 may be electrically connected to the common electrodes CE1, CE2, and CE3.

[0154] The second bank layer 163 may be disposed on the first bank layer 161. The second bank layer 163 may include a material having an etch rate lower than that of the first bank layer 161. As an example, the second bank layer 163 may include titanium (Ti).

[0155] In some embodiments, the second bank layer 163 may include a first surface 163a facing the first bank layer 161 and a side surface 163c facing the first opening OP1. The second bank layer 163 is formed by a wet etching process like the first bank layer 161, but includes a material that is relatively stable to the wet etching process compared to the first bank layer 161, and therefore, the side surface 163c of the second bank layer 163 may have a shape in which it protrudes more toward the first opening OP1 than the side surface 161c of the first bank layer 161. For example, the side surface 161c of the first bank layer 161 may have a shape in which the side surface 161c of the first bank layer 161 is recessed inward from the side surface 163c of the second bank layer 163. Therefore, the second bank layer 163 of the bank structure 160 may include a tip TIP protruding toward the first opening OP1 (i.e., a protruding tip TIP), and an undercut may be formed between a lower portion of the tip TIP of the second bank layer 163 and the side surface 161c of the first bank layer 161.

[0156] In some embodiments, the material may not be smoothly deposited under the protruding tip TIP of the embankment structure 160. Therefore, the materials of the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 may be designed to be deposited in a direction inclined relative to the upper surface of the substrate, rather than being deposited in a third direction Z (e.g., Z-axis direction) perpendicular to the upper surface of the substrate. For example, a deposition process for forming the light-emitting layers EL1, EL2, and EL3 may be performed so that the materials of the light-emitting layers EL1, EL2, and EL3 are deposited in a direction that is not perpendicular to the upper surfaces of the pixel electrodes AE1, AE2, and AE3, for example, in a direction inclined between the first direction X (e.g., X-axis direction) and the third direction Z (e.g., Z-axis direction). For this reason, deposition may be performed even in a partial area hidden by the protruding tip TIP of the embankment structure 160.

[0157] In an embodiment of the present disclosure, when the angle of the deposition process for forming the light-emitting layers EL1, EL2, and EL3 is defined as a first angle, the deposition process for forming the light-emitting layers EL1, EL2, and EL3 may be performed at an inclination angle of 45° to 50° from the upper surface of the pixel electrodes AE1, AE2, and AE3. For example, the first angle may be 45° to 50°. Therefore, the light-emitting layers EL1, EL2, and EL3 may fill the space between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151, and may also be formed on the sidewall of the second opening OP2 in an area hidden by the protruding tip TIP of the embankment structure 160.

[0158] The deposition process for forming the common electrodes CE1, CE2, CE3 may also be performed so that the materials of the common electrodes CE1, CE2, CE3 are deposited in a direction that is not perpendicular to the upper surfaces of the pixel electrodes AE1, AE2, AE3, for example, in a direction that is inclined between the first direction X (for example, the X-axis direction) and the third direction Z (for example, the Z-axis direction). In an embodiment of the present disclosure, when the angle of the deposition process for forming the common electrodes CE1, CE2, and CE3 is defined as the second angle, the deposition process for forming the common electrodes CE1, CE2, and CE3 may also be performed at an inclined angle of 30° or less from the upper surfaces of the pixel electrodes AE1, AE2, and AE3.

[0159] For example, the deposition process for forming the common electrodes CE1, CE2, and CE3 may be performed in an inclined direction closer to the horizontal direction than the deposition process for forming the light emitting layers EL1, EL2, and EL3. Therefore, the common electrodes CE1, CE2, and CE3 may contact the side surface of the first bank layer 161 with a larger area than the light emitting layers EL1, EL2, and EL3. Therefore, the deposition process for forming the common electrodes CE1, CE2, and CE3 may have a higher step coverage characteristic than the deposition process for forming the light emitting layers EL1, EL2, and EL3. For example, the common electrodes CE1, CE2, and CE3 may be deposited to a higher position on the side surface 161c of the first bank layer 161 than the light emitting layers EL1, EL2, and EL3.

[0160] refer to Figure 6 and Figure 8 , the embankment structure 160 includes a tip TIP formed in the second embankment layer 163, and therefore, the light emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer 159 formed by a deposition process performed over the entire surface of the display area DA may form a layer whose materials are disconnected from each other outside the first opening OP1 of the embankment structure 160. Therefore, a pattern including the same material as the light emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer 159 may remain on the embankment structure 160.

[0161] In some embodiments, a plurality of organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and capping patterns 159-1, 159-2, and 159-3 may be disposed on the second bank layer 163 of the bank structure 160 and may surround the emission areas EA1, EA2, and EA3 or the first opening OP1. In a manufacturing process of the display device 10, a stacked structure of the plurality of organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and capping patterns 159-1, 159-2, and 159-3 disposed around the emission areas EA1, EA2, and EA3 may be partially etched so that a pattern shape may be changed. Therefore, portions of the upper surface of the second bank layer 163 of the bank structure 160 may not be covered by the plurality of organic patterns ELP1, ELP2 and ELP3, the electrode patterns CEP1, CEP2 and CEP3, and the covering patterns 159-1, 159-2 and 159-3, and trench portions TP may be formed in these portions by the above patterns.

[0162] Each of the plurality of organic patterns ELP1, ELP2, and ELP3 may be disposed on the second bank layer 163 to partially contact the second bank layer 163. The organic patterns ELP1, ELP2, and ELP3 may include the same material as the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3, respectively. The first organic pattern ELP1 may include the same material as the first light-emitting layer EL1 of the first light-emitting element ED1, the second organic pattern ELP2 may include the same material as the second light-emitting layer EL2 of the second light-emitting element ED2, and the third organic pattern ELP3 may include the same material as the third light-emitting layer EL3 of the third light-emitting element ED3. Because the bank structure 160 includes a tip TIP, such organic patterns ELP1, ELP2, and ELP3 may be traces formed when the deposited material is disconnected from the light-emitting layers EL1, EL2, and EL3 instead of being connected to the light-emitting layers EL1, EL2, and EL3. For example, the organic patterns ELP1 , ELP2 , and ELP3 and the light emitting layers EL1 , EL2 , and EL3 may be spaced apart from each other by the tip TIP of the bank structure 160 .

[0163] refer to Fig. 9, the first organic pattern ELP1 may include a side surface ELP1c of the first organic pattern ELP1 covering a side surface 163c of a portion of the second bank layer 163 overlapping the second opening OP2. As described above, the deposition process of forming the light emitting layers EL1, EL2, and EL3 may be performed at an inclined angle of 45° to 50° from the upper surface of the pixel electrodes AE1, AE2, and AE3, and therefore, in the manufacturing process, the first organic pattern ELP1 may be disposed to simultaneously cover the side surface 163c of the second bank layer 163. In addition, the first organic pattern ELP1 may include an outer surface ELP1e that is partially etched in the manufacturing process in a portion thereof overlapping the outside of the second opening OP2. The outer surface ELP1e of the first organic pattern ELP1 may form the groove portion TP described above, and may contact the second thin film encapsulation layer 173. For ease of explanation, only the first organic pattern ELP1 is described, but all of the organic patterns ELP1, ELP2, and ELP3 may have the same structure.

[0164] like Figure 6 As shown in , a plurality of electrode patterns CEP1, CEP2 and CEP3 may be respectively disposed on a plurality of organic patterns ELP1, ELP2 and ELP3. The electrode patterns CEP1, CEP2 and CEP3 may include a first electrode pattern CEP1, a second electrode pattern CEP2 and a third electrode pattern CEP3 respectively including the same material as the common electrodes CE1, CE2 and CE3 of the light emitting elements ED1, ED2 and ED3. For example, the first electrode pattern CEP1, the second electrode pattern CEP2 and the third electrode pattern CEP3 may be directly disposed on the first organic pattern ELP1, the second organic pattern ELP2 and the third organic pattern ELP3, respectively. The arrangement relationship between the electrode patterns CEP1, CEP2 and CEP3 and the organic patterns ELP1, ELP2 and ELP3 may be the same as the arrangement relationship between the light emitting layers EL1, EL2 and EL3 of the light emitting elements ED1, ED2 and ED3 and the common electrodes CE1, CE2 and CE3. Since the bank structure 160 includes the tip TIP, such electrode patterns CEP1, CEP2, and CEP3 may be traces formed in a case where the deposition material is disconnected from the common electrodes CE1, CE2, and CE3 instead of being connected to the common electrodes CE1, CE2, and CE3. In the display device 10, even in a deposition process without using a mask, the common electrodes CE1, CE2, and CE3 may be formed by the tip TIP of the bank structure 160 (see FIG. Fig. 9 ) are formed separately in different zones.

[0165] refer to Fig. 9, the first electrode pattern CEP1 may include a side surface CEP1c of the first electrode pattern CEP1, which covers the side surface ELP1c of a portion of the first organic pattern ELP1 overlapping with the second opening OP2. In addition, the first electrode pattern CEP1 may include an outer surface CEP1e of the first electrode pattern CEP1 partially etched in a manufacturing process in a portion thereof overlapping with the outside of the second opening OP2. The outer surface CEP1e of the first electrode pattern CEP1 may form the trench portion TP described above and may contact the second thin film encapsulation layer 173. For ease of explanation, only the first electrode pattern CEP1 is described, but all of the electrode patterns CEP1, CEP2, and CEP3 may have the same structure.

[0166] like Figure 6 As shown in , the covering patterns 159-1, 159-2 and 159-3 can be respectively disposed on the electrode patterns CEP1, CEP2 and CEP3. The covering patterns 159-1, 159-2 and 159-3 can include the same material as the covering layer 159 disposed on the common electrodes CE1, CE2 and CE3. The covering patterns 159-1, 159-2 and 159-3 can be directly disposed on the electrode patterns CEP1, CEP2 and CEP3, respectively. The arrangement relationship between the covering patterns 159-1, 159-2 and 159-3 and the electrode patterns CEP1, CEP2 and CEP3 can be the same as the arrangement relationship between the common electrodes CE1, CE2 and CE3 of the light emitting elements ED1, ED2 and ED3 and the covering layer 159. Since the bank structure 160 includes a tip TIP, such capping patterns 159 - 1 , 159 - 2 , and 159 - 3 may be traces formed when the deposited material is disconnected from the capping layer 159 rather than connected to the capping layer 159 .

[0167] refer to Fig. 9 , the first covering pattern 159-1 may not be deposited on the side surface 163c of the second bank layer 163, and may be disposed on the first electrode pattern CEP1. In addition, the first covering pattern 159-1 may include an outer surface 159-1e of the first covering pattern 159-1 partially etched in a manufacturing process in a portion thereof overlapping the outside of the second opening OP2. The outer surface 159-1e of the first covering pattern 159-1 may form a trench portion TP and may contact the second thin film encapsulation layer 173. For ease of explanation, only the first covering pattern 159-1 is described, but all covering patterns 159-1, 159-2, and 159-3 may have the same structure.

[0168] refer to Figure 6 and Fig. 9In some embodiments, the first encapsulation layer 171-1 may be disposed to simultaneously cover the first light emitting element ED1 and the plurality of patterns ELP1, CEP1, and 159-1 disposed on the second bank layer 163. For example, the first encapsulation layer 171-1 may cover the first light emitting element ED1 and the bank structure 160 along the inner sidewall of the second opening OP2, and may be disposed on the bank structure 160 to cover the first organic pattern ELP1, the first electrode pattern CEP1, and the first covering pattern 159-1 disposed around the first opening OP1. However, as Fig. 9 As shown in , the first encapsulation layer 171-1 may be partially etched during the manufacturing process in a portion thereof overlapping with the outside of the second opening OP2. Therefore, the first encapsulation layer 171-1 may not cover the outer surfaces ELP1e, CEP1e, and 159-1e of the plurality of patterns ELP1, CEP1, and 159-1 in a portion thereof overlapping with the outside of the second opening OP2.

[0169] like Figure 8 As shown in FIG. 1 , the first encapsulation layer 171-1 of the display device 10 may have a structure in which the first inorganic layer B11, the first fluidization layer S1, and the second inorganic layer B12 are stacked. The first inorganic layer B11, the first fluidization layer S1, and the second inorganic layer B12 included in the first encapsulation layer 171-1 may be manufactured in the same process.

[0170] In some embodiments, the first inorganic layer B11 may have a function of preventing moisture penetration. The first inorganic layer B11 may be provided to simultaneously cover the first light emitting element ED1 and the first covering pattern 159-1 provided on the embankment structure 160. For example, the first inorganic layer B11 may completely cover the portion of the covering layer 159 overlapping the first opening OP1, and may completely cover the portion of the covering layer 159, the first common electrode CE1, the first embankment layer 161, and the second embankment layer 163 overlapping the second opening OP2. In addition, the first inorganic layer B11 may cover the upper portion of the first covering pattern 159-1 outside the second opening OP2. As an example, the first inorganic layer B11 may include aluminum oxide (Al2O3). 2 O 3 ), titanium oxide (Ti 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (Si 2 N 2 O).

[0171] like Fig. 9As shown in , the first inorganic layer B11 included in the first encapsulation layer 171-1 may be partially etched in the same manufacturing process as the plurality of patterns ELP1, CEP1, and 159-1. Therefore, the first inorganic layer B11 may include an outer surface B11e of the portion of the first inorganic layer B11 overlapping the outside of the second opening OP2. The outer surface B11e of the first inorganic layer B11 may be aligned with the outer surfaces ELP1e, CEP1e, and 159-1e of the plurality of patterns ELP1, CEP1, and 159-1. Therefore, the outer surface B11e of the first inorganic layer B11 may form the groove portion TP described above and may contact the second thin film encapsulation layer 173. For ease of explanation, only the first inorganic layer B11 overlapping the first emission area EA1 is described, but all the first inorganic layers B11, B21, and B31 overlapping the respective emission areas EA1, EA2, and EA3 may have the same structure.

[0172] like Figure 8 As shown in , in some embodiments, the first fluidization layer S1 may have a characteristic of high fluidity. The first fluidization layer S1 may flatten the step of the lower structure. As an example, a relatively large physical step may be formed between the lower portion of the tip TIP of the second bank layer 163 and the side surface 161c of the first bank layer 161 in the display device 10. Generally, when a large step is formed in the display device 10, the step coverage characteristic of the inorganic film covering the step may be deteriorated, and therefore, cracks may be generated in the inorganic film covering the step. The cracks generated in the inorganic film as described above may be a permeation path for external oxygen and moisture of the display device 10. However, the first thin film encapsulation layer 171 of the display device 10 includes a material having a characteristic of high fluidity, and therefore, the step structure caused in the display device 10 may be flattened. Therefore, the display device 10 including the first fluidization layer S1 in the first thin film encapsulation layer 171 can reduce defects caused by the permeation of moisture and oxygen.

[0173] In some embodiments, the first fluidization layer S1 may include a first portion S11 disposed on the first light emitting element ED1 to overlap the first opening OP1 and a second portion S12 disposed on the embankment structure 160 outside the first opening OP1. For example, the first portion S11 of the first fluidization layer S1 and the second portion S12 of the first fluidization layer S1 may be spaced apart from each other. Since the first fluidization layer S1 has fluidity, the first portion S11 and the second portion S12 of the first fluidization layer S1 may be formed during the manufacturing process without a separate additional process, or may be formed by a separate additional plasma etching process after the first fluidization layer S1 is formed.

[0174] In some embodiments, the first portion S11 of the first fluidization layer S1 may be disposed on the first inorganic layer B11 to overlap the second opening OP2 . The first portion S11 of the first fluidization layer S1 may planarize steps caused by the first light emitting element ED1 , the capping layer 159 , and the bank structure 160 .

[0175] The second portion S12 of the first fluidizing layer S1 may be disposed on the first inorganic layer B11 to overlap the outside of the second opening OP2. The second portion S12 of the first fluidizing layer S1 may be disposed on the second bank layer 163. The thickness of the second portion S12 of the first fluidizing layer S1 may decrease in a direction toward the first opening OP1, but is not necessarily limited thereto.

[0176] The first fluidized layer S1 may include a silicon-based inorganic compound. As an example, the first fluidized layer S1 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (Si 2 N 2 O).

[0177] refer to Fig. 9 , the second portion S12 of the first fluidization layer S1 may include an outer surface S12e of the second portion S12, and the outer surface S12e of the second portion S12 is aligned with the outer surfaces ELP1e, CEP1e and 159-1e of the portions of the plurality of patterns ELP1, CEP1 and 159-1 overlapping the outside of the second opening OP2. The outer surface S12e of the second portion S12 included in the first fluidization layer S1 may form the groove portion TP described above, and may contact the second thin film encapsulation layer 173. For ease of explanation, only the first fluidization layer S1 overlapping the first emission area EA1 is described, but all first fluidization layers S1, S2 and S3 overlapping the respective emission areas EA1, EA2 and EA3 may have the same structure.

[0178] In some embodiments, the second inorganic layer B12 may have characteristics similar to those of the first inorganic layer B11. As an example, the second inorganic layer B12 may have a function of preventing moisture penetration.

[0179] like Figure 8As shown in , in some embodiments, the second inorganic layer B12 may completely cover the first fluidization layer S1 and the first inorganic layer B11 in the portion thereof overlapping with the second opening OP2, and may cover the upper surface of the first fluidization layer S1 outside the second opening OP2. The second inorganic layer B12 may be in contact with the first inorganic layer B11 in the portion overlapping with the second opening OP2 and in which the first fluidization layer S1 is not partially disposed. For example, the first fluidization layer S1 may not be disposed on the side surface 163c of the second bank layer 163. Therefore, on the side surface 163c of the second bank layer 163, one surface of the second inorganic layer B12 may be in contact with the first inorganic layer B11. For example, on the side surface 163c of the second bank layer 163, the other surface of the second inorganic layer B12 may be in contact with the second thin film encapsulation layer 173. For example, the second inorganic layer B12 may contact the first inorganic layer B11 on the side surface ELP1c of the first organic pattern ELP1, the side surface CEP1c of the first electrode pattern CEP1, and the side surface 159 - 1c of the capping pattern 159 - 1.

[0180] refer to Fig. 9 , the second inorganic layer B12 may include an outer surface B12e of the second inorganic layer B12, and the outer surface B12e of the second inorganic layer B12 is aligned with the outer surfaces ELP1e, CEP1e and 159-1e of the plurality of patterns ELP1, CEP1 and 159-1 that overlap the outside of the second opening OP2. The outer surface B12e of the second inorganic layer B12 may form the groove portion TP described above. For ease of explanation, only the second inorganic layer B12 overlapping the first emission area EA1 is described, but all second inorganic layers B12, B22 and B32 overlapping the respective emission areas EA1, EA2 and EA3 may have the same structure.

[0181] Fig.10 yes Figure 6 An enlarged cross-sectional view of area "P".

[0182] As described above, the first encapsulation layer 171 - 1 , the second encapsulation layer 171 - 2 , and the third encapsulation layer 171 - 3 may be considered to be disposed at the same layer, but may be formed in different processes in the manufacturing process.

[0183] refer to Figure 6 and Fig.10, the first encapsulation layer 171-1 may be formed after forming the first common electrode CE1, the second encapsulation layer 171-2 may be formed after forming the second common electrode CE2, and the third encapsulation layer 171-3 may be formed after forming the third common electrode CE3. For example, the first encapsulation layer 171-1 may be formed before forming the second light emitting element ED2 and the third light emitting element ED3, and the second encapsulation layer 171-2 may be formed before forming the third light emitting element ED3. For example, the first encapsulation layer 171-1 may completely cover the embankment structure 160 and the second emission area EA2, and then be partially patterned in the manufacturing process. In addition, after forming the first encapsulation layer 171-1, the second encapsulation layer 171-2 may completely cover the embankment structure 160 and the first emission area EA1, and then be partially patterned. In addition, after forming the second encapsulation layer 171-2, the third encapsulation layer 171-3 may completely cover the first emission area EA1, the second emission area EA2, and the embankment structure 160, and then be partially patterned.

[0184] refer to Fig.10 , the first encapsulation layer 171-1 may be partially disposed on the first emission area EA1 and the embankment structure 160 located around the first emission area EA1. In addition, the second encapsulation layer 171-2 may be partially disposed on the second emission area EA2 and the embankment structure 160 located around the second emission area EA2. For example, the first encapsulation layer 171-1 and the second encapsulation layer 171-2 may be spaced apart from each other on the second embankment layer 163 of the embankment structure 160. The second thin film encapsulation layer 173 may be disposed between the first encapsulation layer 171-1 and the second encapsulation layer 171-2 spaced apart from each other. For ease of explanation, the first encapsulation layer 171-1 and the second encapsulation layer 171-2 have been shown and described, but the first encapsulation layer 171-1, the second encapsulation layer 171-2, and the third encapsulation layer 171-3 may all have the same structure.

[0185] Fig.11 and Fig.12 According to the embodiment of the present disclosure Figure 6 FIG. 1 is an enlarged cross-sectional view of the first emission area EA1.

[0186] refer to Fig.11 The display device 20 is different from the display device 10 according to the above-mentioned embodiment of the present disclosure (see Figure 6 ) is that the first encapsulation layer 171-1 includes a first inorganic layer B11, a first fluidizing layer S1, a second inorganic layer B12, a second fluidizing layer S1a, and a third inorganic layer B13. The display device 20 may further include a second fluidizing layer S1a on the second inorganic layer B12, and may further include a third inorganic layer B13 that completely covers the second inorganic layer B12 and the second fluidizing layer S1a.

[0187] In some embodiments, the second fluidizing layer S1a of the display device 20 may have characteristics similar to those of the first fluidizing layer S1 of the display device 10. For example, the second fluidizing layer S1a may have high fluidity and may planarize steps of a lower structure.

[0188] The second fluidization layer S1a of the display device 20 may include a first portion S13 disposed on the first light emitting element ED1 to overlap the first opening OP1 and a second portion S14 disposed on the second bank 163 to overlap the second opening OP2. The first portion S13 and the second portion S14 included in the second fluidization layer S1a may be spaced apart from each other.

[0189] The third inorganic layer B13 of the display device 20 may have characteristics similar to those of the first inorganic layer B11 and the second inorganic layer B12 of the display device 10. For example, the third inorganic layer B13 may cover the lower structure and may prevent the penetration of oxygen and moisture introduced from the outside of the display device 20. The third inorganic layer B13 of the display device 20 may be the uppermost layer of the first encapsulation layer 171-1. Therefore, one surface of the third inorganic layer B13 may be in contact with the second fluidization layer S1a and the second inorganic layer B12, and the other surface of the third inorganic layer B13 may be in contact with the second thin film encapsulation layer 173. The third inorganic layer B13 may be in contact with the second inorganic layer B12 in a portion where the first portion S13 of the second fluidization layer S1a and the second portion S14 of the second fluidization layer S1a are spaced from each other. As far as the element is not described in detail with respect to the figure, it can be understood that the element is at least similar to the corresponding element that has been described elsewhere in the present disclosure.

[0190] refer to Fig.12 The display device 30 is similar to the display device 10 according to the above-mentioned embodiment of the present disclosure (see Figure 6 ) and 20 are different in that the first encapsulation layer 171-1 includes a first inorganic layer B11, a first fluidizing layer S1, a second inorganic layer B12, a second fluidizing layer S1a, a third inorganic layer B13, a third fluidizing layer S1b, and a fourth inorganic layer B14. The display device 30 may further include a third fluidizing layer S1b on the third inorganic layer B13, and may further include a fourth inorganic layer B14 that completely covers the third inorganic layer B13 and the third fluidizing layer S1b.

[0191] In some embodiments of the present disclosure, the third fluidization layer S1b of the display device 30 may have characteristics similar to those of the first fluidization layer S1 and the second fluidization layer S1a of the display device 20, and the fourth inorganic layer B14 of the display device 30 may have characteristics similar to those of the first inorganic layer B11, the second inorganic layer B12 and the third inorganic layer B13 of the display device 20.

[0192] The third fluidization layer S1b of the display device 30 may include a first portion S15 disposed on the first light emitting element ED1 to overlap the first opening OP1 and a second portion S16 disposed on the second bank 163 to overlap the second opening OP2. The first portion S15 and the second portion S16 included in the third fluidization layer S1b may be spaced apart from each other.

[0193] The fourth inorganic layer B14 of the display device 30 may be in contact with the third inorganic layer B13 in a portion where the first portion S15 of the third fluidizing layer S1b and the second portion S16 of the third fluidizing layer S1b are spaced apart from each other. The fourth inorganic layer B14 of the display device 30 may be the uppermost layer of the first encapsulation layer 171-1. Therefore, one surface of the fourth inorganic layer B14 may be in contact with the third fluidizing layer S1b and the third inorganic layer B13, and the other surface of the fourth inorganic layer B14 may be in contact with the second thin film encapsulation layer 173. Other common descriptions have been provided and will therefore be omitted.

[0194] Figures 13 to 15 According to the embodiment of the present disclosure Figure 6 FIG. 1 is an enlarged cross-sectional view of the first emission area EA1.

[0195] refer to Fig.13 , the display device 50 and the display device 10 (see Figure 6 ) is that the first fluidizing layer S1 of the first encapsulation layer 171-1 only includes the first portion S11. In the process of manufacturing the first fluidizing layer S1 of the first encapsulation layer 171-1 in the display device 50, the second portion S12 of the first fluidizing layer S1 may be removed by a plasma etching process (see Figure 8 ). The process of etching the second portion S12 of the first fluidization layer S1 may be performed in the same manufacturing process as the process of forming the first fluidization layer S1. Therefore, the first encapsulation layer 171-1 of the display device 50 may include a first inorganic layer B11 disposed on the first light-emitting element ED1, a first portion S11 of the first fluidization layer S1, and a second inorganic layer B12. In addition, the first encapsulation layer 171-1 of the display device 50 may include a first inorganic layer B11 and a second inorganic layer B12 disposed on the second embankment layer 163 to overlap with the second opening OP2. For example, the first fluidization layer S1 is not disposed on the second embankment layer 163 of the display device 50, and therefore, the first inorganic layer B11 and the second inorganic layer B12 may contact each other on the second embankment layer 163.

[0196] In the display device 50, the first fluidization layer S1 included in the first encapsulation layer 171-1 includes the first portion S11, and therefore, the step of the display device 50 can be flattened. In addition, the first fluidization layer S1 is not included on the second bank layer 163, and the first inorganic layer B11 and the second inorganic layer B12 are in contact with each other, and therefore, the thickness of the display device 50 can be reduced. To the extent that an element is not described in detail with respect to the figure, it can be understood that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure.

[0197] refer to Fig.14 , the display device 60 and the display device 20 (see Fig.11 ) is that the first encapsulation layer 171-1 does not include the second portion S12 of the first fluidization layer S1 on the second bank layer 163 (see Fig.11 ) and the second portion S14 of the second fluidized layer S1a (see Fig.11 ). In the manufacturing process of the display device 60, the second portion S12 of the first fluidized layer S1 and the second portion S14 of the second fluidized layer S1a may be removed by a plasma etching process. Therefore, the first encapsulation layer 171-1 of the display device 60 may reduce the thickness of the display device 60 while flattening the lower step.

[0198] refer to Fig.15 , the display device 70 and the display device 30 (see Fig.12 ) is that the first encapsulation layer 171-1 does not include the second portion S12 of the first fluidization layer S1 on the second bank layer 163 (see Fig.12 ), the second part S14 of the second fluidized layer S1a (see Fig.12 ) and the second portion S16 of the third fluidized layer S1b (see Fig.12 ). In the manufacturing process of the display device 70, the second portion S12 of the first fluidized layer S1, the second portion S14 of the second fluidized layer S1a, and the second portion S16 of the third fluidized layer S1b can be removed by a plasma etching process. Therefore, the first encapsulation layer 171-1 of the display device 70 can reduce the thickness of the display device 70 while flattening the lower step. To the extent that no element is described in detail with respect to this figure, it can be understood that the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure.

[0199] Fig.16 and Fig.17 is a cross-sectional view of a structure including a recessed portion between adjacent bank structures according to an embodiment of the present disclosure.

[0200] refer to Fig.16 and Fig.17Each of the display devices 80 and 90 may include a plurality of embankment structures 160 (e.g., a first embankment structure and a second embankment structure) defining an opening OP0, each of the first embankment structure and the second embankment structure including a first surface 161a disposed toward the substrate and a second surface 163b opposite to the first surface 161a, wherein a width of the second surface 163b of the first embankment structure is greater than a width of the first surface 161a of the first embankment structure, and a width of the second surface 163b of the second embankment structure is greater than a width of the first surface 161a of the second embankment structure.

[0201] The substrate 110 of the display device 80 and the display device 90 may include an emission area EA and a non-emission area BA.

[0202] In some embodiments, the bank structure 160 may be disposed on the non-emission area BA of the substrate 110, and the opening OP0 may be defined by a plurality of bank structures 160 adjacent to each other. Each bank structure 160 may include a first bank layer 161 and a second bank layer 163.

[0203] In some embodiments, the first bank layer 161 may include a first surface 161a facing the substrate 110, a second surface 161b opposite to the first surface 161a, and a side surface 161c facing the opening OP0. Fig.16 and Fig.17 FIG. 4 shows that the side surface 161 c of the first bank layer 161 is inclined, but the present disclosure is not necessarily limited thereto. For example, the side surface 161 c of the first bank layer 161 may be perpendicular to the substrate 110 .

[0204] The second bank layer 163 may be disposed on the first bank layer 161. The second bank layer 163 may include a first surface 163a facing the first bank layer 161, a second surface 163b opposite to the first surface 163a, and a side surface 163c facing the opening OP0.

[0205] In some embodiments, the width of the first surface 163a of the second bank layer 163 may be greater than the width of the second surface 161b of the first bank layer 161. In addition, the side surface 163c of the second bank layer 163 may include a tip TIP that protrudes more toward the opening OP0 than the side surface 161c of the first bank layer 161. Therefore, an undercut may be formed between the protruding tip TIP of the second bank layer 163 and the side surface 161c of the first bank layer 161.

[0206] In some embodiments, the partition area SA may overlap the opening OP0 between the embankment structures 160 spaced apart from each other in the first direction X (e.g., the X-axis direction). The partition area SA included in each of the display devices 80 and 90 may include components constituting the display, such as the light emitting element ED, the driving line, and the circuit. Therefore, the partition area SA of each of the display devices 80 and 90 may also include a step caused by the components.

[0207] The first thin film encapsulation layer 171 may be disposed on the embankment structure 160. The first thin film encapsulation layer 171 may completely cover the embankment structure 160 spaced apart from each other in the first direction X (eg, X-axis direction). For example, the first thin film encapsulation layer 171 may cover the inner surface of the embankment structure 160 in a portion overlapping the opening OP0.

[0208] In some embodiments, the first thin film encapsulation layer 171 may have a structure in which an inorganic layer and a fluidizing layer are stacked. As an example, the first thin film encapsulation layer 171 of each of the display devices 80 and 90 may include a first inorganic layer B11, a first fluidizing layer S1, and a second inorganic layer B12.

[0209] The first inorganic layer B11 may completely cover the adjacent bank structure 160. For example, the first inorganic layer B11 may extend while covering the upper surface of the bank structure 160 and the inner surface of the bank structure 160 overlapping the opening OP0 without being partially etched or spaced apart from each other.

[0210] The first fluidizing layer S1 may be disposed on the first inorganic layer B11.

[0211] refer to Fig.16 In the display device 80, the first fluidization layer S1 may include a first portion S11 disposed on the substrate 110 to overlap the opening OP0 and a second portion S12 disposed on the second bank layer 163 to overlap the non-emission area BA. The first portion S11 and the second portion S12 of the first fluidization layer S1 may be spaced apart from each other.

[0212] refer to Fig.17 , the display device 90 and the display device 80 (see Fig.16 ) is different in that the first fluidizing layer S1 includes only the first portion S11 disposed on the substrate 110 to overlap the opening OP0. Therefore, in the display device 90, the first fluidizing layer S1 may not be disposed on the second bank layer 163, and the first inorganic layer B11 and the second inorganic layer B12 may contact each other.

[0213] refer to Fig.16 and Fig.17, the second inorganic layer B12 may cover the first fluidization layer S1 and the first inorganic layer B11. For example, the second inorganic layer B12 may extend while completely covering the first fluidization layer S1 and the first inorganic layer B11 without portions that are partially etched or spaced apart from each other. Therefore, the first fluidization layer S1 of each of the display devices 80 and 90 may be completely surrounded by the first inorganic layer B11 and the second inorganic layer B12 in a portion thereof that overlaps with the separation area SA between adjacent embankment structures 160.

[0214] As described above, a relatively large physical step may be formed between the lower portion of the tip TIP of the second bank layer 163 and the side surface 161c of the first bank layer 161. Generally, in the portion where a large step is formed in the display device 80 and the display device 90, the step coverage characteristics of the inorganic film may be deteriorated, and therefore, cracks may be generated in the inorganic film. The cracks generated in the inorganic film as described above may be a penetration path for external oxygen and moisture. Therefore, the display device 80 and the display device 90 include a first fluidization layer S1 having a characteristic of high fluidity, and therefore, the steps of the display device 80 and the display device 90 can be flattened. For this reason, the reliability of the display device 80 and the display device 90 can be improved. As far as the element is not described in detail with respect to the figure, it can be understood that the element is at least similar to the corresponding element that has been described elsewhere in the present disclosure.

[0215] The embodiments of the present disclosure have been described above with reference to the accompanying drawings, but those skilled in the art to which the present disclosure pertains will appreciate that various modifications and changes may be made without departing from the technical spirit or essential features of the present disclosure.

Claims

1. A display device, characterized in that: The display device comprises: a substrate, including an emitting region and a non-emitting region; A first pixel electrode is disposed on the emission area of ​​the substrate; a pixel defining layer, disposed on the non-emitting region of the substrate, the pixel defining layer overlapping the first pixel electrode, and the pixel defining layer defining a first opening; a first bank layer disposed on the pixel defining layer and defining a second opening overlapping the first opening; a second bank layer disposed on the first bank layer and including a protruding tip toward the first opening; A first light emitting layer is disposed on the first pixel electrode and in the first opening; a first common electrode disposed on the first light emitting layer and contacting the first bank layer in the second opening; and a first encapsulation layer, disposed on the first common electrode and the second bank layer; wherein the protruding tip of the second bank layer includes a side surface of the second bank layer that protrudes toward the first opening to a greater extent than a side surface of the first bank layer, The first encapsulation layer includes a first inorganic layer that completely covers the first common electrode and the protruding tip of the second bank layer, and a first fluidization layer disposed on the first inorganic layer. The first fluidized layer includes a first portion disposed on the first common electrode and a second portion disposed on the second bank layer, and Wherein, the first portion and the second portion are spaced apart from each other.

2. The display device according to claim 1, characterized in that The first fluidized layer overlaps the protruding tip of the second bank layer, and The first portion completely covers a portion of the first inorganic layer overlapping the first opening.

3. The display device according to claim 1, characterized in that The display device further includes a first electrode pattern, wherein the first electrode pattern surrounds the first opening on the second bank layer. wherein, in a portion of the first common electrode and the first electrode pattern overlapping the protruding tip of the second bank layer, the first common electrode and the first electrode pattern are spaced apart from each other with a space interposed between the first common electrode and the first electrode pattern, and The first portion is disposed in the space between the first common electrode and the first electrode pattern, The second portion overlaps the first electrode pattern outside the first opening.

4. The display device according to claim 1, characterized in that The first encapsulation layer further includes a second inorganic layer that completely covers the first fluidizing layer and a portion of the first inorganic layer that overlaps the second opening.

5. The display device according to claim 4, characterized in that: The display device further includes an organic encapsulation layer disposed on the first encapsulation layer. Among them, on the side surface of the second bank layer, one surface of the second inorganic layer contacts the first inorganic layer, and on the side surface of the second bank layer, the other surface of the second inorganic layer contacts the organic encapsulation layer.

6. The display device according to claim 5, characterized in that: the first inorganic layer includes a first inclined surface in a portion of the first inorganic layer overlapping an outer portion of the second opening, wherein the first fluidizing layer comprises a second inclined surface in a portion of the first fluidizing layer overlapping the outer portion of the second opening, and wherein the second inorganic layer includes a third inclined surface in a portion of the second inorganic layer overlapping the outer portion of the second opening, and The first inclined surface, the second inclined surface, and the third inclined surface are aligned with each other, wherein the first inclined surface, the second inclined surface, and the third inclined surface are in contact with the organic encapsulation layer.

7. The display device according to claim 4, characterized in that: The first encapsulation layer further comprises: a second fluidized layer disposed on the second inorganic layer to overlap the first opening; a third inorganic layer, completely covering the second fluidized layer; a third fluidizing layer disposed on the third inorganic layer to overlap with the first opening; and The fourth inorganic layer completely covers the third fluidized layer.

8. A display device, characterized in that: The display device comprises: a substrate, including an emitting region and a non-emitting region; A first pixel electrode is disposed on the emission area of ​​the substrate; a pixel defining layer, disposed on the non-emitting region of the substrate, the pixel defining layer overlapping the first pixel electrode, and the pixel defining layer defining a first opening; a first bank layer disposed on the pixel defining layer and defining a second opening overlapping the first opening; a second bank layer disposed on the first bank layer and including a protruding tip toward the first opening; A first light emitting layer is disposed on the first pixel electrode and in the first opening; a first common electrode disposed on the first light emitting layer and contacting the first bank layer in the second opening; and a first encapsulation layer, disposed on the first common electrode and the second bank layer; Wherein, the first encapsulation layer comprises: a first inorganic layer completely covering the first common electrode and the protruding tip of the second bank layer in the second opening; A second inorganic layer is disposed on the first inorganic layer; and a first fluidized layer disposed in the first opening between the first inorganic layer and the second inorganic layer, and The first inorganic layer and the second inorganic layer are in contact with each other in portions of the first inorganic layer and the second inorganic layer overlapping the outside of the second opening.

9. A display device, characterized in that: The display device comprises: a substrate, including an emitting region and a non-emitting region; A light emitting element is disposed on the emission area of ​​the substrate; A first bank structure is disposed on the non-emitting region of the substrate; a second embankment structure spaced apart from the first embankment structure, with a separation area provided between the second embankment structure and the first embankment structure; a first inorganic layer covering the first bank structure and the second bank structure; a first fluidized layer disposed on the first inorganic layer; and a second inorganic layer, disposed on the first fluidized layer, wherein each of the first embankment structure and the second embankment structure comprises a first surface disposed toward the substrate and a second surface opposite to the first surface, wherein the width of the second surface of the first embankment structure is greater than the width of the first surface of the first embankment structure, the width of the second surface of the second embankment structure is greater than the width of the first surface of the second embankment structure, and The first fluidized layer is completely surrounded by the first inorganic layer and the second inorganic layer in a portion of the first fluidized layer overlapping the separation area between the first bank structure and the second bank structure.

10. The display device according to claim 9, characterized in that: The first fluidized layer comprises: a first portion disposed in the separation region between the first bank structure and the second bank structure; and a second portion, disposed on the first embankment structure and the second embankment structure, Wherein, the first portion and the second portion of the first fluidized layer are spaced apart from each other.

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