A large bandwidth signal processing device based on SDR

Abstract

The present application provides a large bandwidth signal processing device based on SDR, belonging to the field of signal technology, wherein the antenna is connected to the data processing board through an SMA interface; the data processing board is connected to the server unit through an optical fiber; the antenna is divided into two groups, one group of antennas is two identical logarithmic periodic antennas; the other group of antennas is two horn antennas with constant gain characteristics; the data processing board includes FPGA and DSP; multiple GTH high-speed interfaces are set between FPGA and DSP; FPGA has built-in ADC input and DAC output; the server unit includes a server, a network card, a CPU and a storage hard disk; the data processing board is connected to the server through an optical fiber; the server has a network card inserted; the network card is connected to the CPU through a PCLe bus; the CPU and the storage hard disk are connected through a PCLe bus. The present application directly implements RF sampling, does not require a down-conversion circuit, and greatly reduces the complexity of the device.

Description

Technical Field

[0001] The present application belongs to the field of signal technology, and more specifically, relates to a large-bandwidth signal processing device based on SDR. Background Art

[0002] In the current complex electromagnetic environment, radar signals often cover multiple frequency bands. In order to detect and sort the signals, the reconnaissance receiver needs a wider frequency band range. Digital channelized reconnaissance receivers have the advantages of wide monitoring band, high sensitivity, large dynamic range and the ability to process multiple simultaneously arriving signals. They are the main research direction of radar reconnaissance receivers today. Digital channelized receivers use the software radio (SDR) idea as the theoretical basis, and rely on a general, standard and modular hardware platform to establish a general and open hardware platform with an "A / D-digital signal processing-D / A" model. On this hardware platform, software technology is used as much as possible to realize various functional modules of the radio, such as using a wideband ADC to directly collect RF data and separating channels through programmable digital filters; using a digital signal processor to select the signal frequency band through software programming; and realizing various parameter analysis of the signal through software programming, such as time domain parameters, frequency domain parameters and spatial angles; therefore, there are various functional modules of the radio that are overly dependent on the hardware platform, making the hardware platform more complex. Utility Model Content

[0003] In view of the defects of the prior art, the purpose of this application is to provide a large-bandwidth signal processing device based on SDR, aiming to solve the problem that when the existing digital channelized receiver adopts the software radio method, software technology is usually used to implement various functional modules of the radio station, and there is an excessive reliance on the hardware platform to implement the software functional modules, resulting in a high complexity of the hardware platform.

[0004] To achieve the above object, a large bandwidth signal processing device based on SDR includes: an antenna and a data processing board;

[0005] The antenna is connected to the data processing board via an SMA interface;

[0006] The antennas are divided into two groups, one group of antennas is two identical logarithmic periodic antennas; the other group of antennas is two horn antennas with constant gain characteristics, and the gain of all signals within the frequency band is basically the same;

[0007] The data processing board includes FPGA and DSP; multiple GTH high-speed interfaces are provided between the FPGA and the DSP; the FPGA has a built-in n ADC input and n DAC output; among them, n ≥2.

[0008] Further preferably, the SDR-based large bandwidth signal processing device further includes: a server unit;

[0009] The server unit includes a server, a network card, a CPU and a storage hard disk; the data processing board is connected to the server through an optical fiber; the server is equipped with a network card; the network card is connected to the CPU through a PCLe bus; the CPU and the storage hard disk are connected through a PCLe bus.

[0010] Further preferably, the integrated line of the log-periodic antenna presents a preset angle; and the horn antenna is a rectangular horn antenna.

[0011] Further preferably, the PL side of the FPGA is externally connected to a 2GB DDR4 memory chip, and the PS side is externally connected to a 2GB DDR4 memory chip.

[0012] Further preferably, the JTAG debugging interface of the DSP is connected to two onboard connectors, one onboard connector is used to debug the FPGA, and the other onboard connector is used to debug the DSP.

[0013] Further preferably, the DSP is provided with a memory system including 4 DDR3s;

[0014] Further preferably, the JTAG debugging interface of the FPGA is connected to two onboard connectors, one onboard connector is used to debug the FPGA, and the other onboard connector is used to debug the DSP.

[0015] Further preferably, the storage hard disk is a disk array or a high-speed NVMe solid-state drive.

[0016] Further preferably, the FPGA is based on RFSoC radio frequency FPGA.

[0017] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0018] The present application provides a large-bandwidth signal processing device based on SDR, wherein antennas are divided into two groups, one group of antennas is two identical logarithmic periodic antennas; the other group of antennas is horn antennas; the logarithmic periodic antennas cover signal sampling in the frequency range of 0.3GHz to 2GHz, and the horn antennas cover signal sampling in the frequency range of 2GHz to 6GHz, which can realize reconnaissance and reception of multiple radar signals arriving simultaneously within an instantaneous bandwidth of 1GHz, and does not require RF frequency conversion circuits, thereby greatly reducing the complexity of the device.

[0019] The present application provides a large-bandwidth signal processing device based on SDR, wherein a data processing board includes an FPGA and a DSP, wherein the FPGA has built-in 4-channel analog-to-digital converters and 4-channel digital-to-analog converters, the ADC sampling rate can reach 4.096GSPS, the transient bandwidth can reach 1 GHz, and the frequency covers a frequency range of 300MHz-6GHz; the maximum rate of the DAC can reach 6.554GSPS; the FPGA, as a main controller, can realize multi-receive and multi-transmit signal transmission, acquisition and control; and the DSP can greatly improve the data processing capability, can perform frequency domain division on the wide-band digital signal after AD conversion, and convert high-rate data into multiple low-rate data. At the same time, radar signal detection, pulse descriptor word measurement (PDW), etc. can be programmed in the FPGA, and data can be transmitted to the radar intelligent reconnaissance system in real time, greatly improving the efficiency of data processing.

[0020] The present application provides a high-bandwidth signal processing device based on SDR, wherein the server unit mainly includes a server, a 10G network card, a CPU, and a storage hard disk. After data acquisition, preprocessing, and data processing, the data is sent from the data acquisition and signal processing board to the server via optical fiber. The server is equipped with a 10G network card, and the data is transmitted from the optical fiber to the memory via PCIe. Subsequent signal processing is performed in the server, and the data is stored via PCIe to the hard disk. This type of pipeline design method can effectively avoid data blocking, maximize the use of the server data transmission link, and achieve effective data transmission.

[0021] The present application provides a high-bandwidth signal processing device based on SDR, wherein when the storage hard disk is a disk array, since the disk array is a storage system composed of multiple physical hard disks, they integrate these hard disks together through a specific controller and storage management technology to form a logical single storage unit; the disk array can provide higher data throughput, better fault tolerance and larger storage capacity; the disk array usually adopts RAID (Redundant Array of Independent Disks) technology to manage data storage and redundancy; RAID technology distributes data on multiple hard disks, and realizes data redundancy and dispersed storage through methods such as data striping and redundancy checking; this can improve data reading and writing performance, and provide fault tolerance, that is, when a hard disk fails, the disk array can still maintain data integrity and accessibility.

[0022] The present application provides a high-bandwidth signal processing device based on SDR, wherein when the storage hard disk is a high-speed NVMe solid-state hard disk, the NVMe solid-state hard disk is a high-performance, NUMA (non-uniform memory access) optimized, highly scalable storage protocol for connecting a host and a memory subsystem; the NVMe solid-state hard disk is specially designed for non-volatile storage such as NAND and flash memory, and its protocol is built on a high-speed PCIe channel; the NVMe solid-state hard disk maps I / O commands and responses to the shared memory of the host through a PCIe interface; the interface supports parallel I / O of multi-core processors to promote high throughput and relieve CPU pressure; at the same time, compared with SCSI and ATA command sets, NVMe solid-state hard disks provide a more simplified command set to process I / O requests; compared with the former two, NVMe solid-state hard disks require half the number of CPU instructions, achieving lower latency data reading and writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of a large bandwidth signal processing device based on SDR provided in an embodiment of the present application;

[0024] Figure 2 is a schematic diagram of a log-periodic antenna provided in an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of a horn antenna provided in an embodiment of the present application;

[0026] Figure 4 It is a schematic diagram of a data processing board provided in an embodiment of the present application;

[0027] Figure 5 is a schematic diagram of a server unit provided in an embodiment of the present application;

[0028] Figure 6 This is a flow chart of SDR large bandwidth signal processing provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] For ease of understanding, the English abbreviations and related technical terms involved in the embodiments of the present application are explained and described below.

[0030] SDR: Software Defined Radio; FPGA: Field Programmable Gate Array;

[0031] SMA interface: Smail A Type interface; DSP: microprocessor;

[0032] PS side: processing system, ARM core; PL side: FPGA core;

[0033] DDR: Double Data Rate; JTAG: Joint Test Action Group;

[0034] CPU: Central Processing Unit;

[0035] TCP protocol: Transmission Control Protocol, transmission control protocol.

[0036] NVMe: NonVolatile Memory express.

[0037] The present application provides a large-bandwidth signal processing device based on SDR, which can meet the needs of direct sampling of signals in the frequency range of 0.3GHz-6GHz, does not require RF or lower frequency conversion circuits, greatly reduces the complexity of the device, and can realize the reconnaissance and reception of multiple radar signals arriving simultaneously within an instantaneous bandwidth of 1GHz. The large-bandwidth data is divided into frequency domains through digital channelization processing on FPGA, and high-rate data is converted into multiple low-rate data. Radar signal detection, pulse descriptor word measurement, etc. are programmed in FPGA, and the data is transmitted to the radar intelligent reconnaissance system in real time, finally realizing the evaluation and analysis of the intelligent reconnaissance algorithm verification test set, providing comprehensive and accurate technical support for subsequent practical applications.

[0038] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0039] like Figure 1 As shown, the present application provides a large bandwidth signal processing device based on SDR, including: an antenna, a data processing board, a server unit and a display;

[0040] The antenna is connected to the data processing board through an SMA interface (Smail A Type interface); the data processing board is connected to the server unit through an optical fiber; the server unit is connected to the display;

[0041] (1) The antennas are divided into two groups, such as Figure 2 As shown, the first group of antennas are two identical logarithmic periodic antennas, covering 0.3GHz~2GHz, such as Figure 3 As shown, the second group of antennas are horn antennas, covering 2GHz~6 GHz; the integrated line of the logarithmic periodic antenna presents a certain angle to improve the antenna gain; the standing wave of the logarithmic periodic antenna in the whole frequency band is less than 2, and the antenna gain is greater than 6dB; the horn antenna is preferably a rectangular horn with high aperture efficiency, which can ensure that the gain meets the requirements; the horn antenna can meet the requirement of less than 2.0 at the required frequency point and has good standing wave characteristics;

[0042] (2) If Figure 4As shown, the data processing board includes FPGA and DSP; FPGA uses RFSoC-based radio frequency FPGA as the main controller to realize 4-receive 4-transmit signal transmission, collection and control; DSP can greatly improve data processing capabilities;

[0043] Among them, the RFSoC chip in the FPGA has built-in 4-channel ADC (analog-to-digital converter) and 4-channel DAC (digital-to-analog converter); the ADC sampling rate can reach 4.096GSPS, the instantaneous bandwidth can reach 1GHz, and the frequency covers the frequency range of 300MHz-6GHz; the maximum rate of the DAC can reach 6.554GSPS; the DSP chip is mounted on the FPGA; therefore, the data processing board has the function of collecting broadband RF signals and signal preprocessing, as well as signal processing;

[0044] Further preferably, the PL side of the FPGA of the data processing board is externally connected with a 2GB DDR4 memory chip, and the PS side is externally connected with a 2GB DDR4 memory chip, so as to meet the requirement that the maximum radiation source data that can be stored is not less than 100ms;

[0045] Further preferably, the JTAG debugging interface (Joint Test Action Group) of the DSP converts the signal from 1.87V to 3.3V level through level conversion, and leads it to the onboard connector J35, through which the FPGA can be debugged. At the same time, the JTAG debugging signal is led to the external connector J2, and the DSP can be debugged through the docking connection line;

[0046] Further preferably, the DSP provides a 512MB, 64-bit wide memory system, including 4 DDR3s; the 4 DDR3s are directly connected to the DDR3 controller;

[0047] Further preferably, there are 4 GTH high-speed interfaces between the DSP and the FPGA for data communication;

[0048] Further preferably, the JTAG debugging interface of the FPGA converts the signal from 1.8V to 3.3V level through level conversion and leads it to the onboard connector J8; the FPGA can be debugged through this connector; at the same time, the JTAG debugging signal is led to the external connector J2, and the DSP can be debugged through the docking connection line;

[0049] Further preferably, a 4GB, 64-bit wide memory system is set on the PS side of the FPGA, consisting of four 512 Mb*16DDR4s; the memory system is connected to the hard-core storage controller on the PS side;

[0050] Further preferably, a 2GB, 32-bit wide memory system is set on the PL side of the FPGA, consisting of two 512Mb*16DDR4;

[0051] Further preferably, the PS-side Gigabit Ethernet MAC (GEM) of the FPGA can implement a 10 / 100 / 1000 Mb / s Ethernet interface;

[0052] Further preferably, the FPGA supports 4-channel 12-bit ADC 4.096 GSPS input and 4-channel 14-bit DAC 6.4 GSPS output;

[0053] (3) If Figure 5 As shown, the server unit includes a server, a 10G network card, a CPU and a storage hard disk; after being processed by the data processing board, the data is sent from the data processing board to the server through an optical fiber, the server is equipped with a 10G network card, and the data is transmitted from the optical fiber to the memory CPU via the PCIe bus, and subsequent signal processing is performed in the server, while the data is stored in the hard disk via the PCIe bus; this type of pipeline design method can effectively avoid data blocking, maximize the use of the server data transmission link, and realize effective data transmission;

[0054] It should be pointed out here that considering that the server unit needs to meet the three parts of data transmission, data storage and data processing, there must be enough interfaces to meet the needs of high-speed peripheral data transmission to avoid data blocking caused by bus occupation. Therefore, when selecting a server, it is necessary to meet the needs of multiple PCIe buses;

[0055] Further preferably, the data processing board uses optical fiber to send high data rate data through the optical port network card to the server memory for intelligent signal sorting and other processing. Generally, the optical port rates used are mainly 40Gb, 56Gb and 100Gb three high-speed interfaces; due to the high data rate, the design should leave a certain margin. This application uses a 100Gb optical fiber network card for data transmission;

[0056] It should be pointed out here that the PCIe interface is a high-speed serial point-to-point high-bandwidth transmission with the characteristics of high data transmission rate and strong scalability.

[0057] Further preferably, the storage hard disk may be a disk array or a high-speed NVMe solid-state hard disk storage unit;

[0058] like Figure 6 As shown, the SDR-based large bandwidth signal processing device provided by the present application involves the following parts of data processing, including signal channelization reception, pulse description word measurement, data transmission and data storage;

[0059] Among them, FPGA is used for signal channelization reception and pulse description word measurement. It is responsible for completing the digital channel reception of bandwidth signals, acquiring the characteristic parameters between radar signal pulses, and generating PDW.

[0060] The specific process of data transmission and data storage is as follows: first, the TCP protocol is used to send the original radar data from the FPGA end to the memory CPU of the server unit via the optical fiber transmission medium and PCIe serial longitudinally. The memory CPU performs real-time storage and forwarding of data. The real-time storage medium is a PCIe solid-state drive that supports the NVMe protocol. The data is forwarded to the coprocessor end, that is, the GPU data processing unit. The GPU is responsible for subsequent intelligent sorting and recognition, working mode recognition, intention reasoning and other reconnaissance processing.

[0061] Among them, signal channelization reception is to divide the wide-band digital signal after AD conversion in FPGA into channels to reduce the data rate, and change the wide-band high-speed serial data into narrow-band parallel multi-channel low-speed data;

[0062] Pulse description word measurement is to realize signal detection and extract signal pulse description words, including signal frequency, signal pulse width, signal pulse repetition period and signal arrival time;

[0063] Data transmission is used to send the detected pulse description word to the host computer. Data transmission is based on TCP / IP network transmission protocol and is developed based on high-performance C language.

[0064] Data storage is used to implement pulse description word storage. This module implements parallel data storage based on C++ multi-threading technology.

[0065] In summary, the present application has the following advantages compared with the prior art:

[0066] The present application provides a large-bandwidth signal processing device based on SDR, wherein antennas are divided into two groups, one group of antennas is two identical logarithmic periodic antennas; the other group of antennas is horn antennas; the logarithmic periodic antennas cover signal sampling in the frequency range of 0.3GHz to 2GHz, and the horn antennas cover signal sampling in the frequency range of 2GHz to 6GHz, which can realize reconnaissance and reception of multiple radar signals arriving simultaneously within an instantaneous bandwidth of 1GHz, and does not require RF frequency conversion circuits, thereby greatly reducing the complexity of the device.

[0067] The present application provides a large-bandwidth signal processing device based on SDR, wherein a data processing board includes an FPGA and a DSP, wherein the FPGA has built-in 4-channel analog-to-digital converters and 4-channel digital-to-analog converters, the ADC sampling rate can reach 4.096GSPS, the transient bandwidth can reach 1 GHz, and the frequency covers a frequency range of 300MHz-6GHz; the maximum rate of the DAC can reach 6.554GSPS; the FPGA, as a main controller, can realize multi-receive and multi-transmit signal transmission, acquisition and control; and the DSP can greatly improve the data processing capability, can perform frequency domain division on the wide-band digital signal after AD conversion, and convert high-rate data into multiple low-rate data. At the same time, radar signal detection, pulse descriptor word measurement (PDW), etc. can be programmed in the FPGA, and data can be transmitted to the radar intelligent reconnaissance system in real time, greatly improving the efficiency of data processing.

[0068] The present application provides a high-bandwidth signal processing device based on SDR, wherein the server unit mainly includes a server, a 10G network card, a CPU, and a storage hard disk. After data acquisition, preprocessing, and data processing, the data is sent from the data acquisition and signal processing board to the server via optical fiber. The server is equipped with a 10G network card, and the data is transmitted from the optical fiber to the memory via PCIe. Subsequent signal processing is performed in the server, and the data is stored via PCIe to the hard disk. This type of pipeline design method can effectively avoid data blocking, maximize the use of the server data transmission link, and achieve effective data transmission.

[0069] The present application provides a high-bandwidth signal processing device based on SDR, wherein when the storage hard disk is a disk array, since the disk array is a storage system composed of multiple physical hard disks, they integrate these hard disks together through a specific controller and storage management technology to form a logical single storage unit; the disk array can provide higher data throughput, better fault tolerance and larger storage capacity; the disk array usually adopts RAID (Redundant Array of Independent Disks) technology to manage data storage and redundancy; RAID technology distributes data on multiple hard disks, and realizes data redundancy and dispersed storage through methods such as data striping and redundancy checking; this can improve data reading and writing performance, and provide fault tolerance, that is, when a hard disk fails, the disk array can still maintain data integrity and accessibility.

[0070] The present application provides a high-bandwidth signal processing device based on SDR, wherein, when the storage hard disk is a high-speed NVMe solid-state hard disk, the NVMe solid-state hard disk is a high-performance, NUMA (non-uniform memory access) optimized, highly scalable storage protocol for connecting a host and a memory subsystem; NVMe is specially designed for non-volatile storage such as NAND and flash memory, and its protocol is built on a high-speed PCIe channel; NVMe maps I / O commands and responses to the shared memory of the host through a PCIe interface; the interface supports parallel I / O of multi-core processors to promote high throughput and relieve CPU pressure; at the same time, compared with SCSI and ATA command sets, NVMe provides a more simplified command set to process I / O requests; compared with the former two, NVMe requires half the number of CPU instructions, achieving lower latency data reading and writing.

[0071] It should be understood that expressions such as “include” and “may include” used in the present application indicate the existence of disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements.

[0072] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0073] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A large bandwidth signal processing device based on SDR, characterized in that: include: Antenna and data processing board; The antenna is connected to the data processing board via an SMA interface; The antennas are divided into two groups, one group of antennas is two identical log-periodic antennas; The other set of antennas is two horn antennas with constant gain characteristics; The data processing board includes FPGA and DSP; multiple GTH high-speed interfaces are provided between the FPGA and the DSP; the FPGA has a built-in n ADC input and n DAC output; among them, n ≥2.

2. The SDR-based large bandwidth signal processing device according to claim 1, characterized in that: Also includes: Server unit; The server unit includes a server, a network card, a CPU and a storage hard disk; The data processing board is connected to the server via an optical fiber; a network card is inserted into the server; The network card is connected to the CPU through the PCLe bus; the CPU and the storage hard disk are connected through the PCLe bus.

3. The SDR-based large bandwidth signal processing device according to claim 1, characterized in that: The integrated line of the log-periodic antenna presents a preset angle; the horn antenna is a rectangular horn antenna.

4. The SDR-based large bandwidth signal processing device according to any one of claims 1 to 3, characterized in that: The PL side of the FPGA is equipped with a 2GB DDR4 memory chip, and the PS side is equipped with a 2GB DDR4 memory chip.

5. The SDR-based large bandwidth signal processing device according to any one of claims 1 to 3, characterized in that: The JTAG debugging interface of the DSP is connected to two onboard connectors, one onboard connector is used to debug the FPGA, and the other onboard connector is used to debug the DSP.

6. The SDR-based large bandwidth signal processing device according to any one of claims 1 to 3, characterized in that: The DSP is provided with a memory system including 4 DDR3s.

7. The SDR-based large bandwidth signal processing device according to claim 5, characterized in that: The FPGA's JTAG debugging interface connects two onboard connectors, one onboard connector is used to debug the FPGA, and the other onboard connector is used to debug the DSP.

8. The SDR-based large bandwidth signal processing device according to claim 2, characterized in that: The storage hard disk is a disk array or a high-speed NVMe solid-state hard disk.

9. The SDR-based large bandwidth signal processing device according to any one of claims 1 to 3, characterized in that: The FPGA is based on RFSoC radio frequency FPGA.

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