A VBO signal to eDP signal module and display device

Abstract

The utility model discloses a VBO signal to eDP signal module and a display device, the module comprising: a first connector, on which a VBO interface is provided, for receiving a VBO signal and outputting it through a VBO signal group; a conversion circuit, comprising a signal input end and a signal output end, the signal input end is connected to the VBO signal group, for receiving the VBO signal outputted by the first connector, and converting it into an eDP signal output; a second connector, which is connected to the signal output end of the conversion circuit through the eDP signal group, for receiving the converted eDP signal, and outputting it through the eDP interface; a power supply circuit, which is respectively connected to the first connector, the conversion circuit and the second connector for power supply. The utility model realizes the stable and reliable conversion of VBO signals to eDP signals, and provides strong technical support for the adaptive connection between the driver board or the module interface and the display screen.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to a VBO signal to eDP signal module and a display device. Background Art

[0002] Display screens are used in display systems such as computers, TVs, surveillance and naked-eye 3D. Currently, commonly used interface types for display screens include eDP, VBO and LVDS. If the interface type of the driver board or module connected to the display screen is inconsistent with the interface type of the display screen, it cannot be adapted. Therefore, in this case, the driver board or module interface needs to be converted to ensure that it is consistent with the interface type of the display screen.

[0003] The eDP interface is a fully digital interface based on the DisplayPort architecture and protocol. It can transmit high-resolution signals with simpler connectors and fewer pins, and can achieve simultaneous transmission of multiple data at a much higher transmission rate than LVDS. VBO is a digital interface standard developed specifically for image transmission. Compared with LVDS, it has advantages such as high speed, low power consumption, low EMI, and support for clock alignment. Therefore, both are mostly used in high-definition LCD screens. However, there is currently no stable, reliable, and standard adapter module to achieve the conversion of VBO signals to eDP signals, so it is difficult to ensure the adaptive connection between the driver board or module interface and the display. Summary of the invention

[0004] Purpose of the invention: In view of the above-mentioned deficiencies, the utility model provides a VBO signal to eDP signal module and a display device, which are used to achieve stable and reliable conversion of VBO signals to eDP signals, and provide technical support for the adaptive connection between the driver board or module interface and the display screen.

[0005] Technical solution: The utility model provides a VBO signal to eDP signal module, including:

[0006] A first connector, on which a VBO interface is provided, for receiving a VBO signal and outputting it through a VBO signal group;

[0007] A conversion circuit, comprising a signal input terminal and a signal output terminal, wherein the signal input terminal is connected to the VBO signal group, and is used to receive the VBO signal output by the first connector, and convert it into an eDP signal output;

[0008] A second connector, which is connected to the signal output end of the conversion circuit through the eDP signal group, is used to receive the converted eDP signal and output it through the eDP interface;

[0009] The power supply circuit is respectively connected to the first connector, the conversion circuit and the second connector for power supply.

[0010] Specifically, the VBO signal group includes a first hot plug signal, a first lock signal and a first differential signal, the eDP signal group includes a second hot plug signal, a second auxiliary signal and a second differential signal, and the corresponding relationship between the first differential signal and the second differential signal is specifically:

[0011] If the first differential signal uses 1lane or 2lanes data signal, the second differential signal uses 1lane data signal; if the first differential signal uses 2N lanes data signal, the second differential signal uses N lanes data signal, where N=2,4, and each lane data signal is a differential signal.

[0012] More specifically, the conversion circuit includes a conversion chip, wherein the HTPDN, LOCKN, and EDPX pins of the conversion chip are respectively used to access the first hot plug signal, the first lock signal, and the first differential signal, thereby forming a signal input end; the HPD, AUX, and DPX pins are respectively used to access the second hot plug signal, the second auxiliary signal, and the second differential signal, thereby forming a signal output end.

[0013] Specifically, the power supply circuit includes a first voltage input terminal, a first voltage output terminal, and a second voltage output terminal, and is used to step down the DC voltage connected to the first voltage input terminal to 3.3V and 1.2V voltages and output them through the first voltage output terminal and the second voltage output terminal respectively;

[0014] The conversion circuit comprises a third voltage input terminal and a fourth voltage input terminal, wherein the third voltage input terminal is connected to the first voltage output terminal, the fourth voltage input terminal is connected to the second voltage output terminal, and the first voltage input terminal is connected to the first connector and the second connector.

[0015] More specifically, the power supply circuit includes:

[0016] A first step-down circuit, comprising a first voltage input terminal and a first voltage output terminal, for stepping down a DC voltage connected to the first voltage input terminal to 3.3V and then outputting the voltage through the first voltage output terminal;

[0017] The second step-down circuit includes a second voltage input terminal and a second voltage output terminal, wherein the second voltage input terminal is connected to the first voltage output terminal and is used to step down the 3.3V voltage outputted from the first voltage output terminal to 1.2V and then output it through the second voltage output terminal.

[0018] More specifically, the first buck circuit includes a first buck chip, wherein the VIN pin of the first buck chip is a first voltage input terminal, which is grounded through a first capacitor, and the VIN pin is connected to the EN pin through a first resistor, and the EN pin is grounded through a second resistor; the FB pin is connected to the first voltage output terminal through a third resistor and a fourth resistor connected in series, and the FB pin is grounded through a fifth resistor, and the first voltage output terminal is grounded through a third capacitor and a fourth capacitor connected in parallel; in addition, the BST pin is connected to the SW pin through a second capacitor, the SW pin is connected to the first voltage output terminal through a first inductor, and the GND and EPAD pins are grounded.

[0019] More specifically, the second buck circuit includes a second buck chip, wherein the VIN pin of the second buck chip is the second voltage input terminal, which is grounded through a fifth capacitor and a sixth capacitor connected in parallel; the EN pin is connected to the VIN pin through a sixth resistor, and is grounded through a seventh capacitor; the FB pin is connected to the second voltage output terminal through an eighth capacitor and a seventh resistor connected in parallel, and is grounded through an eighth resistor; the second voltage output terminal is grounded through a ninth capacitor and a tenth capacitor connected in parallel; in addition, the LX pin is connected to the second voltage output terminal through a second inductor, and the GND pin is grounded.

[0020] More specifically, the power supply circuit adopts a PMIC circuit.

[0021] More specifically, the conversion circuit includes a conversion chip, wherein two VCC33 pins of the conversion chip are connected to the first voltage output terminal through a first magnetic bead and are grounded through an eleventh capacitor; four VCCA33 pins are connected to the first voltage output terminal through a second magnetic bead and are grounded through a twelfth capacitor; one VTERM_EDPTX pin is connected to the first voltage output terminal through a third magnetic bead and is grounded through a thirteenth capacitor; one VCCA12 pin is connected to the second voltage output terminal through a fourth magnetic bead and is grounded through a fourteenth capacitor; two VCC12_TX pins are connected to the second voltage output terminal through a fifth magnetic bead and are grounded through a fifteenth capacitor; four VDD12 pins are connected to the second voltage output terminal through a sixth magnetic bead and are grounded through a sixteenth capacitor; four VCC12_RX pins are connected to the second voltage output terminal through a seventh magnetic bead and are grounded through a seventeenth capacitor; one VCCA12_B pin is connected to the second voltage output terminal through an eighth magnetic bead and is grounded through an eighteenth capacitor, wherein the first to eighth magnetic beads have the same specifications, and the eleventh to eighteenth capacitors are respectively connected in parallel with filter capacitors of the same number as the pins connected thereto.

[0022] The utility model also provides a display device, comprising: a driving board and a display panel; the driving board is connected to the display panel via any one of the above-mentioned VBO signal to eDP signal modules.

[0023] Beneficial effects: The utility model forms a stable, reliable and standard adapter module through the first connector, the conversion circuit and the second connector, realizes the stable and reliable conversion of the VBO signal to the eDP signal, and provides strong technical support for the adaptive connection between the driver board or the module interface and the display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a principle block diagram of a VBO signal to eDP signal module in one embodiment of the utility model;

[0025] Figure 2 This is a principle block diagram of a VBO signal to eDP signal module in another embodiment of the present invention;

[0026] Figure 3 This is a connection signal block diagram of a conversion circuit in one embodiment of the utility model;

[0027] Figure 4 This is a connection signal block diagram of a conversion circuit in another embodiment of the utility model;

[0028] Figure 5 This is a circuit structure diagram of a conversion circuit in one embodiment of the utility model;

[0029] Figure 6 This is a circuit structure diagram of a first step-down circuit in an embodiment of the utility model;

[0030] Figure 7 This is a circuit structure diagram of a second step-down circuit in an embodiment of the utility model;

[0031] Figure 8 This is an application scenario diagram of a VBO signal to eDP signal module in one embodiment of the present utility model. DETAILED DESCRIPTION

[0032] In order to make the purpose, features and advantages of the utility model more obvious and easy to understand, the technical solutions in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of them. Based on the embodiments of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0033] Reference Figure 1 , Figure 2The utility model provides a VBO signal to eDP signal module, which includes a first connector (i.e., connector 1 in the figure), a conversion circuit and a second connector (i.e., connector 2 in the figure) connected in sequence, and also includes a power supply circuit, which is respectively connected to the first connector, the conversion circuit and the second connector for power supply.

[0034] Specifically, the first connector is provided with a VBO interface for receiving a VBO signal sent by a front-end device such as a driver board, and outputting the signal to the conversion circuit through a VBO signal group; the VBO signal is converted into an eDP signal after passing through the conversion circuit, and then output to the second connector through an eDP signal group; the second connector is provided with an eDP interface for outputting the converted eDP signal. More specifically, the conversion circuit includes a signal input terminal IN5 and a signal output terminal Out3, the signal input terminal IN5 is connected to the first connector through a VBO signal group, and is used to receive a VBO signal sent by a front-end device such as a processor; the signal output terminal Out3 is connected to the second connector through an eDP signal group, and is used to output the converted eDP signal.

[0035] Reference Figure 3 , Figure 4 , the VBO signal group includes a first hot plug signal HPDN, a first lock signal LOCKN and a first differential signal main Link1, wherein the first hot plug signal HPDN and the first lock signal LOCKN are control signals for controlling the data transmission state, and the first differential signal main Link1 is a data signal for realizing data transmission. Specifically, the eDP signal group includes a second hot plug signal HPD, a second auxiliary signal AUX, and a second differential signal main Link2, wherein the second hot plug signal HPD is a unidirectional channel for detecting the hot plug state and then controlling the signal on and off; the second auxiliary signal AUX is an independent bidirectional half-duplex channel for transmitting configuration parameters and commands; the second differential signal main Link2 is the main channel for realizing data transmission.

[0036] More specifically, the corresponding relationship between the first differential signal and the second differential signal is as follows: if the first differential signal main Link1 uses 1lane or 2lanes data signal, the second differential signal main Link2 uses 1lane data signal; if the first differential signal main Link1 uses 2N lanes data signal, the second differential signal main Link2 uses Nlanes data signal, where N = 2, 4, and each lane data signal is a differential signal. In addition, the second auxiliary signal AUX is also a pair of differential signals, namely, signals DP_AUX+ and DP_AUX-, with a rate of up to 1Mbps.

[0037] For example, refer to Figure 3The first differential signal main Link1 uses 8 lanes of data signals, namely RX_0-, RX_0+, RX_1-, RX_1+, RX_2-, RX_2+, RX_3-, RX_3+, RX_4-, RX_4+, RX_5-, RX_5+, RX_6-, RX_6+, RX_7-, RX_7+, each lane uses a pair of differential signal lines, and the input data rate can reach up to 3.75Gbps. Correspondingly, the second differential signal main Link2 uses 4 lanes of data signals, namely DP_RX_0-, DP_RX_0+, DP_RX_1-, DP_RX_1+, DP_RX_2-, DP_RX_2+, DP_RX_3-, DP_RX_3+, each lane uses a pair of differential signal lines, and the output data rate can reach up to 5.4Gbps. The solution supports video signals with up to 4K resolution, 60Hz refresh rate, and 24bpp color depth, and can be applied to naked-eye 3D display systems or other display systems.

[0038] As another example, refer to Figure 4 , the first differential signal main Link1 adopts 4lanes data signal, namely RX_0-, RX_0+, RX_1-, RX_1+, RX_2-, RX_2+, RX_3-, RX_3+; the corresponding second differential signal main Link2 adopts 2lanes data signal, namely DP_RX_0-, DP_RX_0+, DP_RX_1-, DP_RX_1+. This solution is suitable for video signals with 2K resolution, 60Hz refresh rate, 24bpp color depth, or scenarios with video signals of the same data volume. In addition, according to the video signals with different data volumes, the first differential signal main Link1 can also use 1lane or 2lanes data input, and the corresponding second differential signal main Link2 uses 1lane data output.

[0039] For example, refer to Figure 5The core part of the conversion circuit adopts a conversion chip of model LT87121, wherein the HTPDN and LOCKN pins (i.e., pins 13 and 14) of the conversion chip are used to access the first hot plug signal HPDN and the first lock signal LOCKN, and the EDPX pins (i.e., pins 53, 54, 56, 57, 59, 60, 62, 63, 2, 3, 5, 6, 8, 9, 11, 12) are used to access the first differential signals RX_0-, RX_0+, RX_1-, RX_1+, RX_2-, RX_2+, RX_3-, RX_3+, RX_4-, RX_4+, RX_5-, RX_5+, RX_ 6-, RX_6+, RX_7-, RX_7+, HPD, AUX pins (i.e. pins 30, 31, 32) are used to access the second hot plug signal HPD and the second auxiliary signal DP_AUX+, DP_AUX-, DPX pins (i.e. pins 44, 43, 41, 40, 38, 37, 35, 34) are used to access the second differential signal DP_RX_0-, DP_RX_0+, DP_RX_1-, DP_RX_1+, DP_RX_2-, DP_RX_2+, DP_RX_3-, DP_RX_3+ (here taking 8lanes data input and 4lanes data output as an example).

[0040] Specifically, the power supply circuit includes a first voltage input terminal IN1, a first voltage output terminal Out1 and a second voltage output terminal Out2, wherein the first voltage input terminal IN1 is used to access a DC voltage, specifically, the DC voltage can be a common screen power supply voltage in the range of 5V-12V, and after the DC voltage is stepped down by the power supply circuit, a 3.3V voltage is output through the first voltage output terminal Out1, and a 1.2V voltage is output through the second voltage output terminal Out2; correspondingly, the conversion circuit includes a third voltage input terminal IN3 and a fourth voltage input terminal IN4, wherein the third voltage input terminal IN3 is connected to the first voltage output terminal Out1, and the fourth voltage input terminal IN4 is connected to the second voltage output terminal Out2, thereby realizing the power supply of the conversion circuit. In addition, the first voltage input terminal IN1 is respectively connected to the first connector and the second connector for power supply through a DC voltage signal line.

[0041] For example, refer to Figure 1The power supply circuit includes a first step-down circuit (i.e., DCDC circuit 1 in the figure) and a second step-down circuit (i.e., DCDC circuit 2 in the figure), wherein the first step-down circuit includes a first voltage input terminal IN1 and a first voltage output terminal Out1, and is used to step down the DC voltage connected to the first voltage input terminal IN1 to 3.3V and then output it from the first voltage output terminal Out1; the second step-down circuit includes a second voltage input terminal IN2 and a second voltage output terminal Out2, and the second voltage input terminal IN2 is connected to the first voltage output terminal Out1, and is used to step down the 3.3V voltage connected to the second voltage input terminal IN2 to 1.2V and then output it from the second voltage output terminal Out2. As a commonly used DC power conversion circuit, the DCDC circuit has the characteristics of high efficiency, stable voltage, and low cost.

[0042] Reference Figure 6 The first buck circuit includes a first buck chip, wherein the first buck chip adopts a chip model LC2632C (or other chips with the same package and performance, such as chip MT2499A and XL1410E1, etc.), and its VIN pin (i.e. pin 2) is the first voltage input terminal IN1, thereby connecting to a 12V DC voltage and grounding through a first capacitor C28; the VIN pin is connected to an EN pin (i.e. pin 7) through a first resistor R12, and the EN pin is grounded through a second resistor R15; the FB pin (i.e. pin 5) is connected to a first voltage output terminal Out1 through a third resistor R14 and a fourth resistor R13 connected in series, thereby outputting a 3.3V voltage, and the FB pin is grounded through a fifth resistor R16, and the first voltage output terminal Out1 is grounded through a third capacitor C30 and a fourth capacitor C31 connected in parallel. In addition, the BST pin (ie, pin 1) is connected to the SW pin (ie, pin 3) through the second capacitor C27, the SW pin is connected to the first voltage output terminal Out1 through the first inductor L23, and the GND and EPAD pins (ie, pins 4 and 9) are grounded.

[0043] Reference Figure 7, the second buck circuit includes a second buck chip, wherein the second buck chip adopts a chip of model SY8089 (or other chips with the same package and performance, such as chip TLV62569DBV and MT3520B, etc.), and its VIN pin (i.e. pin 4) is the second voltage input terminal IN2, thereby connecting to a 3.3V voltage, and at the same time grounding through the fifth capacitor C133 and the sixth capacitor C134 connected in parallel; the EN pin (i.e. pin 1) is connected to the VIN pin through the sixth resistor R124, and at the same time grounding through the seventh capacitor C124; the FB pin (i.e. pin 5) is connected to the second voltage output terminal Out2 through the eighth capacitor C125 and the seventh resistor R126 connected in parallel, thereby outputting a 1.2V voltage, and at the same time grounding through the eighth resistor R127; the second voltage output terminal Out2 is grounded through the ninth capacitor C127 and the tenth capacitor C129 connected in parallel. In addition, the LX pin (i.e. pin 3) is connected to the second voltage output terminal Out2 through the second inductor L24, and the GND pin (i.e. pin 2) is grounded.

[0044] As another example, refer to Figure 2 , the power supply circuit includes a power management circuit (i.e., the PMIC circuit in the figure), and the power management circuit includes a first voltage input terminal IN1, a first voltage output terminal Out1, and a second voltage output terminal Out2, which can directly step down the DC voltage connected to the first voltage input terminal IN1 to 3.3V and 1.2V, and then output them through the first voltage output terminal Out1 and the second voltage output terminal Out2 respectively. Compared with the previous solution, this solution replaces the two step-down circuits with one power management circuit, in which the core of the PMIC circuit is the PMIC chip, which is a highly integrated power management chip, so the area of ​​the module can be reduced, but the price is often relatively high.

[0045] Exemplarily, the first connector uses a 51-pin connector with model number FI-RE51S-HF-R1500. Some pins of this connector are connected to the signal input terminal IN5 of the conversion circuit through the above-mentioned VBO signal group, and some other pins are connected to the first voltage input terminal IN1 of the power supply circuit through a DC voltage signal line.

[0046] Exemplarily, the second connector is a 30-pin connector of model HD2S030HA1R6000, some pins of which are connected to the signal output terminal Out3 of the conversion circuit through the above-mentioned eDP signal group, and some pins are connected to the first voltage input terminal IN1 of the power supply circuit through the DC voltage signal line.

[0047] Continue to refer to Figure 5, two VCC33 pins (i.e., pins 7 and 58) of the conversion chip are connected to the first voltage output terminal Out1 through the first magnetic bead FB9, and are grounded through the eleventh capacitor C34; four VCCA33 pins (i.e., pins 17, 33, 46, and 64) are connected to the first voltage output terminal Out1 through the second magnetic bead FB10, and are grounded through the twelfth capacitor C37; one VTERM_EDPTX pin (i.e., pin 39) is connected to the first voltage output terminal Out1 through the third magnetic bead FB11, and is grounded through the thirteenth capacitor C42; one VCCA12 pin (i.e., pin 1) is connected to the second voltage output terminal Out2 through the fourth magnetic bead FB12, and is grounded through the fourteenth capacitor C55; two V The CC12_TX pin (i.e., pins 36 and 42) is connected to the second voltage output terminal Out2 through the fifth magnetic bead FB13, and is grounded through the fifteenth capacitor C52; the four VDD12 pins (i.e., pins 20, 24, 45, and 52) are connected to the second voltage output terminal Out2 through the sixth magnetic bead FB14, and are grounded through the sixteenth capacitor C56; the four VCC12_RX pins (i.e., pins 4, 10, 55, and 61) are connected to the second voltage output terminal Out2 through the seventh magnetic bead FB15, and are grounded through the seventeenth capacitor C49; one VCCA12_B pin (i.e., pin 15) is connected to the second voltage output terminal Out2 through the eighth magnetic bead FB16, and is grounded through the eighteenth capacitor C54. Among them, the specifications of the magnetic beads FB9~FB16 are the same, and they are used to achieve filtering and filter out high-frequency noise in the power supply signal to prevent these noises from affecting the VBO high-speed signal; capacitors C34, C37, C42, C55, C52, C56, C49, and C54 are respectively connected in parallel with 0.1uf capacitors with the same number of pins connected to them. Their functions are: 1. Filter out high-frequency noise on the corresponding power supply to ensure that the power supply signal input to the chip is clean and free of impurities; 2. For energy storage, when the chip needs instantaneous current, the capacitor takes the lead in providing it with current to reduce the fluctuation generated by the power supply.

[0048] The utility model also provides a display device, which includes: a driving board and a display panel; wherein the driving board is used to receive image data sent by a front device such as a host, and output it to the display panel through the above-mentioned VBO signal to eDP signal module.

[0049] For example, refer to Figure 8The utility model provides a naked-eye 3D display, comprising a driver board, a 3D signal processing board, an adapter board (i.e., the above-mentioned VBO signal to eDP signal module) and a 2D / 3D switchable screen, wherein the PC host transmits each frame of image data to the driver board through an HDMI / DP signal line, the driver board performs protocol conversion on the received image data, and then outputs it to the 3D signal processing board through the VBO signal line; the 3D signal processing board converts the image data, and then outputs it to the adapter board through the VBO signal line, and at the same time, the 3D signal processing board also feeds back the 2D / 3D image status to the driver board through the GPIO signal line; the adapter board performs protocol conversion on the received VBO signal, and then outputs it to the 2D / 3D switchable screen through the eDP interface.

[0050] Furthermore, the naked-eye 3D display also includes an eye tracking module and a 3D signal control board, wherein the 3D signal control board is used to receive control instructions from the driver board on one hand, and transmit the 2D / 3D membrane switch signal to the 2D / 3D switchable screen through the FPC signal line; on the other hand, it is used to receive the positioning signal of the eye tracking module, and connect to the 3D signal processing board through the I2C signal line to realize 2D / 3D state reading and switching, as well as 3D parameter reading and writing. In addition, the external power supply is connected to the power supply of each module in the display through the driver board.

[0051] The utility model can design the input and output signal groups according to video signals with different data amounts, so as to be applicable to video signals with different data amounts and expand the scope of use. At the same time, the power supply circuit in the utility model provides a stable and reliable power supply voltage for the conversion circuit, thereby improving safety and stability.

[0052] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited to this. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A VBO signal to eDP signal module, characterized in that: include: A first connector, on which a VBO interface is provided, for receiving a VBO signal and outputting it through a VBO signal group; A conversion circuit, comprising a signal input terminal and a signal output terminal, wherein the signal input terminal is connected to the VBO signal group, and is used to receive the VBO signal output by the first connector, and convert it into an eDP signal output; A second connector, which is connected to the signal output end of the conversion circuit through the eDP signal group, is used to receive the converted eDP signal and output it through the eDP interface; The power supply circuit is respectively connected to the first connector, the conversion circuit and the second connector for power supply.

2. The VBO signal to eDP signal module according to claim 1, characterized in that: The VBO signal group includes a first hot plug signal, a first lock signal and a first differential signal, the eDP signal group includes a second hot plug signal, a second auxiliary signal and a second differential signal, and the corresponding relationship between the first differential signal and the second differential signal is specifically: If the first differential signal uses 1lane or 2lanes data signal, the second differential signal uses 1lane data signal; if the first differential signal uses 2N lanes data signal, the second differential signal uses N lanes data signal, where N=2,4, and each lane data signal is a differential signal.

3. The VBO signal to eDP signal module according to claim 2, characterized in that: The conversion circuit includes a conversion chip, wherein the HTPDN, LOCKN, and EDPX pins of the conversion chip are respectively used to access the first hot plug signal, the first lock signal, and the first differential signal, thereby forming a signal input end; the HPD, AUX, and DPX pins are respectively used to access the second hot plug signal, the second auxiliary signal, and the second differential signal, thereby forming a signal output end.

4. The VBO signal to eDP signal module according to claim 1, characterized in that: The power supply circuit comprises a first voltage input terminal, a first voltage output terminal and a second voltage output terminal, and is used to step down the DC voltage connected to the first voltage input terminal to 3.3V and 1.2V voltages and output them through the first voltage output terminal and the second voltage output terminal respectively; The conversion circuit includes a third voltage input terminal and a fourth voltage input terminal, wherein the third voltage input terminal is connected to the first voltage output terminal, the fourth voltage input terminal is connected to the second voltage output terminal, and the first voltage input terminal is connected to the first connector and the second connector respectively.

5. The VBO signal to eDP signal module according to claim 4, characterized in that: The power supply circuit comprises: A first step-down circuit, comprising a first voltage input terminal and a first voltage output terminal, for stepping down a DC voltage connected to the first voltage input terminal to 3.3V and then outputting the voltage through the first voltage output terminal; The second step-down circuit includes a second voltage input terminal and a second voltage output terminal, wherein the second voltage input terminal is connected to the first voltage output terminal and is used to step down the 3.3V voltage outputted from the first voltage output terminal to 1.2V and then output it through the second voltage output terminal.

6. The VBO signal to eDP signal module according to claim 5, characterized in that: The first buck circuit includes a first buck chip, wherein the VIN pin of the first buck chip is a first voltage input terminal, which is grounded through a first capacitor, and the VIN pin is connected to the EN pin through a first resistor, and the EN pin is grounded through a second resistor; the FB pin is connected to the first voltage output terminal through a third resistor and a fourth resistor connected in series, and the FB pin is grounded through a fifth resistor, and the first voltage output terminal is grounded through a third capacitor and a fourth capacitor connected in parallel; in addition, the BST pin is connected to the SW pin through a second capacitor, the SW pin is connected to the first voltage output terminal through a first inductor, and the GND and EPAD pins are grounded.

7. The VBO signal to eDP signal module according to claim 5, characterized in that: The second buck circuit includes a second buck chip, wherein the VIN pin of the second buck chip is the second voltage input terminal, which is grounded through a fifth capacitor and a sixth capacitor connected in parallel; the EN pin is connected to the VIN pin through a sixth resistor, and is grounded through a seventh capacitor; the FB pin is connected to the second voltage output terminal through an eighth capacitor and a seventh resistor connected in parallel, and is grounded through an eighth resistor; the second voltage output terminal is grounded through a ninth capacitor and a tenth capacitor connected in parallel; in addition, the LX pin is connected to the second voltage output terminal through a second inductor, and the GND pin is grounded.

8. The VBO signal to eDP signal module according to claim 4, characterized in that: The power supply circuit adopts a PMIC circuit.

9. The VBO signal to eDP signal module according to claim 4, characterized in that: The conversion circuit includes a conversion chip, wherein two VCC33 pins of the conversion chip are connected to the first voltage output terminal through a first magnetic bead and are grounded through an eleventh capacitor; four VCCA33 pins are connected to the first voltage output terminal through a second magnetic bead and are grounded through a twelfth capacitor; one VTERM_EDPTX pin is connected to the first voltage output terminal through a third magnetic bead and is grounded through a thirteenth capacitor; one VCCA12 pin is connected to the second voltage output terminal through a fourth magnetic bead and is grounded through a fourteenth capacitor; two VCC12_TX pins are connected to the second voltage output terminal through a fifth magnetic bead and are grounded through a fifteenth capacitor; four VDD12 pins are connected to the second voltage output terminal through a sixth magnetic bead and are grounded through a sixteenth capacitor; four VCC12_RX pins are connected to the second voltage output terminal through a seventh magnetic bead and are grounded through a seventeenth capacitor; one VCCA12_B pin is connected to the second voltage output terminal through an eighth magnetic bead and is grounded through an eighteenth capacitor, wherein the first to eighth magnetic beads have the same specifications, and the eleventh to eighteenth capacitors are respectively connected in parallel with filter capacitors of the same number as the pins connected thereto.

10. A display device, characterized in that: include: A driving board and a display panel; the driving board is connected to the display panel via a VBO signal to eDP signal module as described in any one of claims 1 to 9.

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