A gate oxide layer structure of SiC power device chip

Abstract

The utility model relates to the field of MOS semiconductor technology, and discloses a gate oxide layer structure of a SiC power device chip, including a plurality of mutually parallel MOS cell structures, wherein the bottom surface of the MOS cell is ohmically connected to a drain, and the top surface of the MOS cell is ohmically connected to a metal source; a gate is embedded inside the MOS cell; the MOS cell includes a substrate layer, a diffusion layer, a P-well layer and an N-well layer, wherein the N-well layer is isolated from the diffusion layer by the P-well layer, and the N-well layer is in ohmic contact with the metal source, and the substrate layer is formed by ion implantation of a large amount in the middle and a small amount on both sides. The utility model designs the oxide layer of the gate into two layers, and one of the oxide layers is thickened near the N-well layer area, so that when the gate is connected to the gate voltage, the gate can reduce the influence of its own electric field on the charge in the N-well layer, thereby suppressing the formation of parasitic charge in the N-well layer, which can effectively reduce the hysteresis of the SiC power device.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a gate oxide layer structure of a SiC power device chip. Background Art

[0002] Silicon carbide (SiC) material is the third generation of wide bandgap semiconductor material developed after the first generation of elemental semiconductor materials (Si) and the second generation of compound semiconductor materials (GaAs, GaP, InP, etc.). SiC material is particularly suitable for the manufacture of microwave high-power, high-voltage, high-temperature, radiation-resistant electronic devices due to its wide bandgap, high critical breakdown electric field, high thermal conductivity, and high electron saturation drift velocity.

[0003] In SiC (silicon carbide) power devices, the gate oxide layer refers to the oxide layer located between the gate metal and the SiC semiconductor. In SiC power devices, the design and preparation of the gate oxide layer usually need to take into account the characteristics of the SiC material and the working environment requirements of the device to ensure that the device has excellent performance and stability. Different manufacturing processes and gate oxide layer designs will have a significant impact on the performance of the device. Therefore, in the research and development and production of SiC power devices, the optimization design of the gate oxide layer is a key technical issue.

[0004] The existing patent discloses a method for manufacturing a gate oxide layer of a SiC power device chip and a power device (publication number CN111009464A), wherein the method for manufacturing a gate oxide layer of a SiC power device chip can accurately control the number of introduced elements through multiple injections, which not only ensures the effect of eliminating defects, but also does not introduce too many P / B elements to cause a decrease in gate reliability. Multiple injections optimize the element distribution to ensure that the P injection layer is completely consumed during the thermal oxidation process. In the technology disclosed in this patent, after the SiC power device is connected to the gate voltage, a strong electric field is often formed to form a charge channel, but at the same time, the electric field will also interfere with the charge in the N-well layer, causing the charge to be offset or even parasitic on the N-well layer, thereby reducing the response speed of the SiC power device. Summary of the invention

[0005] The main technical problem solved by the utility model is to provide a gate oxide layer structure of a SiC power device chip, which solves the problems in the above-mentioned background technology.

[0006] To solve the above technical problems, according to one aspect of the utility model, more specifically, a gate oxide layer structure of a SiC power device chip includes a plurality of mutually parallel MOS cell structures, wherein the bottom surface of the MOS cell is ohmically connected to a drain, and the top surface of the MOS cell is ohmically connected to a metal source;

[0007] A gate is embedded inside the MOS cell;

[0008] The MOS cell comprises a substrate layer, a diffusion layer, a P-well layer and an N-well layer, wherein the N-well layer and the diffusion layer are isolated from each other by the P-well layer, and the N-well layer is in ohmic contact with a metal source electrode;

[0009] The substrate layer is formed by ion implantation with a larger amount in the middle and a smaller amount on both sides, and the shape of the substrate layer in a single MOS cell is convex in the middle and concave on both sides;

[0010] A gate oxide layer is deposited between the gate and the MOS cell.

[0011] Furthermore, the N-well layer includes a lightly doped N-well layer and a heavily doped N-well layer, the cross section of the heavily doped N-well layer is formed in the shape of an 'L', and the lightly doped N-well layer is located above the heavily doped N-well layer.

[0012] Furthermore, the lightly doped N-well layer confines charges and suppresses the generation of parasitic charges.

[0013] Furthermore, the heavily doped N-well layer is doped with high-concentration phosphorus ions by ion implantation, and the lightly doped N-well layer is doped with low-concentration phosphorus ions by ion implantation.

[0014] Furthermore, the P-well layer includes a heavily doped P-well layer 1, a lightly doped P-well layer 1 and a lightly doped P-well layer 2, wherein the heavily doped P-well layer 1 and the lightly doped P-well layer 2 are both formed in an 'L' shape, and the heavily doped P-well layer 1 and the lightly doped P-well layer 2 intersect with each other.

[0015] Furthermore, the lightly doped P-well layers between adjacent MOS cells are integrated as one.

[0016] Furthermore, the lightly doped P-well layer 2 and the lightly doped P-well layer 1 are both doped with low-concentration boron ions by ion implantation, and the heavily doped P-well layer 1 is doped with high-concentration boron ions by ion implantation.

[0017] Furthermore, the upper layer of the diffusion layer is formed with a heavily doped N body region by ion implantation, wherein the thickness of the heavily doped N body region is consistent with the thickness of the two short ends of the lightly doped P well layer.

[0018] The beneficial effects of the gate oxide layer structure of a SiC power device chip of the utility model are:

[0019] 1. The utility model designs the gate oxide layer to be two layers, and one of the oxide layers is thickened near the N-well layer area. In this way, when the gate is connected to the gate voltage, the influence of the gate's own electric field on the charge in the N-well layer can be reduced, thereby suppressing the formation of parasitic charges in the N-well layer, which can effectively reduce the hysteresis of the SiC power device.

[0020] 2. The utility model further reduces the hysteresis of the SiC power device by dividing the N-well layer into a heavily doped N-well layer located at the lower layer and a lightly doped N-well layer located at the upper layer.

[0021] 3. The utility model forms an N+ region by doping at the bottom of the U groove, thereby increasing the conduction performance of the device and reducing the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0023] Figure 1 Schematic diagram of the gate oxide structure of a SiC power device chip;

[0024] Figure 2 for Figure 1 A local enlarged and refined image of ;

[0025] Figure 3 Schematic diagram of the structure of SiC power device.

[0026] In the figure: 1. drain; 2. substrate layer; 3. diffusion layer; 4. heavily doped N body region; 5. heavily doped P well layer 1; 6. lightly doped P well layer 1; 7. lightly doped N well layer; 8. metal source; 9. gate; 10. gate oxide layer; 11. heavily doped N well layer; 12. lightly doped P well layer 2. DETAILED DESCRIPTION

[0027] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0028] like Figure 1-3As shown, according to one aspect of the utility model, a gate oxide layer structure of a SiC power device chip is provided, including a plurality of mutually parallel MOS cell structures, the bottom surface of the MOS cell is ohmically connected to a drain 1, and the top surface of the MOS cell is ohmically connected to a metal source 8; a gate 9 is embedded inside the MOS cell; the MOS cell includes a substrate layer 2, a diffusion layer 3, a P-well layer and an N-well layer, the N-well layer and the diffusion layer 3 are isolated by the P-well layer, and the N-well layer is in ohmic contact with the metal source 8; the substrate layer 2 is formed by ion implantation of a large amount in the middle and a small amount on both sides, and the shape of the substrate layer 2 in a single MOS cell is convex in the middle and low on both sides; a gate oxide layer 10 is deposited between the gate 9 and the MOS cell. By designing the gate oxide layer 10 as two layers, and thickening one of the oxide layers close to the N-well layer area, when the gate 9 is connected to the gate voltage, the influence of the gate 9 on the charge in the N-well layer due to its own electric field can be reduced, thereby suppressing the formation of parasitic charges in the N-well layer, which can effectively reduce the hysteresis of the SiC power device.

[0029] In this embodiment, the N-well layer includes a lightly doped N-well layer 7 and a heavily doped N-well layer 11. The cross-section of the heavily doped N-well layer 11 is formed in the shape of an 'L', and the lightly doped N-well layer 7 is located above the heavily doped N-well layer 11. The lightly doped N-well layer 7 constrains charges and suppresses the generation of parasitic charges, dividing the N-well layer into a heavily doped N-well layer located at the lower layer and a lightly and heavily doped N-well layer located at the upper layer, further reducing the hysteresis of the SiC power device.

[0030] In this embodiment, the heavily doped N well layer 11 is doped with 5 to 8.3×10 18 mol / cm 3 Phosphorus element, lightly doped N well layer 7 is doped by ion implantation into 2.5~7.4×10 15 mol / cm 3 Phosphorus element, lightly doped P well layer 2 12, lightly doped P well layer 1 6 are doped by ion implantation into 2.3~5.6×10 16 mol / cm 3 The boron element is heavily doped in the P well layer 1 by ion implantation with 6 to 9.1×10 18 mol / cm 3 of boron.

[0031] In this embodiment, the P-well layer includes a heavily doped P-well layer 15, a lightly doped P-well layer 16 and a lightly doped P-well layer 2 12, wherein the heavily doped P-well layer 15 and the lightly doped P-well layer 2 12 are both formed in an 'L' shape, and the heavily doped P-well layer 15 and the lightly doped P-well layer 2 12 intersect with each other, and the lightly doped P-well layer 16 between adjacent MOS cells is integrated as a whole, and the upper layer of the diffusion layer 3 is formed with a heavily doped N-body region 4 by ion implantation, wherein the thickness of the heavily doped N-body region 4 is consistent with the thickness of the short end of the lightly doped P-well layer 2 12.

[0032] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A gate oxide layer structure of a SiC power device chip, characterized in that: It comprises a plurality of mutually parallel MOS cell structures, wherein the bottom surface of the MOS cell is ohmically connected to a drain electrode (1), and the top surface of the MOS cell is ohmically connected to a metal source electrode (8); A gate (9) is embedded inside the MOS cell; The MOS cell comprises a substrate layer (2), a diffusion layer (3), a P-well layer and an N-well layer, the N-well layer and the diffusion layer (3) are isolated by the P-well layer, and the N-well layer is in ohmic contact with a metal source electrode (8); The substrate layer (2) is formed by ion implantation with a larger amount in the middle and a smaller amount on both sides, and the shape of the substrate layer (2) in a single MOS cell is convex in the middle and concave on both sides; A gate oxide layer (10) is deposited between the gate (9) and the MOS cell.

2. The gate oxide layer structure of a SiC power device chip according to claim 1, characterized in that: The N well layer comprises a lightly doped N well layer (7) and a heavily doped N well layer (11), the cross section of the heavily doped N well layer (11) is in the shape of an 'L', and the lightly doped N well layer (7) is located above the heavily doped N well layer (11).

3. The gate oxide layer structure of a SiC power device chip according to claim 2, characterized in that: The lightly doped N-well layer (7) constrains charges and suppresses the generation of parasitic charges.

4. The gate oxide layer structure of the SiC power device chip according to claim 3, characterized in that: The heavily doped N-well layer (11) is doped with high-concentration phosphorus ions by an ion implantation method, and the lightly doped N-well layer (7) is doped with low-concentration phosphorus ions by an ion implantation method.

5. The gate oxide layer structure of a SiC power device chip according to claim 1, characterized in that: The P-well layer includes a heavily doped P-well layer 1 (5), a lightly doped P-well layer 1 (6) and a lightly doped P-well layer 2 (12), wherein the heavily doped P-well layer 1 (5) and the lightly doped P-well layer 2 (12) are both formed in an 'L' shape, and the heavily doped P-well layer 1 (5) and the lightly doped P-well layer 2 (12) intersect with each other.

6. The gate oxide layer structure of a SiC power device chip according to claim 5, characterized in that: The lightly doped P-well layer (6) between adjacent MOS cells is integrated.

7. The gate oxide layer structure of a SiC power device chip according to claim 6, characterized in that: The lightly doped P-well layer 2 (12) and the lightly doped P-well layer 1 (6) are both doped with low-concentration boron ions by ion implantation, and the heavily doped P-well layer 1 (5) is doped with high-concentration boron ions by ion implantation.

8. The gate oxide layer structure of a SiC power device chip according to claim 1, characterized in that: The upper layer of the diffusion layer (3) is formed with a heavily doped N body region (4) by ion implantation, wherein the thickness of the heavily doped N body region (4) is consistent with the thickness of the short end of the lightly doped P well layer 2 (12).

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