Integrated circuit

Abstract

Various embodiments of the utility model relate to an integrated circuit. The integrated circuit includes a first horizontal conductor and a second horizontal conductor. The integrated circuit includes a first diode between a first first block and a first second block, a second diode between a second first block and a second second block, and a third diode between a third first block and a third second block. The first mold block and the first second mold block are arranged along a first column. The second first mold block and the second second mold block are arranged along a second column. The third first block and the third second block are arranged along a third column. The second first profile block is connected to the first second profile block through a second horizontal conductor. The third first block is conductively connected to the second second block through the first horizontal conductor.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated circuit. Background Art

[0002] The recent trend of integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but provide more functionality at higher speeds. Miniaturization processes also bring more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits while ensuring that standard cell layout design and manufacturing specifications are met. Utility Model Content

[0003] One aspect of the utility model provides an integrated circuit. The integrated circuit includes a first horizontal conductor and a second horizontal conductor, each extending along a first direction. The integrated circuit also includes a first diode formed between a first first block and a first second block, a second diode formed between a second first block and a second second block, and a third diode formed between a third first block and a third second block. The first first block and the first second block are arranged along a second direction perpendicular to the first direction. The second first block and the second second block are arranged along the second direction. The third first block and the third second block are arranged along the second direction. The second first block is conductively connected to the first second block of the first diode through the second horizontal conductor. The third first block is conductively connected to the second second block of the second diode through the first horizontal conductor.

[0004] Another aspect of the utility model provides an integrated circuit. The integrated circuit includes a first row of first type blocks and a first row of second type blocks arranged along a first direction. The integrated circuit also includes a second row of second type blocks and a second row of first type blocks arranged along the first direction. The integrated circuit also includes a first diode formed between the first row of first type blocks and the second row of second type blocks, and a second diode formed between the second row of first type blocks and the first row of second type blocks. The first row of first type blocks and the second row of second type blocks are arranged along a second direction perpendicular to the first direction. The second row of first type blocks and the first row of second type blocks are arranged along the second direction. The integrated circuit also includes a third row of second type blocks and a third row of first type blocks arranged along the first direction. The third row of second type blocks are adjacent to the second row of second type blocks, and the third row of first type blocks are adjacent to the second row of first type blocks. The integrated circuit also includes a fourth row of first type blocks and a fourth row of second type blocks arranged along the first direction. The fourth row of first type blocks are adjacent to the third row of second type blocks, and the fourth row of second type blocks are adjacent to the third row of first type blocks.

[0005] Another aspect of the utility model provides a method for manufacturing an integrated circuit. The method includes making a second-type well in a first-type substrate. The method also includes implanting a first-type dopant into the second-type well to generate a first first-type block in the first row, a second first-type block in the second row, and a third first-type block in the first row. The method also includes implanting a second-type dopant into the second-type well to generate a first second-type block in the second row, a second second-type block in the first row, and a third second-type block in the second row. The first first-type block and the first second-type block are arranged along the first column, and a first diode is formed between the first first-type block and the first second-type block. The second second-type block and the second first-type block are arranged along the second column, and a second diode is formed between the second second-type block and the second first-type block. The third first-type block and the third second-type block are arranged along the third column, and a third diode is formed between the third first-type block and the third second-type block. The method also includes depositing a metal layer above the second-type well and the first-type substrate. The method further includes forming a first horizontal conductor connecting the second second-type block and the third first-type block, and forming a second horizontal conductor connecting the first second-type block and the second first-type block.

[0006] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a layout diagram of a diode string in an ESD protection circuit according to some embodiments.

[0008] Figure 1B to Figure 1C According to some embodiments Figure 1A Cross-sectional view of an ESD protection circuit.

[0009] Figure 1D is a circuit diagram of an ESD protection circuit having a diode string connected to an input pad of an integrated circuit according to some embodiments.

[0010] Figure 1E is a schematic diagram of an integrated circuit device having connection pads near the edge of the device.

[0011] Figure 2A is a layout diagram of a diode string in an ESD protection circuit with an additional SCR device according to some embodiments.

[0012] Figure 2B is a circuit diagram of an ESD protection circuit having a diode string connected to an input pad of an integrated circuit according to some embodiments.

[0013] Figure 2C to Figure 2D An integrated circuit according to some embodiments is Figure 2ACross-sectional views in various cutting planes specified in the layout diagram.

[0014] Figure 3 is a layout diagram of a diode string in an ESD protection circuit according to some embodiments.

[0015] FIG. 4A to FIG. 4C is an example implementation of a p-type block used in an ESD protection circuit according to some embodiments.

[0016] Figure 5 is a flowchart of a method of manufacturing an integrated circuit according to some embodiments.

[0017] Figure 6 is a block diagram of an electronic design automation (EDA) system 600 according to some embodiments.

[0018] Figure 7 is a block diagram of an integrated circuit (IC) manufacturing system 700 and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0019] The present invention provides many different embodiments or examples for implementing the different components of the provided target. The following describes specific examples of components, values, operations, materials, arrangements, etc. to simplify the present invention. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are also expected. For example, in the following description, forming a first component on or on a second component may include an embodiment in which the first component and the second component are formed to be in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0020] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0021] In some embodiments, an electrostatic discharge ("ESD") protection circuit includes a diode string connected to an input pad of an integrated circuit. The diode string includes a plurality of diodes connected in series. Each diode in the diode string is formed between a p-type block and an n-type block. In some embodiments, the p-type block is formed by one or more heavily doped p-type regions, and the n-type block is formed by one or more heavily doped n-type regions. The p-type blocks and n-type blocks used to form the plurality of diodes are arranged in a matrix. The p-type blocks and n-type blocks are alternately arranged along a first direction (e.g., along a row of the matrix), and a conductive connection between two series-connected diodes in the diode string is formed by a conductor extending along the first direction, the conductor connecting the n-type block of one diode to the p-type block of another diode. The conductive connection between two series-connected diodes in the diode string has a reduced resistance compared to some alternative embodiments in which the blocks used to form the diode string are arranged in a matrix having blocks of the same type positioned along the first direction (e.g., only p-type blocks or only n-type blocks). The reduced resistance in the diode string improves the ESD protection of the diode string for the input pad of the integrated circuit.

[0022] In some embodiments, one or more SCR ("silicon controlled rectifier") devices are formed by additional p-type blocks and / or additional n-type blocks arranged in a matrix, and the SCR devices are connected in parallel with the diode string. The combination of the SCR devices and the diode string enhances the ESD protection of the input pads of the integrated circuit.

[0023] Figure 1A FIG. 1 is a layout diagram of a diode string in an ESD protection circuit according to some embodiments. Figure 1A In the embodiment, the ESD protection circuit 100 includes p-type blocks and n-type blocks arranged in a matrix. The matrix includes p-type blocks 111P, n-type blocks 112N, and p-type blocks 113P arranged in a first row along the X direction. The matrix includes n-type blocks 121N, p-type blocks 122P, and n-type blocks 123N arranged in a second row along the X direction. The p-type blocks 111P and n-type blocks 121N are arranged along the Y direction in the first column. The n-type blocks 112N and p-type blocks 122P are arranged along the Y direction in the second column. The p-type blocks 113P and n-type blocks 123N are arranged along the Y direction in the third column. The Y direction is perpendicular to the X direction.

[0024] The first diode D1 is formed between the p-type block 111P and the n-type block 121N. The second diode D2 is formed between the n-type block 112N and the p-type block 122P. The third diode D3 is formed between the p-type block 113P and the n-type block 123N. The n-type block 121N of the first diode D1 and the p-type block 122P of the second diode D2 are conductively connected together through the horizontal conductor 1C2 extending along the X direction. The n-type block 112N of the second diode D2 and the p-type block 113P of the third diode D3 are conductively connected together through the horizontal conductor 1C1 extending along the X direction. Therefore, the first diode D1, the second diode D2 and the third diode D3 are connected in series between the p-type block 111P and the n-type block 123N to form a diode string 180.

[0025] Figure 1B According to some embodiments, the ESD protection circuit 100 is Figure 1A A cross-sectional view of the cutting plane A-A'. Figure 1B , each of the p-type block 111P and the p-type block 113P is implemented as a heavily doped p-type region "P+" in a corresponding n-type well "NW" of the substrate 20, and the n-type block 112N is implemented as a heavily doped n-type region "N+" in a corresponding n-type well "NW" of the substrate 20. The horizontal conductor 1C1 conductively connects the n-type block 112N of the second diode D2 and the p-type block 113P of the third diode D3. The n-type well "NW" is connected to the upper power supply voltage VDD through the heavily doped n-type region 101. The p-type well "PW" is connected to the lower power supply voltage VSSESD through the heavily doped p-type region 109.

[0026] Figure 1C According to some embodiments, the ESD protection circuit 100 is Figure 1A The sectional view of the section plane B-B'. Figure 1C , each of the n-type block 121N and the n-type block 123N is implemented as a heavily doped n-type region "N+" in a corresponding n-type well "NW" of the substrate 20, and the p-type block 122P is implemented as a heavily doped p-type region "P+" in a corresponding n-type well "NW" of the substrate 20. The horizontal conductor 1C2 conductively connects the n-type block 121N of the first diode D1 and the p-type block 122P of the second diode D2. The n-type well "NW" is connected to the upper power supply voltage VDD through the heavily doped n-type region 101. The p-type well "PW" is connected to the lower power supply voltage VSSESD through the heavily doped p-type region 109.

[0027] Figure 1A The diode string 180 in FIG. 1 is configured as an electrostatic discharge (“ESD”) protection device. Figure 1D is a circuit diagram of an ESD protection circuit having a diode string connected to an input pad of an integrated circuit according to some embodiments. Figure 1Eis a schematic diagram of an integrated circuit device having connection pads near the edge of the device.

[0028] exist Figure 1D In FIG. 1 , a diode string 180 is connected between an input pad 52 and a lower power supply VSS. The input pad 52 is connected to an input node 62 of an internal circuit 60. Figure 1A In the example of FIG. 1 , the p-type electrode of the diode string 180 is a p-type block 111P, and the p-type block 111P is connected to the input pad 52. In addition to the diode string 180, another diode 185 is connected between the input pad 52 of the internal circuit 60 and the lower power supply VSS. The diode string 180 and the diode 185 are connected in anti-parallel. In normal operation, the diode string 180 is forward biased, and the diode 185 is reverse biased. The input pad 52 is one of the connection pads 51-55, and is located in the peripheral area of ​​the integrated circuit device 50, such as Figure 1E As shown. Figure 1D to Figure 1E In FIG. 5 , the input pad 52 is configured to receive an input signal from a circuit external to the integrated circuit device 50 , and is configured to transmit the input signal received at the input pad 52 to an input node 62 of the internal circuit 60 .

[0029] exist Figure 1A In the layout diagram of , in each row of the matrix, the p-type blocks and the n-type blocks are alternately arranged along the X direction. For example, in the first row, the n-type block 112N is located between the p-type block 111P and the p-type block 113P. In the second row, the p-type block 122P is located between the n-type block 121N and the n-type block 123N. Compared with some other embodiments in which each row includes only p-type blocks or only n-type blocks, when the p-type blocks and the n-type blocks are alternately arranged, the resistance in the conductor between two adjacent diodes in the diode string 180 is reduced. Due to the reduced resistance in the conductor, the residual resistance of the diode string 180 is reduced when the diode string 180 is turned on under forward bias, thereby improving the ESD current protected by the diode string 180.

[0030] Figure 1A Some modifications of the ESD protection circuit 100 in are within the contemplated scope of the present disclosure. For example, the diode string includes a first type block and a second type block. Figure 1A In an exemplary embodiment of the present invention, each p-type block is implemented as a first-type block, and each n-type block is implemented as a second-type block. In some modified embodiments, each n-type block is implemented as a first-type block, and each p-type block is implemented as a second-type block. The modification includes replacing the newly created n-type block with Figure 1A Each p-type block in and replace it with the newly created p-type block Figure 1A Each n-type block in .

[0031] In some embodiments, the ESD protection of the input pad with the diode string is improved by adding an SCR ("Silicon Controlled Rectifier") device. Figure 2A is a layout diagram of a diode string in an ESD protection circuit with an additional SCR device according to some embodiments. Figure 2B is a circuit diagram of an ESD protection circuit having a diode string connected to an input pad of an integrated circuit according to some embodiments. Figure 2C to Figure 2D An integrated circuit according to some embodiments is Figure 2A Section views in various cutting planes specified in the layout drawing.

[0032] exist Figure 2A , the ESD protection circuit 200 includes p-type blocks and n-type blocks arranged in a matrix. The matrix includes p-type blocks 211P, n-type blocks 212N, and p-type blocks 213P arranged in a first row along the X direction. The matrix includes n-type blocks 221N, p-type blocks 222P, and n-type blocks 223N arranged in a second row along the X direction. The p-type blocks 211P and n-type blocks 221N are arranged in the Y direction in the first column. The n-type blocks 212N and p-type blocks 222P are arranged in the Y direction in the second column. The p-type blocks 213P and n-type blocks 223N are arranged in the Y direction in the third column.

[0033] The first diode D1 is formed between the p-type block 211P and the n-type block 221N. The second diode D2 is formed between the n-type block 212N and the p-type block 222P. The third diode D3 is formed between the p-type block 213P and the n-type block 223N. The n-type block 221N of the first diode D1 and the p-type block 222P of the second diode D2 are conductively connected together through a horizontal conductor 2C2 extending along the X direction. The n-type block 212N of the second diode D2 and the p-type block 213P of the third diode D3 are conductively connected together through a horizontal conductor 2C1 extending along the X direction. Therefore, the first diode D1, the second diode D2 and the third diode D3 are connected in series between the p-type block 211P and the n-type block 223N to form a diode string 280. The diode string 280 is constructed as an electrostatic discharge ("ESD") protection device. As shown in FIG. Figure 2B As shown, a diode string 280 is connected between the input pad 52 and the lower power supply VSSESD. The input pad 52 is connected to the input node 62 of the internal circuit 60. In addition to the diode string 280, another diode 285 is connected between the input pad 52 and the lower power supply VSSESD.

[0034] exist Figure 2A, although two rows of p-type blocks and n-type blocks (i.e., the first and second rows) are used to implement the diodes D1, D2, and D3, four rows of p-type blocks and n-type blocks (i.e., the first, second, third, and fourth rows) are used to implement the additional SCR device. The p-type blocks and n-type blocks in the third row of the matrix include n-type blocks 231N, p-type blocks 232P, and n-type blocks 233N arranged in the X direction. The p-type blocks and n-type blocks in the fourth row of the matrix include p-type blocks 241P, n-type blocks 242N, and p-type blocks 243P arranged in the X direction.

[0035] The p-type block 211P, the n-type block 221N, the n-type block 231N, and the p-type block 241P are arranged in the Y direction in the first column. The n-type block 212N, the p-type block 222P, the p-type block 232P, and the n-type block 242N are arranged in the Y direction in the second column. The p-type block 213P, the n-type block 223N, the n-type block 233N, and the p-type block 243P are arranged in the Y direction in the third column. The p-type block 211P, the n-type block 221N, and the n-type block 231N form the first SCR device SCR1 in the first column. The n-type block 223N, the n-type block 233N, and the p-type block 243P form the second SCR device SCR2 in the third column.

[0036] exist Figure 2B In the circuit diagram of FIG. 5 , a diode string 280 and a diode 285 are connected in anti-parallel between the input pad 52 and the power supply VSSESD. In normal operation, the diode string 280 is forward biased and the diode 285 is reverse biased. The input pad 52 is connected to the input node 62 of the internal circuit 60. In addition, the first SCR device SCR1 (which is composed of Figure 2A The p-type block 211P, the n-type block 221N and the n-type block 231N in the SCR device SCR2 (which is formed by Figure 2A The n-type block 223N, the n-type block 233N and the p-type block 243P in the input circuit are also connected in parallel between the input pad 52 and the lower power supply VSSESD. Figure 2B In the circuit diagram of FIG. 1 , the main SCR device SCR0 connected between the input pad 52 and the lower power supply VSSESD is horizontally formed by the p-type blocks and the n-type blocks in the first and second rows.

[0037] In some embodiments, each of the diodes D1, D2, and D3 is formed with a corresponding n-well in a p-type substrate, and each of the diodes D1, D2, and D3 is associated with a corresponding bipolar junction transistor (BJT), such as Vbe1, Vbe2, or Vbe3. The collectors of the bipolar junction transistors Vbe1, Vbe2, and Vbe3 are located at the p-type substrate. The bases of the bipolar junction transistors Vbe1, Vbe2, and Vbe3 are each located at the n-well associated with the corresponding diode D1, D2, or D3. The emitter of each of the bipolar junction transistors Vbe1, Vbe2, and Vbe3 is located at the p-type electrode of the corresponding diode D1, D2, or D3.

[0038] The resistance between the lower power supply VSSESD and the collectors of the bipolar junction transistors Vbe1, Vbe2 and Vbe3 is simulated using substrate resistor Rsub. The n-type block 221N of the first diode D1 is connected through the horizontal conductor 2C2 ( Figure 2A The conductive connection from the n-type block 212N of the second diode D2 through the horizontal conductor 2C1 ( Figure 2A The conductive connection of the p-type block 213P to the third diode D3 is simulated by the resistor R2. The resistance values ​​of the resistors R1 and R2 are both reduced compared to some other embodiments where each row includes only p-type blocks or only n-type blocks.

[0039] Figure 2C According to some embodiments Figure 2A A cross-sectional view of the ESD protection circuit 200 taken along the cutting plane PP'. Figure 2C In the embodiment, each of the p-type block 211P and the p-type block 241P is implemented as a heavily doped p-type region "P+" in the corresponding n-type well "NW" of the substrate 20, and each of the n-type block 221N and the n-type block 231N is implemented as a heavily doped n-type region "N+" in the corresponding n-type well "NW" of the substrate 20. The diode D1 is formed between the p-type block 211P and the n-type block 221N. The p-type block 211P is connected to an input pad (e.g., Figure 2A The first SCR device SCR1 between the p-type block 211P and the n-type block 231N is formed by a pnp transistor Qpnp1 and an npn transistor Qnpn1.

[0040] The pnp transistor Qpnp1 in the first SCR device SCR1 has an emitter formed at the p-type block 211P, a base formed at the n-type well surrounding the p-type block 211P, and a collector formed at the substrate 20. The n-type electrode of the diode D1 is connected to the base of the pnp transistor Qpnp1 because the heavily doped n-type region "N+" of the n-type block 221N is in ohmic contact with the n-type well "NW" surrounding the n-type block 221N. The n-type well "NW" surrounding the n-type block 221N is connected to the upper power supply voltage VDD through the heavily doped n-type region 201. The conductive connection between the base of the pnp transistor Qpnp1 and the upper power supply voltage VDD is made by the resistor R NW The substrate 20 is connected to the lower power supply voltage VSSESD through the substrate contact 209, which is a heavily doped p-type region "P+".

[0041] The npn transistor Qnpn1 in the first SCR device SCR1 has an emitter formed at the n-type block 231N, a base formed at the substrate 20, and a collector formed at the p-type well "PW" connected to the base of the pnp transistor Qpnp1 in the first SCR device SCR1. The base of the npn transistor Qnpn1 is conductively connected to the collector of the pnp transistor Qpnp1.

[0042] Figure 2D According to some embodiments Figure 2A A cross-sectional view of the ESD protection circuit 200 taken along the cross-sectional plane Q-Q'. Figure 2D In the embodiment, each of the p-type block 213P and the p-type block 243P is implemented as a heavily doped p-type region "P+" in the corresponding n-type well "NW" of the substrate 20, and each of the n-type block 223N and the n-type block 233N is implemented as a heavily doped n-type region "N+" in the corresponding n-type well "NW" of the substrate 20. The diode D3 is formed between the p-type block 213P and the n-type block 223N. The p-type block 243P is connected to an input pad (e.g., Figure 2B The second SCR device SCR2 between the p-type block 243P and the n-type block 223N is formed by a pnp transistor Qpnp2 and an npn transistor Qnpn2.

[0043] The pnp transistor Qpnp2 in the second SCR device SCR2 has an emitter formed at the p-type block 243P, a base formed at the n-type well surrounding the p-type block 243P, and a collector formed at the substrate 20 .

[0044] The npn transistor Qnpn2 in the second SCR device SCR2 has an emitter formed at the n-type block 223N, a base formed at the substrate 20, and a collector formed at the p-type well "PW" connected to the n-type block 223N. A conductive connection from the n-type block 223N to the base of the pnp transistor Qpnp2 is made with a resistor R NW The base of the npn transistor Qnpn2 is conductively connected to the collector of the pnp transistor Qpnp2.

[0045] exist Figure 2A In some embodiments, diodes D1, D2, and D3 are formed of p-type blocks and n-type blocks in the first and second rows, and SCR devices SCR1 and SCR2 are formed of p-type blocks and n-type blocks in the first, second, third, and fourth rows. In some embodiments, another diode string with auxiliary diodes D1', D2', and D3' is formed of p-type blocks and n-type blocks in the third and fourth rows.

[0046] The first auxiliary diode D1' is formed between the p-type block 243P in the fourth row and the n-type block 233N in the third row. The second auxiliary diode D2' is formed between the n-type block 232P in the third row and the n-type block 242N in the fourth row. The third auxiliary diode D3' is formed between the p-type block 241P in the fourth row and the n-type block 231N in the third row.

[0047] The n-type block 233N of the first auxiliary diode D1' and the p-type block 232P of the second auxiliary diode D2' are conductively connected together through the horizontal conductor 2C3 in the third row extending along the X direction. The n-type block 242N of the second auxiliary diode D2' and the p-type block 241P of the third auxiliary diode D3' are conductively connected together through the horizontal conductor 2C4 in the fourth row extending along the X direction. Therefore, the first auxiliary diode D1', the second auxiliary diode D2' and the third auxiliary diode D3' are connected in series between the p-type block 243P and the n-type block 231N to form an auxiliary diode string 280'. In some embodiments, when the p-type block 243P is connected to Figure 2B When the input pad 52 in the circuit is connected and the n-type block 223N is connected to the lower power supply voltage VSSESD, the auxiliary diode string 280′ is connected in parallel with the diode string 280 between the input pad 52 and the lower power supply voltage VSSESD, thereby enabling the ESD protection circuit 200 to protect the larger ESD current at the input pad 52.

[0048] In some embodiments, ESD protection circuit 200 further includes p-type and n-type blocks in the fifth, sixth, and seventh rows. Additional SCR devices and diode strings are formed by combining the p-type and n-type blocks in the fifth, sixth, and seventh rows with the p-type and n-type blocks in the fourth row.

[0049] The fifth row includes an n-type block 251N, a p-type block 252P, and an n-type block 253N arranged in the X direction. The sixth row includes an n-type block 261N, a p-type block 262P, and an n-type block 263N arranged in the X direction. The seventh row includes a p-type block 271P, an n-type block 272N, and a p-type block 273P arranged in the X direction. The n-type block 251N, the n-type block 261N, and the p-type block 271P are aligned with the p-type block 241P in the first column along the Y direction. The p-type block 252P, the p-type block 262P, and the n-type block 272N are aligned with the n-type block 242N in the second column along the Y direction. The n-type block 253N, the n-type block 263N, and the p-type block 273P are aligned with the p-type block 243P in the third column along the Y direction.

[0050] When the n-type block 263N in the sixth row is connected to the lower power supply voltage VSSESD and the p-type block 243P in the fourth row is connected to the input pad (eg Figure 2B When input pad 52 in the input pad is connected, SCR device SCR3 formed by p-type block 243P, n-type block 253N and n-type block 263N in the third column provides additional ESD protection for the input pad.

[0051] In some embodiments, a diode string 280B between p-type block 271P and n-type block 263N is formed by p-type blocks and n-type blocks in the sixth and seventh rows. Diode string 280B includes a first diode between p-type block 271P and n-type block 261N, a second diode between p-type block 262P and n-type block 272N, and a third diode between p-type block 273P and n-type block 263N. The n-type block 261N of the first diode is conductively connected to the p-type block 262P of the second diode through a horizontal conductor 2C6 aligned with the n-type block 261N and p-type block 262P in the sixth row. The n-type block 272N of the second diode is conductively connected to the p-type block 273P of the third diode through a horizontal conductor 2C7 aligned with the n-type block 272N and p-type block 273P in the seventh row.

[0052] When the n-type block 263N in the sixth row is connected to the lower power supply voltage VSSESD and the p-type block 271P in the seventh row is connected to the input pad (eg Figure 2B When the input pad 52 in FIG. 5 is connected, the diode string 280B between the p-type block 271P and the n-type block 263N provides additional ESD protection for the input pad.

[0053] In some embodiments, when the n-type block 251N in the fifth row is connected to the lower supply voltage VSSESD and the p-type block 271P in the seventh row is connected to the input pad (eg, Figure 2B When input pad 52 in the first column is used, SCR device SCR4 formed by p-type block 271P, n-type block 261N, and n-type block 251N in the first column provides additional ESD protection for the input pad.

[0054] In some embodiments, an auxiliary diode string 280'B between the p-type block 243P and the n-type block 251N is formed by the p-type blocks and the n-type blocks in the fourth and fifth rows. The auxiliary diode string 280'B includes a first auxiliary diode between the p-type block 243P and the n-type block 253N, a second auxiliary diode between the p-type block 252P and the n-type block 242N, and a third auxiliary diode between the p-type block 241P and the n-type block 251N. The n-type block 253N of the first auxiliary diode is conductively connected to the p-type block 252P of the second auxiliary diode through a horizontal conductor 2C5 aligned with the n-type block 253N and the p-type block 252P in the fifth row. The n-type block 242N of the second auxiliary diode is conductively connected to the p-type block 241P of the third auxiliary diode through a horizontal conductor 2C4 aligned with the n-type block 242N and the p-type block 241P in the fourth row.

[0055] When the n-type block 251N in the fifth row is connected to the lower power supply voltage VSSESD and the p-type block 243P in the fourth row is connected to the input pad (eg Figure 2B When the input pad 52 in FIG. 1 is connected, the auxiliary diode string 280′B between the p-type block 243P and the n-type block 251N provides additional ESD protection for the input pad.

[0056] exist Figure 2A , the auxiliary diode string 280'B (between the p-type block 243P and the n-type block 251N) and the diode string 280' (between the p-type block 243P and the n-type block 231N) share the fourth row of p-type blocks and n-type blocks as a shared row. The p-type block 243P is also shared by the second SCR device SCR2 in the third column and the third SCR device SCR3 in the third column. The second SCR device SCR2 is formed by the p-type block 243P, the n-type block 233N, and the n-type block 223N. The third SCR device SCR3 is formed by the p-type block 243P, the n-type block 253N, and the n-type block 263N. Because the p-type block and n-type block of the fourth row are shared by the auxiliary diode strings 280' and 280'B as a shared row, Figure 2A The layout area of ​​the ESD protection circuit 200 is reduced.

[0057] The third SCR device SCR3 between the p-type block 243P and the n-type block 263N is formed by a pnp transistor Qpnp3 and an npn transistor Qnpn3, as shown in FIG. Figure 2D As shown in the cross-sectional view.

[0058] exist Figure 2DIn the embodiment, each of the p-type block 243P and the p-type block 273P is implemented as a heavily doped p-type region “P+” in a corresponding n-type well “NW” of the substrate 20, and each of the n-type block 253N and the n-type block 263N is implemented as a heavily doped n-type region “N+” in a corresponding n-type well “NW” of the substrate 20. The p-type block 243P is connected to an input pad (e.g., Figure 2B , and the n-type block 263N is connected to the lower supply voltage VSSESD.

[0059] The pnp transistor Qpnp3 in the SCR device SCR3 has an emitter formed at the p-type block 243P, a base formed at the n-type well surrounding the p-type block 243P, and a collector formed at the substrate 20. The heavily doped n-type region "N+" of the n-type block 263N is conductively connected to the base of the pnp transistor Qpnp3.

[0060] The npn transistor Qnpn3 in the third SCR device SCR3 has an emitter formed at the n-type block 263N, a base formed at the substrate 20, and a collector formed at the p-type well region "PW" connected to the n-type block 253N. A conductive connection from the n-type block 253N to the base of the pnp transistor Qpnp3 is made with a resistor R NW The base of the pnp transistor Qpnp3 is conductively connected to the collector of the npn transistor Qnpn3.

[0061] The fourth SCR device SCR4 between the p-type block 271P and the n-type block 251N is formed by a pnp transistor Qpnp4 and an npn transistor Qnpn4. Figure 2C As shown in the cross-sectional view.

[0062] exist Figure 2C In the embodiment, each of the p-type block 271P and the p-type block 241P is implemented as a heavily doped p-type region “P+” in a corresponding n-type well “NW” of the substrate 20, and each of the n-type block 261N and the n-type block 251N is implemented as a heavily doped n-type region “N+” in a corresponding n-type well “NW” of the substrate 20. The p-type block 271P is connected to an input pad (e.g., Figure 2A , and the n-type block 251N is connected to the lower supply voltage VSSESD.

[0063] The pnp transistor Qpnp4 in the fourth SCR device SCR4 has an emitter formed at the p-type block 271P, a base formed at the n-type well surrounding the p-type block 271P, and a collector formed at the substrate 20. The n-type block 261N is connected to the base of the pnp transistor Qpnp4. The n-type well "NW" surrounding the p-type block 271P and the n-type block 261N is connected to the upper power supply voltage VDD through the heavily doped n-type region 201. The base of the pnp transistor Qpnp4 is conductively connected to the upper power supply voltage VDD by a resistor R NW The substrate 20 is connected to the lower power supply voltage VSSESD through the substrate contact 209, which is a heavily doped p-type region "P+".

[0064] The npn transistor Qnpn4 in the fourth SCR device SCR4 has an emitter formed at the n-type block 251N, a base formed at the substrate 20, and a collector formed at the p-type well region "PW" connected to the base of the pnp transistor Qpnp4 in the fourth SCR device SCR4. The collector of the npn transistor Qnpn4 is conductively connected to the base of the pnp transistor Qpnp4.

[0065] exist Figure 1A and Figure 2A In the embodiment, the diode string is formed by diodes D1, D2 and D3, each of which is implemented by a p-type block and an n-type block aligned along the Y direction in one of the columns. Specifically, the diodes D1, D2 and D3 are implemented in the first column, the second column and the third column respectively. In some alternative embodiments (e.g. Figure 3 In the embodiment in FIG. 1 , the diode string is formed by diodes D1 and D3 implemented in a first row and a diode D2 implemented in a second row.

[0066] Figure 3 FIG. 1 is a layout diagram of a diode string in an ESD protection circuit according to some embodiments. Figure 3 In the embodiment, the ESD protection circuit 300 includes p-type blocks and n-type blocks arranged in a matrix. The matrix includes a p-type block 311P, an n-type block 312N, a p-type block 313P, and an n-type block 314N arranged along the X direction in the first row. The matrix includes an n-type block 321N, a p-type block 322P, an n-type block 323N, and a p-type block 324P arranged along the X direction in the second row. The p-type block 311P and the n-type block 321N are arranged along the Y direction in the first column. The n-type block 312N and the p-type block 322P are arranged along the Y direction in the second column. The p-type block 313P and the n-type block 323N are arranged along the Y direction in the third column. The n-type block 314N and the p-type block 324P are arranged along the Y direction in the fourth column.

[0067] The first diode D1 is formed between the p-type block 311P and the n-type block 312N. The second diode D2 is formed between the p-type block 322P and the n-type block 323N. The third diode D3 is formed between the p-type block 313P and the n-type block 314N. The n-type block 312N of the first diode D1 and the p-type block 322P of the second diode D2 are conductively connected together through a vertical conductor 3C2 extending along the Y direction. The n-type block 323N of the second diode D2 and the p-type block 313P of the third diode D3 are conductively connected together through a vertical conductor 3C3 extending along the Y direction. Therefore, the first diode D1, the second diode D2, and the third diode D3 are connected in series between the p-type block 311P and the n-type block 314N to form a diode string 380. In some embodiments, when the p-type block 311P is connected to the input pad (e.g., Figure 1B When the input pad 52 in FIG. 1 is connected to the n-type block 314N and the n-type block 314N is connected to the lower power supply voltage VSS, the diode string 380 formed by the diodes D1, D2 and D3 provides ESD protection for the input pad.

[0068] exist Figure 1A and Figure 2A In an exemplary embodiment of the present invention, each p-type block is implemented with two heavily doped p-type regions, and each n-type block is implemented with two heavily doped n-type regions. In some other embodiments, the p-type block is implemented with one heavily doped p-type region. In some other embodiments, the p-type block is implemented with more than two heavily doped p-type regions. In some other embodiments, the n-type block is implemented with one heavily doped n-type region. In some other embodiments, the n-type block is implemented with more than two heavily doped n-type regions.

[0069] FIG. 4A to FIG. 4C is an exemplary implementation of a p-type block used in an ESD protection circuit according to some embodiments. Figure 4A In the example of , the p-type block 411P has two heavily doped p-type regions 411P1 and 411P2. In some embodiments, each heavily doped p-type region in the p-type block is implemented with multiple fingers. Figure 4B In FIG. 4 , the heavily doped p-type region 411P1 of the p-type block 411P has three fingers, and the heavily doped p-type region 411P2 of the p-type block 411P has two fingers. Figure 4C In the example of FIG. 4 , the p-type block 411P has a heavily doped p-type region 411P0 . FIG. 4A to FIG. 4C The implementation of a p-type block in is provided as an example. Similar implementations of n-type blocks are within the contemplated scope of the present disclosure.

[0070] exist Figure 1A and Figure 2AIn the exemplary embodiment of the present invention, the combined number of p-type blocks and n-type blocks in each row of the matrix is ​​3. In some embodiments, the combined number of p-type blocks and n-type blocks in the first row, the second row, the third row, the fourth row, the fifth row, the sixth row, or the seventh row is not limited to 3. In some embodiments, the combined number of p-type blocks and n-type blocks in a row of the matrix is ​​greater than 3. For example, in some embodiments, the combined number of the first row of p-type blocks and the first row of n-type blocks is greater than 3, and the combined number of the second row of p-type blocks and the second row of n-type blocks is also greater than 3.

[0071] Figure 5 is a flow chart of a method 500 of fabricating an integrated circuit according to some embodiments. Figure 5 The order in which the operations of method 500 are depicted is for illustration only; the operations of method 500 may be performed in any order. Figure 5 It should be understood that the Figure 5 Additional operations may be performed before, during, and / or after the illustrated method 500 , and some other processes may only be briefly described herein.

[0072] In operation 510 of method 500, a second type of well is fabricated in a first type of substrate. Figure 1B to Figure 1C and Figure 2C to Figure 2D In the exemplary embodiment of FIG. 2 , an n-type well “NW” is formed in the substrate 20 .

[0073] In operation 520 of method 500, a first type dopant is implanted into the second type well to generate a first type block. Figure 1B to Figure 1C In the exemplary embodiment of FIG. 1 , a p-type dopant is implanted into the n-type well “NW”. A heavily doped p-type region “P+” is generated by the p-type dopant. Due to the heavily doped p-type region “P+”, a p-type block 111P and a p-type block 113P are formed in Figure 1A In the first row of the matrix, and the p-type block 122P is formed in Figure 1A in the second row of the matrix.

[0074] In operation 530 of method 500, a second type dopant is implanted into the second type well to generate a second type block. Figure 1B to Figure 1C In the exemplary embodiment of the present invention, n-type dopants are implanted into the n-type well "NW". A heavily doped n-type region "N+" is generated by the n-type dopant. Due to the heavily doped n-type region "N+", an n-type block 112N is formed in Figure 1A In the first row of the matrix, n-type blocks 121N and 123N are formed in Figure 1A in the second row of the matrix.

[0075] In operations 542, 544, and 546 of method 500, a first diode is formed between a first first-type block and a first second-type block along a first column, a second diode is formed between a second second-type block and a second first-type block along a second column, and a third diode is formed between a third first-type block and a third second-type block along a third column. Figure 1A In an exemplary embodiment of the present invention, a first diode D1 is formed between the p-type block 111P and the n-type block 121N in the first column, a second diode D2 is formed between the n-type block 112N and the p-type block 122P in the second column, and a third diode D3 is formed between the p-type block 113P and the n-type block 123N in the third column. After operations 542, 544, and 546, the process proceeds to operations 550 and 560.

[0076] In operation 550 of method 500, a metal layer is deposited over the second type well. Then, in operation 560 of method 500, a horizontal conductor is formed in the metal layer. Figure 1B to Figure 1C In the exemplary embodiment of FIG. 1 , horizontal conductors 1C1 and 1C2 are formed. Horizontal conductor 1C1 conductively connects n-type block 112N and p-type block 113P. Horizontal conductor 1C2 conductively connects n-type block 121N and p-type block 122P.

[0077] Figure 6 is a block diagram of an electronic design automation (EDA) system 600 according to some embodiments.

[0078] In some embodiments, EDA system 600 includes an automatic place and route (APR) system. The methods of designing floorplans described herein represent routing arrangements according to one or more embodiments, and may be implemented, for example, using EDA system 600 according to some embodiments.

[0079] In some embodiments, the EDA system 600 is a general-purpose computing device including a hardware processor 602 and a non-transitory computer-readable storage medium 604. The storage medium 604 is encoded (i.e., stores) with computer program code 606, i.e., a set of executable instructions. The execution of the instructions 606 by the hardware processor 602 (at least in part) represents an EDA tool that implements part or all of the methods described herein (hereinafter referred to as processes and / or methods) according to one or more embodiments.

[0080] The processor 602 is electrically coupled to the computer readable storage medium 604 via a bus 608. The processor 602 is also electrically coupled to an I / O interface 610 via the bus 608. A network interface 612 is also electrically coupled to the processor 602 via the bus 608. The network interface 612 is connected to a network 614 to enable the processor 602 and the computer readable storage medium 604 to be connected to external components via the network 614. The processor 602 is configured to execute computer program code 606 encoded in the computer readable storage medium 604 so that the system 600 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0081] In one or more embodiments, the computer-readable storage medium 604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 604 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 604 includes compact disk-read only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disc (DVD).

[0082] In one or more embodiments, the storage medium 604 stores computer program code 606 configured to enable the system 600 (where such execution (at least in part) represents an EDA tool) to perform a portion or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 604 also stores information that facilitates the execution of a portion or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 604 stores a standard cell library 607 including such standard cells disclosed herein. In one or more embodiments, the storage medium 604 stores one or more layout drawings 609 corresponding to one or more layouts disclosed herein.

[0083] The EDA system 600 includes an I / O interface 610. The I / O interface 610 is coupled to external circuits. In one or more embodiments, the I / O interface 610 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for communicating information and commands to the processor 602.

[0084] The EDA system 600 also includes a network interface 612 coupled to the processor 602. The network interface 612 allows the system 600 to communicate with a network 614 to which one or more other computer systems are connected. The network interface 612 includes a wireless network interface, such as Bluetooth, wireless fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface, such as Ethernet (ETHERNET), universal serial bus (USB), or Institute of Electrical and Electronic Engineers-1364 (IEEE-1364). In one or more embodiments, part or all of the processes and / or methods described are implemented in two or more systems 600.

[0085] The system 600 is configured to receive information through the I / O interface 610. The information received through the I / O interface 610 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 602. The information is transmitted to the processor 602 via the bus 608. The EDA system 600 is configured to receive information related to a user interface (UI) through the I / O interface 610. This UI information is stored as UI 642 in the computer-readable storage medium 604.

[0086] In some embodiments, some or all of the processes and / or methods are implemented via stand-alone application software executed by a processor. In some embodiments, some or all of the processes and / or methods are implemented in the form of application software that is part of additional application software. In some embodiments, some or all of the processes and / or methods are implemented as plug-ins to the application software. In some embodiments, at least one of the processes and / or methods is implemented as application software that is part of an EDA tool. In some embodiments, some or all of the processes and / or methods are implemented as application software used by an EDA system 600. In some embodiments, a tool (e.g., a computer program product available from Cadence Design Systems, Inc.) is used to create an EDA system 600. or another suitable layout generation tool) to generate a layout diagram including standard cells.

[0087] In some embodiments, these processes are implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as one or more optical disks (e.g., digital video disks or digital versatile disks (DVDs)), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, and the like.

[0088] Figure 7 7 is a block diagram of an integrated circuit (IC) manufacturing system 700 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 700 is used to make at least one of the following: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0089] exist Figure 7In the embodiment of the present invention, the IC manufacturing system 700 includes entities such as a design agency 720, a mask house 730, and an IC manufacturer / fabricator (fab) 750, which interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices 760. The entities in the system 700 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes a wired communication channel and / or a wireless communication channel. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design agency 720, the mask agency 730, and the IC foundry 750 are owned by a single larger company. In some embodiments, two or more of the design agency 720, the mask agency 730, and the IC foundry 750 coexist in a shared facility and use shared resources.

[0090] The design organization (or design team) 720 generates an IC design layout diagram 722. The IC design layout diagram 722 includes various geometric patterns designed for the IC device 760. The geometric patterns correspond to the patterns of the metal layers, oxide layers, or semiconductor layers of the various components that constitute the IC device 760 to be manufactured. Various layers are combined to form various IC components. For example, a portion of the IC design layout diagram 722 includes various IC components to be formed in a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnection, and openings for bonding pads. The design organization 720 implements an appropriate design program to form the IC design layout diagram 722. The design program includes one or more of a logic design, a physical design, or a layout and wiring. The IC design layout diagram 722 is presented in one or more data files having geometric pattern information. For example, the IC design layout diagram 722 can be expressed in a GDSII file format or a DFII file format.

[0091] The mask mechanism 730 includes data preparation 732 and mask production 744. The mask mechanism 730 uses the IC design layout drawing 722 to manufacture one or more masks 745 that will be used to manufacture various layers of the IC device 760 according to the IC design layout drawing 722. The mask mechanism 730 performs mask data preparation 732, and when performing mask data preparation 732, the IC design layout drawing 722 is translated into a representative data file ("representative data file, RDF"). The mask data preparation 732 provides RDF to the mask production 744. The mask production 744 includes a mask writer, which converts the RDF into an image on a substrate, such as a mask (reticle) 745 or a semiconductor wafer 753. The design layout drawing 722 is manipulated by the mask data preparation 732 to comply with the characteristics of the mask writer and / or the requirements of the IC foundry 750. In Figure 7 In FIG. 7 , mask data preparation 732 and mask fabrication 744 are illustrated as separate components. In some embodiments, mask data preparation 732 and mask fabrication 744 may be collectively referred to as mask data preparation.

[0092] In some embodiments, mask data preparation 732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, and the like. OPC adjusts IC design layout 722. In some embodiments, mask data preparation 732 includes further resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution aids, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT), which treats OPC as an inverse imaging problem, is also used.

[0093] In some embodiments, mask data preparation 732 includes a mask rule checker (MRC) that checks the IC design layout 722 that has undergone the process in OPC using a set of mask generation rules containing certain geometric constraints and / or connection constraints to ensure that there is sufficient margin to take into account the variability of semiconductor manufacturing processes and similar factors. In some embodiments, the MRC modifies the IC design layout 722 to compensate for the effects of lithography implementation during mask production 744, which may cancel a portion of the modifications implemented by OPC to meet the mask generation rules.

[0094] In some embodiments, mask data preparation 732 includes lithography process checking (LPC), which simulates the process to be performed by IC foundry 750 to manufacture IC device 760. LPC simulates such process based on IC design layout 722 to generate simulated manufactured devices, such as IC device 760. Process parameters in LPC simulation may include parameters related to various processes of IC manufacturing cycle, parameters related to tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations of the above factors. In some embodiments, after the simulated manufactured device has been generated by LPC, if the shape similarity of the simulated device is not enough to meet the design rules, OPC and / or MRC are repeated to further improve IC design layout 722.

[0095] It should be understood that the above description of mask data preparation 732 has been simplified for clarity. In some embodiments, data preparation 732 includes additional features, such as logic operations (LOPs), to modify IC design layout 722 according to manufacturing rules. In addition, the processes applied to IC design layout 722 during data preparation 732 can be performed in a variety of different orders.

[0096] After the mask data preparation 732 and during the mask production 744, a mask 745 or a set of masks 745 are produced based on the modified IC design layout 722. In some embodiments, the mask production 744 includes performing one or more photolithography exposures based on the IC design layout 722. In some embodiments, an electron-beam (e-beam) or a mechanism consisting of multiple electron beams is used to form a pattern on the mask (reticle or mask plate) 745 based on the modified IC design layout 722. The mask 745 can be formed using various techniques. In some embodiments, the mask 745 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 745 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 745 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 745, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask making 744 is used in various processes. For example, such a mask is used: for an ion implantation process to form various doped regions in the semiconductor wafer 753; for an etching process to form various etched regions in the semiconductor wafer 753; and / or for other suitable processes.

[0097] IC foundry 750 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC foundry 750 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end process manufacturing (FEOL manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end process manufacturing (BEOL manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility may provide other services for the foundry company.

[0098] IC foundry 750 includes fabrication tools 752 configured to perform various fabrication operations on semiconductor wafer 753 such that IC device 760 is fabricated according to a mask, such as mask 745. In various embodiments, fabrication tools 752 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes as discussed herein.

[0099] IC foundry 750 uses mask 745 made by mask mechanism 730 to make IC device 760. Therefore, IC foundry 750 at least indirectly uses IC design layout 722 to make IC device 760. In some embodiments, semiconductor wafer 753 is made by IC foundry 750 using mask 745 to form IC device 760. In some embodiments, IC production includes performing one or more photolithography exposures based at least indirectly on IC design layout 722. Semiconductor wafer 753 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 753 also includes one or more of various doped regions, dielectric components, multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0100] One aspect of the present disclosure is about an integrated circuit. The integrated circuit includes a first horizontal conductor and a second horizontal conductor, each extending in a first direction. The integrated circuit includes a first diode formed between a first first type block and a first second type block, a second diode formed between a second first type block and a second second type block, and a third diode formed between a third first type block and a third second type block. The first first type block and the first second type block are arranged along a second direction perpendicular to the first direction. The second first type block and the second second type block are arranged along the second direction. The third first type block and the third second type block are arranged along the second direction. The second first type block is conductively connected to the first second type block of the first diode through the second horizontal conductor. The third first type block is conductively connected to the second second type block of the second diode through the first horizontal conductor.

[0101] In some embodiments, the first type block includes one or more heavily doped p-type regions, and the second type block includes one or more heavily doped n-type regions. In some embodiments, the first type block includes one or more heavily doped n-type regions, and the second type block includes one or more heavily doped p-type regions. In some embodiments, the first first type block, the second second type block, and the third first type block are arranged along the first direction, and wherein the first second type block, the second first type block, and the third second type block are arranged along the first direction. In some embodiments, the integrated circuit further includes: a third horizontal conductor and a fourth horizontal conductor, each extending along the first direction; a fourth diode formed between the fourth first type block and the fourth second type block arranged along the second direction; a fifth diode formed between the fifth first type block and the fifth second type block arranged along the second direction, wherein the fifth first type block is conductively connected to the fourth second type block of the fourth diode through the third horizontal conductor; and a sixth diode formed between the sixth first type block and the sixth second type block arranged along the second direction, wherein the sixth first type block is conductively connected to the fifth second type block of the fifth diode through the fourth horizontal conductor. In some embodiments, the fourth first type block, the fifth second type block, and the sixth first type block are arranged along the first direction, and wherein the fourth second type block, the fifth first type block, and the sixth second type block are arranged along the first direction. In some embodiments, the fourth second type block is adjacent to the third second type block, the fifth first type block is adjacent to the second first type block, and the sixth second type block is adjacent to the first second type block. In some embodiments, the first first type block, the first second type block, and the sixth second type block are arranged along the second direction and form a first silicon-controlled rectifier, and wherein the fourth first type block, the fourth second type block, and the third second type block are arranged along the second direction and form a second silicon-controlled rectifier. In some embodiments, the integrated circuit further comprises: a third horizontal conductor and a fourth horizontal conductor, each extending in the first direction; a fourth diode formed between a fourth first type block and a fourth second type block arranged in the second direction; a fifth diode formed between a fifth first type block and a fifth second type block arranged in the second direction, wherein the fifth first type block is conductively connected to the fourth second type block of the fourth diode through the third horizontal conductor; and a sixth diode formed between a sixth first type block and a sixth second type block arranged in the second direction, wherein the sixth first type block is conductively connected to the fifth second type block of the fifth diode through the fourth horizontal conductor, wherein the fourth first type block is adjacent to the first second type block, the fifth second type block is adjacent to the second first type block, and the sixth first type block is adjacent to the third second type block. In some embodiments, the fourth first type block, the fifth second type block, and the sixth first type block are arranged in the first direction, and wherein the fourth second type block, the fifth first type block, and the sixth second type block are arranged in the first direction.

[0102] Another aspect of the disclosure is about an integrated circuit. The integrated circuit includes a first row of first type blocks and a first row of second type blocks arranged along a first direction. The integrated circuit also includes a second row of second type blocks and a second row of first type blocks arranged along the first direction. The integrated circuit also includes a first diode formed between the first row of first type blocks and the second row of second type blocks, and a second diode formed between the second row of first type blocks and the first row of second type blocks. The first row of first type blocks and the second row of second type blocks are arranged along a second direction perpendicular to the first direction. The second row of first type blocks and the first row of second type blocks are arranged along the second direction. The integrated circuit also includes a third row of second type blocks and a third row of first type blocks arranged along the first direction. The third row of second type blocks are adjacent to the second row of second type blocks, and the third row of first type blocks are adjacent to the second row of first type blocks. The integrated circuit also includes a fourth row of first type blocks and a fourth row of second type blocks arranged along the first direction. The fourth row of first type blocks are adjacent to the third row of second type blocks, and the fourth row of second type blocks are adjacent to the third row of first type blocks.

[0103] In some embodiments, the fourth row of first type blocks, the third row of second type blocks, the second row of second type blocks and the first row of first type blocks are arranged along the second direction in a column of the matrix, and wherein the fourth row of second type blocks, the third row of first type blocks, the second row of first type blocks and the first row of second type blocks are arranged along the second direction in another column of the matrix. In some embodiments, the integrated circuit further comprises: an input pad, which is conductively connected to the first row of first type blocks, wherein the first row of first type blocks, the second row of second type blocks and the third row of second type blocks form a first silicon-controlled rectifier along the first column of the matrix. In some embodiments, the third row of second type blocks in the first column are configured to be connected to a power supply voltage. In some embodiments, the integrated circuit further comprises: a horizontal conductor, which extends along the first direction and conductively connects the second row of second type blocks of the first diode to the second row of first type blocks of the second diode. In some embodiments, the integrated circuit further comprises: an input pad, which is conductively connected to the fourth row of first type blocks, wherein the fourth row of first type blocks, the third row of second type blocks and the second row of second type blocks form a second silicon-controlled rectifier along the third column of the matrix. In some embodiments, the second row of second type blocks in the third column are configured to be connected to a power supply voltage. In some embodiments, the integrated circuit further includes: a horizontal conductor extending along the first direction and conductively connecting the first row of second-type blocks of the first diodes with the first row of first-type blocks of the second diodes.

[0104] Another aspect of the disclosure is a method of manufacturing an integrated circuit. The method includes making a second-type well in a first-type substrate. The method also includes implanting a first-type dopant into the second-type well to generate a first first-type block in a first row, a second first-type block in a second row, and a third first-type block in the first row. The method also includes implanting a second-type dopant into the second-type well to generate a first second-type block in the second row, a second second-type block in the first row, and a third second-type block in the second row. The first first-type block and the first second-type block are arranged along a first column and a first diode is formed between the first first-type block and the first second-type block. The second second-type block and the second first-type block are arranged along a second column and a second diode is formed between the second second-type block and the second first-type block. The third first-type block and the third second-type block are arranged along a third column and a third diode is formed between the third first-type block and the third second-type block. The method also includes depositing a metal layer over the second-type well and the first-type substrate, forming a first horizontal conductor connecting the second second-type block and the third first-type block, and forming a second horizontal conductor connecting the first second-type block and the second first-type block.

[0105] In some embodiments, the method further comprises connecting the first first-type block to an input pad of the integrated circuit.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. An integrated circuit, characterized in that: include: The first horizontal conductor and the second horizontal conductor each extend along a first direction; A first diode is formed between a first first-type block and a first second-type block arranged along a second direction perpendicular to the first direction; A second diode is formed between a second first-type block and a second second-type block arranged along the second direction, wherein the second first-type block is conductively connected to the first second-type block of the first diode through the second horizontal conductor; as well as The third diode is formed between a third first type block and a third second type block arranged along the second direction, wherein the third first type block is conductively connected to the second second type block of the second diode through the first horizontal conductor.

2. The integrated circuit according to claim 1, characterized in that The first first block, the second second block, and the third first block are arranged along the first direction, and the first second block, the second first block, and the third second block are arranged along the first direction.

3. The integrated circuit according to claim 1, characterized in that Also includes: A third horizontal conductor and a fourth horizontal conductor, each extending along the first direction; a fourth diode formed between a fourth first-type block and a fourth second-type block arranged along the second direction; a fifth diode formed between a fifth first-type block and a fifth second-type block arranged along the second direction, wherein the fifth first-type block is conductively connected to the fourth second-type block of the fourth diode through the third horizontal conductor; and A sixth diode is formed between a sixth first-type block and a sixth second-type block arranged along the second direction, wherein the sixth first-type block is conductively connected to the fifth second-type block of the fifth diode through the fourth horizontal conductor.

4. The integrated circuit according to claim 3, characterized in that The fourth second block is adjacent to the third second block, the fifth first block is adjacent to the second first block, and the sixth second block is adjacent to the first second block.

5. The integrated circuit according to claim 3, characterized in that: The first first type block, the first second type block and the sixth second type block are arranged along the second direction and form a first silicon-controlled rectifier, and wherein the fourth first type block, the fourth second type block and the third second type block are arranged along the second direction and form a second silicon-controlled rectifier.

6. The integrated circuit according to claim 1, characterized in that Also includes: A third horizontal conductor and a fourth horizontal conductor, each extending along the first direction; a fourth diode formed between a fourth first-type block and a fourth second-type block arranged along the second direction; a fifth diode formed between a fifth first-type block and a fifth second-type block arranged along the second direction, wherein the fifth first-type block is conductively connected to the fourth second-type block of the fourth diode through the third horizontal conductor; and a sixth diode formed between a sixth first-type block and a sixth second-type block arranged along the second direction, wherein the sixth first-type block is conductively connected to the fifth second-type block of the fifth diode through the fourth horizontal conductor, The fourth first block is adjacent to the first second block, the fifth second block is adjacent to the second first block, and the sixth first block is adjacent to the third second block.

7. An integrated circuit, characterized in that: include: The first row of first-shaped blocks and the first row of second-shaped blocks are arranged along a first direction; The second row of second-shaped blocks and the second row of first-shaped blocks are arranged along the first direction; A first diode is formed between the first row of first-type blocks and the second row of second-type blocks, wherein the first row of first-type blocks and the second row of second-type blocks are arranged along a second direction perpendicular to the first direction; A second diode is formed between the second row of first type blocks and the first row of second type blocks, wherein the second row of first type blocks and the first row of second type blocks are arranged along the second direction; The third row of second blocks and the third row of first blocks are arranged along the first direction, wherein the third row of second blocks is adjacent to the second row of second blocks, and wherein the third row of first blocks is adjacent to the second row of first blocks; and The fourth row of first blocks and the fourth row of second blocks are arranged along the first direction, wherein the fourth row of first blocks is adjacent to the third row of second blocks, and wherein the fourth row of second blocks is adjacent to the third row of first blocks.

8. The integrated circuit according to claim 7, characterized in that The fourth row of first-type blocks, the third row of second-type blocks, the second row of second-type blocks, and the first row of first-type blocks are arranged along the second direction in a column of a matrix, and wherein the fourth row of second-type blocks, the third row of first-type blocks, the second row of first-type blocks, and the first row of second-type blocks are arranged along the second direction in another column of the matrix.

9. The integrated circuit according to claim 7, characterized in that: Also includes: An input pad is conductively connected to the first row of first-type blocks, wherein the first row of first-type blocks, the second row of second-type blocks and the third row of second-type blocks form a first silicon-controlled rectifier along a first column of the matrix.

10. The integrated circuit according to claim 9, characterized in that Also includes: The horizontal conductor extends along the first direction and conductively connects the second-row second-type blocks of the first diodes with the second-row first-type blocks of the second diodes.

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