Low-power-consumption pipeline cathode protection circuit

Abstract

The utility model discloses a low-power-consumption pipeline cathode protection circuit, which is characterized by comprising a power supply unit, a sensing unit, a CPU (central processing unit) and a communication unit, the sensing unit is connected with the CPU, and the CPU is connected with the communication unit; the power supply unit comprises a clock wake-up circuit, a battery parallel circuit, a CPU power supply circuit and a sensing communication power supply circuit; the battery parallel circuit is connected with the CPU power supply circuit, the CPU power supply circuit is connected with the CPU, and the CPU power supply circuit is connected with the clock wake-up circuit; the battery parallel circuit is connected with the power supply end of the sensing communication power supply circuit, the sensing communication power supply circuit is connected with the power supply end of the sensing unit, and the sensing communication power supply circuit is also connected with the power supply end of the communication unit; the clock wake-up circuit is provided with a clock chip U101, and an INT1 port of the clock chip U101 is connected with a wake-up end PA3 of the CPU; the sensing communication power supply circuit is provided with a sensing communication wake-up port, a sensing switching port and a communication switching port. The beneficial effect of the utility model is that the standby energy consumption and the operation energy consumption can be effectively reduced.

Description

Technical Field

[0001] The utility model relates to the anti-corrosion field of cathode protection of metal pipelines, in particular to a low-power pipeline cathode protection circuit. Background Art

[0002] Cathodic protection is to apply an external current to the surface of the corroded metal structure, so that the protected structure becomes the cathode, thereby inhibiting the electron migration caused by metal corrosion and avoiding or reducing the occurrence of corrosion.

[0003] Cathodic protection terminals are generally located outdoors, but outdoor IoT terminals are difficult to maintain, which places stringent requirements on the power consumption of IoT terminals. Therefore, on the premise of meeting various functions, how to reduce the normal working current and standby current of the terminal has great practical value for pipeline cathodic protection terminals. Utility Model Content

[0004] The utility model is a low-power pipeline cathode protection circuit, which can greatly reduce its standby current and operating current while ensuring the normal operation of its basic functions.

[0005] To achieve the above purpose, a low-power pipeline cathode protection circuit has a technical solution: including a power supply unit, a sensor unit, a CPU, and a communication unit, wherein the sensor unit is connected to the CPU, and the CPU is connected to the communication unit; the power supply unit includes a clock wake-up circuit, a battery parallel circuit, a CPU power supply circuit, and a sensor communication power supply circuit;

[0006] The battery parallel circuit is connected to the CPU power circuit, the CPU power circuit is connected to the CPU, and the CPU power circuit is connected to the clock wake-up circuit;

[0007] The battery parallel circuit is connected to the power supply terminal of the sensing communication power supply circuit, the sensing communication power supply circuit is connected to the power supply terminal of the sensing unit, and the sensing communication power supply circuit is also connected to the power supply terminal of the communication unit;

[0008] The clock wake-up circuit is provided with a clock chip U101, and the INT1 port of the clock chip U101 is connected to the wake-up terminal PA3 of the CPU;

[0009] The sensor communication power supply circuit is provided with a sensor communication wake-up port, a sensor switching port and a communication switching port. The PA4 port of the CPU is connected to the sensor communication wake-up port, the PA5 port of the CPU is connected to the sensor switching port, and the PA6 port of the CPU is connected to the communication switching port.

[0010] The CPU is woken up regularly through the clock wake-up circuit, and then the CPU wakes up the sensor communication power supply circuit. After the sensor communication power supply circuit is woken up, the sensor unit or the communication unit is powered on, so as to ensure ultra-low power consumption in standby mode; the CPU power supply circuit does not require a large power supply current. Although the sensor communication power supply circuit needs to supply a large current, the power consumption is slightly higher only when it is used normally after being woken up. The separate design of the two further ensures ultra-low power standby mode; at the same time, the power supply of the sensor unit or the communication unit is switched through the sensor switching port and the communication switching port, so that only one power chip can be used to realize time-sharing power supply to the sensor unit or the communication unit, so as to save hardware costs, and the time-sharing power supply has a smaller total current demand at the same time, lower requirements for total power supply, and better applicability.

[0011] Furthermore, the battery parallel circuit includes a battery BAT102 and a battery BAT103, the negative electrode of the battery BAT103 is grounded, the positive electrode of the battery BAT103 is connected to the positive electrode of the diode D104, the negative electrode of the diode D104 is the total power supply terminal VBIN, and the total power supply terminal VBIN is connected to the sensor communication power supply circuit;

[0012] The negative electrode of the battery BAT102 is grounded, the positive electrode of the battery BAT102 is connected to the drain of the switch tube Q101, the source of the switch tube Q101 is connected to the positive electrode of the diode D103, the negative electrode of the diode D103 is connected to the main power supply terminal VBIN, and the gate of the switch tube Q101 is connected to the CPU.

[0013] The battery BAT103 provides basic power for the CPU and clock wake-up circuit. When the sensing unit or the communication unit needs power, the battery BAT102 is connected, thereby improving the power supply efficiency.

[0014] Furthermore, the CPU power supply circuit is provided with a power supply chip U102, a VIN port of the power supply chip U102 is connected to the main power supply terminal VBIN, and the VIN port of the power supply chip U102 is also connected to the EN port of the power supply chip U102;

[0015] The VIN port of the power chip U102 is connected to ground via a capacitor C106 in series, the VIN port of the power chip U102 is connected to ground via a capacitor C104 in series, and the GND port of the power chip U102 is connected to ground;

[0016] The SW port of the power chip U102 is connected to the front end of the inductor L101, the rear end of the inductor L101 is the power terminal V_CPU, the power terminal V_CPU is connected to the front end of the resistor R105, the rear end of the resistor R105 is connected to the front end of the resistor R106, the rear end of the resistor R106 is grounded, and the common end of the resistor R105 and the resistor R106 is connected to the voltage feedback terminal FB of the power chip U102; the power terminal V_CPU is connected to the CPU and the clock wake-up circuit;

[0017] The power supply terminal V_CPU is connected to the front end of the capacitor C103, and the rear end of the capacitor C103 is connected to the voltage feedback terminal FB of the power supply chip U102; the power supply terminal V_CPU is connected to the front end of the resistor R107, and the front end of the resistor R107 is connected to the VOUT port of the power supply chip U102, the front end of the resistor R107 is connected to the SGND port of the power supply chip U102, and the rear end of the resistor R107 is connected to the PG port of the power supply chip U102;

[0018] The power supply terminal V_CPU is connected to the VDDIO_2 port and the Vref+ port of the CPU, and the VSSIO_2 port and the Vref- port of the CPU are grounded.

[0019] The power supply terminal V_CPU supplies power to the CPU and serves as a reference voltage for the CPU analog input signal. Since the power supply terminal V_CPU has low power consumption, small voltage fluctuation and high precision, the accuracy of CPU sampling is guaranteed.

[0020] Furthermore, the power supply terminal V_CPU is connected to the anode of the diode D101, and the cathode of the diode D101 is connected to the VDD port of the clock chip U101;

[0021] The power supply terminal V_CPU is connected to the front end of the resistor R101, the rear end of the resistor R101 is connected to the SDA port of the clock chip U101, and the SDA port of the clock chip U101 is connected to the PH2 port of the CPU;

[0022] The power supply terminal V_CPU is connected to the front end of the resistor R103, the rear end of the resistor R103 is connected to the SCL port of the clock chip U101, and the SCL port of the clock chip U101 is connected to the PH3 port of the CPU;

[0023] The power supply terminal V_CPU is connected to the front end of the resistor R102, and the rear end of the resistor R102 is connected to the INT1 port of the clock chip U101.

[0024] The clock chip U101 communicates with the CPU through the SDA port and SCL port, and wakes up the CPU through the INT1 port of the clock chip U101. At the same time, the power supply terminal V_CPU provides pull-up power for the SDA port, SCL port and INT1 port of the clock chip U101, and the diode D101 ensures that the clock chip is not limited to being powered by the power supply terminal V_CPU.

[0025] Furthermore, the clock wake-up circuit is provided with a battery BAT101, the negative electrode of the battery BAT101 is grounded, the positive electrode of the battery BAT101 is connected to the front end of the resistor R104, the rear end of the resistor R104 is connected to the positive electrode of the diode D102, the negative electrode of the diode D102 is connected to the VDD port of the clock chip U101, the VDD port of the clock chip U101 is connected to the positive electrode of the capacitor C102, and the negative electrode of the capacitor C102 is grounded;

[0026] The XOUT port of the clock chip U101 is connected to the front end of the crystal oscillator G101, the back end of the crystal oscillator G101 is connected to the XIN port of the clock chip U101, the back end of the crystal oscillator G101 is grounded, and the GND port of the clock chip U101 is grounded.

[0027] The clock chip is redundantly powered by battery BAT101, ensuring long-term stable operation of the clock chip, while diode D102 ensures that multiple power supplies of the clock chip do not affect each other.

[0028] Furthermore, the sensor communication power supply circuit is provided with a power supply chip U103, the total power supply terminal VBIN is connected to the VIN port of the power supply chip U103, the SW port of the power supply chip U103 is connected to the front end of the inductor L102, the rear end of the inductor L102 is connected to the drain of the switch tube Q102, the source of the switch tube Q102 is the power supply terminal V_AD, the power supply terminal V_AD is connected to the front end of the resistor R111, the rear end of the resistor R111 is connected to the front end of the resistor R109, the rear end of the resistor R109 is grounded, and the common end of the resistor R111 and the resistor R109 is connected to the voltage feedback terminal FB of the power supply chip U103;

[0029] The rear end of the inductor L102 is connected to the drain of the switch tube Q103, the source of the switch tube Q103 is the power supply terminal V_COM, the power supply terminal V_COM is connected to the front end of the resistor R112, and the rear end of the resistor R112 is connected to the front end of the resistor R109;

[0030] The gate of the switch tube Q102 is connected to the sensing switching port, the source of the switch tube Q102 is connected to the power supply terminal V_AD, and the power supply terminal V_AD is connected to the sensing unit;

[0031] The gate of the switch tube Q103 is connected to the communication switching port, the source of the switch tube Q103 is connected to the power supply terminal V_COM, and the power supply terminal V_COM is connected to the communication unit;

[0032] The EN port of the power chip U103 is connected to the rear end of the resistor R110, and the front end of the resistor R110 is connected to the sensor communication wake-up port;

[0033] The VIN port of the power chip U103 is connected in series with capacitor C110 and then grounded, the VIN port of the power chip U103 is connected in series with capacitor C111 and then grounded, the SW port of the power chip U103 is connected to the front end of capacitor C107, the rear end of capacitor C107 is connected to the front end of resistor R108, the rear end of resistor R108 is connected to the VBST port of the power chip U103, the rear end of the inductor L102 is connected in series with capacitor C108 and then connected to the front end of resistor R109, the rear end of the inductor L102 is connected in series with capacitor C109 and then grounded, and the GND port of the power chip U103 is grounded.

[0034] By controlling the sensor communication wake-up port through the CPU, the wake-up control of the power chip U103 is realized. By controlling the sensor switching port and the communication switching port through the CPU, the power chip U103 obtains different feedbacks and then outputs different voltages to power the sensor unit or the communication unit.

[0035] Furthermore, the sensing unit is provided with a sampling terminal group and an AI chip U301, and the sampling terminal group is provided with a port YYJD, a port YJD, a port CBD, a port TEST1, and a port TEST2;

[0036] Port YYJD is connected to the front end of resistor R301, the rear end of resistor R301 is connected to the front end of resistor R302, and the rear end of resistor R302 is connected to the AIN6+ port of AI chip U301;

[0037] Port CBD is connected to the front end of resistor R303, the rear end of resistor R303 is connected to the front end of resistor R304, and the rear end of resistor R304 is connected to AIN6- port of AI chip U301;

[0038] Port YYJD is connected in series with bidirectional diode TV301 and then to port CBD; the rear end of resistor R301 is connected in series with capacitor C307 and then to the rear end of resistor R303; the rear end of resistor R302 is connected in series with capacitor C308 and then to the rear end of resistor R304; the rear end of resistor R301 is connected in series with capacitor C302 and then to ground; the rear end of resistor R302 is connected in series with capacitor C303 and then to ground; the rear end of resistor R303 is connected in series with capacitor C309 and then to ground; the rear end of resistor R304 is connected in series with capacitor C310 and then to ground;

[0039] Port YJD is connected to the front end of resistor R305, the rear end of resistor R305 is connected to the front end of resistor R306, and the rear end of resistor R306 is connected to the AIN1+ port of AI chip U301;

[0040] Port CBD is connected to the front end of resistor R307, the rear end of resistor R307 is connected to the front end of resistor R308, and the rear end of resistor R308 is connected to AIN1- port of AI chip U301;

[0041] Port YJD is connected to port CBD in series with bidirectional diode TV302, the rear end of resistor R305 is connected to the rear end of resistor R307 in series with capacitor C313, the rear end of resistor R306 is connected to the rear end of resistor R308 in series with capacitor C314, the rear end of resistor R305 is connected to ground in series with capacitor C311, the rear end of resistor R306 is connected to ground in series with capacitor C312, the rear end of resistor R307 is connected to ground in series with capacitor C315, and the rear end of resistor R308 is connected to ground in series with capacitor C316;

[0042] Port TEST1 is connected to the front end of resistor R310, the rear end of resistor R310 is connected to the front end of resistor R311, and the rear end of resistor R311 is connected to the AIN2+ port of AI chip U301;

[0043] Port CBD is connected to the front end of resistor R315, the rear end of resistor R315 is connected to the front end of resistor R316, and the rear end of resistor R316 is connected to AIN2- port of AI chip U301;

[0044] The port TEST1 is connected to the port CBD via a bidirectional diode TV303 in series, the rear end of the resistor R310 is connected to the rear end of the resistor R315 via a capacitor C321 in series, the rear end of the resistor R311 is connected to the rear end of the resistor R316 via a capacitor C322 in series, the rear end of the resistor R310 is connected to ground via a capacitor C319 in series, the rear end of the resistor R311 is connected to ground via a capacitor C320 in series, the rear end of the resistor R315 is connected to ground via a capacitor C323 in series, and the rear end of the resistor R316 is connected to ground via a capacitor C324 in series;

[0045] Port YJD is connected to the front end of resistor R318, the rear end of resistor R318 is connected to the front end of resistor R319, and the rear end of resistor R319 is connected to the AIN3+ port of AI chip U301;

[0046] Port YYJD is connected to the front end of resistor R322, the rear end of resistor R322 is connected to the front end of resistor R323, and the rear end of resistor R323 is connected to AIN3- port of AI chip U301;

[0047] The port YJD is connected to the port YYJD in series with the bidirectional diode TV305, the rear end of the resistor R318 is connected to the rear end of the resistor R322 in series with the capacitor C334, the rear end of the resistor R319 is connected to the rear end of the resistor R323 in series with the capacitor C335, the rear end of the resistor R318 is connected to the ground, the rear end of the resistor R319 is connected to the ground, the rear end of the resistor R319 is connected to the ground, the rear end of the resistor R322 is connected to the ground, and the rear end of the resistor R323 is connected to the ground.

[0048] Port TEST2 is connected to the front end of resistor R320, the rear end of resistor R320 is connected to the front end of resistor R321, and the rear end of resistor R321 is connected to the AIN4+ port of AI chip U301;

[0049] Port CBD is connected to the front end of resistor R324, the rear end of resistor R324 is connected to the front end of resistor R325, and the rear end of resistor R325 is connected to AIN4- port of AI chip U301;

[0050] The port TEST2 is connected to the port CBD in series with the bidirectional diode TV306, the rear end of the resistor R320 is connected to the rear end of the resistor R324 in series with the capacitor C336, the rear end of the resistor R324 is connected to the rear end of the resistor R325 in series with the capacitor C337, the rear end of the resistor R320 is connected to the ground in series with the capacitor C332, the rear end of the resistor R321 is connected to the ground in series with the capacitor C333, the rear end of the resistor R324 is connected to the ground in series with the capacitor C340, and the rear end of the resistor R325 is connected to the ground in series with the capacitor C341;

[0051] The total power supply terminal VBIN is connected to the front end of the resistor R312, the rear end of the resistor R312 is connected to the front end of the resistor R317, the rear end of the resistor R317 is grounded, the common end of the resistor R312 and the resistor R317 is connected to the front end of the resistor R313, the rear end of the resistor R313 is connected to the front end of the resistor R134, the rear end of the resistor R314 is connected to the AIN5+ port of the AI ​​chip U301, and the AIN5- port of the AI ​​chip U301 is grounded; the front end of the resistor R313 is connected in series with a bidirectional diode TV304 and then grounded, the rear end of the resistor R313 is connected in series with a capacitor C326 and then grounded, and the rear end of the resistor R314 is connected in series with a capacitor C325 and then grounded;

[0052] The SCLK port of the AI ​​chip U301 is connected to the PF7 port of the CPU, the DIN port of the AI ​​chip U301 is connected to the PF6 port of the CPU, and the DOUT port of the AI ​​chip U301 is connected to the PF5 port of the CPU.

[0053] The bidirectional diodes VT301-VT306 are used to ensure that the voltage collected by each channel of the AI ​​chip U301 does not exceed the range; the resistor and capacitor combination before each AI channel can filter the sampling signal to ensure the stability and accuracy of the sampling signal; the AI ​​chip U301 performs voltage division sampling on the main power supply terminal VBIN to determine the state of the main power supply terminal VBIN; the SCLK port, DIN port and DOUT port of the AI ​​chip U301 are connected to the CPU to ensure data communication between the CPU and the AI ​​chip U301.

[0054] Furthermore, the sensing unit is provided with a reference voltage chip U302, the power supply terminal V_AD is connected to the AV+ port of the AI ​​chip U301, the GND port of the AI ​​chip U301 is grounded, the DV+ port of the AI ​​chip U301 is the power supply terminal AD_VCC, the power supply terminal AD_VCC is connected to the VIN port of the reference voltage chip U302, the VOUT port of the reference voltage chip U302 is connected to the REF+ port of the AI ​​chip U301; the REF- port of the AI ​​chip U301 is grounded;

[0055] The VIN port of the reference voltage chip U302 is connected to the front end of the resistor R309, the VOUT port of the reference voltage chip U302 is connected to the back end of the resistor R309, the VIN port of the reference voltage chip U302 is connected to ground via a series capacitor C317, the VOUT port of the reference voltage chip U302 is connected to ground via a series capacitor C318, the power supply terminal AD_VCC is connected to ground via a series capacitor C305, the REF+ port of the AI ​​chip U301 is connected to ground via a series capacitor C306; the power supply terminal AD_VCC is connected to the PF4 port of the CPU.

[0056] A special reference voltage chip U302 provides a high-precision reference voltage signal to the AI ​​chip U301 to ensure the accuracy of the AI ​​chip U301 when converting analog quantities to digital quantities. At the same time, the CPU collects the voltage of the power supply terminal AD_VCC to determine whether the output voltage of the AI ​​chip U301 is normal and whether the reference voltage chip U302 is working normally.

[0057] Furthermore, the sensing unit is provided with a relay J401, a relay J402 and a relay J403;

[0058] The power supply terminal V_AD is connected to the coil of the relay J401 in series, and then connected to the collector of the transistor Q401. The emitter of the transistor Q401 is grounded. The base of the transistor Q401 is connected to the rear end of the resistor R401. The front end of the resistor R401 is connected to the PB3 port of the CPU. Two contacts in a group of normally closed switches of the relay J401 are connected to the port YYJD and the port TEST1 respectively.

[0059] The power supply terminal V_AD is connected to the coil of the relay J402 in series, and then connected to the collector of the transistor Q402. The emitter of the transistor Q402 is grounded. The base of the transistor Q402 is connected to the rear end of the resistor R402. The front end of the resistor R402 is connected to the PB2 port of the CPU. Two contacts in a group of normally closed switches of the relay J402 are connected to the port YYJD and the port YJD respectively.

[0060] The coil of relay J403 in series with the power supply terminal V_AD is connected to the collector of transistor Q403, the emitter of transistor Q403 is grounded, the base of transistor Q403 is connected to the rear end of resistor R403, and the front end of resistor R403 is connected to the PB1 port of CPU; two contacts in a group of normally closed switches of relay J403 are respectively connected to port YJD and the front end of resistor RZ401; the rear end of resistor RZ401 is connected to port YYJD.

[0061] By controlling relays J401-J403 through the CPU, the state control of the power-on potential, open-circuit potential, open-circuit potential, protection current and natural potential is realized to ensure that the collected signal corresponds to the corresponding short-circuit state; transistors Q401-Q403 ensure the isolation of the CPU control signal and the relay, and the coil of the relay is powered by the power supply terminal V_AD, which not only ensures the normal operation of the relay, but also has no power loss in standby mode.

[0062] Furthermore, the communication unit is provided with a communication chip U201 and a SIM card chip U202;

[0063] The power supply terminal V_COM is connected to the BAT port of the communication chip U201, the GND port of the communication chip U201 is grounded, the PG6 port of the CPU is connected to the front end of the resistor R201, the rear end of the resistor R201 is connected to the front end of the resistor R202, the rear end of the resistor R202 is grounded, the common end of the resistor R201 and the resistor R202 is connected to the base of the transistor Q201, the collector of the transistor Q201 is connected to the PWRKEY port of the communication chip U201, and the emitter of the transistor Q201 is grounded;

[0064] The TXD port of the communication chip U201 is connected to the front end of the resistor R204, the rear end of the resistor R204 is connected to the PD6 port of the CPU, the PD7 port of the CPU is connected to the front end of the resistor R203, the rear end of the resistor R203 is connected to the front end of the resistor R205, the rear end of the resistor R205 is grounded, and the common end of the resistor R203 and the resistor R205 is connected to the RXD port of the communication chip U201;

[0065] The SIM_VDD port of the communication chip U201 is connected to the VCC port of the SIM card chip U202, the SIM_RST port of the communication chip U201 is connected to the RST port of the SIM card chip U202, the SIM_CLK port of the communication chip U201 is connected to the CLK port of the SIM card chip U202, the SIM_DATA port of the communication chip U201 is connected to the IO port of the SIM card chip U202, the SIM_VDD port of the communication chip U201 is connected to the front end of the resistor R209, the rear end of the resistor R209 is connected to the IO port of the SIM card chip U202, the GND port of the SIM card chip U202 is grounded, the SIM_VDD port of the communication chip U201 is connected to ground in series with the capacitor C204, and the SIM_VDD port of the communication chip U201 is connected to ground in series with the capacitor C205;

[0066] The AVDD port of the communication chip U201 is connected to the front end of the resistor R207, the rear end of the resistor R207 is connected to the front end of the resistor R208, the rear end of the resistor R208 is grounded, the common end of the resistor R207 and the resistor R208 is connected to the ADC0 port of the communication chip U201, and the common end of the resistor R207 and the resistor R208 is connected in series with the capacitor C206 and then grounded;

[0067] The power supply terminal V_COM is connected to the positive electrode of the light-emitting diode D201, the negative electrode of the light-emitting diode D201 is connected to the front end of the resistor R210, the rear end of the resistor R210 is connected to the collector of the transistor Q202, the emitter of the transistor Q202 is grounded, the STATUS port of the communication chip U201 is connected to the front end of the resistor R214, the rear end of the resistor R214 is connected to the front end of the resistor R213, and the common end of the resistor R214 and the resistor R213 is connected to the base of the transistor Q202;

[0068] The power supply terminal V_COM is connected to the positive electrode of the light-emitting diode D202, the negative electrode of the light-emitting diode D202 is connected to the front end of the resistor R211, the rear end of the resistor R211 is connected to the collector of the transistor Q203, the emitter of the transistor Q203 is grounded, the NETLIGHT port of the communication chip U201 is connected to the front end of the resistor R216, the rear end of the resistor R216 is connected to the front end of the resistor R215, and the common end of the resistor R216 and the resistor R215 is connected to the base of the transistor Q203;

[0069] The power supply terminal V_COM is connected to ground via a series capacitor C201, the power supply terminal V_COM is connected to ground via a series capacitor C202, and the VRTC port of the communication chip U201 is connected to ground via a series capacitor C203.

[0070] By controlling the PG6 port of the CPU, the power on and off of the communication chip U201 is controlled; data communication with the CPU is achieved through the RXD port and TXD port of the communication chip U201; the status and network judgment of the communication chip U201 are achieved through the light-emitting diodes D201 and D202; the normal operation of the remote wireless communication is guaranteed through the connection between the SIM card chip U202 and the communication chip U201.

[0071] The benefits of the utility model are as follows: it can sample and control the pipeline cathodic protection status and transmit information, ensure the normal operation of its basic functions, and greatly reduce its standby current and operating current; the CPU is awakened regularly by the clock awakening circuit to ensure that the CPU performs data collection and remote communication only when needed; the CPU controls the awakening and time-sharing output of the sensor communication power supply circuit, which not only saves hardware costs but also reduces power supply requirements; the battery parallel circuit ensures that the battery BAT102 is connected only when the sensor unit or communication unit requires a large current for normal operation, thereby ensuring power supply efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 Main connection diagram;

[0073] Figure 2 This is the schematic diagram of the power supply unit;

[0074] Figure 3 This is the CPU schematic diagram;

[0075] Figure 4 It is the schematic diagram of the sensor unit relay;

[0076] Figure 5 This is the sampling schematic diagram of the sensing unit;

[0077] Figure 6 This is the schematic diagram of the communication unit. DETAILED DESCRIPTION

[0078] The utility model is further described below in conjunction with embodiments and drawings.

[0079] Embodiment 1

[0080] like Figure 1 As shown, a low-power pipeline cathode protection circuit includes a power supply unit, a sensor unit, a CPU, and a communication unit. The sensor unit is connected to the CPU, and the CPU is connected to the communication unit. The power supply unit includes a clock wake-up circuit, a battery parallel circuit, a CPU power supply circuit, and a sensor communication power supply circuit.

[0081] The battery parallel circuit is connected to the CPU power circuit, the CPU power circuit is connected to the CPU, and the CPU power circuit is connected to the clock wake-up circuit;

[0082] The battery parallel circuit is connected to the power supply terminal of the sensing communication power supply circuit, the sensing communication power supply circuit is connected to the power supply terminal of the sensing unit, and the sensing communication power supply circuit is also connected to the power supply terminal of the communication unit;

[0083] like Figure 2 and Figure 3 As shown, the battery parallel circuit includes a battery BAT102 and a battery BAT103, the negative electrode of the battery BAT103 is grounded, the positive electrode of the battery BAT103 is connected to the positive electrode of the diode D104, and the negative electrode of the diode D104 is the total power supply terminal VBIN, and the total power supply terminal VBIN is connected to the sensor communication power supply circuit;

[0084] The negative electrode of the battery BAT102 is grounded, the positive electrode of the battery BAT102 is connected to the drain of the switch tube Q101, the source of the switch tube Q101 is connected to the positive electrode of the diode D103, the negative electrode of the diode D103 is connected to the main power supply terminal VBIN, and the gate of the switch tube Q101 is connected to the PC1 port of the CPU.

[0085] The CPU power supply circuit is provided with a power supply chip U102, the VIN port of the power supply chip U102 is connected to the main power supply terminal VBIN, and the VIN port of the power supply chip U102 is also connected to the EN port of the power supply chip U102;

[0086] The VIN port of the power chip U102 is connected to ground via a capacitor C106 in series, the VIN port of the power chip U102 is connected to ground via a capacitor C104 in series, and the GND port of the power chip U102 is connected to ground;

[0087] The SW port of the power chip U102 is connected to the front end of the inductor L101, the rear end of the inductor L101 is the power terminal V_CPU, the power terminal V_CPU is connected to the front end of the resistor R105, the rear end of the resistor R105 is connected to the front end of the resistor R106, the rear end of the resistor R106 is grounded, and the common end of the resistor R105 and the resistor R106 is connected to the voltage feedback terminal FB of the power chip U102; the power terminal V_CPU is connected to the CPU and the clock wake-up circuit;

[0088] The power supply terminal V_CPU is connected to the front end of the capacitor C103, and the rear end of the capacitor C103 is connected to the voltage feedback terminal FB of the power supply chip U102; the power supply terminal V_CPU is connected to the front end of the resistor R107, and the front end of the resistor R107 is connected to the VOUT port of the power supply chip U102, the front end of the resistor R107 is connected to the SGND port of the power supply chip U102, and the rear end of the resistor R107 is connected to the PG port of the power supply chip U102;

[0089] The power supply terminal V_CPU is connected to the VDDIO_2 port and the Vref+ port of the CPU, and the VSSIO_2 port and the Vref- port of the CPU are grounded.

[0090] The clock wake-up circuit is provided with a clock chip U101, and the INT1 port of the clock chip U101 is connected to the wake-up terminal PA3 of the CPU;

[0091] The power supply terminal V_CPU is connected to the anode of the diode D101, and the cathode of the diode D101 is connected to the VDD port of the clock chip U101;

[0092] The power supply terminal V_CPU is connected to the front end of the resistor R101, the rear end of the resistor R101 is connected to the SDA port of the clock chip U101, and the SDA port of the clock chip U101 is connected to the PH2 port of the CPU;

[0093] The power supply terminal V_CPU is connected to the front end of the resistor R103, the rear end of the resistor R103 is connected to the SCL port of the clock chip U101, and the SCL port of the clock chip U101 is connected to the PH3 port of the CPU;

[0094] The power supply terminal V_CPU is connected to the front end of the resistor R102, and the rear end of the resistor R102 is connected to the INT1 port of the clock chip U101.

[0095] The clock wake-up circuit is provided with a battery BAT101, the negative electrode of the battery BAT101 is grounded, the positive electrode of the battery BAT101 is connected to the front end of the resistor R104, the rear end of the resistor R104 is connected to the positive electrode of the diode D102, the negative electrode of the diode D102 is connected to the VDD port of the clock chip U101, the VDD port of the clock chip U101 is connected to the positive electrode of the capacitor C102, and the negative electrode of the capacitor C102 is grounded;

[0096] The XOUT port of the clock chip U101 is connected to the front end of the crystal oscillator G101, the back end of the crystal oscillator G101 is connected to the XIN port of the clock chip U101, the back end of the crystal oscillator G101 is grounded, and the GND port of the clock chip U101 is grounded.

[0097] The sensor communication power supply circuit is provided with a sensor communication wake-up port, a sensor switching port and a communication switching port. The PA4 port of the CPU is connected to the sensor communication wake-up port, the PA5 port of the CPU is connected to the sensor switching port, and the PA6 port of the CPU is connected to the communication switching port.

[0098] The sensor communication power supply circuit is provided with a power supply chip U103, the total power supply terminal VBIN is connected to the VIN port of the power supply chip U103, the SW port of the power supply chip U103 is connected to the front end of the inductor L102, the rear end of the inductor L102 is connected to the drain of the switch tube Q102, the source of the switch tube Q102 is the power supply terminal V_AD, the power supply terminal V_AD is connected to the front end of the resistor R111, the rear end of the resistor R111 is connected to the front end of the resistor R109, the rear end of the resistor R109 is grounded, and the common end of the resistor R111 and the resistor R109 is connected to the voltage feedback terminal FB of the power supply chip U103;

[0099] The rear end of the inductor L102 is connected to the drain of the switch tube Q103, the source of the switch tube Q103 is the power supply terminal V_COM, the power supply terminal V_COM is connected to the front end of the resistor R112, and the rear end of the resistor R112 is connected to the front end of the resistor R109;

[0100] The gate of the switch tube Q102 is connected to the sensing switching port, the source of the switch tube Q102 is connected to the power supply terminal V_AD, and the power supply terminal V_AD is connected to the sensing unit;

[0101] The gate of the switch tube Q103 is connected to the communication switching port, the source of the switch tube Q103 is connected to the power supply terminal V_COM, and the power supply terminal V_COM is connected to the communication unit;

[0102] The EN port of the power chip U103 is connected to the rear end of the resistor R110, and the front end of the resistor R110 is connected to the sensor communication wake-up port;

[0103] The VIN port of the power chip U103 is connected in series with capacitor C110 and then grounded, the VIN port of the power chip U103 is connected in series with capacitor C111 and then grounded, the SW port of the power chip U103 is connected to the front end of capacitor C107, the rear end of capacitor C107 is connected to the front end of resistor R108, the rear end of resistor R108 is connected to the VBST port of the power chip U103, the rear end of the inductor L102 is connected in series with capacitor C108 and then connected to the front end of resistor R109, the rear end of the inductor L102 is connected in series with capacitor C109 and then grounded, and the GND port of the power chip U103 is grounded.

[0104] like Figure 5 As shown, the sensing unit is provided with a sampling terminal group and an AI chip U301, and the sampling terminal group is provided with a port YYJD, a port YJD, a port CBD, a port TEST1 and a port TEST2;

[0105] Port YYJD is connected to the front end of resistor R301, the rear end of resistor R301 is connected to the front end of resistor R302, and the rear end of resistor R302 is connected to the AIN6+ port of AI chip U301;

[0106] Port CBD is connected to the front end of resistor R303, the rear end of resistor R303 is connected to the front end of resistor R304, and the rear end of resistor R304 is connected to AIN6- port of AI chip U301;

[0107] Port YYJD is connected in series with bidirectional diode TV301 and then to port CBD; the rear end of resistor R301 is connected in series with capacitor C307 and then to the rear end of resistor R303; the rear end of resistor R302 is connected in series with capacitor C308 and then to the rear end of resistor R304; the rear end of resistor R301 is connected in series with capacitor C302 and then to ground; the rear end of resistor R302 is connected in series with capacitor C303 and then to ground; the rear end of resistor R303 is connected in series with capacitor C309 and then to ground; the rear end of resistor R304 is connected in series with capacitor C310 and then to ground;

[0108] Port YJD is connected to the front end of resistor R305, the rear end of resistor R305 is connected to the front end of resistor R306, and the rear end of resistor R306 is connected to the AIN1+ port of AI chip U301;

[0109] Port CBD is connected to the front end of resistor R307, the rear end of resistor R307 is connected to the front end of resistor R308, and the rear end of resistor R308 is connected to AIN1- port of AI chip U301;

[0110] Port YJD is connected to port CBD in series with bidirectional diode TV302, the rear end of resistor R305 is connected to the rear end of resistor R307 in series with capacitor C313, the rear end of resistor R306 is connected to the rear end of resistor R308 in series with capacitor C314, the rear end of resistor R305 is connected to ground in series with capacitor C311, the rear end of resistor R306 is connected to ground in series with capacitor C312, the rear end of resistor R307 is connected to ground in series with capacitor C315, and the rear end of resistor R308 is connected to ground in series with capacitor C316;

[0111] Port TEST1 is connected to the front end of resistor R310, the rear end of resistor R310 is connected to the front end of resistor R311, and the rear end of resistor R311 is connected to the AIN2+ port of AI chip U301;

[0112] Port CBD is connected to the front end of resistor R315, the rear end of resistor R315 is connected to the front end of resistor R316, and the rear end of resistor R316 is connected to AIN2- port of AI chip U301;

[0113] The port TEST1 is connected to the port CBD via a bidirectional diode TV303 in series, the rear end of the resistor R310 is connected to the rear end of the resistor R315 via a capacitor C321 in series, the rear end of the resistor R311 is connected to the rear end of the resistor R316 via a capacitor C322 in series, the rear end of the resistor R310 is connected to ground via a capacitor C319 in series, the rear end of the resistor R311 is connected to ground via a capacitor C320 in series, the rear end of the resistor R315 is connected to ground via a capacitor C323 in series, and the rear end of the resistor R316 is connected to ground via a capacitor C324 in series;

[0114] Port YJD is connected to the front end of resistor R318, the rear end of resistor R318 is connected to the front end of resistor R319, and the rear end of resistor R319 is connected to the AIN3+ port of AI chip U301;

[0115] Port YYJD is connected to the front end of resistor R322, the rear end of resistor R322 is connected to the front end of resistor R323, and the rear end of resistor R323 is connected to AIN3- port of AI chip U301;

[0116] The port YJD is connected to the port YYJD in series with the bidirectional diode TV305, the rear end of the resistor R318 is connected to the rear end of the resistor R322 in series with the capacitor C334, the rear end of the resistor R319 is connected to the rear end of the resistor R323 in series with the capacitor C335, the rear end of the resistor R318 is connected to the ground, the rear end of the resistor R319 is connected to the ground, the rear end of the resistor R319 is connected to the ground, the rear end of the resistor R322 is connected to the ground, and the rear end of the resistor R323 is connected to the ground.

[0117] Port TEST2 is connected to the front end of resistor R320, the rear end of resistor R320 is connected to the front end of resistor R321, and the rear end of resistor R321 is connected to the AIN4+ port of AI chip U301;

[0118] Port CBD is connected to the front end of resistor R324, the rear end of resistor R324 is connected to the front end of resistor R325, and the rear end of resistor R325 is connected to AIN4- port of AI chip U301;

[0119] The port TEST2 is connected to the port CBD in series with the bidirectional diode TV306, the rear end of the resistor R320 is connected to the rear end of the resistor R324 in series with the capacitor C336, the rear end of the resistor R324 is connected to the rear end of the resistor R325 in series with the capacitor C337, the rear end of the resistor R320 is connected to the ground in series with the capacitor C332, the rear end of the resistor R321 is connected to the ground in series with the capacitor C333, the rear end of the resistor R324 is connected to the ground in series with the capacitor C340, and the rear end of the resistor R325 is connected to the ground in series with the capacitor C341;

[0120] The total power supply terminal VBIN is connected to the front end of the resistor R312, the rear end of the resistor R312 is connected to the front end of the resistor R317, the rear end of the resistor R317 is grounded, the common end of the resistor R312 and the resistor R317 is connected to the front end of the resistor R313, the rear end of the resistor R313 is connected to the front end of the resistor R134, the rear end of the resistor R314 is connected to the AIN5+ port of the AI ​​chip U301, and the AIN5- port of the AI ​​chip U301 is grounded; the front end of the resistor R313 is connected in series with a bidirectional diode TV304 and then grounded, the rear end of the resistor R313 is connected in series with a capacitor C326 and then grounded, and the rear end of the resistor R314 is connected in series with a capacitor C325 and then grounded;

[0121] The SCLK port of the AI ​​chip U301 is connected to the PF7 port of the CPU, the DIN port of the AI ​​chip U301 is connected to the PF6 port of the CPU, and the DOUT port of the AI ​​chip U301 is connected to the PF5 port of the CPU.

[0122] The sensing unit is provided with a reference voltage chip U302, the power supply terminal V_AD is connected to the AV+ port of the AI ​​chip U301, the GND port of the AI ​​chip U301 is grounded, the DV+ port of the AI ​​chip U301 is the power supply terminal AD_VCC, the power supply terminal AD_VCC is connected to the VIN port of the reference voltage chip U302, the VOUT port of the reference voltage chip U302 is connected to the REF+ port of the AI ​​chip U301; the REF- port of the AI ​​chip U301 is grounded;

[0123] The VIN port of the reference voltage chip U302 is connected to the front end of the resistor R309, the VOUT port of the reference voltage chip U302 is connected to the back end of the resistor R309, the VIN port of the reference voltage chip U302 is connected to ground via a series capacitor C317, the VOUT port of the reference voltage chip U302 is connected to ground via a series capacitor C318, the power supply terminal AD_VCC is connected to ground via a series capacitor C305, the REF+ port of the AI ​​chip U301 is connected to ground via a series capacitor C306; the power supply terminal AD_VCC is connected to the PF4 port of the CPU.

[0124] like Figure 4 As shown, the sensing unit is provided with relay J401, relay J402 and relay J403;

[0125] The power supply terminal V_AD is connected to the coil of the relay J401 in series, and then connected to the collector of the transistor Q401. The emitter of the transistor Q401 is grounded. The base of the transistor Q401 is connected to the rear end of the resistor R401. The front end of the resistor R401 is connected to the PB3 port of the CPU. Two contacts in a group of normally closed switches of the relay J401 are connected to the port YYJD and the port TEST1 respectively.

[0126] The power supply terminal V_AD is connected to the coil of the relay J402 in series, and then connected to the collector of the transistor Q402. The emitter of the transistor Q402 is grounded. The base of the transistor Q402 is connected to the rear end of the resistor R402. The front end of the resistor R402 is connected to the PB2 port of the CPU. Two contacts in a group of normally closed switches of the relay J402 are connected to the port YYJD and the port YJD respectively.

[0127] The coil of relay J403 in series with the power supply terminal V_AD is connected to the collector of transistor Q403, the emitter of transistor Q403 is grounded, the base of transistor Q403 is connected to the rear end of resistor R403, and the front end of resistor R403 is connected to the PB1 port of CPU; two contacts in a group of normally closed switches of relay J403 are respectively connected to port YJD and the front end of resistor RZ401; the rear end of resistor RZ401 is connected to port YYJD.

[0128] like Figure 4 As shown, the pipeline test point CF401 is connected in series with the varistor RV401 and then connected to the port TEST2, the pipeline test point CF402 is connected in series with the varistor RV402 and then connected to the port TEST1, the pipeline test point CF403 is connected in series with the varistor RV403 and then connected to the port CBD, the pipeline test point CF404 is connected in series with the varistor RV404 and then connected to the port YJD, and the pipeline test point CF405 is connected in series with the varistor RV405 and then connected to the port YYJD;

[0129] By controlling and sampling port YYJD, port YJD, port CBD, port TEST1 and port TEST2, the data information required for pipeline cathodic protection can be obtained.

[0130] Port TEST2 is connected to port TEST1 via capacitor C401 in series, port TEST1 is connected to port CBD via capacitor C402 in series, port CBD is connected to port YJD via capacitor C403 in series, and port YJD is connected to port YYJD via capacitor C404 in series. By connecting capacitors in series between sampling ports, the sampling data can be filtered to effectively reduce interference.

[0131] like Figure 6 As shown, the communication unit is provided with a communication chip U201 and a SIM card chip U202;

[0132] The power supply terminal V_COM is connected to the BAT port of the communication chip U201, the GND port of the communication chip U201 is grounded, the PG6 port of the CPU is connected to the front end of the resistor R201, the rear end of the resistor R201 is connected to the front end of the resistor R202, the rear end of the resistor R202 is grounded, the common end of the resistor R201 and the resistor R202 is connected to the base of the transistor Q201, the collector of the transistor Q201 is connected to the PWRKEY port of the communication chip U201, and the emitter of the transistor Q201 is grounded;

[0133] The TXD port of the communication chip U201 is connected to the front end of the resistor R204, the rear end of the resistor R204 is connected to the PD6 port of the CPU, the PD7 port of the CPU is connected to the front end of the resistor R203, the rear end of the resistor R203 is connected to the front end of the resistor R205, the rear end of the resistor R205 is grounded, and the common end of the resistor R203 and the resistor R205 is connected to the RXD port of the communication chip U201;

[0134] The SIM_VDD port of the communication chip U201 is connected to the VCC port of the SIM card chip U202, the SIM_RST port of the communication chip U201 is connected to the RST port of the SIM card chip U202, the SIM_CLK port of the communication chip U201 is connected to the CLK port of the SIM card chip U202, the SIM_DATA port of the communication chip U201 is connected to the IO port of the SIM card chip U202, the SIM_VDD port of the communication chip U201 is connected to the front end of the resistor R209, the rear end of the resistor R209 is connected to the IO port of the SIM card chip U202, the GND port of the SIM card chip U202 is grounded, the SIM_VDD port of the communication chip U201 is connected to ground in series with the capacitor C204, and the SIM_VDD port of the communication chip U201 is connected to ground in series with the capacitor C205;

[0135] The AVDD port of the communication chip U201 is connected to the front end of the resistor R207, the rear end of the resistor R207 is connected to the front end of the resistor R208, the rear end of the resistor R208 is grounded, the common end of the resistor R207 and the resistor R208 is connected to the ADC0 port of the communication chip U201, and the common end of the resistor R207 and the resistor R208 is connected in series with the capacitor C206 and then grounded;

[0136] The power supply terminal V_COM is connected to the positive electrode of the light-emitting diode D201, the negative electrode of the light-emitting diode D201 is connected to the front end of the resistor R210, the rear end of the resistor R210 is connected to the collector of the transistor Q202, the emitter of the transistor Q202 is grounded, the STATUS port of the communication chip U201 is connected to the front end of the resistor R214, the rear end of the resistor R214 is connected to the front end of the resistor R213, and the common end of the resistor R214 and the resistor R213 is connected to the base of the transistor Q202;

[0137] The power supply terminal V_COM is connected to the positive electrode of the light-emitting diode D202, the negative electrode of the light-emitting diode D202 is connected to the front end of the resistor R211, the rear end of the resistor R211 is connected to the collector of the transistor Q203, the emitter of the transistor Q203 is grounded, the NETLIGHT port of the communication chip U201 is connected to the front end of the resistor R216, the rear end of the resistor R216 is connected to the front end of the resistor R215, and the common end of the resistor R216 and the resistor R215 is connected to the base of the transistor Q203;

[0138] The power supply terminal V_COM is connected to ground via a series capacitor C201, the power supply terminal V_COM is connected to ground via a series capacitor C202, and the VRTC port of the communication chip U201 is connected to ground via a series capacitor C203.

[0139] like Figure 2As shown in the figure, the calculation formula of the power supply terminal V_CPU is: 0.8V*(1+R105 / R106), and the result is 3.3V. Figure 3 As shown, 3.3V is connected to the VDDIO_2 port and Vref+ port of the CPU, and the VSSIO_2 port and Vref- port of the CPU are grounded; the power supply terminal V_CPU supplies power to the CPU and serves as a reference voltage for the analog input of the CPU.

[0140] like Figure 2 As shown, the calculation formula of the power supply terminal V_AD is: 0.6V*(1+R111 / R109), the calculation result is 5V, and the calculation formula of the power supply terminal V_CPU is: 0.6V*(1+R112 / R109), the calculation result is 3.66V.

[0141] The main principles of the utility model are as follows: the CPU is regularly awakened by a clock wake-up circuit to ensure that the CPU performs data acquisition and remote communication only when needed; the CPU controls the awakening and time-sharing output of the sensor communication power supply circuit, which saves hardware costs and reduces power supply requirements; the battery parallel circuit ensures that the battery BAT102 is connected only when a large current is required for the normal operation of the sensor unit or the communication unit, thereby ensuring power supply efficiency.

[0142] Finally, it should be noted that the above description is only a preferred embodiment of the present invention. Under the guidance of the present invention, ordinary technicians in this field can make a variety of similar expressions without violating the purpose and claims of the present invention, and such changes fall within the scope of protection of the present invention.

Claims

1. Low power consumption pipeline cathodic protection circuit, characterized by: It includes a power supply unit, a sensor unit, a CPU, and a communication unit. The sensor unit is connected to the CPU, and the CPU is connected to the communication unit. The power supply unit includes a clock wake-up circuit, a battery parallel circuit, a CPU power supply circuit, and a sensor communication power supply circuit. The battery parallel circuit is connected to the CPU power circuit, the CPU power circuit is connected to the CPU, and the CPU power circuit is connected to the clock wake-up circuit; The battery parallel circuit is connected to the power supply terminal of the sensing communication power supply circuit, the sensing communication power supply circuit is connected to the power supply terminal of the sensing unit, and the sensing communication power supply circuit is also connected to the power supply terminal of the communication unit; The clock wake-up circuit is provided with a clock chip U101, and the INT1 port of the clock chip U101 is connected to the wake-up terminal PA3 of the CPU; The sensor communication power supply circuit is provided with a sensor communication wake-up port, a sensor switching port and a communication switching port. The PA4 port of the CPU is connected to the sensor communication wake-up port, the PA5 port of the CPU is connected to the sensor switching port, and the PA6 port of the CPU is connected to the communication switching port.

2. The low power consumption pipeline cathodic protection circuit according to claim 1, characterized in that: The battery parallel circuit includes a battery BAT102 and a battery BAT103, the negative electrode of the battery BAT103 is grounded, the positive electrode of the battery BAT103 is connected to the positive electrode of the diode D104, the negative electrode of the diode D104 is the total power supply terminal VBIN, and the total power supply terminal VBIN is connected to the sensor communication power supply circuit; The negative electrode of the battery BAT102 is grounded, the positive electrode of the battery BAT102 is connected to the drain of the switch tube Q101, the source of the switch tube Q101 is connected to the positive electrode of the diode D103, the negative electrode of the diode D103 is connected to the main power supply terminal VBIN, and the gate of the switch tube Q101 is connected to the CPU.

3. The low power consumption pipeline cathode protection circuit according to claim 2, characterized in that: The CPU power supply circuit is provided with a power supply chip U102, the VIN port of the power supply chip U102 is connected to the main power supply terminal VBIN, and the VIN port of the power supply chip U102 is also connected to the EN port of the power supply chip U102; The VIN port of the power chip U102 is connected to ground via a capacitor C106 in series, the VIN port of the power chip U102 is connected to ground via a capacitor C104 in series, and the GND port of the power chip U102 is connected to ground; The SW port of the power chip U102 is connected to the front end of the inductor L101, the rear end of the inductor L101 is the power terminal V_CPU, the power terminal V_CPU is connected to the front end of the resistor R105, the rear end of the resistor R105 is connected to the front end of the resistor R106, the rear end of the resistor R106 is grounded, and the common end of the resistor R105 and the resistor R106 is connected to the voltage feedback terminal FB of the power chip U102; the power terminal V_CPU is connected to the CPU and the clock wake-up circuit; The power supply terminal V_CPU is connected to the front end of the capacitor C103, and the rear end of the capacitor C103 is connected to the voltage feedback terminal FB of the power supply chip U102; the power supply terminal V_CPU is connected to the front end of the resistor R107, and the front end of the resistor R107 is connected to the VOUT port of the power supply chip U102, the front end of the resistor R107 is connected to the SGND port of the power supply chip U102, and the rear end of the resistor R107 is connected to the PG port of the power supply chip U102; The power supply terminal V_CPU is connected to the VDDIO_2 port and the Vref+ port of the CPU, and the VSSIO_2 port and the Vref- port of the CPU are grounded.

4. The low power consumption pipeline cathode protection circuit according to claim 3, characterized in that: The power supply terminal V_CPU is connected to the anode of the diode D101, and the cathode of the diode D101 is connected to the VDD port of the clock chip U101; The power supply terminal V_CPU is connected to the front end of the resistor R101, the rear end of the resistor R101 is connected to the SDA port of the clock chip U101, and the SDA port of the clock chip U101 is connected to the PH2 port of the CPU; The power supply terminal V_CPU is connected to the front end of the resistor R103, the rear end of the resistor R103 is connected to the SCL port of the clock chip U101, and the SCL port of the clock chip U101 is connected to the PH3 port of the CPU; The power supply terminal V_CPU is connected to the front end of the resistor R102, and the rear end of the resistor R102 is connected to the INT1 port of the clock chip U101.

5. The low power consumption pipeline cathode protection circuit according to claim 1, characterized in that: The clock wake-up circuit is provided with a battery BAT101, the negative electrode of the battery BAT101 is grounded, the positive electrode of the battery BAT101 is connected to the front end of the resistor R104, the rear end of the resistor R104 is connected to the positive electrode of the diode D102, the negative electrode of the diode D102 is connected to the VDD port of the clock chip U101, the VDD port of the clock chip U101 is connected to the positive electrode of the capacitor C102, and the negative electrode of the capacitor C102 is grounded; The XOUT port of the clock chip U101 is connected to the front end of the crystal oscillator G101, the back end of the crystal oscillator G101 is connected to the XIN port of the clock chip U101, the back end of the crystal oscillator G101 is grounded, and the GND port of the clock chip U101 is grounded.

6. The low power consumption pipeline cathode protection circuit according to claim 2, characterized in that: The sensor communication power supply circuit is provided with a power supply chip U103, the total power supply terminal VBIN is connected to the VIN port of the power supply chip U103, the SW port of the power supply chip U103 is connected to the front end of the inductor L102, the rear end of the inductor L102 is connected to the drain of the switch tube Q102, the source of the switch tube Q102 is the power supply terminal V_AD, the power supply terminal V_AD is connected to the front end of the resistor R111, the rear end of the resistor R111 is connected to the front end of the resistor R109, the rear end of the resistor R109 is grounded, and the common end of the resistor R111 and the resistor R109 is connected to the voltage feedback terminal FB of the power supply chip U103; The rear end of the inductor L102 is connected to the drain of the switch tube Q103, the source of the switch tube Q103 is the power supply terminal V_COM, the power supply terminal V_COM is connected to the front end of the resistor R112, and the rear end of the resistor R112 is connected to the front end of the resistor R109; The gate of the switch tube Q102 is connected to the sensor switching port, the source of the switch tube Q102 is connected to the power supply terminal V_AD, and the power supply terminal V_AD is connected to the sensor unit; The gate of the switch tube Q103 is connected to the communication switching port, the source of the switch tube Q103 is connected to the power supply terminal V_COM, and the power supply terminal V_COM is connected to the communication unit; The EN port of the power chip U103 is connected to the rear end of the resistor R110, and the front end of the resistor R110 is connected to the sensor communication wake-up port; The VIN port of the power chip U103 is connected in series with capacitor C110 and then grounded, the VIN port of the power chip U103 is connected in series with capacitor C111 and then grounded, the SW port of the power chip U103 is connected to the front end of capacitor C107, the rear end of capacitor C107 is connected to the front end of resistor R108, the rear end of resistor R108 is connected to the VBST port of the power chip U103, the rear end of the inductor L102 is connected in series with capacitor C108 and then connected to the front end of resistor R109, the rear end of the inductor L102 is connected in series with capacitor C109 and then grounded, and the GND port of the power chip U103 is grounded.

7. The low power consumption pipeline cathode protection circuit according to claim 6, characterized in that: The sensing unit is provided with a sampling terminal group and an AI chip U301, and the sampling terminal group is provided with a port YYJD, a port YJD, a port CBD, a port TEST1 and a port TEST2; Port YYJD is connected to the front end of resistor R301, the rear end of resistor R301 is connected to the front end of resistor R302, and the rear end of resistor R302 is connected to the AIN6+ port of AI chip U301; Port CBD is connected to the front end of resistor R303, the rear end of resistor R303 is connected to the front end of resistor R304, and the rear end of resistor R304 is connected to AIN6- port of AI chip U301; Port YYJD is connected in series with bidirectional diode TV301 and then to port CBD; the rear end of resistor R301 is connected in series with capacitor C307 and then to the rear end of resistor R303; the rear end of resistor R302 is connected in series with capacitor C308 and then to the rear end of resistor R304; the rear end of resistor R301 is connected in series with capacitor C302 and then to ground; the rear end of resistor R302 is connected in series with capacitor C303 and then to ground; the rear end of resistor R303 is connected in series with capacitor C309 and then to ground; the rear end of resistor R304 is connected in series with capacitor C310 and then to ground; Port YJD is connected to the front end of resistor R305, the rear end of resistor R305 is connected to the front end of resistor R306, and the rear end of resistor R306 is connected to the AIN1+ port of AI chip U301; Port CBD is connected to the front end of resistor R307, the rear end of resistor R307 is connected to the front end of resistor R308, and the rear end of resistor R308 is connected to AIN1- port of AI chip U301; Port YJD is connected to port CBD in series with bidirectional diode TV302, the rear end of resistor R305 is connected to the rear end of resistor R307 in series with capacitor C313, the rear end of resistor R306 is connected to the rear end of resistor R308 in series with capacitor C314, the rear end of resistor R305 is connected to ground in series with capacitor C311, the rear end of resistor R306 is connected to ground in series with capacitor C312, the rear end of resistor R307 is connected to ground in series with capacitor C315, and the rear end of resistor R308 is connected to ground in series with capacitor C316; Port TEST1 is connected to the front end of resistor R310, the rear end of resistor R310 is connected to the front end of resistor R311, and the rear end of resistor R311 is connected to the AIN2+ port of AI chip U301; Port CBD is connected to the front end of resistor R315, the rear end of resistor R315 is connected to the front end of resistor R316, and the rear end of resistor R316 is connected to AIN2- port of AI chip U301; The port TEST1 is connected to the port CBD via a bidirectional diode TV303 in series, the rear end of the resistor R310 is connected to the rear end of the resistor R315 via a capacitor C321 in series, the rear end of the resistor R311 is connected to the rear end of the resistor R316 via a capacitor C322 in series, the rear end of the resistor R310 is connected to ground via a capacitor C319 in series, the rear end of the resistor R311 is connected to ground via a capacitor C320 in series, the rear end of the resistor R315 is connected to ground via a capacitor C323 in series, and the rear end of the resistor R316 is connected to ground via a capacitor C324 in series; Port YJD is connected to the front end of resistor R318, the rear end of resistor R318 is connected to the front end of resistor R319, and the rear end of resistor R319 is connected to the AIN3+ port of AI chip U301; Port YYJD is connected to the front end of resistor R322, the rear end of resistor R322 is connected to the front end of resistor R323, and the rear end of resistor R323 is connected to AIN3- port of AI chip U301; The port YJD is connected to the port YYJD in series with the bidirectional diode TV305, the rear end of the resistor R318 is connected to the rear end of the resistor R322 in series with the capacitor C334, the rear end of the resistor R319 is connected to the rear end of the resistor R323 in series with the capacitor C335, the rear end of the resistor R318 is connected to the ground, the rear end of the resistor R319 is connected to the ground, the rear end of the resistor R319 is connected to the ground, the rear end of the resistor R322 is connected to the ground, and the rear end of the resistor R323 is connected to the ground. Port TEST2 is connected to the front end of resistor R320, the rear end of resistor R320 is connected to the front end of resistor R321, and the rear end of resistor R321 is connected to the AIN4+ port of AI chip U301; Port CBD is connected to the front end of resistor R324, the rear end of resistor R324 is connected to the front end of resistor R325, and the rear end of resistor R325 is connected to AIN4- port of AI chip U301; The port TEST2 is connected to the port CBD in series with the bidirectional diode TV306, the rear end of the resistor R320 is connected to the rear end of the resistor R324 in series with the capacitor C336, the rear end of the resistor R324 is connected to the rear end of the resistor R325 in series with the capacitor C337, the rear end of the resistor R320 is connected to the ground in series with the capacitor C332, the rear end of the resistor R321 is connected to the ground in series with the capacitor C333, the rear end of the resistor R324 is connected to the ground in series with the capacitor C340, and the rear end of the resistor R325 is connected to the ground in series with the capacitor C341; The total power supply terminal VBIN is connected to the front end of the resistor R312, the rear end of the resistor R312 is connected to the front end of the resistor R317, the rear end of the resistor R317 is grounded, the common end of the resistor R312 and the resistor R317 is connected to the front end of the resistor R313, the rear end of the resistor R313 is connected to the front end of the resistor R134, the rear end of the resistor R314 is connected to the AIN5+ port of the AI ​​chip U301, and the AIN5- port of the AI ​​chip U301 is grounded; the front end of the resistor R313 is connected in series with a bidirectional diode TV304 and then grounded, the rear end of the resistor R313 is connected in series with a capacitor C326 and then grounded, and the rear end of the resistor R314 is connected in series with a capacitor C325 and then grounded; The SCLK port of the AI ​​chip U301 is connected to the PF7 port of the CPU, the DIN port of the AI ​​chip U301 is connected to the PF6 port of the CPU, and the DOUT port of the AI ​​chip U301 is connected to the PF5 port of the CPU.

8. The low power consumption pipeline cathode protection circuit according to claim 7, characterized in that: The sensing unit is provided with a reference voltage chip U302, the power supply terminal V_AD is connected to the AV+ port of the AI ​​chip U301, the GND port of the AI ​​chip U301 is grounded, the DV+ port of the AI ​​chip U301 is the power supply terminal AD_VCC, the power supply terminal AD_VCC is connected to the VIN port of the reference voltage chip U302, the VOUT port of the reference voltage chip U302 is connected to the REF+ port of the AI ​​chip U301; the REF- port of the AI ​​chip U301 is grounded; The VIN port of the reference voltage chip U302 is connected to the front end of the resistor R309, the VOUT port of the reference voltage chip U302 is connected to the back end of the resistor R309, the VIN port of the reference voltage chip U302 is connected to ground via a series capacitor C317, the VOUT port of the reference voltage chip U302 is connected to ground via a series capacitor C318, the power supply terminal AD_VCC is connected to ground via a series capacitor C305, the REF+ port of the AI ​​chip U301 is connected to ground via a series capacitor C306; the power supply terminal AD_VCC is connected to the PF4 port of the CPU.

9. The low power consumption pipeline cathode protection circuit according to claim 7, characterized in that: The sensing unit is provided with a relay J401, a relay J402 and a relay J403; The power supply terminal V_AD is connected to the coil of the relay J401 in series, and then connected to the collector of the transistor Q401. The emitter of the transistor Q401 is grounded. The base of the transistor Q401 is connected to the rear end of the resistor R401. The front end of the resistor R401 is connected to the PB3 port of the CPU. Two contacts in a group of normally closed switches of the relay J401 are respectively connected to the port YYJD and the port TEST1. The power supply terminal V_AD is connected to the coil of the relay J402 in series, and then connected to the collector of the transistor Q402. The emitter of the transistor Q402 is grounded, and the base of the transistor Q402 is connected to the rear end of the resistor R402. The front end of the resistor R402 is connected to the PB2 port of the CPU; two contacts in a group of normally closed switches of the relay J402 are respectively connected to the port YYJD and the port YJD; The coil of the relay J403 in series with the power supply terminal V_AD is connected to the collector of the transistor Q403, the emitter of the transistor Q403 is grounded, the base of the transistor Q403 is connected to the rear end of the resistor R403, and the front end of the resistor R403 is connected to the PB1 port of the CPU; two contacts in a group of normally closed switches of the relay J403 are respectively connected to the port YJD and the front end of the resistor RZ401; the rear end of the resistor RZ401 is connected to the port YYJD.

10. The low power consumption pipeline cathode protection circuit according to claim 6, characterized in that: The communication unit is provided with a communication chip U201 and a SIM card chip U202; The power supply terminal V_COM is connected to the BAT port of the communication chip U201, the GND port of the communication chip U201 is grounded, the PG6 port of the CPU is connected to the front end of the resistor R201, the rear end of the resistor R201 is connected to the front end of the resistor R202, the rear end of the resistor R202 is grounded, the common end of the resistor R201 and the resistor R202 is connected to the base of the transistor Q201, the collector of the transistor Q201 is connected to the PWRKEY port of the communication chip U201, and the emitter of the transistor Q201 is grounded; The TXD port of the communication chip U201 is connected to the front end of the resistor R204, the rear end of the resistor R204 is connected to the PD6 port of the CPU, the PD7 port of the CPU is connected to the front end of the resistor R203, the rear end of the resistor R203 is connected to the front end of the resistor R205, the rear end of the resistor R205 is grounded, and the common end of the resistor R203 and the resistor R205 is connected to the RXD port of the communication chip U201; The SIM_VDD port of the communication chip U201 is connected to the VCC port of the SIM card chip U202, the SIM_RST port of the communication chip U201 is connected to the RST port of the SIM card chip U202, the SIM_CLK port of the communication chip U201 is connected to the CLK port of the SIM card chip U202, the SIM_DATA port of the communication chip U201 is connected to the IO port of the SIM card chip U202, the SIM_VDD port of the communication chip U201 is connected to the front end of the resistor R209, the rear end of the resistor R209 is connected to the IO port of the SIM card chip U202, the GND port of the SIM card chip U202 is grounded, the SIM_VDD port of the communication chip U201 is connected to ground in series with the capacitor C204, and the SIM_VDD port of the communication chip U201 is connected to ground in series with the capacitor C205; The AVDD port of the communication chip U201 is connected to the front end of the resistor R207, the rear end of the resistor R207 is connected to the front end of the resistor R208, the rear end of the resistor R208 is grounded, the common end of the resistor R207 and the resistor R208 is connected to the ADC0 port of the communication chip U201, and the common end of the resistor R207 and the resistor R208 is connected in series with the capacitor C206 and then grounded; The power supply terminal V_COM is connected to the positive electrode of the light-emitting diode D201, the negative electrode of the light-emitting diode D201 is connected to the front end of the resistor R210, the rear end of the resistor R210 is connected to the collector of the transistor Q202, the emitter of the transistor Q202 is grounded, the STATUS port of the communication chip U201 is connected to the front end of the resistor R214, the rear end of the resistor R214 is connected to the front end of the resistor R213, and the common end of the resistor R214 and the resistor R213 is connected to the base of the transistor Q202; The power supply terminal V_COM is connected to the positive electrode of the light-emitting diode D202, the negative electrode of the light-emitting diode D202 is connected to the front end of the resistor R211, the rear end of the resistor R211 is connected to the collector of the transistor Q203, the emitter of the transistor Q203 is grounded, the NETLIGHT port of the communication chip U201 is connected to the front end of the resistor R216, the rear end of the resistor R216 is connected to the front end of the resistor R215, and the common end of the resistor R216 and the resistor R215 is connected to the base of the transistor Q203; The power supply terminal V_COM is connected to ground via a series capacitor C201, the power supply terminal V_COM is connected to ground via a series capacitor C202, and the VRTC port of the communication chip U201 is connected to ground via a series capacitor C203.

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