LDO control circuit and LDO power supply

Abstract

The utility model provides an LDO (Low Dropout Regulator) control circuit, which comprises a band gap circuit of which the first end is coupled with the control signal output end of a current mirror, the second end is connected with an LDO output feedback signal, and the third end is coupled with the first end of an adjusting circuit; the band gap circuit is used for acquiring an LDO output feedback signal and outputting the feedback signal to the adjusting circuit; the first end of the adjusting circuit is coupled with the third end of the band gap circuit, and the second end is coupled with the second end of the current mirror; the adjusting circuit is used for generating an adjusting signal according to a feedback signal output by the LDO and outputting the adjusting signal to the current mirror; the first end of the current mirror is connected with input voltage, the second end is coupled with the second end of the adjusting circuit, and the third end serves as a control signal output end and is coupled with the LDO output voltage end; the current mirror is used for generating a control signal according to the adjusting signal proportion. According to the low-dropout regulator, the band gap circuit is multiplexed, an internal power supply is generated, a traditional independent operational amplifier is omitted, closed-loop control over LDO output voltage is achieved, the consistency of a system is improved, cost is low, and meanwhile good performance is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of analog integrated circuit technology, and specifically but not limited to an LDO control circuit and an LDO power supply. Background Art

[0002] Low dropout regulator (LDO) has the advantages of low cost, low power consumption and simple peripheral circuit, which makes it play a vital role in power management system. LDO is often used in battery-powered devices and portable electronic products. Its operating voltage is low, and the general power supply voltage is about 5V. In chip design, a stable LDO power supply is needed to power the chip. Common power supplies are divided into open-loop and closed-loop modes, such as Figure 1 and Figure 2 shown.

[0003] In open-loop control, the gate of NMOS N1 is clamped at VZ through the voltage regulator D1, so VDD = VZ-Vgs. In the commonly used CMOS process, the voltage regulator is not a standard device, and additional light levels are required to obtain a voltage regulator with good performance. Therefore, several series-connected NMOS with shorted Gate-Drain are usually used to clamp Vgs. Figure 1 As shown, since the Vgs of NMOS fluctuates in a wide range with temperature and process deviation, the open-loop control has a simple structure but poor performance.

[0004] like Figure 2 As shown, the closed-loop control includes an operational amplifier OP, an NMOS driver tube and resistors R1 and R2. The operational amplifier OP is used to amplify the difference between the feedback voltage of the resistors R1 and R2 and the reference voltage VBG, and the output signal controls the gate of the NMOS driver tube; the NMOS driver tube changes the current flowing through the NMOS driver tube according to the change of its gate voltage, thereby adjusting the output voltage; the resistors R1 and R2 act as a voltage divider to generate a feedback voltage signal at the negative input terminal of the operational amplifier OP. The closed-loop control can obtain a VD that varies very little with temperature and process by controlling the gate of the NMOS through the resistor voltage divider of the reference voltage VBG and the output voltage VDD through the operational amplifier closed-loop. Figure 2 As shown, the closed-loop control needs to be controlled by a separate operational amplifier, and the closed-loop control circuit is relatively complex, which appears to be somewhat "wasteful" in low-cost applications with smaller wafer sizes.

[0005] In view of this, it is necessary to provide a new structure to solve at least part of the above problems. Utility Model Content

[0006] In view of one or more problems in the prior art, the utility model proposes an LDO control circuit and an LDO power supply, which are used to solve the problems of poor performance and complex structure of the control circuit in the prior art.

[0007] The technical solution to achieve the purpose of this utility model is:

[0008] The utility model discloses an LDO control circuit, comprising:

[0009] A bandgap circuit, wherein a first end of the bandgap circuit is coupled to a control signal output end of the current mirror, a second end of the bandgap circuit is connected to an LDO output feedback signal, and a third end of the bandgap circuit is coupled to a first end of the regulating circuit; the bandgap circuit is used to obtain the LDO output feedback signal and output it to the regulating circuit;

[0010] A regulating circuit, a first end of which is coupled to the third end of the bandgap circuit, and a second end of which is coupled to the second end of the current mirror; the regulating circuit is used to generate a regulating signal according to the LDO output feedback signal and output the regulating signal to the current mirror;

[0011] A current mirror has a first end connected to an input voltage, a second end coupled to a second end of a regulating circuit, and a third end coupled to an LDO output voltage end as a control signal output end; the current mirror is used to generate a control signal according to a proportion of a regulating signal.

[0012] Preferably, the LDO control circuit further includes a fourth PMOS tube, a gate of which is coupled to the third end of the bandgap circuit, a source of which is coupled to the third end of the current mirror, and a drain of which is coupled to the first end of the regulating circuit.

[0013] Preferably, the regulating circuit includes a first NMOS tube, a second NMOS tube and a third resistor, wherein the gate of the first NMOS tube is coupled to the drain of the second NMOS tube, the drain of the first NMOS tube is coupled to the second end of the current mirror, the source of the first NMOS tube is coupled to the first end of the third resistor and the gate of the second NMOS tube, the other end of the third resistor is grounded, and the source of the second NMOS tube is grounded.

[0014] Preferably, the regulating circuit further includes a fourth resistor, one end of the fourth resistor is coupled to the input voltage, and the other end of the fourth resistor is coupled to the gate of the first NMOS tube and the drain of the second NMOS tube.

[0015] Preferably, the bandgap circuit includes a fifth PMOS tube, a sixth PMOS tube, a first transistor, a second transistor, a fifth resistor and a sixth resistor, wherein the source of the fifth PMOS tube and the source of the sixth PMOS tube are both coupled to the output end of the current mirror and serve as the output voltage end, the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube and coupled to the drain of the sixth PMOS tube and the collector of the second transistor, the drain of the fifth PMOS tube is connected to the gate of the fourth PMOS tube and the collector of the first transistor; the bases of the first transistor and the second transistor are connected and coupled to the LDO output feedback end, the emitter of the first transistor is connected to one end of the fifth resistor and one end of the sixth resistor, the emitter of the second transistor is connected to the other end of the fifth resistor, and the other end of the sixth resistor is grounded.

[0016] Preferably, the current mirror is a 1:K current mirror.

[0017] Preferably, the current mirror includes a first PMOS tube and a second PMOS tube, wherein the sources of the first PMOS tube and the second PMOS tube are connected and connected to the input voltage, the gates of the first PMOS tube and the second PMOS tube are connected and connected to the drain of the first PMOS tube and the second end of the regulation circuit, and the drain of the second PMOS tube is a control signal output end coupled to the LDO output voltage end.

[0018] The utility model also discloses an LDO control circuit, including a first PMOS tube, a second PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third resistor, a fourth resistor, a fifth PMOS tube, a sixth PMOS tube, a first triode, a second triode, a fifth resistor and a sixth resistor; wherein:

[0019] The source of the first PMOS tube is connected to the source of the second PMOS tube and is connected to the input voltage, the gate of the first PMOS tube is connected to the gate of the second PMOS tube and is connected to the drain of the first PMOS tube and the drain of the first NMOS tube, and the drain of the second PMOS tube is coupled to the source of the fourth PMOS tube and serves as an output voltage terminal;

[0020] The gate of the first NMOS tube is coupled to the drain of the second NMOS tube and one end of the fourth resistor, the other end of the fourth resistor is coupled to the input voltage, the source of the first NMOS tube is coupled to the drain of the fourth PMOS tube, the first end of the third resistor and the gate of the second NMOS tube, the other end of the third resistor is grounded, and the source of the second NMOS tube is grounded;

[0021] The source of the fifth PMOS tube and the source of the sixth PMOS tube are both coupled to the drain of the second PMOS tube, the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube and coupled to the drain of the sixth PMOS tube and the collector of the second transistor, the drain of the fifth PMOS tube is coupled to the gate of the fourth PMOS tube and the collector of the first transistor, the bases of the first transistor and the second transistor are connected and coupled to the LDO output feedback end, the emitter of the first transistor is connected to one end of the fifth resistor and one end of the sixth resistor, the emitter of the second transistor is connected to the other end of the fifth resistor, and the other end of the sixth resistor is grounded.

[0022] The utility model also discloses an LDO power supply, comprising a PMOS driving tube, a first feedback resistor, a second feedback resistor and an LDO control circuit as described in any one of the above, wherein the gate of the PMOS driving tube is coupled to its drain and one end of the first feedback resistor, the source of the PMOS driving tube serves as the LDO output voltage end and is coupled to the third end of the current mirror, the other end of the first feedback resistor is coupled to the second end of the bandgap circuit and one end of the second feedback resistor, and the other end of the second feedback resistor is grounded.

[0023] Compared with the prior art, the utility model adopts the above technical solution and has the following technical effects:

[0024] 1. The LDO control circuit of the utility model realizes closed-loop control of the LDO output voltage by multiplexing the bandgap circuit without using a separate operational amplifier.

[0025] 2. The LDO control circuit of the utility model generates an internal power supply through a bandgap loop, thereby improving the consistency of the system.

[0026] 3. The LDO control circuit of the utility model has a simple structure, simplifies the existing circuit design, eliminates the traditional separate operational amplifier, has low cost, and has good performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide a further understanding of the present invention and are used together with the description to explain the embodiments of the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0028] Figure 1 A schematic diagram of the open-loop LDO control circuit structure of the prior art is shown;

[0029] Figure 2 A schematic diagram of the closed-loop LDO control circuit structure of the prior art is shown;

[0030] Figure 3 The schematic diagram of the structure of the LDO control circuit of the utility model is shown. DETAILED DESCRIPTION

[0031] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0032] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The combination of different embodiments, the mutual replacement of some technical features in different embodiments, and the mutual replacement of the same or similar prior art means with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0033] "Coupled" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conductive medium such as a conductor, wherein the electrical conductive medium may contain parasitic inductance or parasitic capacitance, or a connection through an intermediate circuit or component described in the embodiments in the specification; indirect connection may also include a connection through other active or passive devices on the basis of achieving the same or similar functions, such as a connection through circuits or components such as switches, signal amplification circuits, and follower circuits. "Multiple" or "many" means two or more.

[0034] According to one aspect of the utility model, an LDO control circuit, such as Figure 3 As shown, it includes a bandgap circuit 1, a current mirror 2 and a regulating circuit 3. The bandgap circuit 1 is used to obtain the LDO output feedback signal and output it to the regulating circuit 3, the regulating circuit 3 is used to generate a regulating signal according to the LDO output feedback signal and output it to the current mirror 2, and the current mirror 2 is used to generate a control signal according to the ratio of the regulating signal. Wherein:

[0035] A first terminal of the bandgap circuit 1 is coupled to a control signal output terminal of the current mirror 2 , a second terminal of the bandgap circuit 1 is connected to an LDO output feedback signal, and a third terminal of the bandgap circuit 1 is coupled to a first terminal of the regulating circuit 3 .

[0036] A first terminal of the regulating circuit 3 is coupled to the third terminal of the bandgap circuit 1 , and a second terminal of the regulating circuit 3 is coupled to the second terminal of the current mirror 2 .

[0037] The first terminal of the current mirror 2 is connected to the input voltage, the second terminal of the current mirror 2 is coupled to the second terminal of the regulating circuit 3 , and the third terminal of the current mirror 2 is coupled to the LDO output voltage terminal as a control signal output terminal.

[0038] Example 1

[0039] An LDO control circuit includes a bandgap circuit 1, a current mirror 2, and a regulating circuit 3. The bandgap circuit 1 is used to obtain an LDO output feedback signal and output it to the regulating circuit 3, the regulating circuit 3 is used to generate a regulating signal according to the LDO output feedback signal and output it to the current mirror 2, and the current mirror 2 is used to generate a control signal according to the ratio of the regulating signal. Wherein:

[0040] A first terminal of the bandgap circuit 1 is coupled to a control signal output terminal of the current mirror 2 , a second terminal of the bandgap circuit 1 is connected to an LDO output feedback signal, and a third terminal of the bandgap circuit 1 is coupled to a first terminal of the regulating circuit 3 . In a specific embodiment, the bandgap circuit 1 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first transistor Q1, a second transistor Q2, a fifth resistor R5 and a sixth resistor R6, wherein the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are both coupled to the output end of the current mirror 2 and serve as the output voltage end, the gate of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6 and coupled to the drain of the sixth PMOS transistor P6 and the collector of the second transistor Q2, the drain of the fifth PMOS transistor P5 is connected to the first end of the regulating circuit 3 and the collector of the first transistor Q1; the bases of the first transistor Q1 and the second transistor Q2 are connected and coupled to the LDO output feedback end, the emitter of the first transistor Q1 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, the emitter of the second transistor Q2 is connected to the other end of the fifth resistor R5, and the other end of the sixth resistor R6 is grounded.

[0041] The first end of the regulating circuit 3 is coupled to the third end of the bandgap circuit 1, and the second end of the regulating circuit 3 is coupled to the second end of the current mirror 2. In a specific embodiment, the regulating circuit 3 includes a first NMOS transistor N1, a second NMOS transistor N2, and a third resistor R3, wherein the gate of the first NMOS transistor N1 is coupled to the drain of the second NMOS transistor N2, the drain of the first NMOS transistor N1 is coupled to the second end of the current mirror 2, the source of the first NMOS transistor N1 is coupled to the first end of the third resistor R3 and the gate of the second NMOS transistor N2, the other end of the third resistor R3 is grounded, and the source of the second NMOS transistor N2 is grounded. In another specific embodiment, the regulating circuit 3 includes a first NMOS tube N1, a second NMOS tube N2, a third resistor R3 and a fourth resistor R4, wherein the gate of the first NMOS tube N1 is coupled to the drain of the second NMOS tube N2 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is coupled to the input voltage HV, the drain of the first NMOS tube N1 is coupled to the second end of the current mirror 2, the source of the first NMOS tube N1 is coupled to the first end of the third resistor R3 and the gate of the second NMOS tube N2, the other end of the third resistor R3 is grounded, and the source of the second NMOS tube N2 is grounded.

[0042] The first end of the current mirror 2 is connected to the input voltage, the second end of the current mirror 2 is coupled to the second end of the regulating circuit 3, and the third end of the current mirror 2 is coupled to the LDO output voltage end as a control signal output end. In a specific embodiment, the current mirror 2 is a 1:K current mirror. In another specific embodiment, the current mirror 2 includes a first PMOS tube P1 and a second PMOS tube P2, wherein the sources of the first PMOS tube P1 and the second PMOS tube P2 are connected and connected to the input voltage HV, the gates of the first PMOS tube P1 and the second PMOS tube P2 are connected and connected to the drain of the first PMOS tube P1 and the second end of the regulating circuit 3, and the drain of the second PMOS tube P2 is the control signal output end coupled to the LDO output voltage end.

[0043] Example 2

[0044] An LDO control circuit includes a bandgap circuit 1, a current mirror 2, a regulating circuit 3 and a fourth PMOS tube. The bandgap circuit 1 is used to obtain an LDO output feedback signal and output it to the regulating circuit 3, the regulating circuit 3 is used to generate a regulating signal according to the LDO output feedback signal and output it to the current mirror 2, and the current mirror 2 is used to generate a control signal according to the ratio of the regulating signal. Wherein:

[0045] A first terminal of the bandgap circuit 1 is coupled to the control signal output terminal of the current mirror 2 , a second terminal of the bandgap circuit 1 is connected to the LDO output feedback signal, and a third terminal of the bandgap circuit 1 is coupled to the gate of the fourth PMOS tube. In a specific embodiment, the bandgap circuit 1 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first transistor Q1, a second transistor Q2, a fifth resistor R5 and a sixth resistor R6, wherein the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are both coupled to the output end of the current mirror 2 and serve as the output voltage end, the gate of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6 and coupled to the drain of the sixth PMOS transistor P6 and the collector of the second transistor Q2, the drain of the fifth PMOS transistor P5 is connected to the first end of the regulating circuit 3 and the collector of the first transistor Q1; the bases of the first transistor Q1 and the second transistor Q2 are connected and coupled to the LDO output feedback end, the emitter of the first transistor Q1 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, the emitter of the second transistor Q2 is connected to the other end of the fifth resistor R5, and the other end of the sixth resistor R6 is grounded.

[0046] The first end of the regulating circuit 3 is coupled to the drain of the fourth PMOS tube, and the second end of the regulating circuit 3 is coupled to the second end of the current mirror 2. In a specific embodiment, the regulating circuit 3 includes a first NMOS tube N1, a second NMOS tube N2, a third resistor R3 and a fourth resistor R4, wherein the gate of the first NMOS tube N1 is coupled to the drain of the second NMOS tube N2 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is coupled to the input voltage HV, the drain of the first NMOS tube N1 is coupled to the second end of the current mirror 2, the source of the first NMOS tube N1 is coupled to the first end of the third resistor R3 and the gate of the second NMOS tube N2, the other end of the third resistor R3 is grounded, and the source of the second NMOS tube N2 is grounded.

[0047] The first end of the current mirror 2 is connected to the input voltage, the second end of the current mirror 2 is coupled to the second end of the regulating circuit 3, and the third end of the current mirror 2 is coupled to the LDO output voltage end as a control signal output end. In a specific embodiment, the current mirror 2 is a 1:K current mirror. In another specific embodiment, the current mirror 2 includes a first PMOS tube P1 and a second PMOS tube P2, wherein the sources of the first PMOS tube P1 and the second PMOS tube P2 are connected and connected to the input voltage HV, the gates of the first PMOS tube P1 and the second PMOS tube P2 are connected and connected to the drain of the first PMOS tube P1 and the second end of the regulating circuit 3, and the drain of the second PMOS tube P2 is the control signal output end coupled to the LDO output voltage end.

[0048] The gate of the fourth PMOS tube is coupled to the third end of the bandgap circuit 1 , the source of the fourth PMOS tube is coupled to the third end of the current mirror 2 , and the drain of the fourth PMOS tube is coupled to the first end of the regulating circuit 3 .

[0049] like Figure 3 As shown, the LDO control circuit reuses the loop structure of the bandgap circuit 1, so that the output voltage VDD=VBG / R2*R1+Vgs_p3. When the output voltage VDD is too high, that is, the output feedback voltage VBG is too high, the bandgap circuit loop reduces the voltage at point A, the current flowing through the fourth PMOS tube P4 to the third resistor R3 increases, the gate voltage of the second NMOS tube N2 increases, and the gate voltage of the first NMOS tube N1 is pulled down at the same time, so that the current flowing through the first PMOS tube P1 decreases, and the current flowing through the second PMOS tube P2 after amplification by the 1:K current mirror also decreases, and finally the output voltage VDD decreases. The LDO control circuit controls the output voltage VDD through the above loop control, eliminating the separate operational amplifier of the traditional closed-loop LDO, and the system has better performance; at the same time, the internal power supply current generated by the multiplexing bandgap circuit improves the consistency of the system.

[0050] According to another aspect of the utility model, an LDO control circuit is characterized by comprising a first PMOS tube P1, a second PMOS tube P2, a fourth PMOS tube P4, a first NMOS tube N1, a second NMOS tube N2, a third resistor R3, a fourth resistor R4, a fifth PMOS tube P5, a sixth PMOS tube P6, a first triode Q1, a second triode Q2, a fifth resistor R5 and a sixth resistor R6. Wherein:

[0051] The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected and connected to the input voltage HV, the gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected and connected to the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1, and the drain of the second PMOS transistor P2 is coupled to the source of the fourth PMOS transistor P4 and serves as the output voltage terminal VDD;

[0052] The gate of the first NMOS transistor N1 is coupled to the drain of the second NMOS transistor N2 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is coupled to the input voltage HV, the source of the first NMOS transistor N1 is coupled to the drain of the fourth PMOS transistor P4, the first end of the third resistor R3 and the gate of the second NMOS transistor N2, the other end of the third resistor R3 is grounded, and the source of the second NMOS transistor N2 is grounded;

[0053] The source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6 are both coupled to the drain of the second PMOS tube P2, the gate of the fifth PMOS tube P5 is connected to the gate of the sixth PMOS tube P6 and coupled to the drain of the sixth PMOS tube P6 and the collector of the second transistor Q2, the drain of the fifth PMOS tube P5 is coupled to the gate of the fourth PMOS tube P4 and the collector of the first transistor Q1, the bases of the first transistor Q1 and the second transistor Q2 are connected and coupled to the LDO output feedback end, the emitter of the first transistor Q1 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, the emitter of the second transistor Q2 is connected to the other end of the fifth resistor R5, and the other end of the sixth resistor R6 is grounded.

[0054] According to another aspect of the utility model, an LDO power supply includes a PMOS driving tube P3, a first feedback resistor R1, a second feedback resistor R2 and the above-mentioned LDO control circuit, wherein the gate of the PMOS driving tube P3 is coupled to its drain and one end of the first feedback resistor R1, the source of the PMOS driving tube P3 serves as the LDO output voltage end and is coupled to the third end of the current mirror 2, the other end of the first feedback resistor R1 is coupled to the second end of the bandgap circuit 1 and one end of the second feedback resistor R2, and the other end of the second feedback resistor R2 is grounded.

[0055] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input terminal" and "inverting input terminal" in the logic controls involved in the specification or drawings can be interchanged or changed with each other, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic controls.

[0056] The description and application of the utility model here are illustrative, and it is not intended to limit the scope of the utility model to the above-mentioned embodiments. The relevant descriptions of the effects or advantages involved in the specification may not be reflected in the actual experimental examples due to the uncertainty of specific condition parameters or other factors, and the relevant descriptions of the effects or advantages are not used to limit the scope of the utility model. The deformation and changes of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent components are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the utility model can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the utility model. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the utility model.

Claims

1. An LDO control circuit, characterized in that: include: A bandgap circuit (1), wherein a first end is coupled to a control signal output end of a current mirror (2), a second end is connected to an LDO output feedback signal, and a third end is coupled to a first end of a regulating circuit (3); the bandgap circuit (1) is used to obtain the LDO output feedback signal and output it to the regulating circuit (3); A regulating circuit (3), wherein a first end of the regulating circuit (3) is coupled to the third end of the bandgap circuit (1), and a second end of the regulating circuit (3) is coupled to the second end of the current mirror (2); the regulating circuit (3) is used to generate a regulating signal according to the LDO output feedback signal and output the regulating signal to the current mirror (2); A current mirror (2) has a first end connected to an input voltage, a second end coupled to a second end of a regulating circuit (3), and a third end coupled to an LDO output voltage end as a control signal output end; the current mirror (2) is used to generate a control signal according to a ratio of a regulating signal.

2. The LDO control circuit according to claim 1, characterized in that: The LDO control circuit also includes a fourth PMOS tube, whose gate is coupled to the third end of the bandgap circuit (1), whose source is coupled to the third end of the current mirror (2), and whose drain is coupled to the first end of the regulating circuit (3).

3. The LDO control circuit according to claim 1 or 2, characterized in that: The regulating circuit (3) comprises a first NMOS tube, a second NMOS tube and a third resistor, wherein the gate of the first NMOS tube is coupled to the drain of the second NMOS tube, the drain of the first NMOS tube is coupled to the second end of the current mirror (2), the source of the first NMOS tube is coupled to the first end of the third resistor and the gate of the second NMOS tube, the other end of the third resistor is grounded, and the source of the second NMOS tube is grounded.

4. The LDO control circuit according to claim 3, characterized in that: The regulating circuit (3) further comprises a fourth resistor, one end of which is coupled to the input voltage, and the other end of which is coupled to the gate of the first NMOS tube and the drain of the second NMOS tube.

5. The LDO control circuit according to claim 1 or 2, characterized in that: The bandgap circuit (1) comprises a fifth PMOS tube, a sixth PMOS tube, a first transistor, a second transistor, a fifth resistor and a sixth resistor, wherein the source of the fifth PMOS tube and the source of the sixth PMOS tube are both coupled to the output end of the current mirror (2) and serve as the output voltage end, the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube and coupled to the drain of the sixth PMOS tube and the collector of the second transistor, the drain of the fifth PMOS tube is connected to the collector of the first transistor and the first end of the regulating circuit (3); the bases of the first transistor and the second transistor are connected and coupled to the LDO output feedback end, the emitter of the first transistor is connected to one end of the fifth resistor and one end of the sixth resistor, the emitter of the second transistor is connected to the other end of the fifth resistor, and the other end of the sixth resistor is grounded.

6. The LDO control circuit according to claim 1 or 2, characterized in that: The current mirror (2) is a 1:K current mirror.

7. The LDO control circuit according to claim 1 or 2, characterized in that: The current mirror (2) comprises a first PMOS tube and a second PMOS tube, wherein the sources of the first PMOS tube and the second PMOS tube are connected and connected to the input voltage, the gates of the first PMOS tube and the second PMOS tube are connected and connected to the drain of the first PMOS tube and the second end of the regulating circuit, and the drain of the second PMOS tube is a control signal output end coupled to the LDO output voltage end.

8. An LDO power supply, characterized in that: The invention comprises a PMOS driver tube, a first feedback resistor, a second feedback resistor and an LDO control circuit as described in any one of claims 1 to 7, wherein the gate of the PMOS driver tube is coupled to its drain and one end of the first feedback resistor, the source of the PMOS driver tube serves as the LDO output voltage terminal and is coupled to the third end of the current mirror (2), the other end of the first feedback resistor is coupled to the second end of the bandgap circuit (1) and one end of the second feedback resistor, and the other end of the second feedback resistor is grounded.

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