VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device for enhancing reverse resistance effect

Abstract

The utility model relates to the technical field of power semiconductors, and discloses a VDMOS device capable of enhancing reverse blocking effect, which comprises a metal source electrode, a metal grid electrode and an N + substrate, the upper surface of the N + substrate is doped with an N-type buffer layer, the concentration of the N-type buffer layer is gradually reduced from bottom to top, and the concentration of the N-type buffer layer is gradually reduced from bottom to top. N-type heavily-doped semiconductor regions are formed on the two sides of the interior of the N-type buffer layer through ion implantation, P-type heavily-doped semiconductor regions are formed on the two sides of the upper portion of the N-type buffer layer in the same mode, and the lower portions of the P-type heavily-doped semiconductor regions make contact with the upper portions of the N-type heavily-doped semiconductor regions; according to the VDMOS device, the gate dielectric layer composed of Si3N4 and SiO2 is adopted, the thickness of the gate dielectric layer is increased, the single-particle gate penetration phenomenon of the VDMOS device is reduced, the doping concentration of the N-type buffer layer is gradually reduced from bottom to top, the resistance of the device can be reduced, the stability of the VDMOS device can be improved, the metal gate is wrapped by the gate dielectric layer and the silicon dioxide insulating layer, and therefore the reliability of the VDMOS device is improved. And the possibility that the grid electrode of the VDMOS device is radiated is low.

Description

Technical Field

[0001] The utility model relates to the technical field of power semiconductors, and more specifically discloses a VDMOS device with enhanced reverse resistance effect. Background Art

[0002] VDMOS (Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor) plays an important role in various power conversions, especially high-frequency power conversions, due to its advantages of high switching speed, low switching loss, and low driving loss. Power conversion usually includes several conversion modes: AC to DC (AC-DC), DC to AC (DC-AC), DC to DC (DC-DC), and AC to AC (AC-AC).

[0003] Chinese patent publication number CN108074985B discloses a reverse-blocking VDMOS device. The patent points out that the VDMOS device does not have the ability of reverse conduction and reverse blocking. To build a bidirectional switch based on the VDMOS device, it is necessary to connect a diode in series at the drain end of the VDMOS device, and then connect two groups of VDMOS devices and diodes in reverse parallel. In this way, it has a larger on-resistance, increases the loss of the VDMOS device, and reduces the performance of the bidirectional switch. Therefore, the presence of the field blocking layer in the patented technical solution prevents the punch-through effect of the electric field in the drift region, reduces the thickness of the drift region, and enables the device to obtain a lower on-resistance.

[0004] However, the space environment and nuclear radiation environment can easily induce abnormalities and failures in VDMOS devices, among which the impact of the radiation environment on the equipment is the most prominent. The incident particles can penetrate into the device, causing ionizing radiation damage, displacement radiation damage, single particle events, and internal charging and discharging effects on the device, which can easily cause the VDMOS device to have poor reverse resistance and low performance.

[0005] Therefore, a VDMOS device with enhanced reverse resistance effect is designed. Summary of the invention

[0006] The utility model provides a VDMOS device with enhanced reverse resistance effect, which can solve the problem that space environment and nuclear radiation environment easily induce abnormality and failure of VDMOS device, and then easily cause poor reverse resistance effect and low performance of VDMOS device.

[0007] To solve the above technical problems, according to one aspect of the utility model, more specifically, a VDMOS device with enhanced reverse resistance effect includes a metal source, a metal gate and an N+ substrate, the upper surface of the N+ substrate is doped with an N-type buffer layer, the concentration of the N-type buffer layer decreases from bottom to top, the inner two sides of the N-type buffer layer are formed into N-type heavily doped semiconductor regions by ion implantation, the upper two sides of the N-type buffer layer are formed into P-type heavily doped semiconductor regions by the same method, and the lower part of the P-type heavily doped semiconductor region is in contact with the upper part of the N-type heavily doped semiconductor region, the upper surface of the N-type buffer layer has an N-type forward field stop layer, an N-drift region is epitaxially grown on the upper part of the N-drift layer, the inner two sides of the N-drift region are formed into P-pillars by ion implantation, and the side surfaces of the P-pillars are in contact with the The side of the N-type forward field stop layer is in contact with the metal gate, the metal gate is deposited on both sides of the upper part of the N-drift region, a silicon dioxide insulating layer is provided on the outside of the metal gate, the silicon dioxide insulating layer is in an inverted concave shape, the bottom surface of the metal gate is in contact with the gate dielectric layer, the gate dielectric layer and the silicon dioxide insulating layer completely wrap the metal gate, an N-type reverse field stop layer is formed above the N-drift region by ion implantation, a P-type lightly doped region is ion implanted above the N-type reverse field stop layer, the P-type lightly doped region is in a concave shape, a P+ region is highly doped in the P-type lightly doped region, N+ regions are doped on both sides of the P+ region by ion implantation, the metal source is deposited above the P+ region and the N+ region, and the metal source forms an ohmic contact with the P+ region and the N+ region.

[0008] Furthermore, the doping concentration of the P-type heavily doped semiconductor region is greater than the doping concentration of the N-type heavily doped semiconductor region, and the doping concentration of the N-type reverse field stop layer is less than the doping concentration of the N-type forward field stop layer.

[0009] Furthermore, the thickness of the gate dielectric layer is 100 um, and the gate dielectric layer is composed of Si 3 N 4 and SiO 2 .

[0010] Furthermore, the P+ region and the N+ region form a PN junction.

[0011] Furthermore, a metal drain is deposited on the back side of the N+ substrate, and the thickness of the metal drain is 3-7 microns.

[0012] Furthermore, grooves are etched on both sides of the upper side of the N-drift region, and the metal gate and the silicon dioxide insulating layer are in the grooves.

[0013] The beneficial effects of the VDMOS device with enhanced reverse resistance effect of the utility model are as follows:

[0014] The utility model adopts a gate dielectric layer composed of Si3N4 and SiO2, increases the thickness of the gate dielectric layer, can reduce the single particle gate penetration phenomenon of the VDMOS device, and further improves the reverse resistance effect of the device.

[0015] In the utility model, the doping concentration of the N-type buffer layer gradually decreases from bottom to top, which can reduce the device resistance and improve the stability of the VDMOS device. In addition, the gate dielectric layer and the silicon dioxide insulating layer wrap the metal gate, and the gate of the VDMOS device is less likely to be radiated. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0017] Figure 1 The schematic diagram is a structural diagram of a VDMOS device for enhancing reverse resistance effect according to the utility model.

[0018] In the figure: 1. Metal source; 2. P+ region; 3. N+ region; 4. P-type lightly doped region; 5. N-type reverse field stop layer; 6. Silicon dioxide insulating layer; 7. Metal gate; 8. Gate dielectric layer; 9. P column; 10. N-drift region; 11. N-type forward field stop layer; 12. P-type heavily doped semiconductor region; 13. N-type heavily doped semiconductor region; 14. N-type buffer layer; 15. Metal drain; 16. N+ substrate. DETAILED DESCRIPTION

[0019] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0020] According to the attached Figure 1A VDMOS device with enhanced reverse resistance effect is provided, comprising a metal source 1, a metal gate 7 and an N+ substrate 16, the upper surface of the N+ substrate 16 is doped with an N-type buffer layer 14, the concentration of the N-type buffer layer 14 decreases from bottom to top, the inner two sides of the N-type buffer layer 14 are formed by ion implantation to form an N-type heavily doped semiconductor region 13, the upper two sides of the N-type buffer layer 14 are formed by the same method to form a P-type heavily doped semiconductor region 12, and the lower part of the P-type heavily doped semiconductor region 12 is in contact with the upper part of the N-type heavily doped semiconductor region 13, the upper surface of the N-type buffer layer 14 has an N-type forward field stop layer 11, an N-drift region 10 is epitaxially grown on the upper part of the N-drift region 14, the inner two sides of the lower part of the N-drift region 10 are formed by ion implantation to form a P column 9, and the side of the P column 9 is in contact with the N The side of the N-drift region 10 is in contact with the forward field stop layer 11, metal gates 7 are deposited on both sides of the upper part of the N-drift region 10, a silicon dioxide insulating layer 6 is provided on the outside of the metal gate 7, the silicon dioxide insulating layer 6 is in an inverted concave shape, the bottom of the metal gate 7 is in contact with a gate dielectric layer 8, the gate dielectric layer 8 and the silicon dioxide insulating layer 6 completely wrap the metal gate 7, an N-type reverse field stop layer 5 is formed above the N-drift region 10 by ion implantation, a P-type lightly doped region 4 is ion implanted above the N-drift region 10, the P-type lightly doped region 4 is in a concave shape, a P+ region 2 is highly doped in the P-type lightly doped region 4, both sides of the P+ region 2 are doped with N+ regions 3 by ion implantation, a metal source 1 is deposited above the P+ region 2 and the N+ region 3, and the metal source 1 forms an ohmic contact with the P+ region 2 and the N+ region 3.

[0021] When the voltage applied to the metal gate 7 is large enough, the gate dielectric layer 8 between the metal gate 7 and the channel is broken down to form a conductive channel. At this time, charges can flow from the metal source 1 to the metal drain 15, thereby turning on the VDMOS device. When the voltage on the metal gate 7 decreases, the gate dielectric layer 8 gradually recovers, the conductive channel is disconnected, and the VDMOS device cannot be turned on and used.

[0022] The gradual change in the concentration of the N-type buffer layer 14 helps to reduce defects such as dislocations caused by lattice mismatch or a sharp change in doping concentration.

[0023] In this embodiment, the doping concentration of the P-type heavily doped semiconductor region 12 is greater than the doping concentration of the N-type heavily doped semiconductor region 13 , and the doping concentration of the N-type reverse field stop layer 5 is less than the doping concentration of the N-type forward field stop layer 11 .

[0024] In this embodiment, the thickness of the gate dielectric layer 8 is 100um, and the gate dielectric layer 8 is composed of Si3N4 and SiO2. Compared with the traditional VDMOS device, increasing the thickness of the gate dielectric layer 8 can improve the single-particle gate penetration phenomenon, which is beneficial to the stability of the performance of the VDMOS device.

[0025] In this embodiment, the P+ region 2 and the N+ region 3 form a PN junction.

[0026] In this embodiment, a metal drain electrode 15 is deposited on the back side of the N+ substrate 16 , and the thickness of the metal drain electrode 15 is 3-7 microns. The metal drain electrode 15 is made of copper and has low resistance.

[0027] In this embodiment, trenches are etched on both sides of the upper portion of the N-drift region 10 , and the metal gate 7 and the silicon dioxide insulating layer 6 are in the trenches.

[0028] The electrical components that appear in this article are all electrical components that exist in reality.

[0029] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A VDMOS device with enhanced reverse resistance, comprising a metal source (1), a metal gate (7) and an N+ substrate (16), characterized in that: The upper surface of the N+ substrate (16) is doped with an N-type buffer layer (14), the concentration of the N-type buffer layer (14) decreases from bottom to top, the inner two sides of the N-type buffer layer (14) are formed into an N-type heavily doped semiconductor region (13) by ion implantation, the upper two sides of the N-type buffer layer (14) are formed into a P-type heavily doped semiconductor region (12) by the same method, and the lower part of the P-type heavily doped semiconductor region (12) is in contact with the upper part of the N-type heavily doped semiconductor region (13), the upper surface of the N-type buffer layer (14) has an N-type forward field stop layer (11), an N-drift region (10) is epitaxially grown on the upper part of the N-buffer layer (14), the inner two sides of the N-drift region (10) are formed into a P column (9) by ion implantation, the side of the P column (9) is in contact with the side of the N-type forward field stop layer (11), and the upper two sides of the N-drift region (10) are deposited with the N-type heavily doped semiconductor region (12) A metal gate (7), wherein a silicon dioxide insulating layer (6) is provided on the outside of the metal gate (7), wherein the silicon dioxide insulating layer (6) is in an inverted concave shape, wherein the bottom surface of the metal gate (7) contacts a gate dielectric layer (8), wherein the gate dielectric layer (8) and the silicon dioxide insulating layer (6) completely wrap the metal gate (7), and an N-type reverse field blocking layer (5) is formed above the N-drift region (10) by ion implantation, wherein the N-type reverse field A P-type lightly doped region (4) is ion-implanted above the blocking layer (5), the P-type lightly doped region (4) is in a concave shape, a P+ region (2) is highly doped in the P-type lightly doped region (4), both sides of the P+ region (2) are doped with N+ regions (3) by ion implantation, the metal source electrode (1) is deposited above the P+ region (2) and the N+ region (3), and the metal source electrode (1) forms an ohmic contact with the P+ region (2) and the N+ region (3).

2. A VDMOS device with enhanced reverse resistance according to claim 1, characterized in that: The doping concentration of the P-type heavily doped semiconductor region (12) is greater than the doping concentration of the N-type heavily doped semiconductor region (13), and the doping concentration of the N-type reverse field stop layer (5) is less than the doping concentration of the N-type forward field stop layer (11).

3. A VDMOS device with enhanced reverse resistance according to claim 1, characterized in that: The thickness of the gate dielectric layer (8) is 100 um, and the gate dielectric layer (8) is composed of Si3N4 and SiO2.

4. A VDMOS device with enhanced reverse resistance according to claim 1, characterized in that: The P+ region (2) and the N+ region (3) form a PN junction.

5. The VDMOS device with enhanced reverse resistance according to claim 1, characterized in that: A metal drain (15) is deposited on the back side of the N+ substrate (16), and the thickness of the metal drain (15) is 3-7 microns.

6. A VDMOS device with enhanced reverse resistance according to claim 1, characterized in that: Grooves are etched on both sides of the upper side of the N-drift region (10), and the metal gate (7) and the silicon dioxide insulating layer (6) are in the grooves.

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