Network tester

Abstract

The utility model provides a network tester. The network tester comprises a field programmable gate array chip; the at least one port physical layer chip is electrically connected with the field programmable gate array chip; the at least one network transformer is electrically connected with the port physical layer chip; the aviation plug is electrically connected with the network transformer; wherein the field programmable gate array chip sends a test signal to the at least one aviation plug through the port physical layer chip and the network transformer. According to the utility model, the problem that potential fault points are increased due to the fact that testing is carried out through various kinds of switching in the prior art can be solved.

Description

Technical Field

[0001] The utility model relates to the technical field of aviation electronics, in particular to a network tester. Background Art

[0002] Currently, the interfaces of common network testing instruments on the market are mainly electrical ports and optical ports. Therefore, testing the network performance of aviation interfaces needs to be tested through various adapters, which increases potential failure points. Setting up adapters not only takes up space, but also requires installation and removal of adapters, reducing the efficiency of testing work. Utility Model Content

[0003] The utility model aims to provide a network tester to solve the problem in the prior art that various switching is used to perform testing, thereby increasing potential failure points.

[0004] To solve the above technical problems, the technical solution of this novel invention is as follows:

[0005] A network tester, comprising:

[0006] Field Programmable Gate Array chips;

[0007] At least one port physical layer chip electrically connected to the field programmable gate array chip;

[0008] at least one network transformer electrically connected to the port physical layer chip;

[0009] An aviation plug electrically connected to the network transformer;

[0010] The field programmable gate array chip sends the test signal to at least one aviation plug through the port physical layer chip and the network transformer.

[0011] Optionally, the field programmable gate array chip includes: a first chip unit; the first chip unit includes:

[0012] a plurality of first general purpose input / output pins;

[0013] a plurality of second general purpose input / output pins;

[0014] Wherein, the first general input / output pin is electrically connected to the port physical layer chip.

[0015] Optionally, the network tester further includes a display screen, which is electrically connected to the second general input / output pin.

[0016] Optionally, the first chip unit further includes:

[0017] a plurality of first power supply pins;

[0018] The plurality of first power pins are electrically connected to a power source, and the first power pins are connected in parallel with a plurality of energy storage capacitors.

[0019] Optionally, the port physical layer chip includes: a second chip unit; the second chip unit includes:

[0020] a plurality of third general purpose input / output pins;

[0021] a plurality of fourth general purpose input / output pins;

[0022] The third general purpose input / output pin is electrically connected to at least one network transformer, and the fourth general purpose input / output pin is electrically connected to the field programmable gate array chip.

[0023] Optionally, the second chip unit further includes:

[0024] a plurality of second power supply pins;

[0025] A plurality of the second power pins are electrically connected to a power source, and a plurality of energy storage capacitors are connected in parallel to the second power pins.

[0026] Optionally, the network transformer is integrated with the aviation plug.

[0027] Optionally, the at least one aviation plug includes: a 2-core aviation plug, a 3-core aviation plug and / or a 4-core aviation plug.

[0028] The beneficial effects of the utility model are:

[0029] The above scheme of the utility model is to have at least one port physical layer chip electrically connected via a field programmable gate array chip; at least one network transformer electrically connected to the port physical layer chip; and an aviation plug electrically connected to the network transformer; wherein the field programmable gate array chip sends the test signal to at least one aviation plug via the port physical layer chip and the network transformer, and can perform network performance tests on various types of aviation connectors, including throughput, frame loss, delay, and jitter tests. Directly inserting the aviation connector does not require complex switching, avoids adding potential failure points, and does not require installation or disassembly of switching equipment, thereby improving the efficiency of the test work. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The figure is a schematic diagram of the structure of the network tester of the utility model.

[0031] Figure 2 It is a circuit diagram of the first chip unit U44 of the present invention.

[0032] Figure 3FIG. 4 is a circuit diagram of the second chip unit J5 of the present invention.

[0033] Figure 4 FIG. 4 is a circuit diagram of the second chip unit J6 of the present invention.

[0034] Figure 5 The utility model is a schematic diagram of the positions of the field programmable gate array chip, the port physical layer chip and the aviation plug of the network tester on the circuit board.

[0035] Figure 6 This is a schematic diagram of the position of the aviation plug of the utility model.

[0036] Description of reference numerals:

[0037] 1. Field programmable gate array chip, 2. Port physical layer chip, 3. Aviation plug, 31. 2-core aviation plug, 32. 3-core aviation plug, 33. 4-core aviation plug. DETAILED DESCRIPTION

[0038] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0039] like Figure 1 As shown, an embodiment of the utility model provides a network tester, comprising:

[0040] Field programmable gate array chip 1;

[0041] At least one port physical layer chip 2 electrically connected to the field programmable gate array chip 1;

[0042] At least one network transformer electrically connected to the port physical layer chip 2;

[0043] An aviation plug 3 electrically connected to the network transformer;

[0044] The field programmable gate array chip 1 sends the test signal to at least one aviation plug 3 through the port physical layer chip 2 and the network transformer.

[0045] In this embodiment, the field programmable gate array chip 1 generates a test signal and sends the test signal to the port physical layer chip 2. The port physical layer chip 2 converts the test signal, such as MAC or PHY conversion, converts the digital signal into an analog signal suitable for transmission on a physical medium, and then sends the analog signal to at least one aviation plug 3 through a network transformer to implement testing of the aviation plug 3.

[0046] like Figures 2 to 4 As shown, in an optional embodiment of the utility model, the network tester includes:

[0047] A field programmable gate array chip 1, two-port physical layer chips 2, eight aviation plugs 3, and a display screen, wherein the aviation plug 3 is integrated with a network transformer.

[0048] The field programmable gate array chip 1 includes: a first chip unit U44; the first chip unit U44 includes:

[0049] A plurality of first general purpose input / output (I / O) pins, specifically including pins 1A1, 1A2, ..., 1A8;

[0050] A plurality of second general purpose input / output (I / O) pins, specifically including pins 1B1, 1B2, ..., 1B8;

[0051] The first power supply pins include: pins VCCA and VCCB.

[0052] The two-port physical layer chip 2 includes second chip units J5 and J6, and the second chip units J5 and J6 each include:

[0053] Multiple third general-purpose input / output (I / O) pins, including pin MDI0 + 、MDI0 - 、...、MDI3 + 、MDI3 + ;

[0054] a plurality of fourth general purpose input / output (I / O) pins, specifically including pins LED1_GPYN, LED1_GNYP, and LED2N;

[0055] The second power pins include pins CT0, CT1, CT2, and CT3.

[0056] The third general input / output (I / O) pins of the second chip units J5 and J6 are electrically connected to eight network transformers, the fourth general input / output (I / O) pins of the second chip units J5 and J6 are electrically connected to the first general input / output (I / O) pins of the first chip unit U44, and the second general input / output (I / O) pins of the first chip unit U44 are electrically connected to the display screen. The first power pin and the second power pin are electrically connected to the power supply.

[0057] The first power pins VCCA and VCCB are connected in parallel with a plurality of energy storage capacitors, specifically including energy storage capacitors C501, C504, C505, C507, C506, and C502. The second power pins CT0, CT1, CT2, and CT3 are connected in parallel with a plurality of energy storage capacitors, specifically including energy storage capacitors C129, C130, C341, and C342.

[0058] In this embodiment, the first chip unit U44 generates a test signal using a register and a clock signal, and sends the test signal to the second chip unit J5 or J6. The second chip unit J5 or J6 modulates the test signal as a digital signal into an analog signal. The network transformer transforms the test signal as an analog signal and transmits it to the aviation plug 3, and then reaches the aviation connector. The test signal fed back by the aviation connector then passes through the network transformer, the second chip unit J5 or J6, and the first chip unit U44 in sequence. The first chip unit U44 calculates and processes the fed-back test signal and displays it on the screen for viewing the result.

[0059] The model of the first chip unit U44 is XC7K325T, and the model of the second chip unit J5 and J6 is 88E1512. The first chip unit U44 is a semi-custom circuit in the field of application-specific integrated circuits ASIC, which uses a small lookup table to implement combinational logic. Each lookup table is connected to the input of a D flip-flop, and the flip-flop drives other logic circuits or drives I / O. The second chip units J5 and J6 are responsible for implementing the physical layer function of data transmission. The multiple aviation plugs 3 are cascaded on the template. It should be noted here that the template can be a circuit board, and the first chip unit U44, the second chip units J5, J6 and the aviation plug 3 are all arranged on the circuit board.

[0060] like Figure 5 , 6 As shown, in an optional embodiment of the utility model, the at least one aviation plug 3 includes:

[0061] A 2-core aviation plug 31 , a 3-core aviation plug 32 and / or a 4-core aviation plug 33 .

[0062] In the above embodiment of the utility model, the field programmable gate array chip 1 is electrically connected to at least one aviation plug 3 through the port physical layer chip 2 and the network transformer, and can perform network performance tests on various types of aviation connectors, including throughput, frame loss, delay, and jitter tests. Direct insertion into the aviation connector does not require complex switching, avoids adding potential failure points, and does not require installation and disassembly of switching equipment, thereby improving the efficiency of the test work.

[0063] The above is a preferred embodiment of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A network tester, characterized in that: include: Field Programmable Gate Array Chip (1); At least one port physical layer chip (2) electrically connected to the field programmable gate array chip (1); At least one network transformer electrically connected to the port physical layer chip (2); An aviation plug (3) electrically connected to the network transformer; The field programmable gate array chip (1) sends the test signal to at least one aviation plug (3) through the port physical layer chip (2) and the network transformer.

2. The network tester according to claim 1, characterized in that: The field programmable gate array chip (1) comprises: a first chip unit (U44); the first chip unit (U44) comprises: a plurality of first general purpose input / output pins; a plurality of second general purpose input / output pins; Wherein, the first general input / output pin is electrically connected to the port physical layer chip (2).

3. The network tester according to claim 2, characterized in that: The device also includes a display screen, which is electrically connected to the second general input / output pin.

4. The network tester according to claim 2, characterized in that: The first chip unit (U44) further includes: a plurality of first power supply pins; The plurality of first power pins are electrically connected to a power source, and the first power pins are connected in parallel with a plurality of energy storage capacitors.

5. The network tester according to claim 1, characterized in that: The port physical layer chip (2) comprises: a second chip unit (J5); the second chip unit (J5) comprises: a plurality of third general purpose input / output pins; a plurality of fourth general purpose input / output pins; The third general purpose input / output pin is electrically connected to at least one network transformer, and the fourth general purpose input / output pin is electrically connected to the field programmable gate array chip (1).

6. The network tester according to claim 5, characterized in that: The second chip unit (J5) further includes: a plurality of second power supply pins; A plurality of the second power pins are electrically connected to a power source, and a plurality of energy storage capacitors are connected in parallel to the second power pins.

7. The network tester according to claim 1, characterized in that: The network transformer and the aviation plug (3) are integrated.

8. The network tester according to claim 1, characterized in that: The at least one aviation plug (3) comprises: a 2-core aviation plug (31), a 3-core aviation plug (32) and / or a 4-core aviation plug (33).

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